K6T4008V1C, K6T4008U1C Family CMOS SRAM Document Title 512Kx8 bit Low Power and Low Voltage CMOS Static RAM Revision History Revision No. History Draft Data Remark 0.0 Initial Draft January 13, 1998 Advance 0.1 Revisied - Speed bin change KM68U4000C : 85/100ns → 70/85/100ns - DC Characteristics change ICC : 5mA at read/write → 4mA at read ICC1 : 3mA → 4mA ICC2 : 35mA → 30mA ISB : 0.5mA → 0.3mA ISB1 : 10µA → 15µA for commercial parts - Add 32-TSOP1-0820 June 12, 1998 Preliminary 0.11 Errata correct - 32-TSOP1-0813 products: T → TG November 7, 1998 1.0 Finalize January 15, 1999 Final The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. 1 Revision 1.0 January 1999 K6T4008V1C, K6T4008U1C Family CMOS SRAM 512K×8 bit Low Power and Low Voltage CMOS Static RAM FEATURES GENERAL DESCRIPTION • Process Technology: TFT • Organization: 512K×8 • Power Supply Voltage K6T4008V1C Family: 3.0~3.6V K6T4008U1C Family: 2.7~3.3V • Low Data Retention Voltage: 2V(Min) • Three state output and TTL Compatible • Package Type: 32-SOP-525, 32-TSOP2-400F/R 32-TSOP1-0820F, 32-TSOP1-0813.4F The K6T4008V1C and K6T4008U1C families are fabricated by SAMSUNG′s advanced CMOS process technology. The families support various operating temperature range and have various package type for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Power Dissipation Product Family Operating Temperature Vcc Range K6T4008V1C-B Commercial(0~70°C) K6T4008U1C-B K6T4008V1C-F Industrial(-40~85°C) K6T4008U1C-F Speed Standby (ISB1, Max) 3.0~3.6V 701)/85ns 2.7~3.3V 701)/85/100ns 3.0~3.6V 701)/85ns 2.7~3.3V 701)/85/100ns 15µA 30mA 20µA PKG Type Operating (ICC2, Max) 32-SOP 32-TSOP2-F/R 32-TSOP1-F 32-sTSOP1-F 1. The paramerter is measured with 30pF test load. PIN DESCRIPTION FUNCTIONAL BLOCK DIAGRAM A18 1 32 VCC VCC 32 1 A16 2 31 A15 A15 31 2 A18 A16 A14 3 30 A17 A17 30 3 A14 A12 4 29 WE WE 29 4 A12 A7 5 28 A13 A13 28 5 A7 A6 6 27 A8 A8 27 6 A6 A5 7 26 A9 A9 26 7 A5 A4 A4 8 25 A11 A11 25 8 A4 A5 A3 9 24 OE OE 24 9 A3 A6 A2 10 23 A10 A10 23 10 A2 A7 A1 11 22 CS CS 22 11 A1 12 21 I/O8 I/O8 21 12 A0 I/O1 13 20 I/O7 I/O7 20 13 I/O1 I/O2 14 19 I/O6 I/O6 19 14 I/O2 I/O3 15 18 I/O5 I/O5 18 15 I/O3 VSS 16 17 I/O4 I/O4 17 16 VSS A0 32-SOP 32-TSOP2 (Forward) 32-TSOP2 (Reverse) Clk gen. A0 A1 Row select 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-TSOP1 32-STSOP1 (Forward) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A14 A16 A18 OE A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3 Data cont I/O8 Function A0~A18 Address Inputs WE Write Enable Input CS Chip Select Input OE Output Enable Input Name A2 A3 A8 A9 A10 A11 A13 A15 A17 CS Function Vcc Power Vss Ground I/O Circuit Column select Data cont WE Name Memory array 1024 rows 512×8 columns A12 I/O1 A11 A9 A8 A13 WE A17 A15 VCC A18 A16 A14 A12 A7 A6 A5 A4 Precharge circuit. Control logic OE I/O 1~I/O8 Data Inputs/Outputs SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2 Revision 1.0 January 1999 K6T4008V1C, K6T4008U1C Family CMOS SRAM PRODUCT LIST Commercial Temp Products(0~70°C) Part Name Industrial Temp Products(-40~85°C) Function Part Name Function K6T4008V1C-GB70 K6T4008V1C-GB85 K6T4008V1C-VB70 K6T4008V1C-VB85 K6T4008V1C-MB70 K6T4008V1C-MB85 K6T4008V1C-TB70 K6T4008V1C-TB85 K6T4008V1C-YB70 K6T4008V1C-YB85 32-SOP, 70ns, 3.3V, LL 32-SOP, 85ns, 3.3V, LL 32-TSOP2-F, 70ns, 3.3V, LL 32-TSOP2-F, 85ns, 3.3V, LL 32-TSOP2-R, 70ns, 3.3V, LL 32-TSOP2-R, 85ns, 3.3V, LL 32-TSOP1-F, 70ns, 3.3V, LL 32-TSOP1-F, 85ns, 3.3V, LL 32-sTSOP1-F, 70ns, 3.3V, LL 32-sTSOP1-F, 85ns, 3.3V, LL K6T4008V1C-GF70 K6T4008V1C-GF85 K6T4008V1C-VF70 K6T4008V1C-VF85 K6T4008V1C-MF70 K6T4008V1C-MF85 K6T4008V1C-TF70 K6T4008V1C-TF85 K6T4008V1C-YF70 K6T4008V1C-YF85 32-SOP, 70ns, 3.3V, LL 32-SOP, 85ns, 3.3V, LL 32-TSOP2-F, 70ns, 3.3V, LL 32-TSOP2-F, 85ns, 3.3V, LL 32-TSOP2-R, 70ns, 3.3V, LL 32-TSOP2-R, 85ns, 3.3V, LL 32-TSOP1-F, 70ns, 3.3V, LL 32-TSOP1-F, 85ns, 3.3V, LL 32-sTSOP1-F, 70ns, 3.3V, LL 32-sTSOP1-F, 85ns, 3.3V, LL K6T4008U1C-GB70 K6T4008U1C-GB85 K6T4008U1C-GB10 K6T4008U1C-VB70 K6T4008U1C-VB85 K6T4008U1C-VB10 K6T4008U1C-MB70 K6T4008U1C-MB85 K6T4008U1C-MB10 K6T4008U1C-TB70 K6T4008U1C-TB85 K6T4008U1C-TB10 K6T4008U1C-YB70 K6T4008U1C-YB85 K6T4008U1C-YB10 32-SOP, 70ns, 3.0V, LL 32-SOP, 85ns, 3.0V, LL 32-SOP, 100ns, 3.0V, LL 32-TSOP2-F, 70ns, 3.0V, LL 32-TSOP2-F, 85ns, 3.0V, LL 32-TSOP2-F, 100ns, 3.0V, LL 32-TSOP2-R, 70ns, 3.0V, LL 32-TSOP2-R, 85ns, 3.0V, LL 32-TSOP2-R, 100ns, 3.0V, LL 32-TSOP1-F, 70ns, 3.0V, LL 32-TSOP1-F, 85ns, 3.0V, LL 32-TSOP1-F, 100ns, 3.0V, LL 32-sTSOP1-F, 70ns, 3.0V, LL 32-sTSOP1-F, 85ns, 3.0V, LL 32-sTSOP1-F, 100ns, 3.0V, LL K6T4008U1C-GF70 K6T4008U1C-GF85 K6T4008U1C-GF10 K6T4008U1C-VF70 K6T4008U1C-VF85 K6T4008U1C-VF10 K6T4008U1C-MF70 K6T4008U1C-MF85 K6T4008U1C-MF10 K6T4008U1C-TF70 K6T4008U1C-TF85 K6T4008U1C-TF10 K6T4008U1C-YF70 K6T4008U1C-YF85 K6T4008U1C-YF10 32-SOP, 70ns, 3.0V, LL 32-SOP, 85ns, 3.0V, LL 32-SOP, 100ns, 3.0V, LL 32-TSOP2-F, 70ns, 3.0V, LL 32-TSOP2-F, 85ns, 3.0V, LL 32-TSOP2-F, 100ns, 3.0V, LL 32-TSOP2-R, 70ns, 3.0V, LL 32-TSOP2-R, 85ns, 3.0V, LL 32-TSOP2-R, 100ns, 3.0V, LL 32-TSOP1-F, 70ns, 3.0V, LL 32-TSOP1-F, 85ns, 3.0V, LL 32-TSOP1-F, 100ns, 3.0V, LL 32-sTSOP1-F, 70ns, 3.0V, LL 32-sTSOP1-F, 85ns, 3.0V, LL 32-sTSOP1-F, 100ns, 3.0V, LL FUNCTIONAL DESCRIPTION CS OE WE 1) 1) I/O Mode Power H X X High-Z Deselected Standby L H H High-Z Output Disabled Active L L H Dout Read Active L X1) L Din Write Active 1. X means don′t care (Must be in low or high state) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol Ratings Unit Remark VIN,VOUT -0.5 to VCC+0.5 V - VCC -0.3 to 4.6 V - PD 1.0 W - TSTG -65 to 150 °C - 0 to 70 °C K6T4008V1C-L, K6T4008U1C-L -40 to 85 °C K6T4008V1C-P, K6T4008U1C-P TA 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3 Revision 1.0 January 1999 K6T4008V1C, K6T4008U1C Family CMOS SRAM RECOMMENDED DC OPERATING CONDITIONS1) Item Symbol Product Min Typ Max Unit Supply voltage Vcc K6T4008V1C Family K6T4008U1C Family 3.0 2.7 3.3 3.0 3.6 3.3 V Ground Vss All Family 0 0 0 V Input high voltage VIH K6T4008V1C, K6T4008U1C Family 2.2 - Vcc+0.32) V Input low voltage VIL K6T4008V1C, K6T4008U1C Family - 0.6 V -0.3 3) Note: 1. Commercial Product : TA=0 to 70°C, otherwise specified Industrial Product : TA=-40 to 85°C, otherwise specified 2. Overshoot : VCC+2.0V in case of pulse width ≤ 30ns 3. Undershoot : -2.0V in case of pulse width ≤ 30ns 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f=1MHz, TA=25°C) Item Symbol Test Condition Min Max Unit Input capacitance CIN VIN=0V - 8 pF Input/Output capacitance CIO VIO=0V - 10 pF 1. Capacitance is sampled, not 100% tested DC AND OPERATING CHARACTERISTICS Min Typ Max Unit Input leakage current Item ILI VIN=Vss to Vcc -1 - 1 µA Output leakage current ILO CS=VIH or OE=VIH or WE=VIL VIO=Vss to Vcc -1 - 1 µA Operating power supply current Average operating current Symbol Test Conditions ICC IIO=0mA, CS=VIL, VIN=VIL or V IH, Read - - 4 mA ICC1 Cycle time=1µs, 100% duty, IIO=0mA CS≤0.2V,VIN≤0.2V or V IN≥Vcc-0.2V - - 4 mA ICC2 Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN =VIH or VIL - - 30 mA Output low voltage VOL IOL=2.1mA - - 0.4 V Output high voltage VOH IOH=-1.0mA 2.2 - - V Standby Current(TTL) ISB CS=VIH, Other inputs = V IL or VIH - - 0.3 mA Standby Current (CMOS) ISB1 CS≥Vcc-0.2V, Other inputs=0~Vcc - - 151) µA 1. Industrial product = 20µA 4 Revision 1.0 January 1999 K6T4008V1C, K6T4008U1C Family CMOS SRAM AC OPERATING CONDITIONS TEST CONDITIONS(Test Load and Input/Output Reference) Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage:1.5V Output load(see right): CL=100pF+1TTL CL1)=30pF+1TTL CL1) 1. Including scope and jig capacitance 1. 70ns product AC CHARACTERISTICS (K6T4008V1C Family: Vcc=3.0~3.6V, K6T4008U1C Family: Vcc=2.7~3.3V Commercial product:: T A=0 to 70°C, Industrial product: TA=-40 to 85°C) Speed Bins Parameter List Symbol Write 85ns Units 100ns Min Max Min Max Min Max tRC 70 - 85 - 100 - ns Address access time tAA - 70 - 85 - 100 ns Chip select to output tCO - 70 - 85 - 100 ns Output enable to valid output tOE - 35 - 40 - 50 ns Chip select to low-Z output tLZ 10 - 10 - 10 - ns Output enable to low-Z output tOLZ 5 - 5 - 5 - ns Chip disable to high-Z output tHZ 0 25 0 25 0 30 ns Output disable to high-Z output tOHZ 0 25 0 25 0 30 ns Output hold from address change tOH 10 - 10 - 15 - ns Write cycle time tWC 70 - 85 - 100 - ns Chip select to end of write tCW 60 - 70 - 80 - ns Address set-up time tAS 0 - 0 - 0 - ns Address valid to end of write tAW 60 - 70 - 80 - ns Write pulse width tWP 55 - 55 - 70 - ns Write recovery time tWR 0 - 0 - 0 - ns Write to output high-Z tWHZ 0 25 0 25 0 30 ns Data to write time overlap tDW 30 - 35 - 40 - ns Data hold from write time tDH 0 - 0 - 0 - ns End write to output low-Z tOW 5 - 5 - 5 - ns Read cycle time Read 70ns DATA RETENTION CHARACTERISTICS Item Symbol Test Condition Vcc for data retention VDR CS≥Vcc-0.2V Data retention current IDR Vcc=3.0V, CS≥Vcc-0.2V Data retention set-up time tSDR Recovery time tRDR See data retention waveform Min Typ Max Unit 2.0 - 3.6 V - 0.5 0 - - 5 - - 15 1) µA ms 1. Industrial product = 20µA 5 Revision 1.0 January 1999 K6T4008V1C, K6T4008U1C Family CMOS SRAM TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL , WE=VIH) tRC Address tAA tOH Data Out Data Valid Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tOH tAA tCO1 CS tHZ tOE OE Data out High-Z tOLZ tLZ tOHZ Data Valid NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 6 Revision 1.0 January 1999 K6T4008V1C, K6T4008U1C Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tCW(2) tWR(4) CS tAW tWP(1) WE tAS(3) tDW tDH Data Valid Data in tWHZ Data out tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled) tWC Address tAS(3) tCW(2) tWR(4) CS tAW tWP(1) WE tDW Data in Data out tDH Data Valid High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write to the end of write. 2. t CW is measured from the CS going low to end of write. 3. t AS is measured from the address valid to the beginning of write. 4. t WR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. DATA RETENTION WAVE FORM CS controlled VCC tSDR Data Retention Mode tRDR 3.0/2.7V 2.2V VDR CS≥VCC - 0.2V CS GND 7 Revision 1.0 January 1999 K6T4008V1C, K6T4008U1C Family CMOS SRAM PACKAGE DIMENSIONS Units: millimeters(inches) 32 PIN PLASTIC SMALL OUTLINE PACKAGE (525mil) 0~8° #17 14.12±0.30 0.556±0.012 #1 11.43±0.20 0.450±0.008 #16 2.74±0.20 0.108±0.008 3.00 0.118 MAX 20.87 0.822 MAX 20.47±0.20 0.806±0.008 0.20 +0.10 -0.05 0.008+0.004 -0.002 13.34 0.525 #32 0.80±0.20 0.031±0.008 0.10 MAX 0.004 MAX ( 0.71 ) 0.028 +0.100 -0.050 +0.004 0.016 -0.002 0.41 1.27 0.050 0.05 MIN 0.002 8 Revision 1.0 January 1999 K6T4008V1C, K6T4008U1C Family CMOS SRAM PACKAGE DIMENSIONS Units: millimeters(inches) 32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F) +0.10 -0.05 0.008+0.004 -0.002 0.20 20.00±0.20 0.787±0.008 #1 #32 8.40 0.331MAX 0.50 0.0197 #17 #16 0.25 0.010 TYP 0.25 ) 0.010 8.00 0.315 ( 0.05 0.002 MIN 1.00±0.10 0.039±0.004 1.20 0.047MAX 18.40±0.10 0.724±0.004 +0.10 -0.05 0.006+0.004 -0.002 0~8° 0.45 ~0.75 0.018 ~0.030 ( 0.10 MAX 0.004MAX 0.15 0.50 ) 0.020 32 PIN SMALLER THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F) +0.10 -0.05 0.008+0.004 -0.002 0.20 13.40±0.10 0.528±0.008 #1 #32 8.40 0.331 MAX #16 0.25 0.010 TYP #17 1.00±0.10 0.039±0.004 1.20 0.047 MAX 11.80±0.10 0.465±0.004 +0.10 -0.05 0.006+0.004 -0.002 0.05 0.002 MIN 0.15 0~8° 0.45 ~0.75 0.018 ~0.030 ( 9 1.10 MAX 0.004 MAX 0.50 0.0197 0.25 ) 0.010 8.00 0.315 ( 0.50 ) 0.020 Revision 1.0 January 1999 K6T4008V1C, K6T4008U1C Family CMOS SRAM PACKAGE DIMENSIONS Units: millimeters(inches) 32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F) 0.25 ( 0.010 ) #32 0~8° #17 11.76±0.20 0.463±0.008 #1 10.16 0.400 0.45~0.75 0.018 ~ 0.030 #16 21.35 0.841 MAX 1.00±0.10 0.039±0.004 1.20 0.047 MAX 20.95±0.10 0.825±0.004 ( 0.15 +0.10 -0.05 0.006 +0.004 -0.002 0.50 ) 0.020 0.10 MAX 0.004 MAX ( 0.95 ) 0.037 0.40±0.10 0.016±0.004 0.05 MIN 0.002 1.27 0.050 32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R) 0~8° 0.25 ( ) 0.010 #1 #16 11.76±0.20 0.463±0.008 #32 10.16 0.400 0.45 ~0.75 0.018 ~ 0.030 #17 21.35 0.841 MAX 1.00±0.10 0.039±0.004 +0.10 -0.05 0.006 +0.004 -0.002 0.15 ( 0.50 ) 0.020 1.20 0.047 MAX 20.95±0.10 0.825±0.004 0.10 MAX 0.004 MAX ( 0.95 ) 0.037 0.40±0.10 0.016±0.004 1.27 0.050 0.05 MIN 0.002 10 Revision 1.0 January 1999