HD74LVC1G57 Configurable Multiple–Function Gate REJ03D0011–0300Z Rev.3.00 Jun. 29, 2004 Description The HD74LVC1G57 has configurable multiple–function gate in a 6-pin package. The Output state is determined by eight patterns of 3–bit input. The user can choose the logic functions AND, NAND, NOR, EX–NOR. Low voltage and high-speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life. Features • The basic gate function is lined up as renesas uni logic series. • Supply voltage range: 1.65 to 5.5 V Operating temperature range: –40 to +85°C • All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) • Output current: ±4 mA (@VCC = 1.65 V) ±8 mA (@VCC = 2.3 V) ±24 mA (@VCC = 3.0 V) ±32 mA (@VCC = 4.5 V) • All the logical input has hysteresis voltage for the slow transition. • Ordering Information Part Name HD74LVC1G57CPE Package Type WCSP-6 pin HD74LVC1G57CLE Package Code Package Abbreviation TBS-6V CP TBS-6AV CL Article Indication Marking Year code Month code KRYM Rev.3.00 Jun. 29, 2004 page 1 of 1 Taping Abbreviation (Quantity) E (3,000 pcs/reel) HD74LVC1G57 Function Table Inputs IN2 Output IN1 IN0 Y L L L H L L H L L H L H L H H L H L L L H L H L H H L H H H H H H: High level L: Low level Pin Arrangement Height 0.5 mm 0.5 mm pitch 0.17 mm 6–Ball (CP) IN0 0.23 mm 6–Ball (CL) 3 4 Y GND 2 5 VCC IN1 1 6 (Bottom view) 1.4 mm 0.9 mm Pin#1 INDEX IN2 (Top view) Logic Diagram IN0 Y IN1 IN2 Rev.3.00 Jun. 29, 2004 page 2 of 9 HD74LVC1G57 Function Selection Table Logic Function Figure No. 2–input AND 1 2–input AND with both inputs inverted 4 2–input NAND with one input inverted 2, 3 2–input OR with one input inverted 2, 3 2–input NOR 4 2–input NOR with both inputs inverted 1 2–input EX–NOR 5 Logic Configurations VCC A B A B Y A 1 (IN1) (IN2) 6 B A B 2 (GND) (VCC) 5 Y 3 (IN0) (Y) 4 VCC A B Y Figure 1. 2–inputs AND Gate Y A 1 (IN1) (IN2) 6 B 2 (GND) (VCC) 5 Y 3 (IN0) (Y) 4 Y Figure 2. 2–inputs NAND Gate with A input inverted VCC 1 (IN1) A B Y A B Y (IN2) 6 B 2 (GND) (VCC) 5 A 3 (IN0) (Y) 4 Y Figure 3. 2–inputs NAND Gate with B input inverted A Y 1 (IN1) (IN2) 6 B 2 (GND) (VCC) 5 3 (IN0) (Y) 4 Figure 5. 2–inputs EX–NOR Gate Rev.3.00 Jun. 29, 2004 page 3 of 9 1 (IN1) A B Y A B Y (IN2) 6 Y B 2 (GND) (VCC) 5 A 3 (IN0) (Y) 4 Figure 4. 2–inputs NOR Gate VCC A B VCC Y HD74LVC1G57 Absolute Maximum Ratings Item Symbol Supply voltage range Input voltage range *1 Output voltage range *1, 2 Ratings Unit VCC –0.5 to 6.5 VI –0.5 to 6.5 V VO –0.5 to VCC + 0.5 V Test Conditions V Output : H or L –0.5 to 6.5 VCC : OFF Input clamp current IIK –50 mA VI < 0 Output clamp current IOK –50 mA VO < 0 Continuous output current IO ±50 mA VO = 0 to VCC Continuous current through VCC or GND ICC or IGND ±100 mA Package Thermal impedance θja 143 °C/W 123 Storage temperature Notes: Tstg CP CL –65 to 150 °C The absolute maximum ratings are values, which must not individually be exceeded, and furthermore no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. Recommended Operating Conditions Item Symbol Min Max Unit Conditions Supply voltage range VCC 1.65 5.5 V Input voltage range VI 0 5.5 V Output voltage range VO 0 VCC V Output current IOL — 4 mA — 8 VCC = 2.3 V — 16 VCC = 3.0 V — 24 — 32 VCC = 4.5 V — –4 VCC = 1.65 V — –8 VCC = 2.3 V — –16 VCC = 3.0 V — –24 — –32 0 20 0 10 VCC = 3.0 to 3.6 V 0 5 VCC = 4.5 to 5.5 V –40 85 IOH Input transition rise or fall rate Operating free-air temperature ∆t / ∆v Ta Note: Unused or floating inputs must be held high or low. Rev.3.00 Jun. 29, 2004 page 4 of 9 VCC = 1.65 V VCC = 4.5 V ns / V °C VCC = 1.65 to 1.95 V, 2.3 to 2.7 V HD74LVC1G57 Electrical Characteristics Ta = –40 to 85°C Item Threshold voltage Symbol VT + VT– ∆VT Output voltage VOH VOL VCC (V) Min Typ Max 1.8 0.8 — 1.4 2.5 1.2 — 1.7 3.3 1.6 — 2.3 5.0 2.3 — 3.0 1.8 0.4 — 0.7 2.5 0.6 — 1.0 3.3 0.9 — 1.4 5.0 1.5 — 2.0 1.8 0.4 — 0.7 2.5 0.4 — 0.8 3.3 0.4 — 0.9 5.0 0.4 — 1.0 1.65 to 5.5 VCC–0.1 — — 1.65 1.2 — — Unit Test condition V V IOH = –100 µA IOH = –4 mA 2.3 1.9 — — IOH = –8 mA 3.0 2.4 — — IOH = –16 mA 2.3 — — IOH = –24 mA 4.5 3.8 — — IOH = –32 mA 1.65 to 5.5 — — 0.1 IOL = 100 µA 1.65 — — 0.45 IOL = 4 mA 2.3 — — 0.3 IOL = 8 mA 3.0 — — 0.4 IOL = 16 mA 0.55 IOL = 24 mA 4.5 — — 0.55 IOL = 32 mA Input current IIN 0 to 5.5 — — ±5 µA VIN = 5.5 V or GND Quiescent supply current ICC 5.5 — — 10 µA VIN = VCC or GND, IO = 0 ∆ICC 3 to 5.5 — — 500 Output leakage current IOFF 0 — — ±10 µA VIN or VO = 0 to 5.5 V Input capacitance CIN 3.3 — 3.5 — pF VIN = VCC or GND One input at VCC–0.6 V, Other input at VCC or GND Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. Rev.3.00 Jun. 29, 2004 page 5 of 9 HD74LVC1G57 Switching Characteristics VCC = 1.8 ± 0.15 V Ta = –40 to 85°C Item Propagation delay time Symbol tPLH tPHL Min 3.2 FROM Unit Max 14.4 ns Test Conditions (Input) IN CL = 30 pF, RL = 1.0 kΩ TO (Output) Y VCC = 2.5 ± 0.2 V Ta = –40 to 85°C Item Propagation delay time Symbol Min 2.0 tPLH tPHL Unit Max 8.3 ns Test Conditions FROM TO (Input) (Output) IN CL = 30 pF, RL = 500 Ω Y VCC = 3.3 ± 0.3 V Ta = –40 to 85°C Item Propagation delay time Symbol Min 1.5 tPLH tPHL Unit Max 6.3 ns Test Conditions FROM TO (Input) (Output) IN CL = 50 pF, RL = 500 Ω Y VCC = 5.0 ± 0.5 V Ta = –40 to 85°C Item Propagation delay time Symbol tPLH tPHL Min 1.1 Unit Max 5.1 ns Test Conditions CL = 50 pF, RL = 500 Ω FROM TO (Input) (Output) IN Y Operating Characteristics Ta = 25°C Item Symbol Power dissipation capacitance CPD VCC (V) Min Typ Max 1.8 — 20 — 2.5 — 20 — 3.3 — 21 — 5.0 — 22 — Unit pF Test Circuit Measurement point From Output CL * RL Note: CL includes probe and jig capacitance. Rev.3.00 Jun. 29, 2004 page 6 of 9 Test Conditions f = 10 MHz HD74LVC1G57 • Waveforms tr tf Vref Input VI 90% 90% Vref 10% 10% t PLH GND t PHL VOH In phase output Vref Vref VOL VOH Vref Out of phase output Vref t PHL VOL t PLH INPUTS VCC (V) Vref CL RL ≤ 2 ns VCC / 2 30 pF 1.0 kΩ ≤ 2 ns VCC / 2 30 pF 500 Ω 3 V ≤ 2.5 ns 1.5 V 50 pF 500 Ω VCC ≤ 2.5 ns VCC / 2 50 pF 500 Ω VI tr / tf 1.8±0.15 VCC 2.5±0.2 VCC 3.3±0.3 5.0±0.5 Notes: 1. Input waveform : PRR ≤ 10 MHz, Zo = 50 Ω. 2. The output are measured one at a time with one transition per measurement. Rev.3.00 Jun. 29, 2004 page 7 of 9 HD74LVC1G57 Package Dimensions TBS-6V EIAJ Package Code Mass (g) 0.001 JEDEC Code Lead Material D e ZD ZE C E B e B A Pin #1 index area 1 2 C // y1 C 6×φb φx M C A B φx M C C Symbol Rev.3.00 Jun. 29, 2004 page 8 of 9 A A2 y C A1 Seating plane A A1 A2 b D E e x y y1 ZD ZE Dimension in Millimeters Min Typ Max 0.50 0.10 0.15 0.35 0.19 0.15 0.17 0.90 1.40 0.50 0.05 0.05 0.20 0.20 0.20 HD74LVC1G57 TBS-6AV EIAJ Package Code Mass (g) 0.001 JEDEC Code Lead Material D e ZD ZE C E B e B A Pin #1 index area 1 2 C // y1 C 6×φb φx M C A B φx M C C Symbol *Reference value. Rev.3.00 Jun. 29, 2004 page 9 of 9 A A2 y C A1 Seating plane A A1 A2 b D E e x y y1 ZD ZE Dimension in Millimeters Min Nom Max 0.50 0.155 0.185 (0.315)* 0.25 0.20 0.90 1.40 0.50 0.05 0.05 0.20 0.20 0.20 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. 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