AS4C128M16D3B-12BCN
Revision History
2Gb AS4C128M16D3B-12BCN - 96 ball FBGA PACKAGE
Revision
Rev 1.0
Details
Preliminary datasheet
Date
Mar. 2016
Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice
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AS4C128M16D3B-12BCN
Specifications
Features
-
Density : 2G bits
Organization :
-
- 16M words x 16 bits x 8 banks
- Package :
- 96-ball FBGA - Lead-free (RoHS
compliant) and Halogen-free
Power supply : VDD, VDDQ = 1.5V ± 0.075V
Data rate : 1600Mbps
1KB page size for X8 / 2KB page size
-
- Row address: A0 to A13
- Column address: A0 to A9
-
-
-
Eight internal banks for concurrent operation
Burst lengths (BL) : 8 and 4 with Burst Chop (BC)
Burst type (BT) :
- Sequential (8, 4 with BC)
- Interleave (8, 4 with BC)
CAS Latency (CL) : 5, 6, 7, 8, 9, 10, 11
CAS Write Latency (CWL) : 5, 6, 7, 8
Precharge : auto precharge option for each burst access
Driver strength : RZQ/7, RZQ/6 (RZQ = 240 Ω)
Refresh : auto-refresh, self-refresh
Refresh cycles :
- Average refresh period
7.8 μs at 0°C ≤ Tc ≤ +85°C
3.9 μs at +85°C < Tc ≤ +95°C
Operating case temperature range
- Comercial Tc = 0°C to +95°C
-
-
Double-data-rate architecture; two data transfers per clock cycle
The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
Bi-directional differential data strobe (DQS and DQS) is transmitted/
received with data for capturing data at the receiver
DQS is edge-aligned with data for READs; center-aligned with data
for WRITEs
Differential clock inputs (CK and CK)
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data and data mask
referenced to both edges of DQS
Data mask (DM) for write data
Posted CAS by programmable additive latency for better command
and data bus efficiency
On-Die Termination (ODT) for better signal quality
- Synchronous ODT
- Dynamic ODT
- Asynchronous ODT
Multi Purpose Register (MPR) for pre-defined pattern read out
ZQ calibration for DQ drive and ODT
RESET pin for Power-up sequence and reset function
SRT range : Normal/extended
Programmable Output driver impedance control
Table 1. Ordering Information
Part Number
Org
AS4C128M16D3B-12BCN
128Mx16
Temperature
Commercial(Extended)
0°C to 95°C
MaxClock (MHz)
Package
800
96-ball FBGA
Table 2. Speed Grade Information
Speed Grade
Clock Frequency
CAS Latency
tRCD (ns)
tRP (ns)
DDR3-1600
800MHz
11
13.75
13.75
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AS4C128M16D3B-12BCN
Pin Configurations
96-ball FBGA (x16 configuration)
1
2
3
A
VDDQ
DQU5
DQU7
B
VSSQ
VDD
VSS
C
VDDQ
DQU3
DQU1
D
VSSQ
VDDQ
DMU
E
VSS
VSSQ
F
VDDQ
DQL2
G
VSSQ
DQL6
DQSL
H
VREFDQ
VDDQ
DQL4
J
NC
VSS
RAS
K
ODT
VDD
L
NC
CS
M
VSS
BA0
N
VDD
A3
P
VSS
A5
R
VDD
A7
A9
T
VSS
RESET
A13
4
5
6
7
8
DQU4
VDDQ
VSS
A
DQSU
DQU6
VSSQ
B
DQSU
DQU2
VDDQ
C
DQU0
VSSQ
VDD
D
DQL0
DML
VSSQ
VDDQ
E
DQSL
DQL1
DQL3
VSSQ
F
VDD
VSS
VSSQ
G
DQL7
DQL5
VDDQ
H
CK
VSS
NC
J
CAS
CK
VDD
CKE
K
WE
A10/AP
ZQ
NC
L
BA2
NC
VREFCA
VSS
M
A0
A12/BC
BA1
VDD
N
A2
A1
A4
VSS
P
A11
A6
VDD
R
NC
A8
VSS
T
1
2
3
9
4
5
6
7
8
9
A
B
Ball Locations
C
D
Populated ball
E
F
Ball not populated
G
H
J
Top view
K
(See the balls through the package)
L
M
N
P
R
T
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AS4C128M16D3B-12BCN
Signal Pin Description
Pin
Type
Function
CK, CK
Input
Clock : CK and CK are differential clock inputs. All address and control input signals are sampled on
the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to
the crossings of CK and CK
CKE
Input
Clock Enable : CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input
buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (Row Active in any bank). CKE is asynchronous for self
refresh exit. After VREFCA has become stable during the power on and initialization sequence, it must
be maintained during all operations (including Self-Refresh). CKE must be maintained high throughout
read and write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during powerdown. Input buffers, excluding CKE, are disabled during Self -Refresh.
CS
Input
Chip Select : All commands are masked when CS is registered HIGH. CS provides for external Rank
selection on systems with multiple Ranks. CS is considered part of the command code.
ODT
Input
On Die Termination : ODT (registered HIGH) enables termination resistance internal to the DDR3
SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS, NU/TDQS
(When TDQS is enabled via Mode Register A11=1 in MR1) signal for x8 configurations. The ODT pin
will be ignored if the Mode Register (MR1) is programmed to disable ODT.
RAS, CAS, WE
Input
Command Inputs : RAS, CAS and WE (along with CS) define the command being entered.
DM
(DMU), (DML)
Input
BA0 - BA2
Input
Bank Address Inputs : BA0 - BA2 define to which bank an Active, Read, Write or Precharge command
is being applied. Bank address also determines which mode register is to be accessed during a MRS
cycle.
A0 - A14
Input
Address Inputs : Provided the row address for Active commands and the column address for Read /
Write commands to select one location out of the memory array in the respective bank. (A10/AP and
A12/BC have additional functions, see below)
The address inputs also provide the op-code during Mode Register Set commands.
A10 / AP
Input
Autoprecharge : A10 is sampled during Read/Write commands to determine whether Autoprecharge
should be performed to the accessed bank after the Read/Write operation. (HIGH:Autoprecharge;
LOW: No Autoprecharge)A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). if only one bank is to be precharged,
the bank is selected by bank addresses.
A12 / BC
Input
Burst Chop : A12 is sampled during Read and Write commands to determine if burst chop(on-the-fly)
will be performed. (HIGH : no burst chop, LOW : burst chopped). See command truth table for details.
RESET
Input
Active Low Asynchronous Reset : Reset is active when RESET is LOW, and inactive when RESET
is HIGH. RESET must be HIGH during normal operation. RESET is a CMOS rail to rail signal with DC
high and low at 80% and 20% of VDD, i.e. 1.20V for DC high and 0.30V for DC low.
DQ
Input/
Output
Data Input/ Output : Bi-directional data bus.
DQS, DQS
Input/
Output
Data Strobe : Output with read data, input with write data. Edge-aligned with read data, centered in
write data. For the x16, DQSL corresponds to the data on DQL0-DQL7; DQSU corresponds to the data
on DQU0-DQU7. The data strobe DQS, DQSL and DQSU are paired with differential signals DQS,
DQSL and DQSU, respectively, to provide differential pair signaling to the system during reads and
writes. DDR3 SDRAM supports differential data strobe only and does not support single-ended.
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Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is sampled
HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS.
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AS4C128M16D3B-12BCN
Pin
Type
Function
TDQS, TDQS
Output
Termination Data Strobe : TDQS/TDQS is applicable for x8 DRAMs only. When enabled via Mode
Register A11=1 in MR1, DRAM will enable the same termination resistance function on TDQS/TDQS
that is applied to DQS/DQS. When disabled via mode register A11=0 in MR1, DM/TDQS will provide
the data mask function and TDQS is not used. x16 DRAMs must disable the TDQS function via mode
register A11 = 0 in MR1.
NC
No Connect: No internal electrical connection is present.
VDDQ
Supply
DQ power supply: 1.5V +/- 0.075V
VSSQ
Supply
DQ Ground
VDD
Supply
Power Supply: 1.5V +/- 0.075V
VSS
Supply
Ground
VREFDQ
Supply
Reference Voltage for DQ
VREFCA
Supply
Reference Voltage for CA
ZQ
Supply
Reference Pin for ZQ calibration
NOTE : Input only pins ( BA0-BA2, A0-A14, RAS, CAS, WE, CS, CKE, ODT and RESET ) do not supply termination.
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AS4C128M16D3B-12BCN
Simplified State Diagram
CKE L
Power
applied
Power
on
Reset
procedure
MRS, MPR,
write
leveling
Initialization
Self
refresh
SRE
ZQCL
From any
state
RESET
ZQ
calibration
MRS
SRX
REF
ZQCL/ZQCS
Idle
Refreshing
PDE
ACT
PDX
Active
powerdown
Precharge
powerdown
Activating
PDX
CKE L
CKE L
PDE
Bank
active
WRITE
WRITE
READ
WRITE AP
Writing
READ
READ AP
READ
Reading
WRITE
WRITE AP
READ AP
WRITE AP
READ AP
PRE, PREA
Writing
PRE, PREA
PRE, PREA
Precharging
Reading
Automatic
sequence
Command
sequence
ACT = ACTIVATE
MPR = Multipurpose register
MRS = Mode register set
PDE = Power-down entry
PDX = Power-down exit
PRE = PRECHARGE
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PREA = PRECHARGE ALL
READ = RD, RDS4, RDS8
READ AP = RDAP, RDAPS4, RDAPS8
REF = REFRESH
RESET = START RESET PROCEDURE
SRE = Self refresh entry
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SRX = Self refresh exit
WRITE = WR, WRS4, WRS8
WRITE AP = WRAP, WRAPS4, WRAPS8
ZQCL = ZQ LONG CALIBRATION
ZQCS = ZQ SHORT CALIBRATION
Rev.1.0 Mar. 2016
AS4C128M16D3B-12BCN
Basic Functionality
Read and write operation to the DDR3 SDRAM are burst oriented, start at a selected location, and continue for a burst
length of four or eight in a programmed sequence. Operation begins with the registration of an Active command, which
is then followed by a Read or Write command. The address bits registered coincident with the Active command are used
to select the bank and row to be accessed (BA0-BA2 select the bank; A0-A14 select the row).The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst operation,
determine if the auto precharge command is to be issued (via A10/AP), and the select BC4 or BL8 mode “on the fly” (via
A12) if enabled in the mode register.
Prior to normal operation, the DDR3 SDRAM must be powered up and initialized in a predefined manner. The following
sections provide detailed information covering device reset and initialization, register definition, command descriptions
and device operation.
Power-up and Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain RESET below 0.2 x VDD (all other inputs may be undefined). RESET needs to
be maintained for minimum 200μs with stable power. CKE is pulled “Low” anytime before RESET being de-asserted
(min. time 10ns). The power voltage ramp time between 300mV to VDD min must be no longer than 200ms; and during the ramp, VDD > VDDQ and VDD -VDDQ < 0.3 volts.
- VDD and VDDQ are driven from a single power converter output, AND
- The voltage levels on all pins other than VDD,VDDQ,VSS,VSSQ must be less than or equal to VDDQ and VDD on
one side and must be larger than or equal to VSSQ and VSS on the other side. In addition, VTT is limited to 0.95V
max once power ramp is finished, AND
- Vref tracks VDDQ/2.
or
- Apply VDD without any slope reversal before or at the same time as VDDQ.
- Apply VDDQ without any slope reversal before or at the same time as VTT & Vref.
- The voltage levels on all pins other than VDD,VDDQ,VSS,VSSQ must be less than or equal to VDDQ and VDD on
one side and must be larger than or equal to VSSQ and VSS on the other side.
2. After RESET is de-asserted, wait for another 500us until CKE becomes active. During this time, the DRAM will start
internal initialization; this will bedone independently of external clocks.
3. Clocks (CK, CK) need to be started and stabilized for at least 10ns or 5tCK (which is larger) before CKE goes active.
Since CKE is a synchronous signal, the corresponding setup time to clock (tIS) must be met. Also a NOP or Deselect
command must be registered (with tIS set up time to clock) before CKE goes active. Once the CKE registered “High”
after Reset, CKE needs to be continuously registered “High” until the initialization sequenceis finished, including expiration of tDLLK and tZQinit.
4. The DDR3 SDRAM keeps its on-die termination in high-impedance state as long as RESET is asserted. Further, the
SDRAM keeps its on-die termination in high impedance state after RESET deassertion until CKE is registered HIGH.
The ODT input signal may be in undefined state until tIS before CKE is registered HIGH. When CKE is registered
HIGH, the ODT input signal may be statically held at either LOW or HIGH. If RTT_NOM is to be enabled in MR1 and
the on-die termination is required to remain in the high impedance state, the ODT input signal must be statically held
LOW. In all cases, the ODT input signal remains static until the power up initialization sequence is finished, including
the expiration of tDLLK and tZQinit.
5. After CKE is registered high, wait minimum of Reset CKE Exit time, tXPR, before issuing the first MRS command to
load mode register.(tXPR=Max(tXS, 5tCK)]
6. Issue MRS Command to load MR2 with all application settings. (To issue MRS command for MR2, provide “Low” to
BA0 and BA2, “High” to BA1.)
7. Issue MRS Command to load MR3 with all application settings. (To issue MRS command for MR3, provide “Low” to
BA2, “High” to BA0 and BA1.)
8. Issue MRS Command to load MR1 with all application settings and DLL enabled. (To issue ”DLL Enable” command,
provide “Low” to A0, ”High” to BA0 and “Low” to BA1-BA2)
9. Issue MRS Command to load MR0 with all application settings and “DLL reset”. (To issue DLL reset command, provide “High” to A8 and “Low” to BA0-2).
10. Issue ZQCL command to starting ZQ calibration.
11. Wait for both tDLLK and tZQ init completed.
12. The DDR3 SDRAM is now ready for normal operation.
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AS4C128M16D3B-12BCN
Ta
.
Tb
Tc
.
Td
.
Te
.
Tf
.
Tg
.
Th
.
Ti
.
Tj
.
Tk
CK,CK
t CKSRX
VDD /VDDQ
200 us
500 us
RESET
10 ns
t IS
CKE
t XPR **
CMD
*)
BA[2:0]
t ZQinit
t MOD
t MRD
t IS
t MRD
t MRD
t DLLK
MRS
MRS
MRS
MRS
MR2
MR3
MR1
MR0
ZQCL
1)
VALID
VALID
t IS
t IS
Static LOW in case RTT_Nom is eanbled at time Tg, otherwise static HIGH or LOW
ODT
VALID
DRAM_RTT
1) From time point ‘Td’ until ‘Tk’, NOP or DES commands must be applied between MRS and ZQCL commands
Reset and Initialization with Stable Power
The following sequence is required for /RESET at no power interruption initialization.
1. Assert /RESET below 0.2 x VDD anytime when reset is needed (all other inputs may be undefined). /RESET needs to
be maintained for minimum 100ns. CKE is pulled low before /RESET being de-asserted (minimum time 10ns).
2. Follow Power-Up Initialization Sequence steps 2 to 11.
3. The reset sequence is now completed; DDR3 SDRAM is ready for normal operation.
Ta
.
Tb
Tc
.
Td
.
Te
.
Tf
.
Tg
.
Th
.
Ti
.
Tj
.
Tk
.
CK,CK
t CKSRX
VDD /V DDQ
100 ns
500 us
RESET
10 ns
tIS
CKE
t XPR
CMD
1)
BA[2:0]
t ZQin
t MOD
t MRD
tIS
t MRD
t MRD
tDLLK
MRS
MRS
MRS
MRS
MR2
MR3
MR1
MR0
ZQCL
1)
VALID
VALID
t IS
ODT
Static LOW in case RTT_Nom is eanbled at time Tg, otherwise static HIGH or LOW
VALID
DRAM_RTT
1) From time point ‘Td’ until ‘Tk’, NOP or DES commands must be applied between MRS and ZQCL commands
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AS4C128M16D3B-12BCN
Mode Register MR0
The Mode Register MR0 stores the data for controlling various operating modes of DDR3 SDRAM. It controls burst length, read burst type, CAS latency, test mode, DLL reset, WR and DLL control for precharge
power-down, which include various vendor specific options to make DDR3 SDRAM useful for various applications. The mode register is written by asserting low on CS, RAS, CAS, WE, BA0, BA1 and BA2, while
controlling the states of address pins according to the table below.
BA2
BA1
0*1
0
BA0 A 14- A 13
0
0*1
PPD
A11
A10
A9
WR
A8
A7
DLL
TM
A6
A5
A4
CAS Latency
A3
A2
RBT
CL
A1
A0
Address Field
Mode Register 0
BL
A8
DLL Reset
A7
mode
A3
Read Burst Type
A1
A0
BL
0
No
0
Normal
0
Nibble Sequential
0
0
8 (Fixed)
1
Yes
1
Test
1
Interleave
0
1
4 or 8(on the fly)
1
0
4 (Fixed)
1
1
Reserved
A4
A2
DLL Control for
Precharge PD
A12
A12
Write recovery for autoprecharge
A10
A9
WR(cycles)
Reserved
CAS Latency
A6
A5
Latency
0
Slow exit (DLL off)
A11
1
Fast exit (DLL on)
0
0
0
0
0
0
0
0
0
1
*2
5
0
0
1
0
5
0
1
0
6*2
0
1
0
0
6
0
1
1
0
7
1
0
0
0
8
1
0
1
0
9
Reserved
BA1
BA0
MRS mode
0
1
1
7*2
0
0
MR0
1
0
0
8*2
1
0
1
10*2
1
1
0
0
10
1
1
0
12*2
1
1
1
0
11
1
*2
0
0
0
1
R e s e r v e d
0
0
1
1
Reserved
0
1
0
1
Reserved
0
1
MR1
1
0
MR2
1
1
MR3
1
1
14
*1 : BA2, A13 and A14 are reserved for future use and must be programmed to 0 during MRS.
*2 : WR(write recovery for autoprecharge)min in clock cycles is calculated by dividing tWR(in ns) by tCK(in ns) and rounding up to the
next integer: WRmin[cycles] = Roundup(tWR[ns]/tCK[ns]). The WR value in the mode register must be programmed to be equal or
larger than WRmin. The programmed WR value is used with tRP to determine tDAL.
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Mode Register MR1
The Mode Register MR1 stores the data for enabling or disabling the DLL, output driver strength, RTT_Nom
impedance, additive latency, write leveling enable, TDQS enable and Qoff.
The Mode Register 1 is written by asserting low on CS, RAS, CAS, WE, high on BA0, low on BA1 and BA2,
while controlling the states of address pins according to the table below.
BA2
BA1
0*1
0
BA0 A14- A13 A12
1
0*1
Qoff
A11
A10
A9
TDQS
0*1
Rtt_Nom
A8
A7
A6
0*1 Level
Rtt_Nom
A5
D.I.C
A9 A6 A2
A4
A3
AL
A2
Rtt_Nom
TDQS enable
0
Disabled
0
0
0
ODT disabled
1
Enabled
0
0
1
RZQ/4
0
1
0
RZQ/2
0
1
1
RZQ/6
1
0
0
RZQ/12*4
Write leveling enable
A0
D.I.C DLL
Rtt_Nom *3
A11
A7
A1
0
Disabled
1
0
1
RZQ/8*4
1
Enabled
1
1
0
Reserved
1
1
1
Reserved
Address Field
Mode Register 1
A0
DLL Enable
0
Enable
1
Disable
Note : RZQ = 240 ohms
Additive Latency
A4
A3
0
0
0 (AL disabled)
0
1
CL-1
1
0
CL-2
1
1
Reserved
*2
A12
Qoff
0
Output buffer enabled
1
Output buffer disabled *2
*3: In Write leveling Mode (MR1[bit7] = 1)
with MR1[bit12] = 1, all RTT_Nom settings
are allowed; in Write Leveling Mode
(MR1[bit7] = 1) with MR1[bit12] = 0, only
RTT_Nom settings of RZQ/2, RZQ/4 and
RZQ/6 are allowed.
*4: If RTT_Nom is used during Writes,
only the values RZQ/2,RZQ/4 and RZQ/6
are allowed.
A5 A1
*2: Outputs disabled - DQs, DQSs, DQSs.
BA1
BA0
Output Driver Impedance Control
0
0
0
1
RZQ/6
RZQ/7
1
0
Reserved
1
1
Reserved
MRS mode
0
0
MR0
0
1
MR1
1
0
MR2
1
1
MR3
Note : RZQ = 240 ohms
* 1 : BA2, A8, A10, A13 and A14 are reserved for future use (RFU) and must be programmed to 0 during MRS.
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AS4C128M16D3B-12BCN
Mode Register MR2
The Mode Register MR2 stores the data for controlling refresh related features, RTT_WR impedance and
CAS write latency (CWL). The Mode Register 2 is written by asserting low on CS, RAS, CAS, WE, high on
BA1, low on BA0 and BA2, while controlling the states of address pins according to the table below.
BA2
BA1
BA 0
0*1
1
0
A7
A14 - A11
0*1
A9
Rtt_WR
A8
A7
A6
A5
A4
0*1 SRT ASR
A3
A2
A1
0*1
CWL
A0
Address Field
Mode Register 2
Self-refresh temperature range (SRT)
0
Normal operating temperature range
1
Extend temperature self-refresh (Optional)
A6
Auto Self-refresh (ASR)
0
Manual SR Reference (SRT)
1
A10 A9
A10
ASR enable (Optional)
Rtt_WR *2
0
0
Dynamic ODT off
(Write does not affect Rtt value)
0
1
RZQ/4
A5 A4 A3
CAS write Latency (CWL)
0
0
5 (tCK(avg) ≥2.5ns)
1
0
RZQ/2
0
1
1
Reserved
0
0
1
6 (2.5ns >tCK(avg) ≥1.875ns)
0
1
0
7 (1.875ns>tCK(avg) ≥ 1.5ns)
0
1
1
8 (1.5ns>tCK(avg) ≥1.25ns)
9 (1.25ns >tCK(avg) ≥1.07ns)
BA1
BA0
MRS mode
1
0
0
0
0
MR0
1
0
1 10 (1.07ns >tCK(avg) ≥0.935ns)
1
0
Reserved
1
1
Reserved
0
1
MR1
1
1
0
MR2
1
1
1
MR3
* 1 : BA2, A0 ~ A2, A8, A11 ~ A14 are RFU and must be programmed to 0 during MRS.
* 2 : The Rtt_WR value can be applied during writes even when Rtt_Nom is disabled.
During write leveling, Dynamic ODT is not available.
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AS4C128M16D3B-12BCN
Mode Register MR3
The Mode Register MR3 controls Multi Purpose Registers (MPR). The Mode Register 3 is written by asserting low on CS, RAS, CAS, WE, high on BA1 and BA0, and low on BA2 while controlling the states of
address pins according to the table below.
BA 2
BA 1
BA0
0*1
1
1
A13
A12
A11
A10
A9
A8
A7
A6
A3
A2
MPR
MPR Operation
MPR Address
BA0
MRS mode
0
0
MR0
A2
A0
MPR Loc
Address Field
Mode Register 3
A1
A0
MPR location
0
0
Predefined pattern*2
0
1
RFU
1
0
RFU
1
1
RFU
1
MR1
0
Normal operation*
1
0
MR2
1
Dataflow from MPR
MR3
A1
3
MPR
0
1
A4
0*1
BA1
1
A5
* 1 : BA2, A3 - A13 are reserved for future use (RFU) and must be programmed to 0 during MRS.
* 2 : The predefined pattern will be used for read synchronization.
* 3 : When MPR control is set for normal operation, MR3 A[2] = 0, MR3 A[1:0] will be ignored
Burst Length (MR0)
Read and write accesses to the DDR3 are burst oriented, with the burst length being programmable, as
shown in the figure MR0 Programming. The burst length determines the maximum number of column locations that can be accessed for a given read or write command. Burst length options include fixed BC4, fixed
BL8, and on the fly which allows BC4 or BL8 to be selected coincident with the registration of a read on write
command Via A12 (BC). Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.
Burst Chop
In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock cycles
earlier than for the BL8 mode. This means that the starting point for tWR and tWTR will be pulled in by two
clocks. In case of burst length being selected on the fly via A12(BC), the internal write operation starts at the
same point in time like a burst of 8 write operation. This means that during on-the-fly control, the starting
point for tWR and tWTR will not be pulled in by two clocks.
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AS4C128M16D3B-12BCN
Burst Type (MR0)
[Burst Length and Sequence]
Burst length
Operation
Starting address
(A2, A1, A0)
Sequential addressing
(decimal)
Interleave addressing
(decimal)
4 (Burst chop)
READ
000
0, 1, 2, 3, T, T, T, T
0, 1, 2, 3, T, T, T, T
8
001
1, 2, 3, 0, T, T, T, T
1, 0, 3, 2, T, T, T, T
010
2, 3, 0, 1, T, T, T, T
2, 3, 0, 1, T, T, T, T
011
3, 0, 1, 2, T, T, T, T
3, 2, 1, 0, T, T, T, T
100
4, 5, 6, 7, T, T, T, T
4, 5, 6, 7, T, T, T, T
101
5, 6, 7, 4, T, T, T, T
5, 4, 7, 6, T, T, T, T
110
6, 7, 4, 5, T, T, T, T
6, 7, 4, 5, T, T, T, T
111
7, 4, 5, 6, T, T, T, T
7, 6, 5, 4, T, T, T, T
WRITE
0VV
0, 1, 2, 3, X, X, X, X
0, 1, 2, 3, X, X, X, X
1VV
4, 5, 6, 7, X, X, X, X
4, 5, 6, 7, X, X, X, X
READ
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 0, 5, 6, 7, 4
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 0, 1, 6, 7, 4, 5
2, 3, 0, 1, 6, 7, 4, 5
011
3, 0, 1, 2, 7, 4, 5, 6
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 4, 1, 2, 3, 0
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 4, 5, 2, 3, 0, 1
6, 7, 4, 5, 2, 3, 0, 1
111
7, 4, 5, 6, 3, 0, 1, 2
7, 6, 5, 4, 3, 2, 1, 0
VVV
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
WRITE
Remark: T: Output driver for data and strobes are in high impedance.
V: A valid logic level (0 or 1), but respective buffer input ignores level on input pins.
X: Don’t Care.
Notes: 1. Page length is a function of I/O organization and column addressing
2. 0...7 bit number is value of CA [2:0] that causes this bit to be the first read during a burst.
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AS4C128M16D3B-12BCN
Command Truth Table
(a) Note 1,2,3,4 apply to the entire Command truth table
(b) Note 5 applies to all Read/Write commands.
[BA=Bank Address, RA=Row Address, CA=Column Address, BC=Burst Chop, X=Don’t care, V=Valid]
CKE
Function
WE
BA0
BA2
L
L
BA
L
H
L
L
H
X
L
H
Abbreviation
Previous
Cycle
Current
Cycle
CS
Mode Register Set
MRS
H
H
L
L
Refresh
REF
H
H
L
L
Self Refresh Entry
SRE
H
L
L
Self Refresh Exit
Single Bank Precharge
SRX
L
H
A13
A15
A12
/
BC
V
V
V
V
V
H
V
V
V
V
V
X
X
X
X
X
X
X
H
H
V
V
V
V
V
RAS CAS
A10
/
AP
A0
A9,A11
OP Code
PRE
H
H
L
L
H
L
BA
V
V
L
V
PREA
H
H
L
L
H
L
V
V
V
H
V
Bank Activate
ACT
H
H
L
L
H
H
BA
Write (Fixed BL8 or BL4)
WR
H
H
L
H
L
L
BA
RFU
V
L
CA
Write (BL4, on the Fly)
WRS4
H
H
L
H
L
L
BA
RFU
L
L
CA
Write (BL8, on the Fly)
WRS8
H
H
L
H
L
L
BA
RFU
H
L
CA
Write with Auto Precharge
(Fixed BL8 or BL4)
WRA
H
H
L
H
L
L
BA
RFU
V
H
CA
Write with Auto Precharge
(BL4, on the Fly)
WRAS4
H
H
L
H
L
L
BA
RFU
L
H
CA
Write with Auto Precharge
(BL8, on the Fly)
WRAS8
H
H
L
H
L
L
BA
RFU
H
H
CA
Precharge all Banks
Read (Fixed BL8 or BL4)
Notes
7,9,12
7,8,9,12
Row Address (RA)
RD
H
H
L
H
L
H
BA
RFU
V
L
CA
Read (BL4, on the Fly)
RDS4
H
H
L
H
L
H
BA
RFU
L
L
CA
Read (BL8, on the Fly)
RDS8
H
H
L
H
L
H
BA
RFU
H
L
CA
Read with Auto Precharge
(Fixed BL8 or BL4)
RDA
H
H
L
H
L
H
BA
RFU
V
H
CA
Read with Auto Precharge
(BL4, on the Fly)
RDAS4
H
H
L
H
L
H
BA
RFU
L
H
CA
Read with Auto Precharge
(BL8, on the Fly)
RDAS8
H
H
L
H
L
H
BA
RFU
H
H
CA
No Operation
NOP
H
H
L
H
H
H
V
V
V
V
V
10
Device Deselected
DES
H
H
H
X
X
X
X
X
X
X
X
11
ZQ calibration Long
ZQCL
H
H
L
H
H
L
X
X
X
H
X
ZQ calibration Short
ZQCS
H
H
Power Down Entry
PDE
H
L
Power Down Exit
PDX
L
H
L
H
H
L
X
X
X
L
X
L
H
H
H
V
V
V
V
V
H
X
X
X
X
X
X
X
X
L
H
H
H
V
V
V
V
V
H
X
X
X
X
X
X
X
X
6,12
6,12
Note :
1. All DDR3 SDRAM commands are defined by states of CS, RAS, CAS, WE and CKE at the rising edge of the clock. The MSB of BA, RA, and CA are
device density and configuration dependant
2. RESET is Low enable command which will be used only for asynchronous reset so must be maintained HIGH during any function.
3. Bank addresses (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register
4. “V” means “H or L (but a defined logic level)” and “X” means either “defined or undefined (like floating) logic level”
5. Burst reads or writes cannot be terminated or interrupted and Fixed/on the fly BL will be defined by MRS
6. The Power Down Mode does not perform any refresh operations.
7. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
8. Self refresh exit is asynchronous.
9. VREF(Both VREFDQ and VREFCA) must be maintained during Self Refresh operation.
10. The No Operation command (NOP) should be used in cases when the DDR3 SDRAM is in an idle or a wait state. The purpose of the No Operation
command (NOP) is to prevent the DDR3 SDRAM from registering any unwanted commands between operations. A No Operation command will not
terminate a previous operation that is still executing, such as a burst read or write cycle.
11. The Deselect command performs the same function as a No Operation command.
12. Refer to the CKE Truth Table for more detail with CKE transition
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AS4C128M16D3B-12BCN
CKE Truth Table
(a) Note 1~7 apply to the entire Command truth table
(b) CKE low is allowed only if tMRD and tMOD are satisfied
CKE
Current State
2
Previous Cycle
(N-1)
1
Command (N)
Current Cycle
(N)
3
1
Action (N) 3
Notes
14, 15
RAS, CAS, WE, CS
L
L
X
Maintain Power-Down
L
H
DESELECT or NOP
Power Down Exit
11, 14
L
L
X
Maintain Self Refresh
15, 16
L
H
DESELECT or NOP
Self Refresh Exit
8, 12, 16
Bank(s) Active
H
L
DESELECT or NOP
Active Power Down Entry
11, 13, 14
Reading
H
L
DESELECT or NOP
Power Down Entry
11, 13, 14, 17
Power Down
Self Refresh
Writing
H
L
DESELECT or NOP
Power Down Entry
11, 13, 14, 17
Precharging
H
L
DESELECT or NOP
Power Down Entry
11, 13, 14, 17
Refreshing
All Banks Idle
H
L
DESELECT or NOP
Precharge Power Down Entry
11
H
L
DESELECT or NOP
Precharge Power Down Entry
11,13, 14, 18
H
L
REFRESH
Self Refresh Entry
9, 13, 18
For more details with all signals See “Command Truth Table,” on previous page
10
Notes:
1. CKE (N) is the logic state of CKE at clock edge N; CKE (N–1) was the state of CKE at the previous clock edge.
2. Current state is defined as the state of the DDR3 SDRAM immediately prior to clock edge N
3. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N), ODT is not included here
4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document
5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh
6. CKE must be registered with the same value on tCKEmin consecutive positive clock edges. CKE must remain at the valid input level the entire time it
takes to achieve the tCKEmin clocks of registeration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period
of tIS + tCKEmin + tIH.
7. DESELECT and NOP are defined in the Command truth table
8. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXS period. Read or ODT commands
may be issued only after tXSDLL is satisfied.
9. Self Refresh mode can only be entered from the All Banks Idle state.
10. Must be a legal command as defined in the Command Truth Table.
11. Valid commands for Power Down Entry and Exit are NOP and DESELECT only.
12. Valid commands for Self Refresh Exit are NOP and DESELECT only.
13. Self Refresh can not be entered while Read or Write operations. See ‘Self-Refresh Operation” and ‘Power-Down Modes” on later section for a
detailed list of restrictions.
14. The Power Down does not perform any refresh operations.
15. “X” means “don’t care (including floating around VREF)” in Self Refresh and Power Down. It also applies to Address pins
16. VREF (Both VREFDQ and VREFCA) must be maintained during Self Refresh operation.
17. If all banks are closed at the conclusion of the read, write or precharge command, then Precharge Power Down is entered, otherwise Active Power
Down is entered
18. ‘Idle state’ means that all banks are closed(tRP,tDAL,etc. satisfied) and CKE is high and all timings from previous operations are satisfied
(tMRD,tMOD,tRFC,tZQinit,tZQoper,tZQCS,etc)as well as all SRF exit and Power Down exit parameters are satisfied (tXS,tXP,tXPDLL,etc)
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AS4C128M16D3B-12BCN
Absolute Maximum DC Ratings
Symbol
Parameter
Rating
Units
Notes
VDD
Voltage on VDD pin relative to Vss
-0.4 V ~ 1.975 V
V
1,3
VDDQ
Voltage on VDDQ pin relative to Vss
-0.4 V ~ 1.975 V
V
1,3
VIN, VOUT
Voltage on any pin relative to Vss
-0.4 V ~ 1.975 V
V
1
TSTG
Storage Temperature
-55 to +100
°C
1,2
NOTE :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement
conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300mV of each other at all times;and VREF must be not greater than 0.6 x VDDQ,
When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
Operating Temperature Condition
Symbol
Parameter
Rating
Units
Notes
TC
Operating case temperature
0 to +95
°C
1,2,3
NOTE :
1. Operating temperature is the case surface temperature on the center/top side of the DRAM.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During
operation, the DRAM case temperature must be maintained between 0°C to +85°C under all operating conditions.
3. Some applications require operation of the DRAM in the Extended Temperature Range between +85°C and +95°C
case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:
a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9μs.
(This double refresh requirement may not apply for some devices.)
b) If Self-refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the
Manual Self-Refresh mode with Extended Temperature Range capability (MR2 bit [A6, A7] = [0, 1]) or enable the
optional Auto Self-Refresh mode (MR2 bit [A6, A7] = [1, 0]).
Recommended DC Operating Conditions
Rating
Symbol
Parameter
VDD
VDDQ
Min.
Typ.
Max.
Units
Notes
Supply voltage
1.425
1.5
1.575
V
1,2
Supply voltage for Output
1.425
1.5
1.575
V
1,2
NOTE :
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
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AS4C128M16D3B-12BCN
AC and DC Input Measurement Levels
Single-Ended AC and DC Input Levels for Command and Address
Symbol
Parameter
Min.
Max.
Units
Notes
VIHCA (DC100)
DC input logic high
VREF + 0.100
VDD
V
1
VILCA (DC100)
DC input logic low
VSS
VREF - 0.100
V
1
VIHCA (AC175)
AC input logic high
VREF + 0.175
-
V
1,2
VILCA (AC175)
AC input logic low
-
VREF - 0.175
V
1,2
VIHCA (AC150)
AC input logic high
VREF + 0.150
-
V
1,2
VILCA (AC150)
AC input logic low
-
VREF - 0.150
V
1,2
VIHCA (AC135)
AC input logic high
-
-
V
1,2
VILCA (AC135)
AC input logic low
-
-
V
1,2
VIHCA (AC125)
AC input logic high
-
-
V
1,2
VILCA (AC125)
AC input logic low
-
-
V
1,2
VREFCA (DC)
Reference voltage for
ADD, CMD inputs
0.49 * VDD
0.51 * VDD
V
3,4
NOTE :
1. For input only pins except /RESET : VREF = VREFCA (DC).
2. See Overshoot and Undershoot Specifications section.
3. The AC peak noise on VREF may not allow VREF to deviate from VREFCA (DC) by more than ±1% VDD
(for reference : approx. ±15 mV).
4. For reference : approx. VDD/2 ±15 mV.
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AS4C128M16D3B-12BCN
Single-Ended AC and DC Input Levels for DQ and DM
Symbol
Parameter
Min.
Max.
Units
Notes
VIHDQ (DC100)
DC input logic high
VREF + 0.100
VDD
V
1
VILDQ (DC100)
DC input logic low
VSS
VREF - 0.100
V
1
VIHDQ (AC175)
AC input logic high
-
-
V
1,2
VILDQ (AC175)
AC input logic low
-
-
V
1,2
VIHDQ (AC150)
AC input logic high
VREF + 0.150
-
V
1,2
VILDQ (AC150)
AC input logic low
-
VREF - 0.150
V
1,2
VIHDQ (AC135)
AC input logic high
-
-
V
1,2
VILDQ (AC135)
AC input logic low
-
-
V
1,2
VREFDQ (DC)
Reference voltage for
DQ, DM inputs
0.49 * VDD
0.51 * VDD
V
3,4
NOTE :
1. For DQ and DM : VREF = VREFDQ (DC).
2. See Overshoot and Undershoot Specifications section.
3. The AC peak noise on VREF may not allow VREF to deviate from VREFDQ (DC) by more than ±1% VDD
(for reference: approx. ±15 mV).
4. For reference: approx. VDD/2 ±15 mV.
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VREF Tolerances
The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are illustrate in
figure VREF(DC) tolerance and VREF AC-Noise limits. It shows a valid reference voltage VREF(t) as a
function of time. (VREF stands for VREFCA and VREFDQ likewise).
VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to
meet the min/max requirement in Table of “Single-Ended AC and DC Input Levels for Command and
Address”. Furthermore VREF(t) may temporarily deviate from VREF(DC) by no more than +/- 1% VDD.
voltage
VDD
VSS
time
VREF(DC) tolerance and VREF AC-Noise limits
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are
dependent on VREF.
"VREF" shall be understood as VREF(DC), as defined in figure above, VREF(DC) tolerance and VREF ACNoise limits.
This clarifies, that DC-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid
high or low level and therefore the time to which setup and hold is measured. System timing and voltage
budgets need to account for VREF(DC) deviations from the optimum position within the data-eye of the
input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VREF AC-noise. Timing and voltage effects due to AC-noise on VREF up to the specified limit (+/- 1% of VDD) are included in DRAM timings and their associated deratings.
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AS4C128M16D3B-12BCN
AC and DC Logic Input Levels for Differential Signals
Differential signals definition
tDVAC
Differential Input Voltage (i.e. DQS-DQS, CK-CK)
VIH.DIFF.AC.MIN
VIH.DIFF.MIN
0.0
half cycle
VIL.DIFF.MAX
VIL.DIFF.AC.MAX
tDVAC
time
Definition of differential ac-swing and "time above ac level" tDVAC
Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS)
Differential AC and DC Input Levels
Symbol
Parameter
Min.
Max.
Units
Notes
VIHdiff
Differential input high
+0.2
NOTE 3
V
1
VILdiff
Differential input low
NOTE 3
-0.2
V
1
VIHdiff(AC)
Differential input high AC
2 x (VIH(AC) - VREF)
NOTE 3
V
2
VILdiff(AC)
Differential input low AC
NOTE 3
2 x (VIL(AC) - VREF)
V
2
NOTE :
1. Used to define a differential signal slew-rate.
2. for CK - CK use VIH/VIL(AC) of address/command and VREFCA; for strobes (DQS, DQS) use VIH/VIL(AC) of DQs
and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here.
3. These values are not defined, however the single-ended signals CK, CK, DQS, DQS need to be within the respective
limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot.
Refer to "Overshoot and Undershoot specification".
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AS4C128M16D3B-12BCN
Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS
Slew Rate [V/ns]
tDVAC [ps] @ |VIH/Ldiff(AC)| = 350mV
tDVAC [ps] @ |VIH/Ldiff(AC)| = 300mV
Min.
Max.
Min.
Max.
> 4.0
75
-
175
-
4.0
57
-
170
-
3.0
50
-
167
-
2.0
38
-
163
-
1.8
34
-
162
-
1.6
29
-
161
-
1.4
22
-
159
-
1.2
13
-
155
-
1.0
0
-
150
-
< 1.0
0
-
150
-
Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, CK, DQS) has also to comply with certain
requirements for single-ended signals.
CK and CK have to approximately reach VSEH min / VSEL max [ approximately equal to the AC-levels
( VIH(AC) / VIL(AC) ) for Address/command signals ] in every half-cycle.
DQS, DQS have to reach VSEH min / VSEL max [ approximately the ac-levels ( VIH(AC) / VIL(AC) ) for DQ
signals ] in every half-cycle proceeding and following a valid transition.
Note that the applicable AC-levels for Address/command and DQ’s might be different per speed-bin etc.
E.g. if VIH150(AC) / VIL150(AC) is used for Address/command signals, then these AC-levels apply also for
the single-ended components of differential CK and CK.
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VDD or VDDQ
VSEH min
VSEH
VDD/2 or VDDQ/2
CK or DQS
VSEL max
VSEL
VSS or VSSQ
time
Single-ended requirement for differential signals
Note that while Address/command and DQ signal requirements are with respect to VREF, the single-ended
components of differential signals have a requirement with respect to VDD/2; this is nominally the same.
The transition of single-ended signals through the AC-levels is used to measure setup time. For singleended components of differential signals the requirement to reach VSEL max, VSEH min has no bearing on
timing, but adds a restriction on the common mode characteristics of these signals.
Single-ended levels for CK, DQS, CK, DQS
Symbol
VSEH
VSEL
Parameter
Min.
Max.
Units
Notes
Single-ended high-level for strobes
(VDD/2) + 0.175
NOTE 3
V
1,2
Single-ended high-level for CK, CK
(VDD/2) + 0.175
NOTE 3
V
1,2
Single-ended low-level for strobes
NOTE 3
(VDD/2) - 0.175
V
1,2
Single-ended low-level for CK, CK
NOTE 3
(VDD/2) - 0.175
V
1,2
NOTE :
1. For CK, CK use VIH/VIL(AC) of address/command; for strobes (DQS, DQS) use VIH/VIL(AC) of DQs.
2. VIH(AC)/VIL(AC) for DQs is based on VREFDQ; VIH(AC)/VIL(AC) for address/command is based on VREFCA; if a
reduced AC-high or AC-low level is used for a signal group, then the reduced level applies also here.
3. These values are not defined, however the single-ended components of differential signals CK, CK, DQS, DQS need
to be within the respective limits (VIH(DC) max, VIL(DC) min) for single-ended signals as well as the limitations for
overshoot and undershoot. Refer to "Overshoot and Undershoot specifications”.
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AS4C128M16D3B-12BCN
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe,
each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements in
below table. The differential input cross point voltage VIX is measured from the actual cross point of true and
complement signal to the mid level between of VDD and VSS.
VDD
CK, DQS
VIX
VDD/2
VIX
VIX
CK, DQS
VSS
VIX Definition
Cross point voltage for differential input signals ( CK, DQS )
Symbol
Parameter
VIX
Differential Input Cross Point Voltage relative to VDD/2 for CK, CK
VIX
Differential Input Cross Point Voltage relative to VDD/2 for DQS, DQS
Min.
Max.
Units
-150
150
mV
-175
175
mV
-150
150
mV
Notes
1
NOTE :1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CKand CK are monotonic, have a single-ended swing VSEL / VSEH of at least VDD/2 +/- 250 mV, and the differential slew rate of
CK-CK is larger than 3 V/ ns. Refer to the table of Cross point voltage for differential input signals (CK, DQS)
for VSEL and VSEH standard values.
Differential input slew rate definition
Measured
Description
Defined by
From
To
Differential input slew rate for rising edge ( CK-CK and DQS-DQS )
VILdiff (max)
VIHdiff (min)
VIHdiff (min) - VILdiff (max)
Delta TRdiff
Differential input slew rate for falling edge ( CK-CK and DQS-DQS )
VIHdiff (min)
VILdiff (max)
VIHdiff (min) - VILdiff (max)
Delta TFdiff
NOTE : The differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds.
VIHdiffmin
0
VILdiffmax
delta TFdiff
delta TRdiff
Differential Input Slew Rate definition for DQS, DQS, and CK, CK
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Rev.1.0 Mar. 2016
AS4C128M16D3B-12BCN
AC and DC Output Measurement Levels
Single-ended AC & DC Output Levels
Parameter
Symbol
DDR3-1600
Units
Notes
VOH(DC)
DC output high measurement level (for IV curve linearity)
0.8 x VDDQ
V
VOM(DC)
DC output mid measurement level (for IV curve linearity)
0.5 x VDDQ
V
VOL(DC)
DC output low measurement level (for IV curve linearity)
0.2 x VDDQ
V
VOH(AC)
AC output high measurement level (for output SR)
VTT + 0.1 x VDDQ
V
1
VOL(AC)
AC output low measurement level (for output SR)
VTT - 0.1 x VDDQ
V
1
NOTE : 1. The swing of +/-0.1 x VDDQ is based on approximately 50% of the static single ended output high or low
swing with a driver impedance of 40Ω and an effective test load of 25Ω to VTT=VDDQ/2.
Differential AC & DC Output Levels
Parameter
DDR3-1600
Units
Notes
VOHdiff(AC)
AC differential output high measurement level (for output SR)
+0.2 x VDDQ
V
1
VOLdiff(AC)
AC differential output low measurement level (for output SR)
-0.2 x VDDQ
V
1
Symbol
NOTE : 1. The swing of +/-0.2xVDDQ is based on approximately 50% of the static single ended output high or low swing
with a driver impedance of 40Ω and an effective test load of 25Ω to VTT=VDDQ/2 at each of the differential outputs.
Single-ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured
between VOL(AC) and VOH(AC) for single ended signals.
Measured
Description
Defined by
From
To
Single ended output slew rate for rising edge
VOL(AC)
VOH(AC)
VOH(AC)-VOL(AC)
Delta TRse
Single ended output slew rate for falling edge
VOH(AC)
VOL(AC)
VOH(AC)-VOL(AC)
Delta TRse
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production
test.
Single-ended Output Slew Rate definition
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Rev.1.0 Mar. 2016
AS4C128M16D3B-12BCN
Parameter
Symbol
Single ended output SRQse
slew rate
DDR3-1600
Min
Max
2.5
5
Units
V/ns
Description : SR : Slew Rate
Q : Query Output (like in DQ, which stands for Data-in, Query-Output)
se : Single-ended Signals For Ron = RZQ/7 setting
NOTE : (1) In two cased, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.
- Case_1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high
to low of low to high) while all remaining DQ signals in the same byte lane are static (i.e they stay at either high or low).
- Case_2 is defined for a single DQ signals in the same byte lane are switching into the opposite direction (i.e. from low
to high or high to low respectively). For the remaining DQ signal switching into the opposite direction, the regular maximum limit of 5 V/ns applies.
Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured
between VOLdiff(AC) and VOH-diff(AC) for differential signals.
Measured
Description
Defined by
From
To
Differential output slew rate for rising edge
VOLdiff(AC)
VOHdiff(AC)
VOHdiff(AC)-VOLdiff(AC)
Delta TRdiff
Differential output slew rate for falling edge
VOHdiff(AC)
VOLdiff(AC)
VOHdiff(AC)-VOLdiff(AC))
Delta TFdiff
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production
test.
Differential Output Slew Rate definition
Parameter
Differential output
slew rate
Symbol
SRQdiff
DDR3-1600
Min
Max
5
10
Units
V/ns
Description : SR : Slew Rate
Q : Query Output (like in DQ, which stands for Data-in, Query-Output)
diff : Differential Signals
For Ron = RZQ/7 setting
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AS4C128M16D3B-12BCN
Reference Load for AC Timing and Output Slew Rate
Figure represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the
device as well as output slew rate measurements.
It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more
coaxial transmission lines terminated at the tester electronics.
Reference Load for AC Timing and Output Slew Rate
Overshoot/Undershoot Specification
Address and Control Overshoot and Undershoot specifications
Specification
Parameter
DDR3-1600
Unit
Maximum peak amplitude allowed for overshoot area
0.4V
V
Maximum peak amplitude allowed for undershoot area
0.4V
V
Maximum overshoot area above VDD
0.33V-ns
V-ns
Maximum undershoot area below VSS
0.33V-ns
V-ns
Address and Control Overshoot and Undershoot Definition
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AS4C128M16D3B-12BCN
Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications
Specification
Parameter
DDR3-1600
Unit
Maximum peak amplitude allowed for overshoot area
0.4V
V
Maximum peak amplitude allowed for undershoot area
0.4V
V
Maximum overshoot area above VDD
0.13V-ns
V-ns
Maximum undershoot area below VSS
0.13V-ns
V-ns
Clock, Data, Strobe, Mask Overshoot and Undershoot Definition
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AS4C128M16D3B-12BCN
IDD Specification
( VDD = 1.5V±0.075V; VDDQ =1.5V±0.075V )
Conditions
Symbol
Operating One Bank Active-Precharge Current; CKE: High; External clock:
On; tCK, nRC, nRAS, CL: see timing used table; BL: 8; AL: 0; CS: High between ACT and PRE; Command, Address: partially toggling; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time;
Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0
Operating One Bank Active-Read-Precharge Current; CKE: High; External
clock: On; tCK, nRC, nRAS, nRCD, CL: see timing used table; BL: 81; AL: 0;
CS: High between ACT, RD and PRE; Command, Address, Data IO: partially
toggling; DM:stable at 0; Bank Activity: Cycling with one bank active at a time;
Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0
Precharge Power-Down Current Slow Exit; CKE: Low; External clock: On;
tCK, CL: see timing used table; BL: 8; AL: 0; CS: stable at 1; Command, Address: stable at 0; Data IO: FLOATING; DM: stable at 0; Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0; Pre-charge Power Down Mode: Slow Exit
Precharge Power-Down Current Fast Exit; CKE: Low; External clock: On;
tCK, CL: see timing used table; BL: 8; AL: 0; CS: stable at 1; Command, Address: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks
closed; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0; Pre-charge Power Down Mode: Fast Exit
Precharge Standby Current; CKE: High; External clock: On; tCK, CL: see
timing used table; BL: 8; AL: 0; CS: stable at 1; Command, Address: partially
toggling; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed;
Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0
Precharge Quiet Standby Current; CKE: High; External clock: On; tCK, CL:
see timing used table;
BL: 8; AL: 0; CS: stable at 1; Command, Address: stable at 0; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT:
Enabled in Mode Registers; ODT Signal: stable at 0
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IDD max.
Unit
IDD0
70
mA
IDD1
80
mA
IDD2P0
15
mA
IDD2P1
22
mA
IDD2N
35
mA
IDD2Q
35
mA
Rev.1.0 Mar. 2016
AS4C128M16D3B-12BCN
Conditions
Symbol
IDD max.
Unit
Active Power-Down Current; CKE: Low; External clock: On; tCK, CL: see
timing used table; BL: 8; AL: 0; CS: stable at 1; Command, Address: stable at
0; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks open; Output
Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0
IDD3P
35
mA
Active Standby Current; CKE: High; External clock: On; tCK, CL: see timing
used table; BL: 8; AL: 0; CS: stable at 1; Command, Address: partially toggling;
Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks open; Output
Buffer and RTT: Enabled in Mode Registers; ODT Signal: stable at 0
IDD3N
53
mA
Operating Burst Read Current; CKE: High; External clock: On; tCK, CL: see
timing used table; BL: 8; AL: 0; CS: High between RD; Command, Address:
partially toggling; Data IO: seamless read data burst with different data between one burst and the next one; DM: stable at 0; Bank Activity: all banks
open, RD commands cycling through banks: 0,0,1,1,2,2,...; Output Buffer and
RTT: Enabled in Mode Registers; ODT Signal: stable at 0
IDD4R
155
mA
Operating Burst Write Current; CKE: High; External clock: On; tCK, CL: see
timing used table; BL: 8; AL: 0; CS: High between WR; Command, Address:
partially toggling; Data IO: seamless write data burst with different data between one burst and the next one; DM: stable at 0; Bank Activity: all banks
open, WR commands cycling through banks: 0,0,1,1,2,2,...; Output Buffer and
RTT: Enabled in Mode Registers; ODT Signal: stable at HIGH
IDD4W
160
mA
IDD5B
145
mA
IDD6
15
mA
17
mA
Burst Refresh Current; CKE: High; External clock: On; tCK, CL, nRFC: see
timing used table; BL: 8; AL: 0; CS: High between REF; Command, Address:
partially toggling; Data IO: FLOATING; DM:stable at 0; Bank Activity: REF
command every nRFC; Output Buffer and RTT: Enabled in Mode Registers;
ODT Signal: stable at 0
Self Refresh Current: Normal Temperature Range; TCASE: 0- 85°C; Auto
Self-Refresh (ASR): Disabled; Self-Refresh Temperature Range (SRT): Normal; CKE: Low; External clock: Off; CK and CK: LOW; CL: see timing used table; BL: 8; AL: 0; CS, Command, Address, Data IO: FLOATING; DM: stable at
0; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in
Mode Registers; ODT Signal: FLOATING
Self Refresh Current: Extended Temperature Range; TCASE: 0- 95°C;
Auto Self-Refresh (ASR): Disabled; Self-Refresh Temperature Range (SRT):
Extended; CKE: Low; External clock: Off; CK and CK: LOW; CL: see timing
used table; BL: 8; AL: 0; CS, Command, Address, Data IO: FLOATING; DM: IDD6ET
stable at 0; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers; ODT Signal: FLOATING
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Rev.1.0 Mar. 2016
AS4C128M16D3B-12BCN
Conditions
Symbol
IDD max.
Unit
Operating Bank Interleave Read Current; CKE: High; External clock: On;
tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see timing used table; BL: 8; AL:
CL-1; CS: High between ACT and RDA; Command, Address: partially toggling;
Data IO: read data bursts with different data between one burst and the next
one; DM: stable at 0; Bank Activity: two times interleaved cycling through
banks (0, 1, ...7) with different addressing; Output Buffer and RTT: Enabled in
Mode Registers; ODT Signal: stable at 0
IDD7
240
mA
IDD8
14
mA
RESET Low Current; RESET: Low; External clock: off; CK and CK: LOW;
CKE: FLOATING; CS, Command, Address, Data IO: FLOATING; ODT Signal
: FLOATING
NOTE :
1) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
2) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B;
RTT_Wr enable: set MR2 A[10,9] = 10B
3) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit
4) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
5) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range
6) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM
7) Read Burst type : Nibble Sequential, set MR0 A[3]=0B
Timing used for IDD and IDDQ Measured - Loop Patterns
Speed
DDR3-1600
CL-nRCD-nRP
11-11-11
tCKmin
1.25
ns
CL
11
nCK
tRCDmin
11
nCK
tRCmin
39
nCK
tRASmin
28
nCK
tRPmin
11
nCK
tFAW (1KB page size)
24
nCK
tFAW (2KB page size)
32
nCK
tRRD (1KB page size)
5
nCK
tRRD (2KB page size)
6
nCK
tRFC
128
nCK
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Unit
Rev.1.0 Mar. 2016
AS4C128M16D3B-12BCN
Input/Output Capacitance
Parameter
Symbol
DDR3-1600
Min
Max
Units
NOTE
Input/output capacitance
(DQ, DM, DQS, DQS)
CIO
1.4
2.3
pF
1,2,3
Input capacitance
(CK and CK)
CCK
0.8
1.4
pF
2,3
CDCK
0
0.15
pF
2,3,4
CI
0.75
1.3
pF
2,3,6
CDDQS
0
0.15
pF
2,3,5
CDI_CTRL
-0.4
0.2
pF
2,3,7,8
CDI_ADD_CMD
-0.4
0.4
pF
2,3,9,10
Input/output capacitance delta
(DQ, DM, DQS, DQS)
CDIO
-0.5
0.3
pF
2,3,11
Input/output capacitance of ZQ pin
CZQ
-
3
pF
2,3,12
Input capacitance delta
(CK and CK)
Input capacitance
(All other input-only pins)
Input capacitance delta
(DQS and DQS)
Input capacitance delta
(All control input-only pins)
Input capacitance delta
(all ADD and CMD input-only pins)
NOTE :
1. Although the DM pin have different function, the loading matches DQ and DQS
2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is measured according to JEP147("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK
ANALYZER( VNA)") with VDD, VDDQ, VSS, VSSQ applied and all other pins floating (except the pin under test, CKE,
RESET and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off.
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here
4. Absolute value of CCK-CCK
5. Absolute value of CIO(DQS)-CIO(DQS)
6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE
7. CDI_CTRL applies to ODT, CS and CKE
8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(CLK))
9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE
10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK))
11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS))
12. Maximum external load capacitance on ZQ pin: 5pF
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Rev.1.0 Mar. 2016
AS4C128M16D3B-12BCN
DDR3-1600 Speed Bins
Speed Bin
- 12 (DDR3-1600)
CL-nRCD-nRP
11-11-11
Parameter
Unit
Notes
20
ns
7
13.75
(13.125)
-
ns
7
tRP
13.75
(13.125)
-
ns
7
tRC
48.75
(48.125)
-
ns
7
Symbol
Min
Max
tAA
13.75
(13.125)
tRCD
Precharge command period
Active to active/auto-refresh command time
Internal read command to first data
Active to read or write delay time
Active to precharge command period
Average Clock
Cycle Time
CL = 5
CL = 6
CL = 7
CL = 8
CL = 9
CL = 10
CL = 11
35
9 * tREFI
ns
tCK(avg)
3.0
3.3
ns
1,2,3,5
CWL = 6,7
tCK(avg)
Reserved
Reserved
ns
4
CWL = 5
tCK(avg)
2.5
3.3
ns
1,2,3,5
CWL = 6
tCK(avg)
Reserved
Reserved
ns
4
CWL = 7
tCK(avg)
Reserved
Reserved
ns
4
CWL = 5
tCK(avg)
Reserved
Reserved
ns
4
CWL = 6
tCK(avg)
1.875
< 2.5
ns
1,2,3,5
CWL = 7
tCK(avg)
Reserved
Reserved
ns
4
CWL = 5
tCK(avg)
Reserved
Reserved
ns
4
CWL = 6
tCK(avg)
1.875
< 2.5
ns
1,2,3,5
CWL = 7
tCK(avg)
Reserved
Reserved
ns
4
CWL = 5, 6
tCK(avg)
Reserved
Reserved
ns
4
CWL = 7
tCK(avg)
1.5
< 1.875
ns
1,2,3,5
CWL = 5, 6
tCK(avg)
Reserved
Reserved
ns
4
CWL = 7
tCK(avg)
1.5
< 1.875
ns
1,2,3,5
CWL = 8
tCK(avg)
Reserved
Reserved
ns
4
CWL = 5, 6,7
tCK(avg)
Reserved
Reserved
ns
4
CWL = 8
tCK(avg)
1.25
< 1.5
ns
1,2,3
Supported CL setting
Supported CWL setting
Confidential
6
tRAS
CWL = 5
- 32/41 -
5, 6, 7, 8, 9, 10,11
nCK
5, 6, 7, 8
nCK
Rev.1.0 Mar. 2016
AS4C128M16D3B-12BCN
Speed Bin Table Notes
NOTE :
1. The CL setting and CWL setting result in tCK(avg) Min and tCK(avg) Max requirements. When making a selection
of tCK(avg), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting.
2. tCK(avg) Min limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL all possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC
standard tCK(avg) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(avg) [ns], rounding
up to the next "Supported CL".
3. tCK(avg) Max limits: Calculate tCK(avg) = tAA Max / CL Selected and round the resulting tCK(avg) down to the
next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(avg) Max corresponding to CL
selected.
4. "Reserved" settings are not allowed. User must program a different value.
5. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are
not subject to production tests but verified by design/characterization. .
6. tREFI depends on operating case temperature (Tc).
7. For devices supporting optional downshift to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125 ns or lower. SPD
settings must be programmed to match. For example, DDR3-1600(CL11) devices supporting downshift to
DDR3-1333(CL9) or DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte16), tRCDmin (Byte
18), and tRPmin (Byte 20). DDR3-1600 devices supporting down binning to DDR3-1333 or DDR3-1066 should
program 13.125ns in SPD byte for tAAmin (Byte 16), tRCDmin (Byte 18) and tRPmin (Byte 20). Once tRP (Byte 20)
is programmed to 13.125ns, tRCmin (Byte 21,23) also should be programmed accodingly.For example, 49.125ns,
(tRASmin + tRPmin = 36ns + 13.125ns) for DDR3-1333 and 48.125ns (tRASmin + tRPmin = 35ns + 13.125ns) for
DDR3-1600.
Confidential
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Rev.1.0 Mar. 2016
AS4C128M16D3B-12BCN
AC Characteristics
( VDD = 1.5V±0.075V; VDDQ =1.5V±0.075V )
- 12 (DDR3-1600)
Parameter
Symbol
Min
Max
Unit
it
Average clock cycle time
tCK(avg)
Minimum clock cycle time
(DLL-off mode)
tCK
(DLL-off)
8
-
ns
Average CK high level width
tCH(avg)
0.47
0.53
tCK(avg)
Average CK low level width
tCL(avg)
0.47
0.53
tCK(avg)
6
-
ns
4
-
nCK
7.5
-
ns
4
-
nCK
ote
ps
Please refer Speed Bins
6
Active Bank A to Active Bank B
command period for 1KB page size
tRRD
Active Bank A to Active Bank B
command period for 2KB page size
tRRD
Four activate window for 1KB page size
tFAW
30
-
ns
Four activate window for 2KB page size
tFAW
40
-
ns
Address and Control input hold time
(VIH/VIL (DC100) levels)
tIH(base)
DC100
120
-
ps
16
Address and Control input setup time
(VIH/VIL (AC175) levels)
tIS(base)
AC175
45
-
ps
16
Address and Control input setup time
(VIH/VIL (AC150) levels)
tIS(base)
AC150
170
-
ps
16,24
DQ and DM input hold time
(VIH/VIL (DC100) levels)
tDH(base)
DC100
45
-
ps
17
DQ and DM input setup time
(VIH/VIL (AC175) levels)
tDS(base)
AC175
-
-
ps
17
DQ and DM input setup time
(VIH/VIL (AC150) levels)
tDS(base)
AC150
10
-
ps
17
Control and Address Input pulse width
for each input
tIPW
560
-
ps
25
DQ and DM Input pulse width
for each input
tDIPW
360
-
ps
25
DQ high impedance time
tHZ(DQ)
-
225
ps
13,14
DQ low impedance time
tLZ(DQ)
-450
225
ps
13,14
DQS, DQS high impedance time
(RL + BL/2 reference)
tHZ(DQS)
-
225
ps
13,14
DQS, DQS low impedance time
(RL - 1 reference)
tLZ(DQS)
-450
225
ps
13,14
tDQSQ
-
100
ps
12,13
CAS to CAS command delay
tCCD
4
-
nCK
DQ output hold time from DQS, DQS
tQH
0.38
-
tCK(avg)
12,13
DQS, DQS rising edge output
access time from rising CK, CK
tDQSCK
-225
225
ps
12,13
DQS latching rising transitions
to associated clock edges
tDQSS
-0.27
0.27
tCK(avg)
DQS, DQS to DQ Skew,
per group, per access
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AS4C128M16D3B-12BCN
- 12 (DDR3-1600)
Symbol
Min
Max
Unit
Note
DQS falling edge hold time
from rising CK
tDSH
0.18
-
tCK(avg)
29
DQS falling edge setup time
to rising CK
tDSS
0.18
-
tCK(avg)
29
DQS input high pulse width
tDQSH
0.45
0.55
tCK(avg)
27,28
DQS input low pulse width
tDQSL
0.45
0.55
tCK(avg)
26,28
DQS output high time
tQSH
0.40
-
tCK(avg)
12,13
DQS output low time
tQSL
0.40
-
tCK(avg)
12,13
Mode register set command cycle time
tMRD
Parameter
4
-
nCK
15
-
ns
12
-
nCK
tRPRE
0.9
-
tCK(avg)
13,19
Read postamble time
tRPST
0.3
-
tCK(avg)
11,13
Write preamble time
tWPRE
0.9
-
tCK(avg)
1
Write postamble time
tWPST
0.3
-
tCK(avg)
1
tWR
15
-
ns
Mode register set command update
delay
tMOD
Read preamble time
Write recovery time
Auto precharge write recovery
+ Precharge time
Multi-purpose register recovery time
Internal write to read command delay
Internal read to precharge command
delay
tDAL(min)
tMPRR
Valid clock requirement after Selfrefresh entry or Power-down entry
tCKSRE
Exit Self-refresh to commands
not requiring a locked DLL
-
nCK
22
7.5
-
ns
18
4
-
nCK
18
7.5
-
ns
4
-
nCK
tCKE(min)
+1nCK
-
10
-
ns
tRTP
tCKESR
5
-
nCK
10
-
ns
5
-
nCK
tRFC(min)
+10
-
tCKSRX
tXS
nCK
1
tWTR
Minimum CKE low width for Self-refresh
entry to exit timing
Valid clock requirement before Selfrefresh exit or Power-down exit
WR + roundup [tRP / tCK(avg)]
ns
5
-
tXSDLL
tDLLK
(min)
-
Auto-refresh to Active/Auto-refresh
command time
tRFC
160
-
Average Periodic Refresh Interval
0°C < Tc < +85°C
tREFI
-
7.8
Average Periodic Refresh Interval
+85°C < Tc < +95°C
tREFI
-
3.9
CKE minimum high and low pulse width
tCKE
5
-
ns
3
-
nCK
Exit Self-refresh to commands
requiring a locked DLL
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nCK
nCK
ns
μs
μs
Rev.1.0 Mar. 2016
AS4C128M16D3B-12BCN
- 12 (DDR3-1600)
Parameter
Symbol
Min
Max
Exit reset from CKE high to a valid
command
tRFC(min)
+10
-
tXPR
5
-
nCK
DLL locking time
tDLLK
512
-
nCK
tPD
tCKE(min)
9*tREFI
24
-
ns
2
10
-
nCK
2
6
-
ns
3
-
nCK
-
nCK
Power-down entry to exit time
Exit precharge power-down with
DLL frozen to commands requiring
a locked DLL
Exit power-down with DLL on to any
valid command; Exit precharge
power-down with DLL frozen to
commands not requiring a locked DLL
Command pass disable delay
tXPDLL
Unit
Note
ns
15
tXP
tCPDED
1
-
Timing of ACT command to
Power-down entry
tACTPDEN
1
Timing of PRE command to
Power-down entry
tPRPDEN
1
Timing of RD/RDA command to
Power-down entry
tRDPDEN
RL+4+1
Timing of WR command to Power-down
entry (BL8OTF, BL8MRS, BL4OTF)
tWRPDEN
(min)
WL + 4 + [tWR/tCK(avg)]
nCK
9
Timing of WR command to Power-down
entry (BC4MRS)
tWRPDEN
(min)
WL + 2 + [tWR/tCK(avg)]
nCK
9
nCK
10
nCK
10
nCK
20,21
7
-
Timing of WRA command to Power-down
tWRAPDEN
entry (BL8OTF, BL8MRS, BL4OTF)
WL+4
+WR+1
-
Timing of WRA command to Power-down
tWRAPDEN
entry (BC4MRS)
WL+2
+WR+1
-
Timing of REF command to Power-down
entry
tREFPDEN
1
-
nCK
20
nCK
20
nCK
Timing of MRS command to Power-down
tMRSPDEN
entry
tMOD
(min)
-
RTT turn-on
tAON
-225
225
ps
tAONPD
2
8.5
ns
tAOF
0.3
0.7
tCK(avg)
tAOFPD
2
8.5
ns
Asynchronous RTT turn-on delay
(Power-down with DLL frozen)
RTT_Nom and RTT_WR turn-off time
from ODTLoff reference
Asynchronous RTT turn-off delay
(Power-down with DLL frozen)
ODT high time without write command
or with write command and BC4
ODTH4
ODT high time with Write command
and BL8
ODTH8
4
6
-
nCK
nCK
RTT dynamic change skew
tADC
0.3
0.7
tCK(avg)
Power-up and reset calibration time
tZQinit
512
-
nCK
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8
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AS4C128M16D3B-12BCN
- 12 (DDR3-1600)
Parameter
Symbol
Min
Max
Unit
Normal operation full calibration time
tZQoper
256
-
nCK
Normal operation short calibration time
tZQCS
64
-
nCK
23
First DQS pulse rising edge after write
leveling mode is programmed
tWLMRD
40
nCK
3
tWLDQSEN
25
nCK
3
Write leveling setup time from rising CK,
CK crossing to rising DQS, DQS crossing
tWLS
165
Write leveling hold time from rising DQS,
DQS crossing to rising CK, CK crossing
tWLH
165
Write leveling output delay
tWLO
0
7.5
ns
Write leveling output error
tWLOE
0
2
ns
Absolute clock period
tCK(abs)
tCK(avg)min +
tJIT(per)min
tCK(avg)max +
tJIT(per)max
ps
Absolute clock high pulse width
tCH(abs)
0.43
-
tCK(avg)
30
Absolute clock low pulse width
tCL(abs)
0.43
-
tCK(avg)
31
Clock period jitter
tJIT(per)
-70
70
ps
tJIT(per,lck)
-60
60
ps
DQS, DQS delay after write leveling
mode is pro-grammed
Clock period jitter during DLL locking
period
-
ps
ps
tJIT(cc)
-
140
ps
Cycle to cycle period jitter during DLL
locking period
tJIT(cc,lck)
-
120
ps
Cumulative error across 2 cycles
tERR(2per)
-103
103
ps
Cumulative error across 3 cycles
tERR(3per)
-122
122
ps
Cumulative error across 4 cycles
tERR(4per)
-136
136
ps
Cumulative error across 5 cycles
tERR(5per)
-147
147
ps
Cumulative error across 6 cycles
tERR(6per)
-155
155
ps
Cumulative error across 7 cycles
tERR(7per)
-163
163
ps
Cumulative error across 8 cycles
tERR(8per)
-169
169
ps
Cumulative error across 9 cycles
tERR(9per)
-175
175
ps
Cumulative error across 10 cycles
tERR(10per)
-180
180
ps
Cumulative error across 11 cycles
tERR(11per)
-184
184
ps
Cumulative error across 12 cycles
tERR(12per)
-188
188
ps
Cycle to cycle period jitter
Cumulative error across
n = 13,14,...49,50 cycles
Confidential
tERR(nper)
tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min
tERR(nper)max = (1 + 0.68ln(n))*tJIT(per)max
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Note
ps
32
Rev.1.0 Mar. 2016
AS4C128M16D3B-12BCN
Notes for AC Electrical Characteristics
NOTE :
1. Actual value dependant upon measurement level definitions which are TBD.
2. Commands requiring a locked DLL are: READ (and READA) and synchronous ODT commands.
3. The max values are system dependent.
4. WR as programmed in mode register.
5. Value must be rounded-up to next higher integer value.
6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.
7. ODT turn on time (min.) is when the device leaves high impedance and ODT resistance begins to turn on.
ODT turn on time (max.) is when the ODT resistance is fully on. Both are measured from ODTLon.
8. ODT turn-off time (min.) is when the device starts to turn-off ODT resistance. ODT turn-off time (max.) is when
the bus is in high impedance. Both are measured from ODTLoff.
9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer.
10. WR in clock cycles as programmed in MR0.
11. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on
the right side.
12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter,
this parameter needs to be derated by TBD.
13. Value is only valid for RON34.
14. Single ended signal parameter. Refer to the section of tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Notes for definition
and measurement method.
15. tREFI depends on operating case temperature (Tc).
16. tIS(base) and tIH(base) values are for 1V/ns command/addresss single-ended slew rate and 2V/ns CK, CK
differential slew rate, Note for DQ and DM signals, VREF(DC) = VREFDQ(DC). For input only pins except RESET,
VREF(DC) = VREFCA(DC). See Address / Command Setup, Hold and Derating section.
17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew
rate. Note for DQ and DM signals,VREF(DC)= VREFDQ(DC). For input only pins except RESET, VREF(DC) =
VREFCA(DC). See Data Setup, Hold and and Slew Rate Derating section.
18. Start of internal write transaction is defined as follows ;
For BL8 (fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL.
For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL.
For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL.
19. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side.
20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh
are in progress, but power-down IDD spec will not be applied until finishing those operation.
21. Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied,
there are cases where additional time such as tXPDLL(min) is also required.
22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.
23. One ZQCS command can effectively correct a minimum of 0.5 % (ZQCorrection) of RON and RTT impedance error
within 64 nCK for all speed bins assuming the maximum sensitivities specified in the “Output Driver Voltage and
Temperature Sensitivity” and “ODT Voltage and Temperature Sensitivity” tables. The appropriate interval between
ZQCS commands can be determined from these tables and other application specific parameters.
One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage
(Vdriftrate) drift rates that the SDRAM is subject to in the application, is illustrated. The interval could be defined by
the following formula:
ZQCorrection
(TSens x Tdriftrate) + (VSens x Vdriftrate)
where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature
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AS4C128M16D3B-12BCN
and voltage sensitivities.
24. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100 ps of
derating to accommodate for the lower alternate threshold of 150 mV and another 25 ps to account for the earlier
reference point [(175 mv - 150 mV) / 1 V/ns].
25. Pulse width of a input signal is defined as the width between the first crossing of VREF(DC) and the consecutive
crossing of VREF(DC).
26. tDQSL describes the instantaneous differential input low pulse width on DQS - DQS, as measured from one falling
edge to the next consecutive rising edge.
27. tDQSH describes the instantaneous differential input high pulse width on DQS - DQS, as measured from one rising
edge to the next consecutive falling edge.
28. tDQSH,act + tDQSL,act = 1 tCK,act ; with tXYZ,act being the actual measured value of the respective timing
parameter in the application.
29. tDSH,act + tDSS,act = 1 tCK,act ; with tXYZ,act being the actual measured value of the respective timing parameter
in the application.
30. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following
falling edge.
31. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following
rising edge.
32. n = from 13 cycles to 50 cycles. This row defines 38 parameters.
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AS4C128M16D3B-12BCN
Package Diagram (x16)
96-Ball Fine Pitch Ball Grid Array Outline
Unit: mm
* BSC (Basic Spacing between Center)
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AS4C128M16D3B-12BCN
PART NUMBERING SYSTEM
AS4C
DRAM
128M16D3B
128M16=128Mx16
D3=DDR3
B=B Die Rev
12
12=800MHz
B
B = FBGA
C
C=Commercial
(Extended) (0°C~ 95°C)
N
Indicates Pb and
Halogen Free
Alliance Memory, Inc.
511 Taylor Way,
San Carlos, CA 94070
Tel: 650-610-6800
Fax: 650-620-9211
www.alliancememory.com
Copyright © Alliance Memory
All Rights Reserved
© Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their
respective companies. Alliance reserves the right to make changes to this document and its products at any time
without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data
contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right
to change or correct this data at any time, without notice. If the product described herein is under development,
significant changes to these specifications are possible. The information in this product data sheet is intended to be
general descriptive information for potential customers and users, and is not intended to operate as, or provide, any
guarantee or warranty to any user or customer. Alliance does not assume any responsibility or liability arising out of
the application or use of any product described herein, and disclaims any express or implied warranties related to the
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Confidential
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