Cypress BCM20730A2KFBG Single-chip bluetooth transceiver for wireless input device Datasheet


CYW20730
Single-Chip Bluetooth Transceiver for
Wireless Input Devices
The Cypress CYW20730 is a Bluetooth 3.0-compliant, stand-alone baseband processor with an integrated 2.4 GHz transceiver. It is
ideal for wireless input device applications including game controllers, keyboards, 3D glasses, remote controls, gestural input devices,
and sensor devices. Built-in firmware adheres to the Bluetooth Human Interface Device (HID) profile and Bluetooth Device ID profile
specifications.
The CYW20730 radio has been designed to provide low power, low cost, and robust communications for applications operating in the
globally available 2.4 GHz unlicensed ISM band. It is fully compliant with Bluetooth Radio Specification 3.0.
The single-chip Bluetooth transceiver is a monolithic component implemented in a standard digital CMOS process and requires
minimal external components to make a fully compliant Bluetooth device. The CYW20730 is available in three package options: a 32pin, 5 mm × 5 mm QFN, a 40-pin, 6 mm × 6 mm QFN, and a 64-pin, 7 mm × 7 mm BGA.
Cypress Part Numbering Scheme
Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion,
there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides
Cypress ordering part number that matches an existing IoT part number.
Table 1. Mapping Table for Part Number between Broadcom and Cypress
Broadcom Part Number
Cypress Part Number
BCM20730
CYW20730
BCM20730A2KML2GT
CYW20730A2KML2GT
BCM20730A1KML2G
CYW20730A1KML2G
BCM20730A1KMLG
CYW20730A1KMLG
BCM20730A1KFBGT
CYW20730A1KFBGT
BCM20730A2KFBG
CYW20730A2KFBG
BCM20730A1KFBG
CYW20730A1KFBG
BCM20730A1KML2GT
CYW20730A1KML2GT
BCM20730A2KML2G
CYW20730A2KML2G
BCM20730A1KMLGT
CYW20730A1KMLGT
BCM20730A2KFBGT
CYW20730A2KFBGT
Acronyms and Abbreviations
In most cases, acronyms and abbreviations are defined on first use.
For a comprehensive list of acronyms and other terms used in Cypress documents, go to http://www.cypress.com/glossary.
Applications
■
Wireless pointing devices: mice, trackballs, gestural controls
■
Point-of-sale (POS) input devices
■
Wireless keyboards
■
Remote sensors
■
3D glasses
■
Home automation
■
Remote controls
■
Personal health and fitness monitoring
■
Game controllers
Cypress Semiconductor Corporation
Document Number: 002-14824 Rev. *J
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 25, 2017
CYW20730
Features
■
On-chip support for common keyboard and mouse interfaces
eliminates external processor
■
Programmable keyscan matrix interface, up to 8 × 20 keyscanning matrix
■
3-axis quadrature signal decoder
■
Shutter control for 3D glasses
■
Infrared modulator
■
IR learning
■
Triac control
■
Triggered Broadcom Fast Connect
■
Supports Adaptive Frequency Hopping
■
Excellent receiver sensitivity
■
Bluetooth specification 3.0 compatible, including enhanced
power control (Unicast Connectionless Data)
■
Bluetooth HID profile version 1.0 compliant
■
Bluetooth Device ID profile version 1.3 compliant
■
Bluetooth AVRCP-CT profile version 1.3 compliant
Document Number: 002-14824 Rev. *J
■
10-bit auxiliary ADC with 28 analog channels
■
On-chip support for serial peripheral interface (master and
slave modes)
■
Broadcom Serial Communications (BSC) interface (compatible
with Philips® (now NXP) I2C slaves)
■
Programmable output power control meets Class 2 or Class 3
requirements
■
Class 1 operation supported with external PA and T/R switch
■
Integrated ARM Cortex™-M3 based microprocessor core
■
On-chip power-on reset (POR)
■
Support for EEPROM and serial flash interfaces
■
Integrated low-dropout regulator (LDO)
■
On-chip software controlled power management unit
■
Three package types are available:
❐ 32-pin QFN package (5 mm × 5 mm)
❐ 40-pin QFN package (6 mm × 6 mm)
❐ 64-pin BGA package (7 mm × 7 mm)
■
RoHS compliant
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CYW20730
Figure 1. Functional Block Diagram
Muxed on GPIO
UART_TXD
UART_RXD
Tx RTS_N
Rx
CTS_N
1.2V VDD_CORE
Domain
WDT
Processing
Unit
(ARM -CM3)
Test
UART
Periph 320K
UART ROM
1.2V
SDA/
MOSI
SCL/
SCK MISO
BSC/SPI
Master
Interface
(BSC is I2C compaƟble)
60K
RAM
VDD_CORE
VSS,
VDDO,
VDDC
28 ADC
Inputs
1.2V
1.2V
POR
CT ɇ ѐ
ADC
1.2V
LDO
1.425V to 3.6V
MIA
POR
System Bus
1.62V to 3.6V
32 kHz
LPCLK
Peripheral
Interface
Block
hclk
(24 MHz to 1 MHz)
RF Control
and Data
2.4 GHz
Radio
T/R
Switch
VDD_IO
Domain
I/O Ring Bus
Bluetooth
Baseband
Core
24
MHz
RF I/O
I/O Ring
Control
Registers
Volt. Trans
GPIO
Control/
Status
Registers
IR
Mod.
and
Learning
SPI
M/S
Keyboard
Matrix
Scanner
w/FIFO
3 -Axis
Mouse
Signal
Controller
3-D Glasses
and Triac
Frequency
Synthesizer
1.2V VDD_RF
Domain
IR
I/O
8 x 20
Scan
Matrix
6 Quadrature
Inputs (3 pair) +
High Current
Driver Controls
28 ADC
Inputs
24 MHz
Ref Xtal
Power
WAKE
40 GPIO
AutoCal
PMU
PWM
40 GPIO on the 64-pin BGA
(22 GPIO on the 40-pin QFN)
(14 GPIO on the 32-pin QFN)
32 kHz
LPCLK
128 kHz
LPO
128 kHz
LPCLK
÷4
32 kHzyƚĂů;ŽƉƟŽŶĂůͿ
1.62V to 3.6V
VDD_IO
IoT Resources
Cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right IoT device for your
design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of
information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software
updates. Customers can acquire technical documentation and software from the Cypress Support Community website 
(http://community.cypress.com/).
Document Number: 002-14824 Rev. *J
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CYW20730
Contents
1. Functional Description ................................................. 5
1.1 Keyboard Scanner ................................................. 5
1.2 Mouse Quadrature Signal Decoder ....................... 6
1.3 Shutter Control for 3D Glasses ............................. 6
1.4 Infrared Modulator ................................................. 7
1.5 Infrared Learning ................................................... 7
1.6 Triac Control .......................................................... 8
1.7 Broadcom Proprietary Control Signaling and
Triggered Broadcom Fast Connect ...................... 8
1.8 Bluetooth Baseband Core ..................................... 8
1.9 ADC Port ............................................................... 9
1.10 Serial Peripheral Interface ................................. 10
1.11 Microprocessor Unit .......................................... 12
1.12 Integrated Radio Transceiver ............................ 14
1.13 Peripheral Transport Unit .................................. 15
1.14 Clock Frequencies ............................................. 15
1.15 GPIO Port .......................................................... 17
Document Number: 002-14824 Rev. *J
1.16 PWM .................................................................. 18
1.17 Power Management Unit ................................... 19
2. Pin Assignments ........................................................ 20
2.1 Pin Descriptions .................................................. 20
2.2 Ball Maps ............................................................. 28
3. Specifications ............................................................. 31
3.1 Electrical Characteristics ..................................... 31
3.2 RF Specifications ................................................ 34
3.3 Timing and AC Characteristics ............................ 36
4. Mechanical Information ............................................. 41
4.1 Tape Reel and Packaging Specifications ............ 44
5. Ordering Information .................................................. 45
A. Appendix: Acronyms and Abbreviations ................ 46
A.1 References .......................................................... 47
Document History .......................................................... 48
Sales, Solutions, and Legal Information ...................... 50
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CYW20730
1. Functional Description
1.1 Keyboard Scanner
The keyboard scanner is designed to autonomously sample keys and store them into buffer registers without the need for the host
microcontroller to intervene. The scanner has the following features:
■
Ability to turn off its clock if no keys pressed.
■
Sequential scanning of up to 160 keys in an 8 x 20 matrix.
■
Programmable number of columns from 1 to 20.
■
Programmable number of rows from 1 to 8.
■
16-byte key-code buffer (can be augmented by firmware).
■
128 kHz clock – allows scanning of full 160-key matrix in about 1.2 ms.
■
N-key rollover with selective 2-key lockout if ghost is detected.
■
Keys are buffered until host microcontroller has a chance to read it, or until overflow occurs.
■
Hardware debouncing and noise/glitch filtering.
■
Low-power consumption. Single-digit µA-level sleep current.
1.1.1 Theory of Operation
The key scan block is controlled by a state machine with the following states:
Idle
The state machine begins in the idle state. In this state, all column outputs are driven high. If any key is pressed, a transition occurs
on one of the row inputs. This transition causes the 128 kHz clock to be enabled (if it is not already enabled by another peripheral)
and the state machine to enter the scan state. Also in this state, an 8-bit row-hit register and an 8-bit key-index counter is reset to 0.
Scan
In the scan state, a row counter counts from 0 up to a programmable number of rows minus 1. Once the last row is reached, the row
counter is reset and the column counter is incremented. This cycle repeats until the row and column counters are both at their
respective terminal count values. At that point, the state machine moves into the Scan-End state.
As the keys are being scanned, the key-index counter is incremented. This counter is the value compared to the modifier key codes
stored, or in the key-code buffer if the key is not a modifier key. It can be used by the microprocessor as an index into a lookup table
of usage codes.
Also, as the n-th row is scanned, the row-hit register is ORed with the current 8-bit row input values if the current column contains two
or more row hits. During the scan of any column, if a key is detected at the current row, and the row-hit register indicates that a hit
was detected in that same row on a previous column, then a ghost condition may have occurred, and a bit in the status register is set
to indicate this.
Scan End
This state determines whether any keys were detected while in the scan state. If yes, the state machine returns to the scan state. If
no, the state machine returns to the idle state, and the 128 kHz clock request signal is made inactive.
The microcontroller can poll the key status register.
Document Number: 002-14824 Rev. *J
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CYW20730
1.2 Mouse Quadrature Signal Decoder
The mouse signal decoder is designed to autonomously sample two quadrature signals commonly generated by optomechanical
mouse apparatus. The decoder has the following features:
■
Three pairs of inputs for X, Y, and Z (typical scroll wheel) axis signals. Each axis has two options:
For the X axis, choose P2 or P32 as X0 and P3 or P33 as X1.
❐ For the Y axis, choose P4 or P34 as Y0 and P5 or P35 as Y1.
❐ For the Z axis, choose P6 or P36 as Z0 and P7 or P37 as Z1.
❐
■
Control of up to four external high current GPIOs to power external optoelectronics:
Turn-on and turn-off time can be staggered for each HC-GPIO to avoid simultaneous switching of high currents and having multiple
high-current devices on at the same time.
❐ Sample time can be staggered for each axis.
❐ Sense of the control signal can be active high or active low.
❐ Control signal can be tristated for off condition or driven high or low, as appropriate.
❐
1.2.1 Theory of Operation
The mouse decoder block has four 16-bit PWMs for controlling external quadrature devices and sampling the quadrature inputs at its
core.
The GPIO signals may be used to control such items as LEDs, external ICs that may emulate quadrature signals, photodiodes, and
photodetectors.
1.3 Shutter Control for 3D Glasses
The CYW20730, combined with the CYW20702, provides full system support for 3D glasses on televisions. The CYW20702 gets
frame synchronization signals from the TV, converts them into proprietary timing control messages, then passes these messages to
the CYW20730. The CYW20730 uses these messages to synchronize the shutter control for the 3D glasses with the television frames.
The CYW20730 can provide up to four synchronized control signals for left and right eye shutter control. These four lines can output
pulses with microsecond resolution for on and off timing. The total cycle time can be set for any period up to 65535 msec. The pulses
are synchronized to each other for left and right eye shutters.
The CYW20730 seamlessly adjusts the timing of the control signals based on control messages from the CYW20702, ensuring that
the 3D glasses remain synchronized to the TV display frame.
3D hardware control on the CYW20730 works independently of the rest of the system. The CYW20730 negotiates sniff with the
CYW20702 and, except for sniff resynchronization periods, most of the CYW20730 circuitry remains in a low power state while the
3D glasses subsystem continues to provide shutter timing and control pulses. This significantly reduces total system power
consumption.
The CYW20730A2 has the new BT SIG 3DG profile, as well as legacy mode 3DG, included in ROM. This allows it to support a smaller
and lower cost external memory of 4 KB.
Document Number: 002-14824 Rev. *J
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CYW20730
1.4 Infrared Modulator
The CYW20730 includes hardware support for infrared TX. The hardware can transmit both modulated and unmodulated waveforms.
For modulated waveforms, hardware inserts the desired carrier frequency into all IR transmissions. IR TX can be sourced from
firmware-supplied descriptors, a programmable bit, or the peripheral UART transmitter.
If descriptors are used, they include IR on/off state and the duration between 1–32767 µsec. The CYW20730 IR TX firmware driver
inserts this information in a hardware FIFO and makes sure that all descriptors are played out without a glitch due to underrun. See
Figure 2.
Figure 2. Infrared TX
1.5 Infrared Learning
The CYW20730 includes hardware support for infrared learning. The hardware can detect both modulated and unmodulated signals.
For modulated signals, the CYW20730 can detect carrier frequencies between 10 kHz and 500 kHz and the duration that the signal
is present or absent. The CYW20730 firmware driver supports further analysis and compression of learned signal. The learned signal
can then be played back through the CYW20730 IR TX subsystem. See Figure 3.
Figure 3. Infrared RX
Document Number: 002-14824 Rev. *J
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CYW20730
1.6 Triac Control
The CYW20730 includes hardware support for zero-crossing detection and trigger control for up to four triacs. The CYW20730 detects
zero-crossing on the AC zero detection line and uses that to provide a pulse that is offset from the zero-crossing. This allows the
CYW20730 to be used in dimmer applications, as well as any other applications that require a control signal that is offset from an
input event.
1.7 Broadcom Proprietary Control Signaling and Triggered Broadcom Fast Connect
Broadcom Proprietary Control Signaling (BPCS) and Triggered Broadcom Fast Connect (TBFC) are Broadcom-proprietary baseband
(ACL) suspension and low latency reconnection mechanisms that reestablish the baseband connection with the peer controller that
also supports BPCS/TBFC.
The CYW20730 uses BPCS primitives to allow a Human Interface Device (HID) to suspend all RF traffic after a configurable idle
period with no reportable activity. To conserve power, it can then enter one of its low power states while still logically remaining
connected at the L2CAP and HID layers with the peer device. When an event requires the HID to deliver a report to the peer device,
the CYW20730 uses the TBFC and BPCS mechanisms to reestablish the baseband connection and can immediately resume L2CAP
traffic, greatly reducing latency between the event and delivery of the report to the peer device.
Certain applications may make use of the CYW20730 Baseband Fast Connect (BFC) mechanism for power savings and lower
latencies not achievable by using even long sniff intervals by completely eliminating the need to maintain an RF link, while still being
able to establish ACL and L2CAP connections much faster than regular methods.
1.8 Bluetooth Baseband Core
The Bluetooth Baseband Core (BBC) implements all of the time-critical functions required for high performance Bluetooth operation.
The BBC manages the buffering, segmentation, and data routing for all connections. It also buffers data that passes through it, handles
data flow control, schedules ACL TX/RX transactions, monitors Bluetooth slot usage, optimally segments and packages data into
baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition to these functions, it
independently handles HCI event types and HCI command types.
The following transmit and receive functions are also implemented in the BBC hardware to increase TX/RX data reliability and security
before sending over the air:
■
Receive Functions: symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic
redundancy check (CRC), data decryption, and data dewhitening.
■
Transmit Functions: data framing, FEC generation, HEC generation, CRC generation, link key generation, data encryption, and
data whitening.
1.8.1 Frequency Hopping Generator
The frequency hopping sequence generator selects the correct hopping channel number depending on the link controller state,
Bluetooth clock, and device address.
1.8.2 E0 Encryption
The encryption key and the encryption engine are implemented using dedicated hardware to reduce software complexity and provide
minimal processor intervention.
1.8.3 Link Control Layer
The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the Link Control Unit
(LCU). This layer consists of the Command Controller, which takes software commands, and other controllers that are activated or
configured by the Command Controller to perform the link control tasks. Each task performs a different Bluetooth link controller state.
STANDBY and CONNECTION are the two major states. In addition, there are five substates: page, page scan, inquiry, inquiry scan,
and sniff.
1.8.4 Adaptive Frequency Hopping
The CYW20730 gathers link quality statistics on a channel-by-channel basis to facilitate channel assessment and channel map
selection. The link quality is determined by using both RF and baseband signal processing to provide a more accurate frequency hop
map.
Document Number: 002-14824 Rev. *J
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CYW20730
1.8.5 Bluetooth Version 3.0 Features
The CYW20730 supports Bluetooth 3.0, including the following options:
■
Enhanced Power Control
■
Unicast Connectionless Data
■
HCI Read Encryption Key Size command
The CYW20730 also supports the following Bluetooth version 2.1 features:
■
Extended Inquiry Response
■
Sniff Subrating
■
Encryption Pause and Resume
■
Secure Simple Pairing
■
Link Supervision Timeout Changed Event
■
Erroneous Data Reporting
■
Non-Automatically-Flushable Packet Boundary Flag
■
Security Mode 4
1.8.6 Test Mode Support
The CYW20730 fully supports Bluetooth Test mode, as described in Part 1 of the Bluetooth 3.0 specification. This includes the
transmitter tests, normal and delayed loopback tests, and the reduced hopping sequence.
In addition to the standard Bluetooth Test mode, the device supports enhanced testing features to simplify RF debugging and qualification as well as type-approval testing.
1.9 ADC Port
The CYW20730 contains a 16-bit ADC (effective number of bits is 10).
Additionally:
■
There are 28 analog input channels in the 64-pin package, 12 analog input channels in the 40-pin package, and 9 analog input
channels in the 32-pin package. All channels are multiplexed on various GPIOs.
■
The conversion time is 10 s.
■
There is a built-in reference with supply- or band-gap based reference modes.
■
The maximum conversion rate is 187 kHz.
■
There is a rail-to-rail input swing.
The ADC consists of an analog ADC core that performs the actual analog-to-digital conversion and digital hardware that processes
the output of the ADC core into valid ADC output samples. Directed by the firmware, the digital hardware also controls the input
multiplexers that select the ADC input signal Vinp and the ADC reference signals Vref.
Table 2. ADC Modes
Mode
ENOB (Typical)
Maximum Sampling Rate (kHz)
Latencya (s)
0
13
5.859
171
1
12.6
11.7
85
2
12
46.875
21
3
11.5
93.75
11
4
10
187
5
a. Settling time after switching channels.
Document Number: 002-14824 Rev. *J
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CYW20730
1.10 Serial Peripheral Interface
The CYW20730 has two independent SPI interfaces. One is a master-only interface and the other can be either a master or a slave.
Each interface has a 16-byte transmit buffer and a 16-byte receive buffer. To support more flexibility for user applications, the
CYW20730 has optional I/O ports that can be configured individually and separately for each functional pin, as shown in Table 3. The
CYW20730 acts as an SPI master device that supports 1.8V or 3.3V SPI slaves, as shown in Table 3. The CYW20730 can also act
as an SPI slave device that supports a 1.8V or 3.3V SPI master, as shown in Table 3.
Table 3. CYW20730 First SPI Set (Master Mode)
SPI_CLK
SPI_MOSI
SPI_MISO
SPI_CSa
Configuration set 1
SCL
SDA
P24
–
Configuration set 2
SCL
SDA
P26
–
Configuration set 3
(Default for serial flash)
SCL
SDA
P32
P33
Configuration set 4
SCL
SDA
P39
–
Pin Name
a. Any GPIO can be used as SPI_CS when SPI is in master mode.
Table 4. CYW20730 Second SPI Set (Master Mode)
SPI_CLK
SPI_MOSI
SPI_MISO
SPI_CSa
Configuration set 1
P3
P0
P1
–
Configuration set 2
P3
P0
P5
–
Configuration set 3
P3
P2
P1
–
Configuration set 4
P3
P2
P5
–
Configuration set 5
P3
P4
P1
–
Configuration set 6
P3
P4
P5
–
Configuration set 7
P3
P27
P1
–
Configuration set 8
P3
P27
P5
–
Configuration set 9
P3
P38
P1
–
Configuration set 10
P3
P38
P5
–
Configuration set 11
P7
P0
P1
–
Configuration set 12
P7
P0
P5
–
Configuration set 13
P7
P2
P1
–
Configuration set 14
P7
P2
P5
–
Configuration set 15
P7
P4
P1
–
Pin Name
Configuration set 16
P7
P4
P5
–
Configuration set 17
P7
P27
P1
–
Configuration set 18
P7
P27
P5
–
Configuration set 19
P7
P38
P1
–
Configuration set 20
P7
P38
P5
–
Configuration set 21
P24
P0
P25
–
Configuration set 22
P24
P2
P25
–
Configuration set 23
P24
P4
P25
–
Configuration set 24
P24
P27
P25
–
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CYW20730
Table 4. CYW20730 Second SPI Set (Master Mode) (Cont.)
SPI_CLK
SPI_MOSI
SPI_MISO
SPI_CSa
Configuration set 25
P24
P38
P25
–
Configuration set 26
P36
P0
P25
–
Configuration set 27
P36
P2
P25
–
Configuration set 28
P36
P4
P25
–
Configuration set 29
P36
P27
P25
–
Configuration set 30
P36
P38
P25
–
Pin Name
a. Any GPIO can be used as SPI_CS when SPI is in master mode.
Table 5. CYW20730 Second SPI Set (Slave Mode)a
SPI_CLK
SPI_MOSI
SPI_MISO
SPI_CS
Configuration set 1
Pin Name
P3
P0
P1
P2
Configuration set 2
P3
P0
P5
P2
Configuration set 3
P3
P4
P1
P2
Configuration set 4
P3
P4
P5
P2
Configuration set 5
P7
P0
P1
P2
Configuration set 6
P7
P0
P5
P2
Configuration set 7
P7
P4
P1
P2
Configuration set 8
P7
P4
P5
P2
Configuration set 9
P3
P0
P1
P6
Configuration set 10
P3
P0
P5
P6
Configuration set 11
P3
P4
P1
P6
Configuration set 12
P3
P4
P5
P6
Configuration set 13
P7
P0
P1
P6
Configuration set 14
P7
P0
P5
P6
Configuration set 15
P7
P4
P1
P6
Configuration set 16
P7
P4
P5
P6
Configuration set 17
P24
P27
P25
P26
Configuration set 18
P24
P33
P25
P26
Configuration set 19
P24
P38
P25
P26
Configuration set 20
P36
P27
P25
P26
Configuration set 21
P36
P33
P25
P26
Configuration set 22
P36
P38
P25
P26
Configuration set 23
P24
P27
P25
P32
Configuration set 24
P24
P33
P25
P32
Configuration set 25
P24
P38
P25
P32
Configuration set 26
P36
P27
P25
P32
Configuration set 27
P36
P33
P25
P32
Configuration set 28
P36
P38
P25
P32
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CYW20730
Table 5. CYW20730 Second SPI Set (Slave Mode)a
SPI_CLK
SPI_MOSI
SPI_MISO
SPI_CS
Configuration set 29
Pin Name
P24
P27
P25
P39
Configuration set 30
P24
P33
P25
P39
Configuration set 31
P24
P38
P25
P39
Configuration set 32
P36
P27
P25
P39
Configuration set 33
P36
P33
P25
P39
Configuration set 34
P36
P38
P25
P39
a. Additional configuration sets are available upon request.
1.11 Microprocessor Unit
The CYW20730 microprocessor unit (µPU) executes software from the link control (LC) layer up to the application layer components
that ensure adherence to the Bluetooth Human Interface Device (HID) profile and Audio/Video Remote Control Profile (AVRCP). The
microprocessor is based on an ARM Cortex™-M3, 32-bit RISC processor with embedded ICE-RT debug and JTAG interface units.
The µPU has 320 KB of ROM for program storage and boot-up, 60 KB of RAM for scratch-pad data, and patch RAM code.
The internal boot ROM provides power-on reset flexibility, which enables the same device to be used in different HID applications with
an external serial EEPROM or with an external serial flash memory. At power-up, the lowest layer of the protocol stack is executed
from the internal ROM memory.
External patches may be applied to the ROM-based firmware to provide flexibility for bug fixes and feature additions. The device can
also support the integration of user applications.
1.11.1 EEPROM Interface
The CYW20730 provides a Broadcom Serial Control (BSC) master interface. The BSC is programmed by the CPU to generate four
types of BSC bus transfers: read-only, write-only, combined read/write, and combined write/read. BSC supports both low-speed and
fast mode devices. The BSC is compatible with a Philips® (now NXP) I2C slave device, except that master arbitration (multiple I2C
masters contending for the bus) is not supported.
The EEPROM can contain customer application configuration information including: application code, configuration data, patches,
pairing information, BD_ADDR, baud rate, SDP service record, and file system information used for code.
Native support for the Microchip® 24LC128, Microchip 24AA128, and ST Micro® M24128-BR is included.
1.11.2 Serial Flash Interface
The CYW20730 includes an SPI master controller that can be used to access serial flash memory. The SPI master contains an AHB
slave interface, transmit and receive FIFOs, and the SPI core PHY logic.
Devices natively supported include the following:
■
Atmel® AT25BCM512B
■
MXIC® MX25V512ZUI-20G
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CYW20730
1.11.3 Internal Reset
Figure 4. Internal Reset Timing
VDDO POR delay
~ 2 ms
VDDO
VDDO POR threshold
VDDO POR
VDDC POR threshold
VDDC
VDDC POR delay
~ 2 ms
VDDC POR
Crystal
warm‐up
delay:
~ 5 ms
Baseband Reset
Start reading EEPROM and
firmware boot
Crystal Enable
1.11.4 External Reset
The CYW20730 has an integrated power-on reset circuit that completely resets all circuits to a known power-on state. An external
active low reset signal, RESET_N, can be used to put the CYW20730 in the reset state. The RESET_N pin has an internal pull-up
resistor and, in most applications, it does not require that anything be connected to it. RESET_N should only be released after the
VDDO supply voltage level has been stabilized.
Figure 5. External Reset Timing
Pulse width
>50 µs
RESET_N
Crystal
warm‐up
delay:
~ 5 ms
Baseband Reset
Start reading EEPROM and
firmware boot
Crystal Enable
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CYW20730
1.12 Integrated Radio Transceiver
The CYW20730 has an integrated radio transceiver that is optimized for 2.4 GHz Bluetooth® wireless systems. It has been designed
to provide low power, low cost, and robust communications for applications operating in the globally available 2.4 GHz unlicensed
ISM band. It is fully compliant with Bluetooth Radio Specification 3.0 and meets or exceeds the requirements to provide the highest
communication link quality of service.
1.12.1 Transmitter Path
The CYW20730 features a fully integrated transmitter. The baseband transmit data is GFSK modulated in the 2.4 GHz ISM band.
Digital Modulator
The digital modulator performs the data modulation and filtering required for the GFSK signal. The fully digital modulator minimizes
any frequency drift or anomalies in the modulation characteristics of the transmitted signal.
Power Amplifier
The CYW20730 has an integrated power amplifier (PA) that can transmit up to +4 dBm for class 2 operation.
1.12.2 Receiver Path
The receiver path uses a low IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit
synchronizer. The receiver path provides a high degree of linearity, an extended dynamic range, and high-order, on-chip channel
filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology, which has built-in out-of-band attenuation,
enables the CYW20730 to be used in most applications without off-chip filtering.
Digital Demodulator and Bit Synchronizer
The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit
synchronization algorithm.
Receiver Signal Strength Indicator
The radio portion of the CYW20730 provides a receiver signal strength indicator (RSSI) to the baseband. This enables the controller
to take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the
transmitter should increase or decrease its output power.
1.12.3 Local Oscillator
The local oscillator (LO) provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. The
CYW20730 uses an internal loop filter.
1.12.4 Calibration
The CYW20730 radio transceiver features a self-contained automated calibration scheme. No user interaction is required during
normal operation or during manufacturing to provide optimal performance. Calibration compensates for filter, matching network, and
amplifier gain and phase characteristics to yield radio performance within 2% of what is optimal. Calibration takes process and
temperature variations into account, and it takes place transparently during normal operation and hop setting times.
1.12.5 Internal LDO Regulator
The CYW20730 has an integrated 1.2V LDO regulator that provides power to the digital and RF circuits. The 1.2V LDO regulator
operates from a 1.425V to 3.63V input supply with a 30 mA maximum load current.
Note: Always place the decoupling capacitors near the pins as closely together as possible.
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CYW20730
1.13 Peripheral Transport Unit
1.13.1 Broadcom Serial Communications Interface
The CYW20730 provides a 2-pin master BSC interface, which can be used to retrieve configuration information from an external
EEPROM or to communicate with peripherals such as track-ball or touch-pad modules, and motion tracking ICs used in mouse
devices. The BSC interface is compatible with I2C slave devices. The BSC does not support multimaster capability or flexible waitstate insertion by either master or slave devices.
The following transfer clock rates are supported by the BSC:
■
100 kHz
■
400 kHz
■
800 kHz (Not a standard I2C-compatible speed.)
■
1 MHz (Compatibility with high-speed I2C-compatible devices is not guaranteed.)
The following transfer types are supported by the BSC:
■
Read (Up to 16 bytes can be read.)
■
Write (Up to 16 bytes can be written.)
■
Read-then-Write (Up to 16 bytes can be read and up to 16 bytes can be written.)
■
Write-then-Read (Up to 16 bytes can be written and up to 16 bytes can be read.)
Hardware controls the transfers, requiring minimal firmware setup and supervision.
The clock pin (SCL) and data pin (SDA) are both open-drain I/O pins. Pull-up resistors external to the CYW20730 are required on
both the SCL and SDA pins for proper operation.
1.13.2 UART Interface
The UART is a standard 2-wire interface (RX and TX) and has adjustable baud rates from 9600 bps to 1.5 Mbps. The baud rate can
be selected via a vendor-specific UART HCI command. The interface supports the Bluetooth 3.0 UART HCI (H5) specification. The
default baud rate for H5 is 115.2 kbaud.
Both high and low baud rates can be supported by running the UART clock at 24 MHz.
The CYW20730 UART operates correctly with the host UART as long as the combined baud rate error of the two devices is within ±5%.
1.14 Clock Frequencies
The CYW20730 is set with crystal frequency of 24 MHz.
1.14.1 Crystal Oscillator
The crystal oscillator requires a crystal with an accuracy of ±20 ppm as defined by the Bluetooth specification. Two external load
capacitors in the range of 5 pF to 30 pF are required to work with the crystal oscillator. The selection of the load capacitors is crystal
dependent. Table 6 on page 16 shows the recommended crystal specification.
Figure 6. Recommended Oscillator Configuration — 12 pF Load Crystal
22 pF
XIN
Crystal
XOUT
20 pF
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CYW20730
Table 6. Reference Crystal Electrical Specifications
Conditions
Minimum
Typical
Maximum
Unit
Nominal frequency
Parameter
–
–
24.000
–
MHz
Oscillation mode
–
Fundamental
@25°C
–
±10
Tolerance stability over temp
@0°C to +70°C
–
Equivalent series resistance
–
–
Load capacitance
–
Operating temperature range
–
–
ppm
±10
–
ppm
–
50
W
–
12
–
pF
–
0
–
+70
°C
Storage temperature range
–
–40
–
+125
°C
Drive level
–
–
–
200
W
Aging
–
–
–
±10
ppm/year
Shunt capacitance
–
–
–
2
pF
Frequency tolerance
HID Peripheral Block
The peripheral blocks of the CYW20730 all run from a single 128 kHz low-power RC oscillator. The oscillator can be turned on at the
request of any of the peripherals. If the peripheral is not enabled, it shall not assert its clock request line.
The keyboard scanner is a special case in that it may drop its clock request line even when enabled and then reassert the clock
request line if a keypress is detected.
32 kHz Crystal Oscillator
Figure 7 shows the 32 kHz crystal (XTAL) oscillator with external components and Table 7 on page 17 lists the oscillator’s characteristics. It is a standard Pierce oscillator using a comparator with hysteresis on the output to create a single-ended digital output. The
hysteresis was added to eliminate any chatter when the input is around the threshold of the comparator and is ~100 mV. This circuit
can be operated with a 32 kHz or 32.768 kHz crystal oscillator or be driven with a clock input at similar frequency. The default
component values are: R1 = 10 M, C1 = C2 = ~10 pF. The values of C1 and C2 are used to fine-tune the oscillator.
Figure 7. 32 kHz Oscillator Block Diagram
C2
R1
32.768 kHz
XTAL
C1
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CYW20730
Table 7. XTAL Oscillator Characteristics
Parameter
Symbol
Conditions
Minimum
Typical
Maximum
Unit
Output frequency
Foscout
–
–
32.768
–
kHz
–
Crystal dependent
–
100
–
ppm
Tstartup
–
–
–
500
ms
Pdrv
For crystal selection
0.5
–
–
W
XTAL series
resistance
Rseries
For crystal selection
–
–
70
k
XTAL shunt
capacitance
Cshunt
For crystal selection
–
–
1.3
pF
Frequency
tolerance
Start-up time
XTAL drive level
1.15 GPIO Port
The CYW20730 has 14 general-purpose I/Os (GPIOs) in the 32-pin package, 22 GPIOs in the 40-pin package, and 40 GPIOs in the
64-pin package. All GPIOs support programmable pull-up and pull-down resistors, and all support a 2 mA drive strength except P26,
P27, P28, and P29, which provide a 16 mA drive strength at 3.3V supply.
1.15.1 Port 0–Port 1, Port 8–Port 23, and Port 28–Port 38
All of these pins can be programmed as ADC inputs.
1.15.2 Port 26–Port 29
P[26:29] consists of four pins. All pins are capable of sinking up to 16 mA for LED. These pins also have the PWM function, which
can be used for LED dimming.
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CYW20730
1.16 PWM
The CYW20730 has four internal PWM channels. The PWM module consists of the following:
■
■
PWM1–4
Each of the four PWM channels, PWM1–4, contains the following registers:
10-bit initial value register (read/write)
❐ 10-bit toggle register (read/write)
❐ 10-bit PWM counter value register (read)
❐
The PWM configuration register is shared among PWM1–4 (read/write). This 12-bit register is used:
To configure each PWM channel.
❐ To select the clock of each PWM channel
❐ To change the phase of each PWM channel
Figure 8 shows the structure of one PWM channel.
■
❐
Figure 8. PWM Channel Block Diagram
pwm_cfg_adr register
pwm#_init_val_adr register
pwm#_togg_val_adr register
enable
clk_sel
o_flip
10
10
pwm#_cntr_adr
10
cntr value is CM3 readable
pwm_out
Example: PWM cntr w/ pwm#_init_val = 0 (dashed line)
PWM cntr w/ pwm#_init_val = x (solid line)
10'H3FF
pwm_togg_val_adr
10'Hx
10'H000
pwm_out
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CYW20730
1.17 Power Management Unit
The Power Management Unit (PMU) provides power management features that can be invoked by software through power
management registers or packet-handling in the baseband core.
1.17.1 RF Power Management
The BBC generates power-down control signals for the transmit path, receive path, PLL, and power amplifier to the 2.4 GHz transceiver, which then processes the power-down functions accordingly.
1.17.2 Host Controller Power Management
Power is automatically managed by the firmware based on input device activity. As a power-saving task, the firmware controls the
disabling of the on-chip regulator when in deep Sleep mode.
1.17.3 BBC Power Management
There are several low-power operations for the BBC:
■
Physical layer packet handling turns RF on and off dynamically within packet TX and RX.
■
Bluetooth-specified low-power connection sniff mode. While in these low-power connection modes, the CYW20730 runs on the
Low Power Oscillator and wakes up after a predefined time period.
The CYW20730 automatically adjusts its power dissipation based on user activity. The following power modes are supported:
■
Active mode
■
Idle mode
■
Sleep mode
■
HIDOFF mode
The CYW20730 transitions to the next lower state after a programmable period of user inactivity. Busy mode is immediately entered
when user activity resumes.
In HIDOFF mode, the CYW20730 baseband and core are powered off by disabling power to LDOOUT. The VDDO domain remains
powered up and will turn the remainder of the chip on when it detects user events. This mode minimizes chip power consumption and
is intended for long periods of inactivity.
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CYW20730
2. Pin Assignments
2.1 Pin Descriptions
Table 8. Pin Descriptions
Pin Number
32-Pin QFN
40-pin QFN
64-pin BGA
Pin Name
I/O
Power Domain
Description
Radio I/O
6
8
F1
RF
I/O
VDD_RF
RF antenna port
4
6
D1
VDDIF
I
VDD_RF
IFPLL power supply
5
7
E1
VDDFE
I
VDD_RF
RF front-end supply
7
9
H1
VDDVCO
I
VDD_RF
VCO, LOGEN supply
8
10
H2
VDDPLL
I
VDD_RF
RFPLL and crystal oscillator supply
RF Power Supplies
Power Supplies
11
13
H6
VDDC
I
N/A
Baseband core supply
–
–
D4, E2, E5,
F2, G1, G2
VSS
I
N/A
Ground
28
34
A6, D7
VDDO
I
VDDO
I/O pad and core supply
14
16
–
VDDM
I
VDDM
I/O pad supply
Clock Generator and Crystal Interface
9
11
H3
XTALI
I
VDD_RF
Crystal oscillator input. See “Crystal
Oscillator” on page 15 for options.
10
12
G3
XTALO
O
VDD_RF
Crystal oscillator output.
Low-power oscillator (LPO) input is
used.
Alternative Function:
1
40
A3
XTALI32K
I
VDDO
■
P11 and P27 in 32-QFN only
■
P11 in 40-QFN only
■
P39 in 64-BGA only
Low-power oscillator (LPO) output.
Alternative Function:
32
39
B3
XTALO32K
O
VDDO
■
P12 and P26 in 32-QFN only
■
P12 in 40-QFN only
■
P38 in 64-BGA only
Core
18
20
G8
RESET_N
I/O PU
VDDO
Active-low system reset with open-drain
output & internal pull-up resistor
17
19
G7
TMC
I
VDDO
Test mode control
High: test mode
Connect to GND if not used.
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CYW20730
Table 8. Pin Descriptions (Cont.)
Pin Number
32-Pin QFN
40-pin QFN
64-pin BGA
Pin Name
I/O
Power Domain
Description
UART
12
14
H5
UART_RXD
I
VDDMa
UART serial input – Serial data input for
the HCI UART interface. Leave unconnected if not used.
Alternative function:
■
13
15
G5
UART_TXD
O, PU
VDDMa
GPIO3
UART serial output – Serial data output
for the HCI UART interface. Leave
unconnected if not used.
Alternative Function:
■
GPIO2
BSC
Data signal for an external I2C device.
Alternative function:
15
17
F7
SDA
I/O, PU
VDDMa
■
SPI_1: MOSI (master only)
■
GPIO0
■
CTS
Clock signal for an external I2C device.
Alternative function:
16
18
E8
SCL
I/O, PU
VDDMa
■
SPI_1: SPI_CLK (master only)
■
GPIO1
■
RTS
LDO Regulator Power Supplies
2
4
B1
LDOIN
I
LDO
Battery input supply for the LDO
3
5
C1
LDOOUT
O
LDO
LDO output
a. VDDO for 64-pin package.
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CYW20730
Table 9. GPIO Pin Descriptionsa
Pin Number
32-Pin
QFN
19
20
22
21
23
40-pin
QFN
21
22
24
23
25
64-pin
BGA
F6
G6
H8
F8
H7
Pin Name
P0
P1
P2
P3
P4
Document Number: 002-14824 Rev. *J
Default Direction
Input
Input
Input
Input
Input
After POR
Floating
Floating
Floating
Floating
Floating
Power
Domain
VDDO
VDDO
VDDO
VDDO
VDDO
Alternate Function Description
■
GPIO: P0
■
Keyboard scan input (row): KSI0
■
A/D converter input
■
Peripheral UART: puart_tx
■
SPI_2: MOSI (master and slave)
■
IR_RX
■
60 Hz_main
■
Not available during TMC=1
■
GPIO: P1
■
Keyboard scan input (row): KSI1
■
A/D converter input
■
Peripheral UART: puart_rts
■
SPI_2: MISO (master and slave)
■
IR_TX
■
GPIO: P2
■
Keyboard scan input (row): KSI2
■
Quadrature: QDX0
■
Peripheral UART: puart_rx
■
Triac control 2
■
SPI_2: SPI_CS (slave only)
■
SPI_2: SPI_MOSI (master only)
■
GPIO: P3
■
Keyboard scan input (row): KSI3
■
Quadrature: QDX1
■
Peripheral UART: puart_cts
■
SPI_2: SPI_CLK (master and slave)
■
GPIO: P4
■
Keyboard scan input (row): KSI4
■
Quadrature: QDY0
■
Peripheral UART: puart_rx
■
SPI_2: MOSI (master and slave)
■
IR_TX
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CYW20730
Table 9. GPIO Pin Descriptionsa (Cont.)
Pin Number
32-Pin
QFN
–
–
–
24
40-pin
QFN
26
27
28
29
64-pin
BGA
E6
F5
C5
F4
Pin Name
P5
P6
PWM2
P7
P8
Default Direction
Input
Input
Input
Input
After POR
Floating
Floating
Floating
Floating
Power
Domain
VDDO
VDDO
VDDO
VDDO
Alternate Function Description
■
GPIO: P5
■
Keyboard scan input (row): KSI5
■
Quadrature: QDY1
■
Peripheral UART: puart_tx
■
SPI_2: MISO (master and slave)
■
GPIO: P6
■
Keyboard scan input (row): KSI6
■
Quadrature: QDZ0
■
Peripheral UART: puart_rts
■
SPI_2: SPI_CS (slave only)
■
60Hz_main
■
Triac control 1
■
GPIO: P7
■
Keyboard scan input (row): KSI7
■
Quadrature: QDZ1
■
Peripheral UART: puart_cts
■
SPI_2: SPI_CLK (master and slave)
■
GPIO: P8
■
Keyboard scan output (column): KSO0
■
A/D converter input
External T/R switch control: ~tx_pd
Alternative Function:
■
–
–
1
3
2
40
A1
D2
C2
P9
P10
PWM3
P11
Input
Input
Input
Floating
Floating
Floating
VDDO
VDDO
VDDO
■
P33 in 32-QFN only
■
GPIO: P9
■
Keyboard scan output (column): KSO1
■
A/D converter input
■
External T/R switch control: tx_pd
■
GPIO: P10
■
Keyboard scan output (column): KSO2
■
A/D converter input
■
GPIO: P11
■
Keyboard scan output (column): KSO3
■
A/D converter input
XTALI32K (32-QFN and 40-QFN only)
Alternative Function:
■
■
Document Number: 002-14824 Rev. *J
P27 in 32-QFN only
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CYW20730
Table 9. GPIO Pin Descriptionsa (Cont.)
Pin Number
32-Pin
QFN
32
40-pin
QFN
39
64-pin
BGA
B2
Pin Name
P12
Default Direction
Input
After POR
Floating
Power
Domain
VDDO
Alternate Function Description
■
GPIO: P12
■
Keyboard scan output (column): KSO4
■
A/D converter input
XTALO32K (32-QFN and 40-QFN only)
Alternative Function:
■
29
30
31
–
–
–
–
–
35
36
37
–
–
–
–
–
F3
D3
A2
C8
H4
C7
B8
A8
P13
PWM3
P14
PWM2
P15
P16
P17
P18
P19
P20
Document Number: 002-14824 Rev. *J
Input
Floating
VDDO
■
P26 in 32-QFN only
■
GPIO: P13
■
Keyboard scan output (column): KSO5
■
A/D converter input
Triac control 3
Alternative Function:
■
Input
Floating
VDDO
■
P28 in 32-QFN only
■
GPIO: P14
■
Keyboard scan output (column): KSO6
■
A/D converter input
Triac control 4
Alternative Function:
■
Input
Input
Input
Input
Input
Input
Floating
Floating
Floating
Floating
Floating
Floating
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
■
P38 in 32-QFN only
■
GPIO: P15
■
Keyboard scan output (column): KSO7
■
A/D converter input
■
IR_RX
■
60Hz_main
■
GPIO: P16
■
Keyboard scan output (column): KSO8
■
GPIO: P17
■
Keyboard scan output (column): KSO9
■
A/D converter input
■
GPIO: P18
■
Keyboard scan output (column): KSO10
■
A/D converter input
■
GPIO: P19
■
Keyboard scan output (column): KSO11
■
A/D converter input
■
GPIO: P20
■
Keyboard scan output (column): KSO12
■
A/D converter input
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CYW20730
Table 9. GPIO Pin Descriptionsa (Cont.)
Pin Number
32-Pin
QFN
–
–
–
27
26
32
40-pin
QFN
–
–
–
33
32
38
64-pin
BGA
C6
G4
E3
A7
B7
A4
Pin Name
P21
P22
P23
P24
P25
P26
PWM0
Default Direction
Input
Input
Input
Input
Input
Input
After POR
Floating
Floating
Floating
Floating
Floating
Floating
Power
Domain
VDDO
VDDO
VDDO
VDDO
VDDO
VDDO
Alternate Function Description
■
GPIO: P21
■
Keyboard scan output (column): KSO13
■
A/D converter input
■
Triac control 3
■
GPIO: P22
■
Keyboard scan output (column): KSO14
■
A/D converter input
■
Triac control 4
■
GPIO: P23
■
Keyboard scan output (column): KSO15
■
A/D converter input
■
GPIO: P24
■
Keyboard scan output (column): KSO16
■
SPI_2: SPI_CLK (master and slave)
■
SPI_1: MISO (master only)
■
Peripheral UART: puart_tx
■
GPIO: P25
■
Keyboard scan output (column): KSO17
■
SPI_2: MISO (master and slave)
■
Peripheral UART: puart_rx
■
GPIO: P26
■
Keyboard scan output (column): KSO18
■
SPI_2: SPI_CS (slave only)
■
SPI_1: MISO (master only)
■
Optical control output: QOC0
Triac control 1
Alternative Function:
■
P12 in 32-QFN only
Current: 16 mA
■
1
1
B4
P27
PWM1
Input
Floating
VDDO
■
GPIO: P27
■
Keyboard scan output (column): KSO19
■
SPI_2: MOSI (master and slave)
■
Optical control output: QOC1
Triac control 2
Alternative Function:
■
P11 in 32-QFN only
Current: 16 mA
■
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CYW20730
Table 9. GPIO Pin Descriptionsa (Cont.)
Pin Number
32-Pin
QFN
29
40-pin
QFN
–
64-pin
BGA
B5
Pin Name
P28
PWM2
Default Direction
Input
After POR
Floating
Power
Domain
VDDO
Alternate Function Description
■
GPIO: P28
■
Optical control output: QOC2
■
A/D converter input
■
LED1
IR_TX
Alternative Function:
■
P13 in 32-QFN only
Current: 16 mA
■
–
–
A5
P29
PWM3
Input
Floating
VDDO
■
GPIO: P29
■
Optical control output: QOC3
■
A/D converter input
■
LED2
IR_RX
Current: 16 mA
■
–
–
25
24
–
–
31
30
E4
E7
D6
D8
P30
P31
P32
P33
Input
Input
Input
Input
Floating
Floating
Floating
Floating
VDDO
VDDO
VDDO
VDDO
■
GPIO: P30
■
A/D converter input
■
Pairing button pin in default FW
■
Peripheral UART: puart_rts
■
GPIO: P31
■
A/D converter input
■
EEPROM WP pin in default FW
■
Peripheral UART: puart_tx
■
GPIO: P32
■
A/D converter input
■
Quadrature: QDX0
■
SPI_2: SPI_CS (slave only)
■
SPI_1: MISO (master only)
■
Auxiliary clock output: ACLK0
■
Peripheral UART: puart_tx
■
GPIO: P33
■
A/D converter input
■
Quadrature: QDX1
■
SPI_2: MOSI (slave only)
■
Auxiliary clock output: ACLK1
Peripheral UART: puart_rx
Alternative Function:
■
■
Document Number: 002-14824 Rev. *J
P8 in 32-QFN only
Page 26 of 50
CYW20730
Table 9. GPIO Pin Descriptionsa (Cont.)
Pin Number
32-Pin
QFN
–
–
–
–
30
40-pin
QFN
–
–
–
–
–
64-pin
BGA
B6
D5
C4
C3
B3
Pin Name
P34
P35
P36
P37
P38
Default Direction
Input
Input
Input
Input
Input
After POR
Floating
Floating
Floating
Floating
Floating
Power
Domain
VDDO
VDDO
VDDO
VDDO
VDDO
Alternate Function Description
■
GPIO: P34
■
A/D converter input
■
Quadrature: QDY0
■
Peripheral UART: puart_rx
■
External T/R switch control: tx_pd
■
GPIO: P35
■
A/D converter input
■
Quadrature: QDY1
■
Peripheral UART: puart_cts
■
GPIO: P36
■
A/D converter input
■
Quadrature: QDZ0
■
SPI_2: SPI_CLK (master and slave)
■
Auxiliary Clock Output: ACLK0
■
Battery detect pin in default FW
■
External T/R switch control: ~tx_pd
■
GPIO: P37
■
A/D converter input
■
Quadrature: QDZ1
■
SPI_2: MISO (slave only)
■
Auxiliary clock output: ACLK1
■
GPIO: P38
■
A/D converter input
■
SPI_2: MOSI (master and slave)
■
IR_TX
XTALO32K (64-BGA only)
Alternative Function:
■
–
–
A3
P39
Input
Floating
VDDO
■
P14 in 32-QFN only
■
GPIO: P39
■
SPI_2: SPI_CS (slave only)
■
SPI_1: MISO (master only)
■
Infrared control: IR_RX
■
External PA ramp control: PA_Ramp
■
XTALI32K (64-BGA only)
■
60Hz_main
a. During Power-On Reset, all inputs are disabled.
Document Number: 002-14824 Rev. *J
Page 27 of 50
CYW20730
2.2 Ball Maps
P32
P25
P24
VDDO
P13/P28
P14/P38
P15
P12/P26/XTALO32K
Figure 9. 32-Pin QFN Ball Map
32 31 30 29 28 27 26 25
P11/P27/XTALI32K
1
24
P8/P33
LDO_IN
2
23
P4
LDO_OUT 3
22
P2
VDDIF
4
21
P3
VDDFE
5
20
P1
RF
6
19
P0
VDDVCO
7
18
RST_N
VDDPLL
8
17
TMC
Document Number: 002-14824 Rev. *J
SCL
SDA
VDDM
UART_TXD
UART_RXD
VDDC
10 11 12 13 14 15 16
XTALO
XTALI
9
Page 28 of 50
CYW20730
XTALI32K/P11
XTALO32K/P12
P26/PWM0
P15
P14
P13
VDDO
P24
P25
P32
Figure 10. 40-pin QFN Ball Map
40
39
38
37
36
35
34
33
32
31
28
P7
LDOIN
4
27
P6
LDOOUT
5
26
P5
VDDIF
6
25
P4
VDDFE
7
24
P2
RF
8
23
P3
VDDVCO
9
22
P1
VDDPLL
10
21
P0
11
12
13
14
15
16
17
18
19
20
RESET_N
3
TMC
P9
SCL
P8
SDA
29
VDDM
2
UART_TXD
P10
UART_RXD
P33
VDDC
30
XTALO
1
XTALI
P27/PWM1
Document Number: 002-14824 Rev. *J
Page 29 of 50
CYW20730
Figure 11. 64-pin BGA Ball Map
1
2
3
4
5
6
7
8
A
P9
P15
P39/
XTALI32K
P26/
PWM0
P29/
PWM3
VDDO
P24
P20
A
B
LDOIN
P12
P38/
XTALO32K
P27/
PWM1
P28/
PWM2
P34
P25
P19
B
C
LDOOUT
P11
P37
P36
P7
P21
P18
P16
C
D
VDDIF
P10
P14
VSS
P35
P32
VDDO
P33
D
E
VDDFE
VSS
P23
P30
VSS
P5
P31
SCL
E
F
RF
VSS
P13
P8
P6
P0
SDA
P3
F
G
VSS
VSS
XTALO
P22
UART_
TXD
P1
TMC
RESET
_N
G
H
VDDVCO
VDDPLL
XTALI
P17
UART_
RXD
VDDC
P4
P2
H
1
2
3
4
5
6
7
8
Document Number: 002-14824 Rev. *J
Page 30 of 50
CYW20730
3. Specifications
3.1 Electrical Characteristics
Table 10 shows the maximum electrical rating for voltages referenced to VDD pin.
Table 10. Maximum Electrical Rating
Rating
DC supply voltage for RF domain
DC supply voltage for core domain
DC supply voltage for VDDM domain (UART/I2C)
DC supply voltage for VDDO domain
DC supply voltage for VR3V
DC supply voltage for VDDFE
Voltage on input or output pin
Operating ambient temperature range
Storage temperature range
Symbol
–
–
–
–
–
–
–
Topr
Tstg
Value
1.4
1.4
3.8
3.8
3.8
1.4
VSS – 0.3 to VDD + 0.3
0 to +70
–40 to +125
Unit
V
V
V
V
V
V
V
°C
°C
Table 11 shows the power supply characteristics for the range TJ = 0 to 125°C.
Table 11. Power Supply
Parameter
DC supply voltage for RF
DC supply voltage for Core
DC supply voltage for VDDM (UART/I2C)
DC supply voltage for VDDO
DC supply voltage for LDOIN
DC supply voltage for VDDFE
Supply noise for VDDO (peak-to-peak)
Supply noise for LDOIN (peak-to-peak)
Minimuma
1.14
1.14
1.62
1.62
1.425
1.14
Typical
1.2
1.2
–
–
–
1.2b
–
–
–
–
Maximuma
1.26
1.26
3.63
3.63
3.63
Unit
V
V
V
V
V
1.26
100
100
V
mV
mV
a. Overall performance degrades beyond minimum and maximum supply voltages.
b. 1.2V for Class 2 output with internal VREG.
Document Number: 002-14824 Rev. *J
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CYW20730
Table 13 shows the digital level characteristics for (VSS = 0V).
Table 12. LDO Regulator Electrical Specifications
Parameter
Conditions
Min
Input voltage range
–
Default output voltage
–
Range
Output voltage
Step size
Accuracy at any step
Load current
–
Typ
Max
Unit
1.425
–
3.63
V
–
1.2
–
V
0.8
–
1.4
V
–
40 or 80
–
mV
–5
–
+5
%
–
–
30
mA
–0.2
–
0.2
%VO/V
Line regulation
Vin from 1.425 to 3.63V, Iload = 30 mA
Load regulation
Iload from 1 µA to 30 mA, Vin = 3.3V, Bonding
R = 0.3
–
0.1
0.2
%VO/mA
Quiescent current
No load @Vin = 3.3V
*Current limit enabled
–
6
–
µA
Power-down current
Vin = 3.3V, worst@70°C
–
5
200
nA
Table 13. ADC Specifications
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
ADC Characteristics
Number of Input
channels
–
–
–
28
–
–
Channel switching rate
fch
–
–
–
133.33
kch/s
Vinp
–
0
–
3.63
V
–
Changing refsel
7.5
–
–
s
Input resistance
Rinp
Effective, single-ended
–
500
–
k
Input capacitance
Cinp
–
–
–
5
pF
Conversion rate
fC
–
5.859
–
187
kHz
Conversion time
TC
–
5.35
–
170.7
s
Resolution
R
–
–
16
–
bits
Effective number of bits
–
–
–
See Table 2
on page 9
–
Absolute voltage
measurement error
–
Using on-chip ADC firmware driver
–
±2
–
%
Current
I
Iavdd1p2 + Iavdd3p3
–
–
1
mA
Power
P
–
–
1.5
–
mW
Leakage current
Ileakage
T = 25°C
–
–
100
nA
Power-up time
Input signal range
Reference settling time
Tpowerup
–
–
–
200
s
Integral nonlinearity3
INL
–
–1
–
1
LSBa
Differential nonlinearitya
DNL
–
–1
–
1
LSBa
a. LSBs are expressed at the 10-bit level.
Document Number: 002-14824 Rev. *J
Page 32 of 50
CYW20730
Table 14. Digital Levela
Symbol
Min
Typ
Max
Unit
Input low voltage
Characteristics
VIL
–
–
0.4
V
Input high voltage
VIH
0.75 × VDDO
–
–
V
Input low voltage (VDDO = 1.62V)
VIL
–
–
0.4
V
Input high voltage (VDDO = 1.62V)
VIH
1.2
–
–
V
Output low voltageb
VOL
–
–
0.4
V
Output high voltageb
VOH
VDDO – 0.4
–
–
V
Input capacitance (VDDMEM domain)
CIN
–
0.12
–
pF
a. This table is also applicable to VDDMEM domain.
b. At the specified drive current for the pad.
Table 15. Current Consumption a
Operational Mode
Conditions
Typ
Max
Unit
Receive
Receiver and baseband are both operating, 100% ON.
–
26.6
mA
Transmit
Transmitter and baseband are both operating, 100% ON.
–
24 at 2 dBm, 19 at
0 dBm
mA
DM1
Average current when the device is in the transmit state,
100% utilization of available slots.
15.2
–
mA
DH1
Average current when the device is in the receive state,
100% utilization of available slots.
16.67
–
mA
Sleep
Internal LPO is in use.
28.4
–
A
1.5
–
A
HIDOFF
–
Sniff mode, 11.25 ms
Slave
2.8
–
mA
Sniff mode, 22.5 ms
Slave
1.27
–
mA
Sniff mode, 60 ms
Slave
750
–
A
Sniff mode, 100 ms
Slave
500
–
A
Sniff mode, 495 ms
Slave
125
–
A
a. Current consumption measurements are taken at VBAT with the assumption that VBAT is connected to VDDIO and LDOIN.
Caution: This device is susceptible to permanent damage from electrostatic discharge (ESD). Proper precautions are required during
handling and mounting to avoid excessive ESD.
Table 16. ESD Tolerance
Model
Tolerance
Human Body Model (HBM)
± 2000V
Charged Device Model (CDM)
± 400V
Machine Model (MM)
± 150V
Document Number: 002-14824 Rev. *J
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CYW20730
3.2 RF Specifications
Table 17. Receiver RF Specifications
Parameter
Mode and Conditions
Min
Typ
Max
Unit
Receiver Section
Frequency range
2402
–
2480
MHz
–
–88.0
–84.0
dBm
–
–84.0
–
dBm
–
–16
–
–
dBm
–
–10
–
–
dBm
GFSK, 0.1%BERa
–
–
11.0
dB
GFSK, 0.1%BER
a
–
–
0.0
dB
C/I 2 MHz adjacent channel
GFSK, 0.1%BER
a
–
–
–30.0
dB
C/I 3 MHz adjacent channel
GFSK, 0.1%BERb
–
–
–40.0
dB
GFSK, 0.1%BER
a
–
–
–9.0
dB
C/I 1 MHz adjacent to image channel GFSK, 0.1%BER
a
–
–
–20.0
dB
RX sensitivity (standard)
RX sensitivity (low current)
–
GFSK, 0.1%BER, 1 Mbps
Input IP3
Maximum input
Interference Performance
C/I cochannel
C/I 1 MHz adjacent channel
C/I image channel
Out-of-Band Blocking Performance (CW)
b
30 MHz to 2000 MHz
0.1%BER
–
–10.0
–
dBm
2000 MHz to 2399 MHz
0.1%BER
–
–27
–
dBm
2498 MHz to 3000 MHz
0.1%BER
–
–27
–
dBm
3000 MHz to 12.75 GHz
0.1%BER
–
–10.0
–
dBm
Spurious Emissions
30 MHz to 1 GHz
–
–
–
–57.0
dBm
1 GHz to 12.75 GHz
–
–
–
–55.0
dBm
a. Desired signal is 10 dB above the reference sensitivity level (defined as –70 dBm).
b. Desired signal is 3 dB above the reference sensitivity level (defined as –70 dBm).
Document Number: 002-14824 Rev. *J
Page 34 of 50
CYW20730
Table 18. Transmitter RF Specifications
Parameter
Min
Typ
Max
Unit
Frequency range
2402
–
2480
MHz
Output power adjustment range
–6.0
–
4.0
dBm
Default output power
–
4.0
–
dBm
Output power variation
–
2.0
–
dB
20 dB bandwidth
–
900
1000
kHz
|M – N| = 2
–
–
–20
dBm
|M – N| 3
–
–
–40
dBm
Transmitter Section
Adjacent Channel Power
Out-of-Band Spurious Emission
30 MHz to 1 GHz
–
–
–36.0
dBm
1 GHz to 12.75 GHz
–
–
–30.0
dBm
1.8 GHz to 1.9 GHz
–
–
–47.0
dBm
5.15 GHz to 5.3 GHz
–
–
–47.0
dBm
–
–
±75
kHz
DH1 packet
–
–
±25
kHz
DH3 packet
–
–
±40
kHz
LO Performance
Initial carrier frequency tolerance
Frequency Drift
DH5 packet
–
–
±40
kHz
Drift rate
–
–
20
kHz/50 µs
Average deviation in payload
(sequence used is 00001111)
140
–
175
kHz
Maximum deviation in payload
(sequence used is 10101010)
115
–
–
kHz
–
1
–
MHz
Frequency Deviation
Channel spacing
Document Number: 002-14824 Rev. *J
Page 35 of 50
CYW20730
3.3 Timing and AC Characteristics
In this section, use the numbers listed in the Reference column of each table to interpret the following timing diagrams.
3.3.1 UART Timing
Table 19. UART Timing Specifications
Reference
Characteristics
Min
Max
Unit
1
Delay time, UART_CTS_N low to UART_TXD valid
–
24
Baud out
cycles
2
Setup time, UART_CTS_N high before midpoint of stop bit
–
10
ns
3
Delay time, midpoint of stop bit to UART_RTS_N high
–
2
Baud out
cycles
Figure 12. UART Timing
Document Number: 002-14824 Rev. *J
Page 36 of 50
CYW20730
3.3.2 SPI Timing
The SPI interface supports clock speeds up to 12 MHz with VDDIO ≥ 2.2V. The supported clock speed is 6 MHz when 2.2V ≥ VDDIO
≥ 1.62V.
Figure 13 shows the timing diagram. SPI timing values for different values of SCLK and VDDM are shown in Table 20, Table 21 on
page 38, Table 22 on page 38, Table 23 on page 39.
Figure 13. SPI Timing Diagram
CS
5
6
SCLK
Mode 1
SCLK
Mode 3
2
1
MSB
MOSI
LSB
4
3
MISO
Invalid bit
MSB
LSB
Table 20. SPI1 Timing Values — SCLK = 12 MHz and VDDM = 3.2Va
Reference
Characteristics
Symbol
Min
Typicalb
Max
Unit
1
Output setup time, from MOSI 
data valid to sample edge of SCLK
Tds_mo
–
20
–
ns
2
Output hold time, from sample
edge of SCLK to MOSI data update
Tdh_mo
–
63
–
ns
3
Input setup time, from MISO data valid
to sample edge of SCLK
Tds_mi
–
TBD
–
ns
4
Input hold time, from sample 
edge of SCLK to MISO data update
Tdh_mi
–
TBD
–
ns
5c
Time from CS assert to first SCLK edge Tsu_cs
½ SCLK period – 1
–
–
ns
6c
Time from first SCLK edge to CS
deassert
½ SCLK period
–
–
ns
Thd_cs
a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 12 MHz. The speed can be adjusted to as low as 400 Hz by
configuring the firmware.
b. Typical timing based on 20 pF/1 MΩ load and SCLK = 12 MHz.
c. CS timing is firmware controlled.
Document Number: 002-14824 Rev. *J
Page 37 of 50
CYW20730
Table 21. SPI1 Timing Values — SCLK = 6 MHz and VDDM = 1.62Va
Reference
Characteristics
Symbol
Min
Typicalb
Max
Unit
1
Output setup time, from MOSI data valid
to sample edge of SCLK
Tds_mo
–
41
–
ns
2
Output hold time, from sample 
edge of SCLK to MOSI data update
Tdh_mo
–
120
–
ns
3
Input setup time, from MISO 
data valid to sample edge of SCLK
Tds_mi
–
TBD
–
ns
4
Input hold time, from sample 
edge of SCLK to MISO data update
Tdh_mi
–
TBD
–
ns
5c
Time from CS assert to first SCLK edge
Tsu_cs
½ SCLK period – 1
–
–
ns
6c
Time from first SCLK edge to CS
deassert
Thd_cs
½ SCLK period
–
–
ns
a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 6 MHz. The speed can be adjusted to as low as 400 Hz by
configuring the firmware.
b. Typical timing based on 20 pF/1 MΩ load and SCLK = 6 MHz.
c. CS timing is firmware controlled.
Table 22. SPI2 Timing Values — SCLK = 12 MHz and VDDM = 3.2Va
Reference
Characteristics
Symbol
Min
Typicalb
Max
Unit
1
Output setup time, from MOSI 
data valid to sample edge of SCLK
Tds_mo
–
26
–
ns
2
Output hold time, from sample 
edge of SCLK to MOSI data update
Tdh_mo
–
56
–
ns
3
Input setup time, from MISO 
data valid to sample edge of SCLK
Tds_mi
–
TBD
–
ns
4
Input hold time, from sample 
edge of SCLK to MISO data update
Tdh_mi
–
TBD
–
ns
5c
Time from CS assert to first SCLK edge
Tsu_cs
½ SCLK period – 1
–
–
ns
6c
Time from first SCLK edge to CS
deassert
Thd_cs
½ SCLK period
–
–
ns
a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 12 MHz. The speed can be adjusted to as low as 400 Hz by
configuring the firmware.
b. Typical timing based on 20 pF//1 MΩ load and SCLK = 12 MHz.
c. CS timing is firmware controlled in master mode and can be adjusted as required in slave mode.
Document Number: 002-14824 Rev. *J
Page 38 of 50
CYW20730
Table 23. SPI2 Timing Values — SCLK = 6 MHz and VDDM = 1.62Va
Symbol
Min
Typicalb
Max
Unit
1
Output setup time, from MOSI 
data valid to sample edge of SCLK
Tds_mo
–
50
–
ns
2
Output hold time, from sample 
edge of SCLK to MOSI data update
Tdh_mo
–
120
–
ns
3
Input setup time, from MISO 
data valid to sample edge of SCLK
Tds_mi
–
TBD
–
ns
4
Input hold time, from sample 
edge of SCLK to MISO data update
Tdh_mi
–
TBD
–
ns
5c
Time from CS assert to first SCLK edge
Tsu_cs
½ SCLK period – 1
–
–
ns
6c
Time from first SCLK edge to CS
deassert
Thd_cs
½ SCLK period
–
–
ns
Reference
Characteristics
a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 6 MHz. The speed can be adjusted to as low as 400 Hz by
configuring the firmware.
b. Typical timing based on 20 pF//1 MΩ load and SCLK = 6 MHz.
c. CS timing is firmware controlled in master mode and can be adjusted as required in slave mode.
Document Number: 002-14824 Rev. *J
Page 39 of 50
CYW20730
3.3.3 BSC Interface Timing
Table 24. BSC Interface Timing Specifications
Reference
Characteristics
Min
Max
Unit
100
1
Clock frequency
–
400
800
kHz
1000
2
START condition setup time
650
–
ns
3
START condition hold time
280
–
ns
4
Clock low time
650
–
ns
5
Clock high time
280
–
ns
0
–
ns
6
Data input hold time
a
7
Data input setup time
100
–
ns
8
STOP condition setup time
280
–
ns
9
Output valid from clock
–
400
ns
650
–
ns
10
Bus free time
b
a. As a transmitter, 300 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
b. Time that the cbus must be free before a new transaction can start.
Figure 14. BSC Interface Timing Diagram
Document Number: 002-14824 Rev. *J
Page 40 of 50
CYW20730
4. Mechanical Information
Figure 15. 32-Pin QFN Package
Document Number: 002-14824 Rev. *J
Page 41 of 50
CYW20730
Figure 16. 40-pin QFN Package
Document Number: 002-14824 Rev. *J
Page 42 of 50
CYW20730
Figure 17. 64-pin FBGA Package
Document Number: 002-14824 Rev. *J
Page 43 of 50
CYW20730
4.1 Tape Reel and Packaging Specifications
Table 25. CYW20730 5 × 5 × 1 mm QFN, 32-Pin Tape Reel Specifications
Parameter
Value
2500 pieces
Quantity per reel
Reel diameter
13 inches
Hub diameter
7 inches
Tape width
12 mm
Tape pitch
8 mm
Table 26. CYW20730 6 × 6 × 1 mm QFN, 40-Pin Tape Reel Specifications
Parameter
Value
Quantity per reel
4000 pieces
Reel diameter
13 inches
Hub diameter
4 inches
Tape width
16 mm
Tape pitch
12 mm
Table 27. CYW20730 7 × 7 × 0.8 mm WFBGA, 64-Pin Tape Reel Specifications
Parameter
Value
Quantity per reel
2500 pieces
Reel diameter
13 inches
Hub diameter
4 inches
Tape width
16 mm
Tape pitch
12 mm
The top left corner of the CYW20730 package is situated near the sprocket holes, as shown in Figure 18.
Figure 18. Pin 1 Orientation
Pin 1: Top left corner of package toward sprocket holes
Document Number: 002-14824 Rev. *J
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CYW20730
5. Ordering Information
Table 28. Ordering Information
Part Number
Package
Ambient Operating Temperature
CYW20730A2KML2G
32-pin QFN
0°C to 70°C
CYW20730A2KMLG
40-pin QFN
0°C to 70°C
CYW20730A2KFBG
64-pin BGA
0°C to 70°C
CYW20730A1KML2G
32-pin QFN
0°C to 70°C
CYW20730A1KMLG
40-pin QFN
0°C to 70°C
CYW20730A1KFBG
64-pin BGA
0°C to 70°C
Document Number: 002-14824 Rev. *J
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CYW20730
A. Appendix: Acronyms and Abbreviations
The following list of acronyms and abbreviations may appear in this document.
Term
ADC
Description
analog-to-digital converter
AFH
adaptive frequency hopping
AHB
advanced high-performance bus
APB
advanced peripheral bus
APU
audio processing unit
ARM7TDMI-S™
Acorn RISC Machine 7 Thumb instruction, Debugger, Multiplier, Ice, Synthesizable
BSC
Broadcom Serial Control
BTC
Bluetooth controller
COEX
coexistence
DFU
device firmware update
DMA
direct memory access
EBI
external bus interface
HCI
Host Control Interface
HV
high voltage
IDC
initial digital calibration
IF
intermediate frequency
IRQ
interrupt request
JTAG
Joint Test Action Group
LCU
link control unit
LDO
low drop-out
LHL
lean high land
LPO
low power oscillator
LV
LogicVision™
MIA
multiple interface agent
PCM
pulse code modulation
PLL
phase locked loop
PMU
power management unit
POR
power-on reset
PWM
pulse width modulation
QD
quadrature decoder
RAM
random access memory
RF
radio frequency
ROM
read-only memory
RX/TX
receive, transmit
SPI
serial peripheral interface
SW
software
UART
universal asynchronous receiver/transmitter
UPI
µ-processor interface
Document Number: 002-14824 Rev. *J
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CYW20730
Term
WD
Description
watchdog
A.1 References
The references in this section may be used in conjunction with this document.
Note: Cypress provides customer access to technical documentation and software through its Customer Support Portal (CSP) and
Downloads & Support site (see IoT Resources on page 3).
For documents, replace the “x” in the document number with the largest number available in the repository to ensure that you have
the most current version of the document.
Document Name
Broadcom Number
Cypress Number
20702-DS10x-R
002-14772
Items
[1] Single-Chip Bluetooth® Transceiver and Baseband Processor
Document Number: 002-14824 Rev. *J
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CYW20730
Document History
Document Title: CYW20730 Single-Chip Bluetooth Transceiver for Wireless Input Devices
Document Number: 002-14824
Revision
ECN
Orig. of
Change
Submission
Date
**
–
–
04/27/2010
20730-DS100-RI:
Initial release
06/25/2010
20730-DS101-R:
Added:
• “Shutter Control for 3D Glasses” on page 10.
• “Infrared Modulator” on page 10.
• “Infrared Learning” on page 11.
• “Triac Control” on page 12.
• “Broadcom Proprietary Control Signalling and Triggered Baseband Fast Connect” on
page 12.
• Figure 5: “Internal Reset Timing,” on page 17.
• Figure 6: “External Reset Timing,” on page 17.
• Figure 10: “40-pin QFN Ball Map,” on page 33.
• Figure 11: “64-pin BGA Ball Map,” on page 34.
• “SPI Timing” on page 41.
• Figure 16: “40-pin QFN,” on page 44.
• Figure 17: “64-pin FBGA,” on page 45.
• Revised:
• “Microprocessor Unit” on page 16.
• Table 6: “Pin Descriptions,” on page 25.
• Table 11: “ADC Specifications,” on page 36.
• Table 14: “Receiver RF Specifications,” on page 38.
• Table 15: “Transmitter RF Specifications,” on page 39.
• Table 21: “Ordering Information,” on page 50.
03/23/2011
20730-DS102-R:
Added:
• Table 1: “ADC Modes,” on page 18
Revised:
• Figure 1: “Functional Block Diagram,” on page 2
• “ADC Port” on page 17
• “Internal LDO Regulator” on page 22
• “UART Interface” on page 23
• Table 6: “XTAL Oscillator Characteristics,” on page 25
• Table 8: “GPIO Pin Descriptions,” on page 30
• Table 10: “Power Supply,” on page 39
• Table 11: “LDO Regulator Electrical Specifications,” on page 40
• Table 12: “ADC Specifications,” on page 41
• Table 14: “Current Consumption,” on page 42
• Table 15: “Receiver RF Specifications,” on page 43
• Table 16: “Transmitter RF Specifications,” on page 44
• Table 18: “SPI Interface Timing Specifications,” on page 46
• Table 21: “BCM20730 6 × 6 × 1 mm QFN, 40-Pin Tape Reel Specifications,” on
page 52
• Table 22: “BCM20730 7 × 7 × .8 mm WFBGA, 64-Pin Tape Reel Specifications,” on
page 52
Deleted:
• Placeholder for Figure 4: Triac Control
• Placeholder for Figure 18: BCM20730, 6 x 6 QFN Package Tray
• Placeholder for Figure 19: BCM20730, 7 x 7 FBGA Package Tray
04/06/2011
20730-DS103-R:
Revised:
• Table 14: “Current Consumption,” on page 42
• Table 23: “Ordering Information,” on page 54
05/09/2011
20730-DS104-R:
Revised:
• Figure 1: “Functional Block Diagram,” on page 2
• “ADC Port” on page 17
• Table 10: “Power Supply,” on page 39
*A
*B
*C
*D
–
–
–
–
–
–
–
–
Document Number: 002-14824 Rev. *J
Description of Change
Page 48 of 50
CYW20730
Document Title: CYW20730 Single-Chip Bluetooth Transceiver for Wireless Input Devices
Document Number: 002-14824
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
*E
–
–
06/29/2011
20730-DS105-R:
Added:
• Figure 9: “32-Pin QFN Ball Map,” on page 39
• Figure 16: “32-Pin QFN Package,” on page 52
• Table 20: “BCM20730 5 × 5 × 1 mm QFN, 32-Pin Tape Reel Specifications,” on
page 55
Revised:
• General Description and Features on Cover
• Figure 1: “Functional Block Diagram,” on page 2
• “ADC Port” on page 17
• Table 2: “BCM20730 First SPI Set (Master Mode),” on page 18
• Table 2: “BCM20730 First SPI Set (Master Mode),” on page 18
• Table 2: “BCM20730 First SPI Set (Master Mode),” on page 18
• Figure 5: “External Reset Timing,” on page 22
• “GPIO Port” on page 27
• “BBC Power Management” on page 29
• Table 7: “Pin Descriptions,” on page 30
• Table 8: “GPIO Pin Descriptions,” on page 32
• Table 12: “ADC Specifications,” on page 44
*F
–
–
09/20/2011
20730-DS106-R:
Changed from a Preliminary Data Sheet to a Data Sheet.
*G
–
–
10/10/2012
20730-DS107-R:
Revised:
• “SPI Timing” on page 49
09/09/2013
20730-DS108-R:
Revised:
• <Cross-Ref>Section 1.3: “Shutter Control for 3D Glasses,” on page 6
• Table 28, “Ordering Information,” on page 45
Added:
• Table 16, “ESD Tolerance,” on page 33
*H
–
–
*I
5522944
UTSV
11/16/2016
Updated to Cypress template
*J
5700376
AESATMP7
04/25/2017
Updated Cypress Logo and Copyright.
Document Number: 002-14824 Rev. *J
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CYW20730
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC®Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Lighting & Power Control
cypress.com/iot
cypress.com/powerpsoc
Memory
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/memory
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP| PSoC 6
Cypress Developer Community
Forums | WICED IoT Forums | Projects | Video | Blogs |
Training | Components
Technical Support
cypress.com/support
cypress.com/psoc
cypress.com/touch
cypress.com/usb
cypress.com/wireless
50
© Cypress Semiconductor Corporation, 2010-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-14824 Rev. *J
Revised April 25, 2017
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