AD ADV7314 Multiformat 216 mhz video encoder with six nsv 14-bit dac Datasheet

Multiformat 216 MHz
Video Encoder with Six NSV™ 14-Bit DACs
ADV7314
FEATURES
High Definition Input Formats
8-/10-,16-/20-, 24-/30-Bit (4:2:2, 4:4:4) Parallel YCrCb
Compliant with:
SMPTE 293M (525p)
BTA T-1004 EDTV2 525p
ITU-R BT.1358 (625p/525p)
ITU-R BT.1362 (625p/525p)
SMPTE 274M (1080i) at 30 Hz and 25 Hz
SMPTE 296M (720p)
RGB in 3 10-Bit 4:4:4 Input Format
HDTV RGB Supported:
RGB and RGBHV
Other High Definition Formats Using Async
Timing Mode
High Definition Output Formats
YPrPb Progressive Scan (EIA-770.1, EIA-770.2)
YPrPb HDTV (EIA 770.3)
RGB, RGBHV
CGMS-A (720p/1080i)
Macrovision Rev 1.1 (525p/625p)
CGMS-A (525p)
Standard Definition Input Formats
CCIR-656 4:2:2 8-/10-/16-/20-Bit Parallel Input
Standard Definition Output Formats
Composite NTSC M/N
Composite PAL M/N/B/D/G/H/I, PAL-60
SMPTE 170M NTSC Compatible Composite Video
ITU-R BT.470 PAL Compatible Composite Video
S-Video (Y/C)
EuroScart RGB
Component YPrPb (Betacam, MII, SMPTE/EBU N10)
Macrovision Rev 7.1.L1
CGMS/WSS
Closed Captioning
GENERAL FEATURES
Simultaneous SD and HD Inputs and Outputs
Oversampling up to 216 MHz
Programmable DAC Gain Control
Sync Outputs in All Modes
Purchase of licensed I2C components of Analog Devices or one of its
sublicensed Associated Companies conveys a license for the purchaser under
the Philips I2C Patent Rights to use these components in an I2C system,
provided that the system conforms to the I2C Standard Specification as
defined by Philips.
On-Board Voltage Reference
Six 14-Bit NSV Precision Video DACs
2-Wire Serial I2C ® Interface
Dual Input/Output Supply 2.5 V/3.3 V Operation
Analog and Digital Supply 2.5 V
On-Board PLL
64-Lead LQFP Package
Lead (Pb) Free Product
APPLICATIONS
High End DVD
High End PS DVD Recorders/Players
SD/Prog Scan/HDTV Display Devices
SD/HDTV Set Top Boxes
Professional Video Systems
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
ADV7314
STANDARD DEFINITION
CONTROL BLOCK
COLOR CONTROL
BRIGHTNESS
DNR
GAMMA
PROGRAMMABLE FILTERS
SD TEST PATTERN
Y9–Y0
C9–C0
S9–S0
D
E
M
U
X
PROGRAMMABLE
RGB MATRIX
HIGH DEFINITION
CONTROL BLOCK
HD TEST PATTERN
HSYNC
VSYNC
BLANK
TIMING
GENERATOR
CLKIN_A
CLKIN_B
PLL
COLOR CONTROL
ADAPTIVE FILTER CTRL
SHARPNESS FILTER
14-BIT
DAC
O
V
E
R
S
A
M
P
L
I
N
G
14-BIT
DAC
14-BIT
DAC
14-BIT
DAC
14-BIT
DAC
14-BIT
DAC
I2C
INTERFACE
GENERAL DESCRIPTION
The ADV®7314 is a high speed, digital-to-analog encoder on a
single monolithic chip. It includes six high speed NSV video
D/A converters with TTL compatible inputs.
The ADV7314 has separate 8-/10-/16-/20-bit input ports that
accept data in high definition and/or standard definition video
format. For all standards, external horizontal, vertical and
blanking signals, or EAV/SAV timing codes control the insertion of appropriate synchronization signals into the digital data
stream and therefore the output signal.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
ADV7314
DETAILED FEATURES
High Definition Programmable Features (720p/1080i)
2 Oversampling (148.5 MHz)
Internal Test Pattern Generator
(Color Hatch, Black Bar, Flat Field/Frame)
Fully Programmable YCrCb to RGB Matrix
Gamma Correction
Programmable Adaptive Filter Control
Programmable Sharpness Filter Control
CGMS-A (720p/1080i)
Digital Noise Reduction (DNR)
Multiple Chroma and Luma Filters
Luma-SSAF™ Filter with Programmable
Gain/Attenuation
PrPb SSAF
Separate Pedestal Control on Component and
Composite/S-Video Outputs
VCR FF/RW Sync Mode
Macrovision Rev 7.1.L1
CGMS/WSS
Closed Captioning
Programmable Features (525p/625p)
8 Oversampling (216 MHz Output)
Internal Test Pattern Generator
(Color Hatch, Black Bar, Flat Frame)
Individual Y and PrPb Output Delay
Gamma Correction
Programmable Adaptive Filter Control
Fully Programmable YCrCb to RGB Matrix
Undershoot Limiter
Macrovision Rev 1.1 (525p/625p)
CGMS-A (525p)
Standards Directly Supported
Standard Definition Programmable Features
16 Oversampling (216 MHz)
Internal Test Pattern Generator (Color Bars, Black Bar)
Controlled Edge Rates for Sync, Active Video
Individual Y and PrPb Output Delay
Gamma Correction
Resolution
Frame Rate
(Hz)
Clk Input
(MHz)
Standard
720480
720576
720483
720480
720576
1280720
19201080
19201080
29.97
25
59.94
59.94
50
60
30
25
27
27
27
27
27
74.25
74.25
74.25
ITU-R BT.656
ITU-R BT.656
SMPTE 293M
BTA T-1004
ITU-R BT.1362
SMPTE 296M
SMPTE 274M
SMPTE 274M*
Other standards are supported in Async Timing mode.
*SMPTE 274M-1998: System no.6
DETAILED FUNCTIONAL BLOCK DIAGRAM
HD PIXEL
INPUT
CLKIN_B
Y
DEINTERLEAVE
CR
TEST
PATTERN
CB
SHARPNESS
AND
ADAPTIVE
FILTER
CONTROL
Y COLOR
CR COLOR
CB COLOR
PS 8
HDTV 2
4:2:2
TO
4:4:4
DAC
DAC
P_HSYNC
P_VSYNC
P_BLANK
TIMING
GENERATOR
CLOCK
CONTROL
AND PLL
DAC
U
UV SSAF
S_HSYNC
S_VSYNC
S_BLANK
V
TIMING
GENERATOR
DAC
RGB
MATRIX
SD 16
CLKIN_A
CB
SD PIXEL
INPUT
CR
DEINTERLEAVE Y
TEST
PATTERN
DNR
GAMMA
COLOR
CONTROL
SYNC
INSERTION
LUMA
AND
CHROMA
FILTERS
–2–
2 OVERSAMPLING
FSC
MODULATION
DAC
DAC
CGMS
WSS
REV. 0
ADV7314
TABLE OF CONTENTS
PROGRAMMABLE DAC GAIN CONTROL . . . . . . . . . .
Gamma Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HD Sharpness Filter Control and Adaptive Filter
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HD Sharpness Filter and Adaptive Filter Application
Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SD DIGITAL NOISE REDUCTION . . . . . . . . . . . . . . . .
Coring Gain Border . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Coring Gain Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DNR Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Border Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Size Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DNR Input Select Control . . . . . . . . . . . . . . . . . . . . . . . .
DNR Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Offset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SD ACTIVE VIDEO EDGE . . . . . . . . . . . . . . . . . . . . . . . .
SAV/EAV Step Edge Control . . . . . . . . . . . . . . . . . . . . . .
BOARD DESIGN AND LAYOUT CONSIDERATIONS .
DAC Termination and Layout Considerations . . . . . . . .
Video Output Buffer and Optional Output Filter . . . . . . .
PC BOARD LAYOUT CONSIDERATIONS . . . . . . . . . .
Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . .
Analog Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . .
APPENDIX 1—COPY GENERATION MANAGEMENT
SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PS CGMS Data Registers 2–0 . . . . . . . . . . . . . . . . . . . . .
SD CGMS Data Registers 2–0 . . . . . . . . . . . . . . . . . . . . .
Function of CGMS Bits . . . . . . . . . . . . . . . . . . . . . . . . . .
CGMS Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . .
APPENDIX 2—SD WIDE SCREEN SIGNALING . . . . . .
APPENDIX 3—SD CLOSED CAPTIONING . . . . . . . . . .
APPENDIX 4—TEST PATTERNS . . . . . . . . . . . . . . . . . .
APPENDIX 5—SD TIMING MODES . . . . . . . . . . . . . . .
Mode 0 (CCIR-656)—Slave Option . . . . . . . . . . . . . . . .
Mode 0 (CCIR-656)—Master Option . . . . . . . . . . . . . . .
Mode 1—Slave Option . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 1—Master Option . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 2—Slave Option . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 2—Master Option . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 3—Master/Slave Option . . . . . . . . . . . . . . . . . . . . .
APPENDIX 6—HD TIMING . . . . . . . . . . . . . . . . . . . . . .
APPENDIX 7—VIDEO OUTPUT LEVELS . . . . . . . . . . .
HD YPrPb Output Levels . . . . . . . . . . . . . . . . . . . . . . . .
RGB Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
YPrPb Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . .
APPENDIX 8—VIDEO STANDARDS . . . . . . . . . . . . . . .
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . .
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1
DETAILED FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
DETAILED FUNCTIONAL BLOCK DIAGRAM . . . . . . . 2
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
DYNAMIC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . 5
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 6
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 14
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 15
TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . 17
REGISTER ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Subaddress Register (SR7–SR0) . . . . . . . . . . . . . . . . . . . 18
INPUT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . 31
Standard Definition Only . . . . . . . . . . . . . . . . . . . . . . . . . 31
Progressive Scan Only or HDTV Only . . . . . . . . . . . . . . . 31
Simultaneous Standard Definition
and Progressive Scan or HDTV . . . . . . . . . . . . . . . . . . 32
Progressive Scan At 27 Mhz (Dual Edge)
or 54 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
OUTPUT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . 34
TIMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
HD Async Timing Mode . . . . . . . . . . . . . . . . . . . . . . . . . 35
HD Timing Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
SD Real-Time Control, Subcarrier Reset,
and Timing Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
SD VCR FF/RW Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Vertical Blanking Interval . . . . . . . . . . . . . . . . . . . . . . . . . 39
SD Subcarrier Frequency Registers . . . . . . . . . . . . . . . . . 39
Square Pixel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
FILTER SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
HD Sinc Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
SD Internal Filter Response . . . . . . . . . . . . . . . . . . . . . . . 41
Typical Performance Characteristics . . . . . . . . . . . . . . . . . . 42
COLOR CONTROLS AND RGB MATRIX . . . . . . . . . . . 46
HD/PS Y Level, Cr Level, Cb Level . . . . . . . . . . . . . . . . 46
HD RGB Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Programming the RGB Matrix . . . . . . . . . . . . . . . . . . . . . 46
SD Luma and Color Control . . . . . . . . . . . . . . . . . . . . . . 46
SD Hue Adjust Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
SD Brightness Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
SD Brightness Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Double Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
REV. 0
–3–
48
49
50
51
53
53
53
53
53
54
54
54
54
55
55
56
56
56
58
58
58
58
60
60
60
60
60
62
63
64
66
66
67
68
69
70
71
72
73
74
74
75
76
80
82
ADV7314–SPECIFICATIONS
(VAA = 2.375 V–2.625 V, VDD = 2.375 V–2.625 V; VDD_IO = 2.375 V–3.6 V,
VREF = 1.235 V, RSET = 3040 , RLOAD = 150 . All specifications TMIN to TMAX
(0C to 70C), unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
Test Conditions
1
STATIC PERFORMANCE
Resolution
Integral Nonlinearity
Differential Nonlinearity2, +ve
Differential Nonlinearity2, –ve
DIGITAL OUTPUTS
Output Low Voltage, VOL
Output High Voltage, VOH
Three-State Leakage Current
Three-State Output Capacitance
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH
Input Low Voltage, VIL
Input Leakage Current
Input Capacitance, CIN
ANALOG OUTPUTS
Full-Scale Output Current
Output Current Range
DAC-to-DAC Matching
Output Compliance Range, VOC
Output Capacitance, COUT
VOLTAGE REFERENCE
Internal Reference Range, VREF
External Reference Range, VREF
VREF Current4
POWER REQUIREMENTS
Normal Power Mode
IDD5
IDD_IO
IAA7, 8
Sleep Mode
IDD
IAA
IDD_IO
Power Supply Rejection Ratio
14
2.0
1.0
3.0
Bits
LSB
LSB
LSB
0.4 [0.4]3
3
2.4 [2.0]
± 1.0
2
2
0.8
3
2
4.1
4.1
0
1.15
1.15
4.33
4.33
1.0
1.0
7
1.235
1.235
± 10
170
110
95
172
1.0
39
200
10
250
0.01
4.6
4.6
1.4
1.3
1.3
1906
45
V
V
mA
pF
V
V
mA
pF
ISINK = 3.2 mA
ISOURCE = 400 mA
VIN = 0.4 V, 2.4 V
VIN = 2.4 V
mA
mA
%
V
pF
V
V
mA
mA
mA
mA
mA
mA
mA
SD Only [16]
PS Only [8]
HDTV Only [2]
SD [16, 10 Bit] + PS [8, 20 Bit]
mA
mA
mA
%/%
NOTES
1
Oversampling disabled. Static DAC performance will be improved with increased oversampling ratios.
2
DNL measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal step value; for –ve DNL,
the actual step value lies below the ideal step value.
3
Value in brackets for V DD_IO = 2.375 V–2.75 V.
4
External current required to overdrive internal V REF.
5
IDD, the circuit current, is the continuous current required to drive the digital core.
6
Guaranteed maximum by characterization.
7
IAA is the total current required to supply all DACs including the V REF circuitry and the PLL circuitry.
8
All DACs on.
Specifications subject to change without notice.
–4–
REV. 0
ADV7314
DYNAMIC SPECIFICATIONS
Parameter
(VAA = 2.375 V–2.625 V, VDD = 2.375 V–2.625 V; VDD_IO = 2.375 V–3.6 V, VREF = 1.235 V, RSET =
3040 , RLOAD = 150 . All specifications TMIN to TMAX (0C to 70C), unless otherwise noted.)
Min
Typ
Max
Unit
Test Conditions
Luma Ramp Unweighted
Flat Field Full Bandwidth
PROGRESSIVE SCAN MODE
Luma Bandwidth
Chroma Bandwidth
SNR
SNR
12.5
5.8
65.6
72
MHz
MHz
dB
dB
HDTV MODE
Luma Bandwidth
Chroma Bandwidth
30
13.75
MHz
MHz
STANDARD DEFINITION MODE
Hue Accuracy
Color Saturation Accuracy
Chroma Nonlinear Gain
Chroma Nonlinear Phase
Chroma/Luma Intermodulation
Chroma/Luma Gain Inequality
Chroma/Luma Delay Inequality
Luminance Nonlinearity
Chroma AM Noise
Chroma PM Noise
Differential Gain
Differential Phase
SNR
SNR
0.44
0.20
0.84
–0.2
0
97.5
0
0.1
84
75.3
0.09
0.12
63.5
77.7
∞
%
±%
±∞
±%
±%
ns
±%
dB
dB
%
∞
dB
dB
Specifications subject to change without notice.
REV. 0
–5–
Referenced to 40 IRE
NTSC
NTSC
Luma Ramp
Flat Field Full Bandwidth
ADV7314
TIMING SPECIFICATIONS
(VAA = 2.375 V–2.625 V, VDD = 2.375 V–2.625 V; VDD_IO = 2.375 V–3.6 V, VREF = 1.235 V, RSET =
3040 , RLOAD = 150 . All specifications TMIN to TMAX (0C to 70C), unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
400
kHz
ms
ms
ms
Conditions
1
MPU PORT
SCLOCK Frequency
SCLOCK High Pulsewidth, t1
SCLOCK Low Pulsewidth, t2
Hold Time (Start Condition), t3
0
0.6
1.3
0.6
Setup Time (Start Condition), t4
0.6
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
RESET Low Time
100
300
300
0.6
100
ANALOG OUTPUTS
Analog Output Delay2
Output Skew
CLOCK CONTROL AND PIXEL PORT3
fCLK
fCLK
Clock High Time t9
Clock Low Time t10
Data Setup Time t111
Data Hold Time t121
SD Output Access Time t13
SD Output Hold Time t14
HD Output Access Time t13
HD Output Hold Time t14
PIPELINE DELAY4
ms
7
1
The first clock is generated after
this period
Relevant for repeated start
condition
ns
ns
ns
ms
ns
ns
ns
27
81
40
40
2.0
2.0
15
5.0
14
5.0
63
76
35
41
36
MHz
MHz
% of one clk cycle
% of one clk cycle
ns
ns
ns
ns
ns
ns
Progressive Scan Mode
HDTV Mode/ASYNC Mode
clk cycles
clk cycles
clk cycles
clk cycles
clk cycles
SD [2, 16]
SD Component Mode [16]
PS [1]
PS [8]
HD [2, 1]
NOTES
1
Guaranteed by characterization.
2
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.
3
Data: C [9:0]; Y [9:0], S[9:0]
Control: P_HSYNC, P_VSYNC, P_BLANK, S_HSYNC, S_VSYNC, S_BLANK.
4
SD, PS = 27 MHz, HD = 74.25 MHz.
Specifications subject to change without notice.
–6–
REV. 0
ADV7314
CLKIN_A
t9
CONTROL
INPUTS
t12
t10
P_HSYNC,
P_VSYNC,
P_BLANK
Y9–Y0
Y0
Y1
Y2
Y3
Y4
Y5
C9–C0
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
t11
t13
CONTROL
OUTPUTS
t14
t9 = CLOCK HIGH TIME
t10 = CLOCK LOW TIME
t11 = DATA SETUP TIME
t12 = DATA HOLD TIME
Figure 1. HD Only 4:2:2 Input Mode [Input Mode 010]; PS Only 4:2:2 Input Mode [Input Mode 001]
CLKIN_A
t9
CONTROL
INPUTS
t12
t10
P_HSYNC,
P_VSYNC,
P_BLANK
Y9–Y0
Y0
Y1
Y2
Y3
Y4
Y5
C9–C0
Cb0
Cb1
Cb2
Cb3
Cb4
Cb5
t11
S9–S0
Cr0
Cr1
t13
Cr2
Cr3
Cr4
Cr5
CONTROL
OUTPUTS
t14
t9 = CLOCK HIGH TIME
t10 = CLOCK LOW TIME
t11 = DATA SETUP TIME
t12 = DATA HOLD TIME
Figure 2. HD Only 4:4:4 Input Mode [Input Mode 010]; PS Only 4:4:4 Input Mode [Input Mode 001]
REV. 0
–7–
ADV7314
CLKIN_A
t9
CONTROL
INPUTS
t12
t10
P_HSYNC,
P_VSYNC,
P_BLANK
Y9–Y0
G0
G1
G2
G3
G4
G5
C9–C0
B0
B1
B2
B3
B4
B5
t11
R0
S9–S0
t13
R1
R2
R3
R4
R5
CONTROL
OUTPUTS
t14
t9 = CLOCK HIGH TIME
t10 = CLOCK LOW TIME
t11 = DATA SETUP TIME
t12 = DATA HOLD TIME
Figure 3. HD RGB 4:4:4 Input Mode [Input Mode 010]
CLKIN_B*
t9
CONTROL
INPUTS
t10
P_HSYNC,
P_VSYNC,
P_BLANK
Y9–Y0
Cb0
Y0
Cr0
Y1
t12
Crxxx
Yxxx
t12
t11
t11
t13
CONTROL
OUTPUTS
t14
t9 = CLOCK HIGH TIME
t10 = CLOCK LOW TIME
t11 = DATA SETUP TIME
t12 = DATA HOLD TIME
*CLKIN_B MUST BE USED IN THIS PS MODE.
Figure 4. PS 4:2:2 110-Bit Interleaved at 27 MHz HSYNC/ VSYNC Input Mode [Input Mode 100]
–8–
REV. 0
ADV7314
CLKIN_A
t9
CONTROL
INPUTS
t10
P_HSYNC,
P_VSYNC,
P_BLANK
Y9–Y0
Cb0
Y0
Cr0
Y1
Yxxx
t13
t12
t11
Crxxx
t14
CONTROL
OUTPUTS
t9 = CLOCK HIGH TIME
t10 = CLOCK LOW TIME
t11 = DATA SETUP TIME
t12 = DATA HOLD TIME
Figure 5. PS 4:2:2 110-Bit Interleaved at 54 MHz HSYNC/ VSYNC Input Mode [Input Mode 111]
CLKIN_B*
t9
3FF
Y9–Y0
t10
00
00
XY
t12
Cb0
Y0
Cr0
Y1
t12
t11
t11
t13
CONTROL
OUTPUTS
t14
t9 = CLOCK HIGH TIME
t10 = CLOCK LOW TIME
t11 = DATA SETUP TIME
t12 = DATA HOLD TIME
*CLKIN_B USED IN THIS PS ONLY MODE.
Figure 6. PS Only 4:2:2 110-Bit Interleaved at 27 MHz EAV/SAV Input Mode [Input Mode 100]
CLKIN_A
t9
Y9–Y0
3FF
t11
t10
00
00
XY
Cb0
Y0
Cr0
Y1
t13
t12
t14
CONTROL
OUTPUTS
t9 = CLOCK HIGH TIME
t10 = CLOCK LOW TIME
t11 = DATA SETUP TIME
t12 = DATA HOLD TIME
NOTE: Y0, Cb0 SEQUENCE AS PER SUBADDRESS 0x01 BIT 1
Figure 7. PS Only 4:2:2 110-Bit Interleaved at 54 MHz EAV/SAV Input Mode [Input Mode 111]
REV. 0
–9–
ADV7314
CLKIN_B
t9
CONTROL
INPUTS
t12
t10
P_HSYNC,
P_VSYNC,
P_BLANK
Y9–Y0
Y0
Y1
Y2
Y3
Y4
Y5
C9–C0
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
HD INPUT
t11
CLKIN_A
CONTROL
INPUTS
S_HSYNC,
S_VSYNC,
S_BLANK
S9–S0
t9
t12
t10
SD INPUT
Cb0
Y0
Y1
Cr0
Cb1
Y2
t11
Figure 8. HD 4:2:2 and SD (10-Bit) Simultaneous Input Mode [Input Mode 101]; SD Oversampled
[Input Mode 110] HD Oversampled
CLKIN_B
t9
CONTROL
INPUTS
t12
t10
P_HSYNC,
P_VSYNC,
P_BLANK
Y9–Y0
Y0
Y1
Y2
Y3
Y4
Y5
C9–C0
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
PS INPUT
t11
CLKIN_A
t9
CONTROL
INPUTS
S_HSYNC,
S_VSYNC,
S_BLANK
S9–S0
t12
t10
SD INPUT
Cb0
Y0
Y1
Cr0
Cb1
Y2
t11
Figure 9. PS (4:2:2) and SD (10-Bit) Simultaneous Input Mode [Input Mode 011]
–10–
REV. 0
ADV7314
CLKIN_B
t10
t9
CONTROL
INPUTS
P_HSYNC,
P_VSYNC,
P_BLANK
Y9–Y0
PS INPUT
Cb0
t11
Y0
Cr0
Crxxx
Y1
t12
Yxxx
t12
t11
CLKIN_A
CONTROL
INPUTS
t9
S_HSYNC,
S_VSYNC,
S_BLANK
t12
t10
SD INPUT
S9–S0
Cb0
Y0
Cr0
Cb1
Y1
Y2
t11
Figure 10. PS (10-Bit) and SD (10-Bit) Simultaneous Input Mode [Input Mode 100]
CLKIN_A
t9
CONTROL
INPUTS
t12
t10
S_HSYNC,
S_VSYNC,
S_BLANK
S9–S0/Y9–Y0*
IN SLAVE MODE
Cb0
Cr0
Cb2
Cr2
t11
Cb4
Cr4
t13
CONTROL
OUTPUTS
IN MASTER/SLAVE MODE
t14
*SELECTED BY ADDRESS 0x01 BIT 7
Figure 11. 10-/8-Bit SD Only Pixel Input Mode [Input Mode 000]
REV. 0
–11–
ADV7314
CLKIN_A
t9
CONTROL
INPUTS
t12
t10
S_HSYNC,
S_VSYNC,
S_BLANK
IN SLAVE MODE
Y1
Y2
Y3
Cr0
Cb2
Cr2
Y0
S9–S0/Y9–Y0*
Cb0
C9–C0
t11
t13
CONTROL
OUTPUTS
IN MASTER/SLAVE MODE
t14
*SELECTED BY ADDRESS 0x01 BIT 7
Figure 12. 20-/16-Bit SD Only Pixel Input Mode [Input Mode 000]
P_HSYNC
P_VSYNC
A
P_BLANK
Y9–Y0
Y0
Y1
Y2
Y3
C9–C0
Cb0
Cr0
Cr1
Cb1
B
A = 16 CLK CYCLES FOR 525p
A = 12 CLK CYCLES FOR 626p
A = 44 CLK CYCLES FOR 1080i @ 30Hz, 25Hz
A = 70 CLK CYCLES FOR 720p
AS RECOMMENDED BY STANDARD
B (MIN) = 122 CLK CYCLES FOR 525p
B (MIN) = 132 CLK CYCLES FOR 625p
B (MIN) = 236 CLK CYCLES FOR 1080i @ 30Hz, 25Hz
B (MIN) = 300 CLK CYCLES FOR 720p
Figure 13. HD 4:2:2 Input Timing Diagram
–12–
REV. 0
ADV7314
P_HSYNC
P_VSYNC
a
P_BLANK
Y9–Y0
Cb
Cr
Y
Y
b
a = 32 CLK CYCLES FOR 525p
a = 24 CLK CYCLES FOR 625p
AS RECOMMENDED BY STANDARD
b(MIN) = 244 CLK CYCLES FOR 525p
b(MIN) = 264 CLK CYCLES FOR 625p
Figure 14. PS 4:2:2 110-Bit Interleaved Input Timing Diagram
S_HSYNC
S_VSYNC
PAL = 24 CLKCYCLES
NTSC = 32 CLKCYCLES
S_BLANK
S9–S0/Y9–Y0*
Cb
PAL = 24 CLK CYCLES
NTSC = 32 CLK CYCLES
*SELECTED BY ADDRESS 0x01 BIT 7
Figure 15. SD Timing Input for Timing Mode 1
t3
t5
t3
SDA
t1
t6
SCLK
t2
t4
t7
Figure 16. MPU Port Timing Diagram
REV. 0
Y
–13–
t8
Cr
Y
ADV7314
ABSOLUTE MAXIMUM RATINGS*
VAA to AGND . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to –0.3 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to –0.3 V
VDD_IO to IO_GND . . . . . . . . . . . . –0.3 V to VDD_IO to +0.3 V
Ambient Operating Temperature (TA) . . . . . . . . . 0∞C to 70∞C
Storage Temperature (TS) . . . . . . . . . . . . . . . –65∞C to +150∞C
Infrared Reflow Soldering (20 secs) . . . . . . . . . . . . . . . . 260∞C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL CHARACTERISTICS
JC = 11∞C/W
JA = 47∞C/W
The ADV7314 is a Pb-free environmentally friendly product. It is
manufactured using the most up-to-date materials and processes.
The coating on the leads of each device is 100% pure Sn electroplate. The device is suitable for Pb-free applications and is able to
withstand surface-mount soldering at up to 255∞C [± 5∞C]. In
addition, it is backward compatible with conventional SnPb soldering processes. This means that the electroplated Sn coating can
be soldered with Sn/Pb solder pastes at conventional reflow temperatures of 220∞C to 235∞C.
ORDERING GUIDE*
Model
Package Description
Package Option
ADV7314KST
Plastic Quad Flatpack
(LQFP)
ST-64
*Analog output short circuit to any power supply or common can be of an indefinite duration.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADV7314 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
–14–
REV. 0
ADV7314
S_VSYNC
S_HSYNC
S0
S1
S2
S3
VDD
S4
DGND
S5
S6
S7
S8
S9
CLKN_B
GND_IO
PIN CONFIGURATION
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48 S_BLANK
VDD_IO 1
Y0 2
PIN 1
IDENTIFIER
47 RSET1
46 VREF
Y1 3
Y2 4
45 COMP1
Y3 5
44 DAC A
ADV7314
Y4 6
43 DAC B
LQFP
Y5 7
42 DAC C
TOP VIEW
(Not to Scale)
Y6 8
41 VAA
40 AGND
Y7 9
VDD 10
DGND 11
39 DAC D
Y8 12
37 DAC F
Y9 13
36 COMP2
C0 14
35 RSET2
34 EXT_LF
38 DAC E
C1 15
33 RESET
C2 16
CLKIN_A
RTC_SCR_TR
C9
C8
C7
C6
C5
P_VSYNC
P_BLANK
P_HSYNC
SCLK
SDA
I 2C
ALSB
C4
C3
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Input/Output
Function
11, 57
DGND
G
Digital Ground.
40
AGND
G
Analog Ground.
32
CLKIN_A
I
Pixel Clock Input for HD (74.25 MHz Only, PS Only (27 MHz), SD Only
(27 MHz).
63
CLKIN_B
I
Pixel Clock Input. Requires a 27 MHz reference clock for Progressive Scan
mode or a 74.25 MHz (74.1758 MHz) reference clock in HDTV mode. This
clock is only used in dual modes.
36, 45
COMP2, COMP1 O
Compensation Pin for DACs. Connect 0.1 mF capacitor from COMP pin
to VAA.
44
DAC A
O
CVBS/Green/Y/Y Analog Output.
43
DAC B
O
Chroma/Blue/U/Pb Analog Output.
42
DAC C
O
Luma/Red/V/Pr Analog Output.
39
DAC D
O
In SD Only Mode: CVBS/Green/Y Analog Output.
In HD Only mode and simultaneous HD/SD mode: Y/Green [HD] Analog
Output.
38
DAC E
O
In SD Only Mode: Luma/Blue/U Analog Output.
In HD Only mode and simultaneous HD/SD mode: Pr/Red Analog Output.
37
DAC F
O
In SD Only Mode: Chroma/Red/V Analog Output.
In HD Only mode and simultaneous HD/SD mode: Pb/Blue [HD] Analog
Output.
23
P_HSYNC
I
Video Horizontal Sync Control Signal for HD in Simultaneous SD/HD Mode
and HD.
24
P_VSYNC
I
Video Vertical Sync Control Signal for HD in Simultaneous SD/HD Mode
and HD.
25
P_BLANK
I
Video Blanking Control Signal for HD in Simultaneous SD/HD Mode and HD.
48
S_BLANK
I/O
Video Blanking Control Signal for SD only.
REV. 0
–15–
ADV7314
Pin No.
Mnemonic
Input/Output
Function
50
S_HSYNC
I/O
Video Horizontal Sync Control Signal for SD Only.
49
S_VSYNC
I/O
Video Vertical Sync Control Signal for SD Only.
2–9, 12–13
Y9–Y0
I
SD or Progressive Scan/HDTV Input Port for Y Data. Input port for interleaved progressive scan data. The LSB is set up on Pin Y0. For 8-bit data
input, LSB is set up on Y2.
14–18, 26–30 C9–C0
I
Progressive Scan/HDTV Input Port. In 4:4:4 Input mode, this port is used for
the Cb[Blue/U] data. The LSB is set up on Pin C0. For 8-bit data input, LSB
is set up on C2.
51–55, 58–62 S9–S0
I
SD or Progressive Scan/HDTV Input Port for Cr [Red/V] Data in 4:4:4 Input
Mode. LSB is set up on Pin S0. For 8-bit data input, LSB is set up on S2.
33
RESET
I
This input resets the on-chip timing generator and sets the ADV7314 into
default register setting. RESET is an active low signal.
35, 47
RSET2, RSET1
I
A 3040 W resistor must be connected from this pin to AGND and is used
to control the amplitudes of the DAC outputs.
22
SCLK
I
I2C Port Serial Interface Clock Input.
21
SDA
I/O
I2C Port Serial Data Input/Output.
20
ALSB
I
TTL Address Input. This signal sets up the LSB of the I2C address. When
this pin is tied low, the I2C filter is activated, reducing noise on the I2C
interface.
1
VDD_IO
P
Power Supply for Digital Inputs and Outputs.
10, 56
VDD
P
Digital Power Supply.
41
VAA
P
Analog Power Supply.
46
VREF
I/O
Optional External Voltage Reference Input for DACs or Voltage Reference
Output (1.235 V).
34
EXT_LF
I
External Loop Filter for the Internal PLL.
31
RTC_SCR_TR
I
Multifunctional Input. Real-time control (RTC) input, timing reset input,
subcarrier reset input.
19
I 2C
I
This input pin must be tied high (VDD_IO) for the ADV7314 to interface
over the I2C port.
64
GND_IO
Digital Input/Output Ground.
TERMINOLOGY
SD
Standard definition video, conforming to ITU-R BT.601/656.
HD
High definition video, such as progressive scan or HDTV.
PS
Progressive scan video, conforming to SMPTE 293M, ITU-R BT.1358, BTA T-1004 EDTV2, BTA 1362
HDTV
High definition television video, conforming to SMPTE 274M or SMPTE 296M.
YCrCb
SD, HD, or PS component digital video.
YPrPb
HD, SD, or PS component analog video.
–16–
REV. 0
ADV7314
MPU PORT DESCRIPTION
The ADV7314 supports a 2-wire serial (I2C compatible) microprocessor bus driving multiple peripherals. Two inputs, serial
data (SDA) and serial clock (SCL), carry information between
any device connected to the bus. Each slave device is recognized
by a unique address. The ADV7314 has four possible slave
addresses for both read and write operations. These are unique
addresses for each device and are illustrated in Figure 17. The
LSB sets either a read or write operation. Logic 1 corresponds
to a read operation, while Logic 0 corresponds to a write operation. A1 is set by setting the ALSB pin of the ADV7314 to
Logic 0 or Logic 1. When ALSB is set to 1, there is greater
input bandwidth on the I2C lines, which allows high speed data
transfers on this bus. When ALSB is set to 0, there is reduced
input bandwidth on the I2C lines, which means that pulses of
less than 50 ns will not pass into the I2C internal controller.
This mode is recommended for noisy systems.
1
1
0
1
0
1
A1
X
ADDRESS
CONTROL
SET UP BY
ALSB
READ/WRITE
CONTROL
0
1
WRITE
READ
Figure 17. ADV7314 Slave Address = D4h
To control the various devices on the bus, the following protocol
must be followed. First, the master initiates a data transfer by
establishing a start condition, defined by a high-to-low transition
on SDA, while SCL remains high. This indicates that an address/
data stream will follow. All peripherals respond to the start
condition and shift the next eight bits (7-bit address + R/W bit).
The bits are transferred from MSB down to LSB. The peripheral that recognizes the transmitted address responds by pulling
the data line low during the ninth clock pulse. This is known as
an acknowledge bit. All other devices withdraw from the bus at
REV. 0
this point and maintain an idle condition. The idle condition is
when the device monitors the SDA and SCL lines waiting for
the start condition and the correct transmitted address. The
R/W bit determines the direction of the data.
A Logic 0 on the LSB of the first byte means that the master
will write information to the peripheral. A Logic 1 on the LSB
of the first byte means that the master will read information
from the peripheral.
The ADV7314 acts as a standard slave device on the bus. The
data on the SDA pin is eight bits wide, supporting the 7-bit
addresses plus the R/W bit. It interprets the first byte as the
device address and the second byte as the starting subaddress.
There is a subaddress auto-increment facility, which allows data
to be written to or read from registers in ascending subaddress
sequence starting at any valid subaddress. A data transfer is
always terminated by a stop condition. The user can also access
any unique subaddress register on a one-by-one basis without
having to update all the registers.
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
with normal read and write operations, then these cause an
immediate jump to the idle condition. During a given SCL high
period, the user should issue only one start condition, one stop
condition, or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
ADV7314 will not issue an acknowledge and will return to the
idle condition. If in auto-increment mode the user exceeds the
highest subaddress, the following action will be taken:
1. In read mode, the highest subaddress register contents
will continue to be output until the master device issues a
no-acknowledge. This indicates the end of a read. A
no-acknowledge condition is when the SDA line is not
pulled low on the ninth pulse.
2. In write mode, the data for the invalid byte will not be loaded
into any subaddress register, a no-acknowledge will be issued
by the ADV7314, and the part will return to the idle condition.
–17–
ADV7314
Before writing to the subcarrier frequency registers, the ADV7314
must have been reset at least once since power-up.
next read or write operation accesses. All communications with
the part through the bus start with an access to the subaddress
register. A read/write operation is then performed from/to the
target address, which increments to the next address until a stop
command on the bus is performed.
The four subcarrier frequency registers must be updated starting with subcarrier frequency register 0 through subcarrier
frequency register 3. The subcarrier frequency will not update
until the last subcarrier frequency register byte has been received
by the ADV7314.
Register Programming
Figure 18 illustrates an example of the data transfer for a write
sequence and the start and stop conditions.
The following section describes the functionality of each register.
All registers can be read from as well as written to unless otherwise stated.
Figure 19 shows bus write and read sequences.
Subaddress Register (SR7–SR0)
The communications register is an 8-bit write-only register. After
the part has been accessed over the bus and a read/write operation is selected, the subaddress is set up. The subaddress register
determines to/from which register the operation takes place.
REGISTER ACCESS
The MPU can write to or read from all of the registers of the
ADV7314 except the subaddress registers, which are write-only
registers. The subaddress register determines which register the
SDATA
SCLOCK
S
1–7
9
8
START ADRR R/W ACK
1–7
8
9
SUBADDRESS ACK
1–7
8
DATA
9
P
ACK
STOP
Figure 18. Bus Data Transfer
WRITE
SEQUENCE
S
SLAVE ADDR
A(S)
SUB ADDR
A(S)
DATA
S
SLAVE ADDR A(S)
S = START BIT
P = STOP BIT
DATA
A(S) P
LSB = 1
LSB = 0
READ
SEQUENCE
A(S)
SUB ADDR
A(S) S SLAVE ADDR
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
A(S)
DATA
A(M)
DATA
A(M)
P
A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER
Figure 19. Write and Read Sequence
–18–
REV. 0
ADV7314
SR7SR0 Register
00h Power
Mode
Register
Bit Description
Bit 7
Sleep Mode. With this control enabled, the current
consumption is reduced to A level. All DACs and
the internal PLL cct are disabled. I2C registers can
be read from and written to in sleep mode.
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2 Bit 1 Bit 0
0
1
PLL and Oversampling Control. This control
allows the internal PLL cct to be powered down
and the oversampling to be switched off.
DAC F. Power on/off.
DAC E. Power on/off.
DAC D. Power on/off.
DAC C. Power on/off.
DAC B. Power on/off.
DAC A. Power on/off.
PLL on
1
PLL off
0
DAC F off
1
DAC F on
0
DAC E off
1
DAC E on
0
DAC D off
1
DAC D on
0
DAC D off
1
DAC C on
0
DAC B off
1
DAC B on
0
DAC A off
DAC A on
Mode Select BTA T-1004 or 1362 Compatibility
Register
Clock Edge
Reserved
Disabled
1
Enabled
0
Cb clocked on rising edge
1
Y clocked on rising edge
0
Only for PS dual
edge clk mode
Only for PS
interleaved input at
27 MHz
38h
0
0
0
Only if two input
Must be set if the phase
clocks are used
delay between the two
input clocks is <9.25 ns or
>27.75 ns.
SD input only
0
0
1
PS input only
0
1
0
HDTV input only
0
1
1
SD and PS [20-bit]
1
0
0
SD and PS [10-bit]
1
0
1
SD and HDTV [SD
oversampled
1
1
0
SD and HDTV [HDTV
oversampled]
1
1
1
PS only [at 54 MHz]
1
Input Mode
REV. 0
0
0
Clock Align
Y/S Bus Swap
Register Reset
Value (Shaded)
FCh
Sleep Mode on
0
1
01h
Register Setting
Sleep Mode off
0
10-bit data on S Bus
1
10-bit data on Y Bus
–19–
SD Only. 10-Bit/
20-Bit Input mode
ADV7314
SR7SR0 Register
02h Mode Register 0
Bit Description
Reserved
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Test Pattern Black Bar
RGB Matrix
Bit 2 Bit 1 Bit 0 Register Setting
0
0
Zero must be written to
these bits
0
Disabled
1
Enabled
0
Sync on RGB
0
1
RGB/YUV Output
0
RGB component outputs
1
SD Sync
HD Sync
03h
04h
05h
06h
07h
08h
09h
0Ah
Positive Gain to DAC Output
Voltage
Negative Gain to DAC Output
Voltage
0Bh
DAC D,E,F Output
Level
Positive Gain to DAC Output
Voltage
Negative Gain to DAC Output
Voltage
0Ch
0Dh
0Eh
0Fh
YUV component outputs
0
1
x
x
x
x
x
x
0
x
x
x
x
x
x
0
x
x
x
x
x
0
x
x
x
x
x
0
x
x
x
x
x
0
x
x
x
x
x
0
x
x
x
x
x
0
x
x
x
x
x
0
No Sync output
Output SD syncs on
S_HSYNC output, S_VSYNC
output, S_BLANK output
No Sync output
Output HD syncs on
P_HSYNC output, P_VSYNC
output, P_BLANK output
LSB for GY
LSB for RV
LSB for BU
LSB for GV
LSB for GU
Bit 9–2 for GY
Bit 9–2 for GU
Bit 9–2 for GV
Bit 9–2 for BU
Bit 9–2 for RV
0%
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
…
+0.018%
0.036%
……
0
0
1
0
1
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
+7.382%
+7.5%
–7.5%
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
…
1
0
–7.382%
–7.364%
…….
–0.018%
0%
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
…
1
0
0
+0.018%
0.036%
……
+7.382%
+7.5%
–7.5%
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
1
1
1
0
1
1
0
1
0
0
1
0
0
1
1
0
1
0
…
1
1
0
–7.382%
–7.364%
…….
–0.018%
Note 3
Note 3
0
1
RGB Matrix 0
RGB Matrix 1
RGB Matrix 2
RGB Matrix 3
RGB Matrix 4
RGB Matrix 5
RGB Matrix 6
DAC A,B,C Output
Level2
11h, Bit 2 must
be enabled also
Disable Programmable
RGB Matrix
Enable Programmable
RGB Matrix
No Sync
Sync on all RGB outputs
1
1
Reset Value
20h
x
x
x
x
x
x
x
x
Reserved
Reserved
03h
F0h
4Eh
0Eh
24h
92h
7Ch
00h
00h
00h
00h
00h
00h
1
For more detail, refer to Appendix 7.
For more detail on the programmable output levels, refer to the Programmable DAC Gain Control section.
3
Must be written to after power-up/reset.
2
–20–
REV. 0
ADV7314
SR7SR0 Register
10h HD Mode
Register 1
Bit Description
HD Output Standard
Bit 7
Bit 6
Bit 5
Bit 4
HD Input Control Signals
HD 625p
HD Macrovision for 525p/625p
0
0
1
1
0
1
0
1
Bit 1
0
0
1
Bit 0
0
1
0
1
1
0
1
Enabled
0
1
0
1
HD Pixel Data Valid
0
1
0
HD Test Pattern Enable
0
1
HD Test Pattern Hatch/Field
0
1
HD VBI Open
HD Undershoot Limiter
HD Sharpness Filter
REV. 0
Register Setting
EIA770.2 output
EIA770.1 output
Output levels for full input
range
Reserved
HSYNC, VSYNC, BLANK
EAV/SAV codes
Async timing mode
Reserved
525p
625p
1080i
720p
BLANK active high
BLANK active low
Macrovision off
Macrovision on
Pixel data valid off
Pixel data valid on
Reserved
HD test pattern off
HD test pattern on
Hatch
Field/Frame
Disabled
0
1
HD BLANK Polarity
HD Mode
Register 2
Bit 2
0
1
HD 720p
11h
Bit 3
0
0
1
0
1
0
Disabled
–11 IRE
–6 IRE
1
1
–1.5 IRE
Disabled
Enabled
0
1
–21–
Reset Values
00h
00h
ADV7314
SR7SR0 Register
12h
HD Mode
Register 3
Bit Description
Bit 7
HD Y Delay with
Respect to Falling Edge
of HSYNC
Bit 6
HD with Respect to
Falling Edge of HSYNC
HD CGMS
HD CGMS CRC
13h
HD Mode
Register 4
Bit 5
Bit 4
Bit 3
0
0
0
0
0
0
1
0
1
1
0
1
0
1
0
0
0
0
1
0
1
1
0
1
0
1
0
1 clk cycle
2 clk cycle
3 clk cycle
4 clk cycle
0 clk cycle
0
1
HD Double Buffering
0
0
1
0
1
0
0
1
0
1
0
1
HD Timing Reset
x
0
0
Reserved
0
Lines/Frame 1
0
0
0
0
1
HD Sync on PrPb
0
1
HD Color DAC Swap
0
1
HD Gamma Curve A/B
0
1
00h
0 must be written to this bit
Disabled
Enabled
Disabled
Enabled
DAC E = Pb; DAC F = Pr
00h
DAC E = Pr; DAC F = Pb
Gamma Curve A
Gamma Curve B
Disabled
0
1
Enabled
Mode A
0
HD Adaptive Filter
Mode 2
Disabled
Enabled
A low-high-low transition resets the
internal HD timing counters
30 Hz/2200 total samples/line
25 Hz/2640 total samples/line
0 should be written to these bits
VSYNC Input
Update Field/line counter
Field/line counter free running
0
1
HD Gamma Curve
Enable
4Ch
Cr after falling edge of HSYNC
0 must be written to this bit
8-bit input
10-bit input
Disabled
Enabled
0 must be written to this bit
Disabled
Enabled
Field Input
Reserved
HD RGB Input
1
HD Adaptive Filter
Enable2
0
1
0
1
HD VSYNC/Field
Input
1 clk cycle
2 clk cycle
3 clk cycle
4 clk cycle
Disabled
Enabled
Disabled
Enabled
Cb after falling edge of HSYNC
Reset Value
00h
4:4:4
4:2:2
1080i Frame Rate
HD Mode
Register 6
Register Setting
0 clk cycle
HD Cr/Cb Sequence
HD Chroma Input
15h
Bit 0
0
0
1
Sinc Filter on DAC D,
E, F
Reserved
HD Chroma SSAF
HD Mode
Register 5
Bit 1
0
0
1
Reserved
HD Input Format
14h
Bit 2
0
0
Mode B
Disabled
1
Enabled
NOTES
1
When set to 0, the line and field counters automatically wrap around at the end of the field/frame of the standard selected. When set to 1 , the field/line
counters are free running and wrap around when external sync signals indicate so.
2
Adaptive Filter mode is not available in PS only @ 54 MHz input mode.
–22–
REV. 0
ADV7314
SR7SR0
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
15h
Register
HD Y Level1
HD Cr Level1
HD Cb Level1
Bit Description
Register
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Setting
x
x
x
x
x
x
x
x
Y color value
x
x
x
x
x
x
x
x
Cr color value
x
x
x
x
x
x
x
x
Cb color value
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
HD Gamma Curve Enable
HD Mode
Register 6
0
1
0
1
HD Adaptive Filter Mode
HD Adaptive Filter Enable
20h
21h 2
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h 2
HD Sharpness
Filter Gain
HD CGMS
HD CGMS
HD CGMS
HD Gamma
HD Gamma
HD Gamma
HD Gamma
HD Gamma
HD Gamma
HD Gamma
HD Gamma
HD Gamma
HD Gamma
HD Gamma
HD Gamma
HD Gamma
HD Gamma
HD Gamma
HD Gamma
HD Gamma
HD Gamma
HD Gamma
HD Gamma
A1
A
A
A
A
A
A
A
A
A
B
B
B
B
B
B
B
B
B
B
0
1
HD Sharpness Filter Gain Value A
HD Sharpness Filter Gain Value B 0
0
..
0
1
..
1
HD CGMS Data Bits
0
HD CGMS Data Bits
C15
HD CGMS Data Bits
C7
HD Gamma Curve A Data Points x
HD Gamma Curve A Data Points x
HD Gamma Curve A Data Points x
HD Gamma Curve A Data Points x
HD Gamma Curve A Data Points x
HD Gamma Curve A Data Points x
HD Gamma Curve A Data Points x
HD Gamma Curve A Data Points x
HD Gamma Curve A Data Points x
HD Gamma Curve A Data Points x
HD Gamma Curve B Data Points x
HD Gamma Curve B Data Points x
HD Gamma Curve B Data Points x
HD Gamma Curve B Data Points x
HD Gamma Curve B Data Points x
HD Gamma Curve B Data Points x
HD Gamma Curve B Data Points x
HD Gamma Curve B Data Points x
HD Gamma Curve B Data Points x
HD Gamma Curve B Data Points x
0
0
..
1
0
..
1
0
C14
C6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
..
1
0
..
1
0
C13
C5
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
NOTES
1
Used for internal test pattern only.
2
Programmable gamma correction is not available in PS only mode @ 54 MHz operation.
REV. 0
–23–
0
1
..
1
0
..
1
0
C12
C4
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
..
0
1
..
1
0
0
..
1
0
..
1
0
0
..
1
0
..
1
0
1
..
1
0
..
1
C19
C11
C3
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
C18
C10
C2
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
C17
C9
C1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
C16
C8
C0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Gain A = 0
Gain A = +1
……
Gain A = +7
Gain A = –8
……
Gain A = –1
Gain B = 0
Gain B = +1
…….
Gain B = +7
Gain B = –8
……..
Gain B = –1
CGMS 19–16
CGMS 15–8
CGMS 7–0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
Reset Value
A0h
80h
80h
00h
00h
00h
00h
00h
00h
00h
Disabled
Enabled
Mode A
Mode B
Disabled
Enabled
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
ADV7314
SR7–SR0
38h
Register
HD Adaptive Filter
Gain 1
Bit Description
HD Adaptive Filter
Gain 1 Value A
HD Adaptive Filter
Gain 1 Value B
39h
HD Adaptive Filter
Gain 2
HD Adaptive Filter
Gain 3
Bit 6
Bit 5
Bit 4
Bit 2
0
Bit 1
0
Bit 0
0
Register Setting
Gain A = 0
0
..
0
..
0
..
1
..
Gain A = +1
……
0
1
1
0
1
0
1
0
Gain A = +7
Gain A = –8
..
1
..
1
..
1
..
1
……
Gain A = –1
0
0
0
0
0
1
Gain B = 0
Gain B = +1
..
0
..
1
..
1
..
1
…….
Gain B = +7
1
..
0
..
0
..
0
..
Gain B = –8
……..
1
1
1
1
0
0
0
0
Gain B = –1
Gain A = 0
0
..
0
..
0
..
1
..
Gain A = +1
……
0
1
1
0
1
0
1
0
Gain A = +7
Gain A = –8
..
1
..
1
..
1
..
1
……
Gain A = –1
0
0
0
0
0
0
0
1
Gain B = 0
Gain B = +1
..
0
..
1
..
1
..
1
…….
Gain B = +7
1
0
0
0
Gain B = –8
..
1
..
1
..
1
..
1
……..
Gain B = –1
HD Adaptive Filter
Gain 3 Value A
HD Adaptive Filter
Gain 3 Value B
Bit 3
0
0
0
HD Adaptive Filter
Gain 2 Value A
HD Adaptive Filter
Gain 2 Value B
3Ah
Bit 7
0
0
0
0
0
0
0
1
Gain A = 0
Gain A = +1
..
0
..
1
..
1
..
1
……
Gain A = +7
1
..
0
..
0
..
0
..
Gain A = –8
……
1
1
1
1
0
0
0
0
Gain A = –1
Gain B = 0
0
..
0
..
0
..
1
..
Gain B = +1
…….
0
1
1
0
1
0
1
0
Gain B = +7
Gain B = –8
..
1
..
1
..
1
..
1
……..
Gain B = –1
Value
00h
00h
00h
3Bh
HD Adaptive Filter
Threshold A
HD Adaptive Filter
Threshold A Value
x
x
x
x
x
x
x
x
Threshold A
00h
3Ch
HD Adaptive Filter
Threshold B
HD Adaptive Filter
Threshold B Value
x
x
x
x
x
x
x
x
Threshold B
00h
3Dh
HD Adaptive Filter
Threshold C
HD Adaptive Filter
Threshold C Value
x
x
x
x
x
x
x
x
Threshold C
00h
–24–
REV. 0
ADV7314
SR7–
SR0 Register
3Eh
3Fh
40h
SD Mode Register 0
Register Setting
Bit Description
Reserved
Reserved
SD Standard
Bit 7
Bit 6
Bit 5 Bit 4 Bit 3
SD Luma Filter
SD Chroma Filter
41h
42h
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Bit 2
0
0
1
1
0
1
0
1
NTSC
PAL B, D, G, H, I
PAL M
PAL N
LPF NTSC
LPF PAL
Notch NTSC
Notch PAL
SSAF Luma
Luma CIF
Luma QCIF
Reserved
1.3 MHz
0.65 MHz
1.0 MHz
2.0 MHz
Reserved
Chroma CIF
Chroma QCIF
3.0 MHz
0
1
Disabled
Enabled
0
1
0
1
0
1
0
1
Reserved
SD Mode Register 1 SD UV SSAF
SD DAC Output 2
Refer to Output
Configuration section
0
1
Refer to Output
Configuration section
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
No pedestal on YUV
7.5 IRE pedestal on YUV
Y = 700/300 mV
Y = 714/286 mV
0
1
SD Square Pixel
0
1
SD VCR FF/RW Sync
0
1
SD Pixel Data Valid
SD SAV/EAV Step Edge
Control
0
1
0
1
SD Pedestal
0
1
0
1
SD Mode Register 2 SD Pedestal YPrPb Output
0
1
SD Output Levels Y
SD Output Levels PrPb
SD VBI Open
0
1
SD CC Field Control
Reserved
REV. 0
Bit 0
0
1
0
1
0
1
0
1
SD DAC Output 1
43h
Bit 1
0
0
1
1
0
1
0
1
0
–25–
0
0
700 mV p-p[PAL]; 1000 mV
p-p[NTSC]
0
1
1
1
0
1
700 mV p-p
1000 mV p-p
648 mV p-p
Disabled
Enabled
CC disabled
CC on odd field only
CC on even field only
CC on both fields
Reserved
Reset
Value
00h
00h
00h
00h
08h
00h
ADV7314
SR7–
SR0 Register
Bit Description
4 4 h SD Mode Register SD VSYNC–3H
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
0
Disabled
1
VSYNC = 2.5 lines [PAL]
VSYNC = 3 lines [NTSC]
SD RTC/TR/SCR*
0
0
1
1
SD Active Video Length
0
1
SD Chroma
0
1
SD Burst
0
1
SD Color Bars
SD DAC Swap
45h
46h
47h
0
1
0
1
Reserved
Reserved
SD Mode Register SD PrPb Scale
0
1
SD Y Scale
0
1
SD Hue Adjust
0
1
SD Brightness
0
1
SD Luma SSAF Gain
48h
Reserved
Reserved
Reserved
SD Mode Register Reserved
0
1
0
0
0
Reserved
SD Double Buffering
0
0
1
SD Input Format
0
0
1
1
SD Digital Noise
SD Gamma Curve
0
1
0
1
0
1
SD Gamma Control
49h
0
1
0
1
0
1
0
1
SD Mode Register SD Undershoot Limiter
0
0
1
1
Reserved
SD Black Burst Output
0
0
1
SD Chroma Delay
Reserved
Reserved
0
0
1
1
0
1
0
1
0
0
0
1
0
1
Reset
Value
00h
Genlock disabled
Subcarrier reset
Timing reset
RTC enabled
720 pixels
710 [NTSC]/702 [PAL]
Chroma enabled
Chroma disabled
Enabled
Disabled
Disabled
Enabled
DAC B = Luma, DAC C = Chroma
DAC B = Chroma, DAC C = Luma
00h
00h
Disabled
00h
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
0 must be written to
0 must be written to
0 must be written to
00h
0 must be written
Disabled
Enabled
8-bit input
16-bit input
10-bit input
20-bit input
Disabled
Enabled
Disabled
Enabled
Gamma Curve A
Gamma Curve B
Disabled
–11 IRE
–6 IRE
–1.5 IRE
0 must be written
Disabled
Enabled
Disabled
4 clk cycles
8 clk cycles
Reserved
0 must be written
0 must be written
to
00h
to
to
to
*See Figure 31, RTC Timing and Connections.
–26–
REV. 0
ADV7314
SR7SR0 Register
4Ah SD Timing Register 0
Bit Description
SD Slave/Master Mode
Bit 7
SD Timing Mode
SD BLANK Input
SD Luma Delay
SD Timing Reset
4Bh SD Timing Register 1
x
0
1
0
0
0
1
1
0
1
0
1
0
0
0
0
1
1
x
x
x
x
x
Extended Data on Even x
Fields
Extended Data on Even x
Fields
Data on Odd Fields
x
Data on Odd Fields
x
Pedestal on Odd Fields 17
Pedestal on Odd Fields 25
Pedestal on Even Fields 17
Pedestal on Even Fields 25
HSYNC to Pixel Data
Adjust
FSC Register 0
FSC Register 1
FSC Register 2
FSC Register 3
FSC Phase
Closed Captioning
52h
SD Closed Captioning
53h
54h
55h
56h
57h
58h
SD
SD
SD
SD
SD
SD
Closed Captioning
Closed Captioning
Pedestal Register 0
Pedestal Register 1
Pedestal Register 2
Pedestal Register 3
0
0
0
0
0
0
1
1
0
1
0
1
x
x
0
0
1
1
0
1
0
1
0
1
0
1
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Extended Data Bit 15–8
00h
x
x
16
24
16
24
x
x
15
23
15
23
x
x
14
22
14
22
x
x
13
21
13
21
x
x
12
20
12
20
x
x
11
19
11
19
x
x
10
18
10
18
Data Bit 7–0
Data Bit 15–8
Setting any of these bits to 1 will
disable pedestal on the line
number indicated by the bit
settings.
00h
00h
00h
00h
00h
00h
0
0
1
1
0
1
0
1
LINE 1
HSYNC
LINE 313
tA
tC
tB
VSYNC
Figure 20. Timing Register 1 in PAL Mode
REV. 0
Mode 0
Mode 1
Mode 2
Mode 3
Enabled
Disabled
No delay
2 clk cycles
4 clk cycles
6 clk cycles
–40 IRE
–7.5 IRE
A low-high-low transistion will
reset the internal SD timing
counters
Ta = 1 clk cycle
Ta = 4 clk cycles
Ta = 16 clk cycles
Ta = 128 clk cycles
Tb = 0 clk cycle
Tb = 4 clk cycles
Tb = 8 clk cycles
Tb = 18 clk cycles
Tc = Tb
Tc = Tb + 32 s
1 clk cycle
4 clk cycles
16 clk cycles
128 clk cycles
0 clk cycles
1 clk cycle
2 clk cycles
3 clk cycles
Subcarrier Frequency Bit
Subcarrier Frequency Bit
Subcarrier Frequency Bit
Subcarrier Frequency Bit
Subcarrier Phase Bit 9–2
Extended Data Bit 7–0
SD HSYNC to VSYNC Rising
Edge Delay [Mode 1
only] VSYNC Width
[Mode 2 only]
SD
SD
SD
SD
SD
SD
0
1
0
1
SD HSYNC Width
SD HSYNC to VSYNC delay
4Ch
4Dh
4Eh
4Fh
50h
51h
0
0
1
1
0
1
SD Min. Luma Value
Reset
Value
08h
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
0
Slave mode
1
Master mode
–27–
LINE 314
00h
7–0
15–8
23–16
31–24
16h
7Ch
F0h
21h
00h
00h
ADV7314
SR7–
SR0 Register
5 9 h SD CGMS/WSS 0
Bit Description
SD CGMS Data
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
19
18
17
16
CGMS Data Bits C19–C16
SD CGMS CRC
0
1
SD CGMS on Odd
0
1
SD CGMS on Even
SD WSS
5Ah
SD CGMS/WSS 1
SD CGMS/WSS Data
5Bh
5Ch
SD CGMS/WSS 2
SD LSB Register
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
SD
5Dh
5Eh
5Fh
60h
61h
SD Y Scale
SD V Scale
SD U Scale
SD Hue Register
SD Brightness/
WSS
CGMS/WSS Data
LSB for Y Scale
LSB for U Scale
LSB for V Scale
LSB for FSC Phase
Y Scale Value
V Scale Value
U Scale Value
Hue Adjust Value
Brightness Value
Blank WSS Data
62h
SD Luma SSAF
SD Luma SSAF
Gain/Attenuation
63h
SD DNR 0
Coring Gain Border
Coring Gain Data
64h
SD DNR 1
0
1
0
1
13
12
11
10
9
8
5
4
3
2
1
x
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
1
1
1
1
0
0
1
0
0
0
1
1
0
0
1
1
0
0
0
0
0
1
0
1
0
1
0
1
0
0
0
…
1
1
0
0
…
1
1
0
0
…
1
1
0
1
…
0
1
15
14
7
6
x
x
x
x
x
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
DNR Threshold
Border Area
Block Size Control
0
0
1
1
0
0
1
1
0
0
0
…
1
1
0
1
0
1
0
1
0
1
0
0
0
…
1
1
0
1
0
1
–28–
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
CGMS Data Bits C13–C8 or
WSS Data Bits C13–C8
CGMS Data Bits C15–C14
CGMS/WSS Data Bits C7–C0
SD Y Scale Bit 1–0
SD U Scale Bit 1–0
SD V Scale Bit 1–0
Subcarrier Phase Bits 1–0
SD Y Scale Bit 7–2
SD V Scale Bit 7–2
SD U Scale Bit 7–2
SD Hue Adjust Bit 7–0
SD Brightness Bit 6–0
Disabled
Enabled
–4 dB
0 dB
+4 dB
No gain
+1/16 [–1/8]
+2/16 [–2/8]
+3/16 [–3/8]
+4/16 [–4/8]
+5/16 [–5/8]
+6/16 [–6/8]
+7/16 [–7/8]
+8/16 [–1]
No gain
+1/16 [–1/8]
+2/16 [–2/8]
+3/16 [–3/8]
+4/16 [–4/8]
+5/16 [–5/8]
+6/16 [–6/8]
+7/16 [–7/8]
+8/16 [–1]
0
1
…
62
63
2 pixels
4 pixels
8 pixels
16 pixels
Reset Value
00h
00h
00h
00h
00h
00h
00h
00h
00h
Line 23
00h
00h
In DNR
Mode the
values in
brackets
apply
00h
REV. 0
ADV7314
SR7SR0 Register
6 5 h SD DNR 2
Bit Description
DNR Input Select
DNR Mode
DNR Block Offset
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
70h
71h
72h
73h
74h
75h
76h
77h
78h
79h
7Ah
7Bh
SD Gamma A
SD Gamma A
SD Gamma A
SD Gamma A
SD Gamma A
SD Gamma A
SD Gamma A
SD Gamma A
SD Gamma A
SD Gamma A
SD Gamma B
SD Gamma B
SD Gamma B
SD Gamma B
SD Gamma B
SD Gamma B
SD Gamma B
SD Gamma B
SD Gamma B
SD Gamma B
SD Brightness Detect
Field Count Register
7Ch 10-Bit Input
REV. 0
SD Gamma Curve A
SD Gamma Curve A
SD Gamma Curve A
SD Gamma Curve A
SD Gamma Curve A
SD Gamma Curve A
SD Gamma Curve A
SD Gamma Curve A
SD Gamma Curve A
SD Gamma Curve A
SD Gamma Curve B
SD Gamma Curve B
SD Gamma Curve B
SD Gamma Curve B
SD Gamma Curve B
SD Gamma Curve B
SD Gamma Curve B
SD Gamma Curve B
SD Gamma Curve B
SD Gamma Curve B
SD Brightness Value
Field Count
Reserved
Reserved
Reserved
Revision Code
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Points
Points
Points
Points
Points
Points
Points
Points
Points
Points
Points
Points
Points
Points
Points
Points
Points
Points
Points
Points
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
0
0
1
Filter A
0
1
0
Filter B
0
1
1
Filter C
1
0
0
Filter D
0
DNR mode
1
DNR Sharpness mode
0
0
0
0
0 pixel offset
0
0
0
1
1 pixel offset
…
…
…
…
…
1
1
1
0
14 pixel offset
1
1
1
1
15 pixel offset
x
x
x
x
x
x
x
x
A0
x
x
x
x
x
x
x
x
A1
x
x
x
x
x
x
x
x
A2
x
x
x
x
x
x
x
x
A3
x
x
x
x
x
x
x
x
A4
x
x
x
x
x
x
x
x
A5
x
x
x
x
x
x
x
x
A6
x
x
x
x
x
x
x
x
A7
x
x
x
x
x
x
x
x
A8
x
x
x
x
x
x
x
x
A9
x
x
x
x
x
x
x
x
B0
x
x
x
x
x
x
x
x
B1
x
x
x
x
x
x
x
x
B2
x
x
x
x
x
x
x
x
B3
x
x
x
x
x
x
x
x
B4
x
x
x
x
x
x
x
x
B5
x
x
x
x
x
x
x
x
B6
x
x
x
x
x
x
x
x
B7
x
x
x
x
x
x
x
x
B8
x
x
x
x
x
x
x
x
B9
x
x
x
x
x
x
x
x
Read only
x
x
x
Read only
0
0 must be written to this
0
0 must be written to this
0
0 must be written to this
x
x
Read Only
0
0
0
0
0
0
1
0
Must write this for 10 bit
Data Input (SD, PS, HD)
–29–
Reset Value
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
ADV7314
SR7SR0
7Dh
7Eh
7Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
Register
Reserved
Reserved
Reserved
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Bit Description
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MV
MV
MV
MV
MV
MV
MV
MV
MV
MV
MV
MV
MV
MV
MV
MV
MV
MV
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
Control
Control
Control
Control
Control
Control
Control
Control
Control
Control
Control
Control
Control
Control
Control
Control
Control
Control
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bit
–30–
Register Setting
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Reset Value
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
0 must be written to
bits
REV. 0
ADV7314
INPUT CONFIGURATION
Progressive Scan Only or HDTV Only
Address [01h] Input Mode 001 or 010, Respectively
When 10-bit input data is applied, the following bits must be
set to 1:
YCrCb Progressive Scan, HDTV, or any other HD YCrCb data
can be input in 4:2:2 or 4:4:4. In 4:2:2 input mode, the Y data
is input on Pins Y9–Y0 and the CrCb data on Pins C9–C0. In
4:4:4 input mode, Y data is input on Pins Y9–Y0, Cb data on
Pins C9–C0, and Cr data on Pins S9–S0.
Address 0x7C, Bit 1 (Global 10-Bit Enable)
Address 0x13, Bit 2 (HD 10-Bit Enable)
Address 0x48, Bit 4 (SD 10-Bit Enable)
Note that the ADV7314 defaults to simultaneous standard
definition and progressive scan on power-up. Address[01h]:
Input Mode = 011.
If the YCrCb data does not conform to SMPTE 293M (525p),
ITU-R BT.1358M (625p), SMPTE 274M (1080i), SMPTE
296M (720p), or BTA T-1004/1362, the async timing mode must
be used.
Standard Definition Only
Address [01h] Input Mode = 000
RGB data can be input in 4:4:4 format in PS Input mode only
or in HDTV Input mode only when HD RGB input is enabled.
G data is input on Pins Y9–Y0, R data on S9–S0, and B data
on C9–C0.
The 8-bit/10-bit multiplexed input data is input on Pins S9–S0
(or Y9–Y0, depending on Register Address 0x01, Bit7), with S0
being the LSB in 10-bit input mode. Input standards supported
are ITU-R BT.601/656.
The clock signal must be input on the CLKIN_A pin.
In 16-bit input mode, the Y pixel data is input on Pins S9–S2,
and CrCb data is input on Pins C9–C2. The 27 MHz clock
input must be input on the CLKIN_A pin.
MPEG2
DECODER
ADV7314
Input sync signals are optional and are input on the S_VSYNC,
S_ HSYNC, and S_BLANK pins.
YCrCb
27MHz
Cb 10
Cr 10
INTERLACED
TO
PROGRESSIVE
ADV7314
3
MPEG2
DECODER
27MHz
YCrCb
10
S_VSYNC
S_HSYNC
S_BLANK
10
3
C[9:0]
S[9:0]
Y[9:0]
P_VSYNC
P_HSYNC
P_BLANK
Figure 22. Progressive Scan Input Mode
CLKIN_A
S[9:0] or Y[9:0]*
*Selected by Address 0x01 Bit 7
Figure 21 . SD Only Input Mode
REV. 0
Y
CLKIN_A
–31–
ADV7314
ALIGN bit [Address 01h, Bit 3] must be set accordingly. If the
application uses the same clock source for both SD and PS, the
CLOCK ALIGN bit must be set since the phase difference
between both inputs is less than 9.25 ns.
Simultaneous Standard Definition and
Progressive Scan or HDTV
Address [01h]: Input Mode 011(SD 40-Bit, PS 20-Bit) or
101 (SH and HD, SD Oversampled), 110 (SD and HD, HD
Oversampled)
YCrCb PS, HDTV, or any other HD data must be input in
4:2:2 format. In 4:2:2 input mode, the HD Y data is input on
Pins Y9–Y0 and the HD CrCb data on C9–C0.
CLKIN_A
CLKIN_B
If PS 4:2:2 data is interleaved onto a single 10-bit bus, Y9–Y0 are
used for the input port. The input data is to be input at 27 MHz
with the data clocked on the rising and falling edge of the input
clock. The input mode register at Address 01h is set accordingly.
If the YCrCb data does not conform to SMPTE 293M (525p),
ITU-R BT.1358M (625p), SMPTE 274M (1080i), SMPTE
296M (720p), or BTA T-1004, the Async Timing mode must
be used.
tDELAY
tDELAY
9.25ns OR
27.75ns
Figure 25. Clock Phase with Two Input Clocks
Progressive Scan at 27 MHz (Dual Edge) or 54 MHz
Address [01h]: Input Mode 100 OR 111, Respectively
Standard definition data is input on Pins S9–S0, with S0 being the
LSB. Using 8-bit input format, the data is input on Pins S9–S2.
YCrCb progressive scan data can be input at 27 MHz or 54
MHz. The input data is interleaved onto a single 8-/10-bit bus
and is input on Pins Y9–Y0. When a 27 MHz clock is supplied,
the data is clocked in on the rising and falling edge of the input
clock and CLOCK EDGE [Address 01h, Bit 1] must be set
accordingly.
The clock input for SD must be input on CLKIN_A, and the
clock input for HD must be input on CLKIN_B.
The following figures show the possible conditions. (a) Cb data
on the rising edge and (b) Y data on the rising edge.
The 8-bit or 10-bit standard definition data must be compliant
to ITU-R BT.601/656 in 4:2:2 format.
Synchronization signals are optional. SD syncs are input on pins
S_VSYNC, S_ HSYNC, and S_BLANK.
CLKIN_B
HD syncs are input on Pins P_VSYNC, P_ HSYNC, P_BLANK.
Y9–Y0
3FF
00
00
XY
Cb0
Y0
Cr0
Y1
ADV7314
3
MPEG2
DECODER
27MHz
YCrCb
10
CrCb 10
INTERLACED TO
Y
10
PROGRESSIVE
3
27MHz
Figure 26a. Clock Edge Address 01h, Bit 1
Should Be Set to 0
S_VSYNC
S_HSYNC
S_BLANK
CLKIN_A
S[9:0]
CLKIN_B
Y9–Y0
C[9:0]
YCrC b 10
HDTV
DECODER
1080 i
720 p
CrCb 10
Y
10
3
74.25MHz
XY
Y0
Cb0
Y1
Cr0
With a 54 MHz clock, the data is latched on the every rising edge.
CLKIN
ADV7314
27MHz
00
Figure 26b. Clock Edge Address 01h, Bit 1
Should Be Set to 1
P_VSYNC
P_HSYNC
P_BLANK
Figure 23. Simultaneous PS and SD Input
SDTV
DECODER
00
Y[9:0]
CLKIN_B
3
3FF
PIXEL INPUT
DATA
S_VSYNC
S_HSYNC
S_BLANK
3FF
00
00
XY
Cb0
Y0
Cr0
Y1
Figure 26c. Input Sequence in PS Bit Interleaved
Mode, EAV/SAV Followed by Cb0 Data
CLKIN_A
S[9:0]
MPEG2
DECODER
C[9:0]
YCrCb
Y[9:0]
27MHz OR
54MHz
ADV7314
CLKIN_A
P_VSYNC
P_HSYNC
P_BLANK
INTERLACED
TO
PROGRESSIVE
CLKIN_B
Figure 24. Simultaneous HD and SD Input
YCrCb 10
3
If in simultaneous SD/HD input mode, the two clock phases
differ by less than 9.25 ns or more than 27.75 ns, the CLOCK
Y[9:0]
P_VSYNC
P_HSYNC
P_BLANK
Figure 27. 1 10-Bit PS at 27 MHz or 54 MHz
–32–
REV. 0
ADV7314
Table I provides an overview of all possible input configurations.
Table I. Input Configurations
Input Format
ITU-R BT.656
PS Only
HDTV Only
HD RGB
Total Bits
8
4:2:2
Input Video
YCrCb
Input Pins
S9-S2 [MSB = S9]
Subaddress
01h
48h
Register Setting
00h
00h
10
4:2:2
YCrCb
S9-S0 [MSB = S9]
01h
48h
00h
10h
16
4:2:2
Y
CrCb
S9-S2 [MSB = S9]
Y9-Y2 [MSB = Y9]
01h
48h
00h
08h
20
4:2:2
Y
CrCb
S9-S0 [MSB = S9]
Y9-Y0 [MSB = Y9]
01h
48h
00h
18h
8
4:2:2
YCrCb
Y9-Y2 [MSB = Y9]
01h
48h
80h
00h
10
4:2:2
YCrCb
Y9-Y0 [MSB = Y9]
01h
48h
80h
10h
8 [27 MHz clock]
4:2:2
YCrCb
Y9-Y2 [MSB = Y9]
01h
13h
10h
40h
10 [27 MHz clock]
4:2:2
YCrCb
Y9-Y0 [MSB = Y9]
01h
10h
44h
70h
8 [54 MHz clock]
4:2:2
YCrCb
Y9-Y2 [MSB = Y9]
13h
01h
10 [54 MHz clock]
4:2:2
YCrCb
Y9-Y0 [MSB = Y9]
13h
70h
40h
10h
16
4:2:2
Y
Y9-Y2 [MSB = Y9]
13h
01h
44h
10h
20
4:2:2
CrCb
Y
C9-C2 [MSB = C9]
Y9-Y0 [MSB = Y9]
13h
01h
40h
10h
24
4:4:4
CrCb
Y
C9-C0 [MSB = C9]
Y9-Y2 [MSB = Y9]
13h
01h
44h
10h
Cb
Cr
C9-C2 [MSB = C9]
S9-S2 [MSB = S9]
13h
00h
Y
Cb
Y9-Y0 [MSB = Y9]
C9-C0 [MSB = C9]
01h
13h
10h
04h
30
4:4:4
16
4:2:2
Cr
Y
S9-S0 [MSB = S9]
Y9-Y2 [MSB = Y9]
01h
20h
20
4:2:2
CrCb
Y
C9-Y2 [MSB = C9]
Y9-Y0 [MSB = Y9]
13h
01h
40h
20h
24
4:4:4
CrCb
Y
C9-C0 [MSB = C9]
Y9-Y2 [MSB = Y9]
13h
01h
44h
20h
Cb
Cr
C9-Y2 [MSB = C9]
S9-S2 [MSB = S9]
13h
00h
Y
Cb
Y9-Y0 [MSB = Y9]
C9-C0 [MSB = C9]
01h
13h
20h
04h
Cr
G
S9-S0 [MSB = S9]
Y9-Y2 [MSB = Y9]
01h
10h or 20h
B
C9-C2 [MSB = C9]
13h
00h
R
G
S9-S2 [MSB = S9]
Y9-Y0 [MSB = Y9]
15h
01h
02h
10h or 20h
B
R
C9-C0 [MSB = C9]
S9-S0 [MSB = S9]
13h
15h
04h
02h
30
4:4:4
24
4:4:4
30
REV. 0
4:4:4
ITU-R BT.656 and PS
8
8
4:2:2
4:2:2
YCrCb
YCrCb
S9-S2 [MSB = S9]
Y9-Y2 [MSB = Y9]
01h
13h
40h
40h
ITU-R BT.656 and PS
10
4:2:2
YCrCb
S9-S0 [MSB = S9]
48h
01h
00h
40h
10
4:2:2
YCrCb
Y9-Y0 [MSB = Y9]
13h
48h
44h
10h
ITU-R BT.656 and PS or HDTV 8
16
4:2:2
4:2:2
YCrCb
Y
S9-S2 [MSB = S9]
Y9-Y2 [MSB = Y9]
01h
13h
30h or 50h or 60h
60h
ITU-R BT.656 and PS or HDTV 10
4:2:2
CrCb
YCrCb
C9-C2 [MSB = C9]
S9-S0 [MSB = S9]
48h
01h
00h
30h or 50h or 60h
20
4:2:2
Y
CrCb
Y9-Y0 [MSB = Y9]
C9-C0 [MSB = C9]
13h
48h
60h
10h
–33–
ADV7314
OUTPUT CONFIGURATION
These tables show which output signals are assigned to the DACs when the control bits are set accordingly.
Table II. Output Configuration in SD Only Mode
RGB/YUV
Output 02h,
Bit 5
0
SD DAC
Output 1
42h, Bit 2
0
SD DAC
Output 2
42h, Bit 1
0
DAC A
CVBS
DAC B
Luma
DAC C
Chroma
DAC D DAC E
G
B
DAC F
R
0
0
1
G
B
R
CVBS
Luma
Chroma
0
1
0
G
Luma
Chroma
CVBS
B
R
0
1
1
CVBS
B
R
G
Luma
Chroma
1
0
0
CVBS
Luma
Chroma
Y
U
V
1
0
1
Y
U
V
CVBS
Luma
Chroma
1
1
0
Y
Luma
Chroma
CVBS
U
V
1
1
1
CVBS
U
V
Y
Luma
Chroma
0
Luma/Chroma Swap 44h, Bit 7
Table as above
1
Table above with all Luma/Chroma instances swapped
Table III. Output Configuration in HD/PS Only Mode
HD Input
Format
YCrCb 4:2:2
HD RGB
Input 15h,
Bit 1
0
RGB/YPrP
b Output
02h, Bit 5
0
HD Color
Swap 15h,
Bit 3
0
DAC A DAC B DAC C DAC D DAC E DAC F
N/A
N/A
N/A
G
B
R
YCrCb 4:2:2
0
0
1
N/A
N/A
N/A
G
R
B
YCrCb 4:2:2
0
1
0
N/A
N/A
N/A
Y
Pb
Pr
YCrCb 4:2:2
0
1
1
N/A
N/A
N/A
Y
Pr
Pb
YCrCb 4:4:4
0
0
0
N/A
N/A
N/A
G
B
R
YCrCb 4:4:4
0
0
1
N/A
N/A
N/A
G
R
B
YCrCb 4:4:4
0
1
0
N/A
N/A
N/A
Y
Pb
Pr
YCrCb 4:4:4
0
1
1
N/A
N/A
N/A
Y
Pr
Pb
RGB 4:4:4
1
0
0
N/A
N/A
N/A
G
B
R
RGB 4:4:4
1
0
1
N/A
N/A
N/A
G
R
B
RGB 4:4:4
1
1
0
N/A
N/A
N/A
G
B
R
RGB 4:4:4
1
1
1
N/A
N/A
N/A
G
R
B
Table IV. Output Configuration in Simultaneous SD and HD/PS Mode
RGB/YPrP
b Output
02h, Bit 5
0
HD Color
Swap 15h,
Bit 3
0
DAC A
CVBS
DAC B DAC C
Luma
Chroma
DAC D
G
DAC E
B
DAC F
R
ITU-R BT.656 and
HD YCrCb in 4:2:2
0
1
CVBS
Luma
Chroma
G
R
B
ITU-R BT.656 and
HD YCrCb in 4:2:2
1
0
CVBS
Luma
Chroma
Y
Pb
Pr
ITU-R BT.656 and
HD YCrCb in 4:2:2
1
1
CVBS
Luma
Chroma
Y
Pr
Pb
Input Formats
ITU-R BT.656 and
HD YCrCb in 4:2:2
–34–
REV. 0
ADV7314
HD Async Timing Mode
[Subaddress 10h, Bit 3,2]
oversampling rates are not available in async timing mode. When
using async mode, the PLL must be turned off [Subaddress
00h, Bit 1 = 1].
For any input data that does not conform to the standards
selectable in input mode, Subaddress 01h, asynchronous timing mode can be used to interface to the ADV7314. Timing
control signals for HSYNC, VSYNC, and BLANK have to be
programmed by the user. Macrovision and programmable
Figures 28a and 28b show an example of how to program the
ADV7314 to accept a different high definition standard other
than SMPTE 293M, SMPTE 274M, SMPTE 296M, or
ITU-R BT.1358. The truth table in Table V must be followed
when programming the control signals in async timing mode.
TIMING MODES
CLK
P_HSYNC
PROGRAMMABLE
INPUT TIMING
P_VSYNC
P_BLANK
SET ADDRESS 10h,
BIT 6 TO 1
ACTIVE VIDEO
HORIZONTAL SYNC
ANALOG
OUTPUT
81
66
a
66
b
243
c
1920
e
d
Figure 28a. Async Timing Mode—Programming Input Control Signals for SMPTE 295M Compatibility
CLK
P_HSYNC
P_VSYNC
0
P_BLANK
SET ADDRESS 10h,
BIT 6 TO 1
1
ACTIVE VIDEO
HORIZONTAL SYNC
ANALOG OUTPUT
a
b
c
d
Figure 28b. Async Timing Mode—Programming Input Control Signals for Bilevel Sync Signal
REV. 0
–35–
e
ADV7314
Table V. Async Timing Mode Truth Table
P_HSYNC
1 -> 0
0
0 -> 1
1
1
P_VSYNC
0
0 -> 1
0 or 1
0 or 1
0 or 1
P_BLANK*
0 or 1
0 or 1
0
0 -> 1
1 -> 0
50% point of falling edge of tri-level horizontal sync signal
25% point of rising edge of tri-level horizontal sync signal
50% point of falling edge of tri-level horizontal sync signal
50% start of active video
50% end of active video
Reference in
Figures 28a and 28b
a
b
c
d
e
*When async timing mode is enabled, P_BLANK [Pin 25] becomes an active high input. P_BLANK is set to active low at Address 10h, Bit 6.
For standards that do not require a tri-sync level, P_BLANK must be tied low at all times.
HD Timing Reset
[Subaddress 14h, Bit 0]
A timing reset is achieved in setting the HD timing reset control
bit at Address 14h from 0 to 1. In this state, the horizontal and
vertical counters will remain reset. On setting this bit back to 0,
the internal counters will commence counting again.
The minimum time the pin has to be held high is one clock
cycle, otherwise this reset signal might not be recognized. This
timing reset applies to the HD timing counters only.
–36–
REV. 0
ADV7314
SD Real-Time Control, Subcarrier Reset, and Timing Reset
[Subaddress 44h, Bit 2,1]
This reset signal will have to be held high for a minimum of one
clock cycle.
Together with the RTC_SCR_TR pin and SD Mode Register 3,
the ADV7314 can be used in timing reset mode, subcarrier phase
reset mode, or RTC mode.
Since the field counter is not reset, it is recommended that the
reset signal should be applied in Field 7 [PAL] or Field 3
[NTSC]. The reset of the phase will then occur on the next
field, i.e., Field 1, being lined up correctly with the internal
counters. The field count register at Address 7Bh can be used to
identify the number of the active field.
Timing Reset Mode
A timing reset is achieved in a low-to-high transition on the
RTC_SCR_TR pin (Pin 31). In this state, the horizontal and
vertical counters will remain reset. On releasing this pin (set to
low), the internal counters will commence counting again, the
field count will start on Field 1, and the subcarrier phase will
be reset.
RTC Mode
In RTC mode, the ADV7314 can be used to lock to an external
video source. The real-time control mode allows the ADV7314
to automatically alter the subcarrier frequency to compensate
for line length variations. When the part is connected to a device
that outputs a digital datastream in the RTC format (such as an
ADV7183A video decoder, see Figure 31), the part will automatically change to the compensated subcarrier frequency on a
line by line basis. This digital datastream is 67 bits wide and the
subcarrier is contained in Bits 0 to 21. Each bit is two clock
cycles long. 00h should be written into all four subcarrier
frequency registers when using this mode.
The minimum time the pin has to be held high is one clock
cycle; otherwise this reset signal might not be recognized.
This timing reset applies to the SD timing counters only.
Subcarrier Phase Reset
A low-to-high transition on the RTC_SCR_TR pin (Pin 31) will
reset the subcarrier phase to zero on the field following the
subcarrier phase reset when the SD RTC/TR/SCR control bits
at Address 44h are set to 01.
DISPLAY
307
START OF FIELD 4 OR 8
310
FSC PHASE = FIELD 4 OR 8
313
320
NO TIMING RESET APPLIED
DISPLAY
START OF FIELD 1
307
1
2
3
4
FSC PHASE = FIELD 1
5
6
7
21
TIMING RESET PULSE
TIMING RESET APPLIED
Figure 29. Timing Reset Timing Diagram
DISPLAY
307
310
START OF FIELD 4 OR 8
313
FSC PHASE = FIELD 4 OR 8
320
NO FSC RESET APPLIED
DISPLAY
307
310
START OF FIELD 4 OR 8
313
FSC PHASE = FIELD 1
320
FSC RESET PULSE
FSC RESET APPLIED
Figure 30. Subcarrier Reset Timing Diagram
REV. 0
–37–
ADV7314
Reset Sequence
A reset is activated with a high-to-low transition on the RESET pin
[Pin 33] according to the timing specifications. The ADV7314
will revert to the default output configuration. Figure 32 illustrates the RESET sequence timing.
SD VCR FF/RW Sync
[Subaddress 42h, Bit 5]
In DVD record applications where the encoder is used with a
decoder, the VCR FF/RW Sync control bit can be used for nonstandard input video, i.e., in fast forward or rewind modes.
In fast forward mode, the sync information at the start of a new
field in the incoming video usually occurs before the correct
number of lines/field are reached. In rewind mode, this sync
signal usually occurs after the total number of lines/field are
reached. Conventionally this means that the output video will
have corrupted field signals, one generated by the incoming
video and one when the internal lines/field counters reach the
end of a field.
When the VCR FF/RW sync control is enabled [Subaddress 42h,
Bit 5] the lines/field counters are updated according to the
incoming VSYNC signal and the analog output matches the
incoming VSYNC signal.
This control is available in all slave timing modes except Slave
Mode 0.
ADV7314
CLKIN_A
DAC A
DAC B
LCC1
COMPOSITE
VIDEO
e.g., VCR
OR CABLE
GLL
RTC_SCR_TR
P19–P10
VIDEO
DECODER
Y9-Y0/S9–S0*
ADV7183A
DAC C
DAC D
DAC E
*SELECTED BY REGISTER
ADDRESS 01h BIT 7
DAC F
4 BITS
RESERVED
14 BITS
H/L TRANSITION
SUBCARRIER
COUNT START
PHASE
LOW
128
13
0
SEQUENCE
BIT2
21
FSC PLL INCREMENT1
RESET
BIT3
RESERVED
0
RTC
TIME SLOT 01
14
6768
19
VALID INVALID
SAMPLE SAMPLE
8/LINE
LOCKED
CLOCK
5 BITS
RESERVED
NOTES
1F
SC PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7314 FSC DDS REGISTER IS FSC PLL INCREMENTS BITS 21:0
PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS
OF THE ADV7314.
2SEQUENCE BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED; NTSC: 0 = NO CHANGE
3SEQUENCE BIT
RESET ADV7314 DDS
Figure 31. RTC Timing and Connections
RESET
DACs
A, B, C
XXXXXX
DIGITAL TIMING
XXXXXX
OFF
DIGITAL TIMING SIGNALS SUPPRESSED
VALID VIDEO
TIMING ACTIVE
PIXEL DATA
VALID
Figure 32. RESET Timing Sequence
–38–
REV. 0
ADV7314
Vertical Blanking Interval
SD Subcarrier Frequency Registers
[Subaddress 4Ch–4Fh]
The ADV7314 accepts input data that contains VBI data [e.g.,
CGMS, WSS, VITS] in SD and HD modes.
Four 8-bit registers are used to set up the subcarrier frequency.
The value of these registers is calculated in using the following
equation:
For SMPTE 293M [525p] standards, VBI data can be inserted
on Lines 13 to 42 of each frame, or Lines 6 to 43 for ITU-R
BT.1358 [625p] standard. For SD NTSC, this data can be
present on Lines 10 to 20, and in PAL on Lines 7 to 22.
Subcarrier Frequency Register =
If VBI is disabled [Address 11h, Bit 4 for HD; Address 43h,
Bit 4 for SD], VBI data is not present at the output and the
entire VBI is blanked. These control bits are valid in all master
and slave modes.
For example, in NTSC mode,
Ê 227.5 ˆ
23
Subcarrier FrequencyValue = Á
˜ ¥ 2 = 569408542
Ë 1716 ¯
In Slave Mode 0, if VBI is enabled, the blanking bit in the EAV/
SAV code is overwritten; it is possible to use VBI in this timing
mode as well.
In Slave mode 1 or 2, the BLANK control bit must be set to
enabled [Address 4Ah, Bit 3] to allow VBI data to pass through
the ADV7314; otherwise the ADV7314 automatically blanks the
VBI to standard.
If CGMS is enabled and VBI is disabled, the CGMS data will
nevertheless be available at the output.
# Subcarrier Frequency Value
¥ 223
#27 MHz clk cycles in one video line
SD FSC Register 0: 1Eh
SD FSC Register 1: 7Ch
SD FSC Register 2: F0h
SD FSC Register 3: 21h
Refer to the MPU Port Description section for more details on
how to access the subcarrier frequency registers.
Square Pixel Timing [Register 42h, Bit 4]
In square pixel mode, the following timing diagrams apply.
ANALOG
VIDEO
EAV CODE
INPUT PIXELS
NTSC/PAL M SYSTEM
(525 LINES/60Hz)
PAL SYSTEM
(625 LINES/50Hz)
C
F 0 0 X 8 1 8 1
Y
Y
r
F 0 0 Y 0 0 0 0
4 CLOCK
SAV CODE
0 F F A A A
0 F F B B B
C
C
8 1 8 1 F 0 0 X C Y C Y C
Y r Y b
b
0 0 0 0 F 0 0 Y b
r
ANCILLARY DATA
(HANC)
4 CLOCK
272 CLOCK
1280 CLOCK
4 CLOCK
4 CLOCK
344 CLOCK
1536 CLOCK
START OF ACTIVE
VIDEO LINE
END OF ACTIVE
VIDEO LINE
Figure 33. EAV/SAV Embedded Timing
HSYNC
FIELD
PAL = 44 CLOCK CYCLES
NTSC = 44 CLOCK CYCLES
BLANK
PIXEL
DATA
Cb
PAL = 136 CLOCK CYCLES
NTSC = 208 CLOCK CYCLES
Figure 34. Active Pixel Timing
REV. 0
–39–
Y
Cr
Y
ADV7314
FILTER SECTION
HD Sinc Filter
Table VI shows an overview of the programmable filters available on the ADV7314.
0.5
0.4
Table VI. Selectable Filters of the ADV7314
0.3
SD Luma LPF NTSC
SD Luma LPF PAL
SD Luma Notch NTSC
SD Luma Notch PAL
SD Luma SSAF
SD Luma CIF
SD Luma QCIF
SD Chroma 0.65 MHz
SD Chroma 1.0 MHz
SD Chroma 1.3 MHz
SD Chroma 2.0 MHz
SD Chroma 3.0 MHz
SD Chroma CIF
SD Chroma QCIF
SD UV SSAF
HD Chroma Input
HD Sinc Filter
HD Chroma SSAF
40h
40h
40h
40h
40h
40h
40h
40h
40h
40h
40h
40h
40h
40h
42h
13h
13h
13h
0.2
GAIN (dB)
Subaddress
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
5
10
15
20
FREQUENCY (MHz)
25
30
Figure 35. HD Sinc Filter Enabled
0.5
0.4
0.3
0.2
GAIN (dB)
Filter
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
5
10
15
20
FREQUENCY (MHz)
25
30
Figure 36. HD Sinc Filter Disabled
–40–
REV. 0
ADV7314
SD Internal Filter Response
[Subaddress 40h; Subaddress 42, Bit 0]
The Y filter supports several different frequency responses including two low-pass responses, two notch responses, an extended
(SSAF) response, with or without gain boost/attenuation, a CIF
response and a QCIF response. The UV filter supports several
different frequency responses, including six low-pass responses,
a CIF response and a QCIF response, as can be seen in the
Typical Performance Characteristics graphs.
In addition to the chroma filters listed in Table VII, the ADV7314
contains an SSAF filter specifically designed for and applicable
to the color difference component outputs, U and V.
This filter has a cutoff frequency of about 2.7 MHz and –40 dB
at 3.8 MHz, as can be seen in Figure 37. This filter can be
controlled with Address 42h, Bit 0.
If this filter is disabled, the selectable chroma filters shown in
Table VII can be used for the CVBS or Luma/Chroma signal.
If SD SSAF gain is enabled, there are 12 possible responses in
the range from –4 dB to +4 dB [Subaddress 47h, Bit 4]. The
desired response can be chosen by the user by programming the
correct value via the I2C [Subaddress 62h]. The variation of
frequency responses can be seen in the Typical Performance
Characteristics graphs.
EXTENDED UV FILTER MODE
0
GAIN (dB)
–10
Table VII. Internal Filter Specifications
Filter
Pass-Band Ripple 3 dB Bandwidth
(dB)
(MHz)
Luma LPF NTSC
Luma LPF PAL
Luma Notch NTSC
Luma Notch PAL
Luma SSAF
Luma CIF
Luma QCIF
Chroma 0.65 MHz
Chroma 1.0 MHz
Chroma 1.3 MHz
Chroma 2.0 MHz
Chroma 3.0 MHz
Chroma CIF
Chroma QCIF
0.16
0.1
0.09
0.1
0.04
0.127
Monotonic
Monotonic
Monotonic
0.09
0.048
Monotonic
Monotonic
Monotonic
–30
–40
4.24
4.81
2.3/4.9/6.6
3.1/5.6/6.4
6.45
3.02
1.5
0.65
1
1.395
2.2
3.2
0.65
0.5
–50
–60
0
1
2
3
4
5
FREQUENCY (MHz)
Figure 37. UV SSAF Filter
1
Pass-band ripple refers to the maximum fluctuations from the 0 dB response in
the pass band, measured in dB. The pass band is defined to have 0 Hz to fc
(Hz) frequency limits for a low-pass filter, 0 Hz to f1 (Hz) and f2 (Hz) to
infinity for a notch filter, where fc, f1, f2 are the –3 dB points.
2
3 dB bandwidth refers to the –3 dB cutoff frequency.
REV. 0
–20
–41–
6
ADV7314–Typical Performance Characteristics
PROG SCAN Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4
0
–10
–10
–20
–20
–30
–30
GAIN (dB)
GAIN (dB)
PROG SCAN Pr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4
0
–40
–40
–50
–50
–60
–60
–70
–70
–80
0
20
40
60
80 100 120 140
FREQUENCY (MHz)
160
180
–80
200
TPC 1. PS – UV 8 Oversampling Filter—Linear
0
20
40
60
80 100 120 140
FREQUENCY (MHz)
160
180
200
TPC 4. PS – UV 8 Oversampling Filter—SSAF
Y RESPONSE IN PS OVERSAMPLING MODE
Y PASSBAND IN PS OVERSAMPLING MODE
1.0
0
0.5
–10
0
–0.5
–30
GAIN (dB)
GAIN (dB)
–20
–40
–1.0
–1.5
–50
–60
–2.0
–70
–2.5
–80
0
20
40
60
80 100 120 140
FREQUENCY (MHz)
160
180
–3.0
200
TPC 2. PS –Y 8 Oversampling Filter
0
2
–10
–10
–20
–20
–30
–30
–40
–50
–60
–60
–70
–70
40
60
80
100
FREQUENCY (MHz)
120
12
–40
–50
20
10
Y RESPONSE IN HDTV OVERSAMPLING MODE
0
GAIN (dB)
GAIN (dB)
Pr/Pb RESPONSE IN HDTV OVERSAMPLING MODE
0
6
8
FREQUENCY (MHz)
TPC 5. PS – Y 8 Oversampling Filter—Pass Band
0
–80
4
–80
140
TPC 3. HDTV – UV 2 Oversampling Filter
0
20
40
60
80
100
FREQUENCY (MHz)
120
140
TPC 6. HDTV – Y 2 Oversampling Filter
–42–
REV. 0
0
0
–10
–10
–20
–20
MAGNITUDE (dB)
MAGNITUDE (dB)
ADV7314
–30
–40
–30
–40
–50
–50
–60
–60
–70
–70
0
2
4
6
8
FREQUENCY (MHz)
10
12
0
4
6
8
FREQUENCY (MHz)
10
12
TPC 10. Luma PAL Low-Pass Filter
0
0
–10
–10
–20
–20
MAGNITUDE (dB)
MAGNITUDE (dB)
TPC 7. Luma NTSC Low-Pass Filter
2
–30
–40
–50
–30
–40
–50
–60
–60
–70
0
2
4
6
8
FREQUENCY (MHz)
10
–70
12
0
TPC 8. Luma NTSC Notch Filter
2
4
6
8
FREQUENCY (MHz)
10
12
TPC 11. Luma PAL Notch Filter
Y RESPONSE IN SD OVERSAMPLING MODE
0
0
–10
–10
MAGNITUDE (dB)
GAIN (dB)
–20
–30
–40
–50
–30
–40
–60
–50
–70
–60
–80
0
20
40
60
80 100 120 140
FREQUENCY (MHz)
160
180
–70
200
0
TPC 9. Y—16 Oversampling Filter
REV. 0
–20
2
4
6
8
FREQUENCY (MHz)
10
TPC 12. Luma SSAF Filter up to 12 MHz
–43–
12
ADV7314
5
4
4
2
MAGNITUDE (dB)
MAGNITUDE (dB)
0
–2
–4
–6
3
2
1
–8
0
–10
–1
–12
0
1
2
3
5
4
6
0
7
1
2
0
0
–10
MAGNITUDE (dB)
1
–1
–2
–3
5
6
7
–20
–30
–40
–50
–60
–4
–70
–5
0
1
2
3
4
5
6
0
7
2
4
6
8
10
12
10
12
FREQUENCY (MHz)
FREQUENCY (MHz)
TPC 17. Luma CIF LP Filter
TPC 14. Luma SSAF Filter—Programmable Attenuation
0
0
–10
MAGNITUDE (dB)
–10
MAGNITUDE (dB)
4
TPC 16. Luma SSAF Filter—Programmable Gain
TPC 13. Luma SSAF Filter—Programmable Responses
MAGNITUDE (dB)
3
FREQUENCY (MHz)
FREQUENCY (MHz)
–20
–30
–40
–20
–30
–40
–50
–50
–60
–60
–70
0
–70
0
2
4
6
8
10
12
2
4
6
8
FREQUENCY (MHz)
FREQUENCY (MHz)
TPC 18. Chroma 3.0 MHz LP Filter
TPC 15. Luma QCIF LP Filter
–44–
REV. 0
0
0
–10
–10
–20
–20
MAGNITUDE (dB)
MAGNITUDE (dB)
ADV7314
–30
–40
–30
–40
–50
–50
–60
–60
–70
–70
0
2
4
6
8
10
12
0
2
4
FREQUENCY (MHz)
0
0
–10
–10
–20
–20
–30
–40
10
12
–30
–40
–50
–50
–60
–60
–70
–70
0
2
4
6
8
10
12
0
2
4
FREQUENCY (MHz)
6
8
10
12
FREQUENCY (MHz)
TPC 20. Chroma 1.0 MHz LP Filter
TPC 23. Chroma 0.65 MHz LP Filter
0
0
–10
–10
–20
–20
MAGNITUDE (dB)
MAGNITUDE (dB)
8
TPC 22. Chroma 1.3 MHz LP Filter
MAGNITUDE (dB)
MAGNITUDE (dB)
TPC 19. Chroma 2.0 MHz LP Filter
–30
–40
–30
–40
–50
–50
–60
–60
–70
–70
0
2
4
6
8
10
12
0
FREQUENCY (MHz)
2
4
6
8
FREQUENCY (MHz)
TPC 21. Chroma CIF LP Filter
REV. 0
6
FREQUENCY (MHz)
TPC 24. Chroma QCIF LP Filter
–45–
10
12
ADV7314
COLOR CONTROLS AND RGB MATRIX
Programming the RGB Matrix
HD/PS Y Level, Cr Level, Cb Level
[Subaddress 16h–18h]
The RGB matrix should be enabled [Address 02h, Bit 3], the
output should be set to RGB [Address 02h, Bit 5], sync on
PrPb should be disabled [Address 15h, Bit 2], sync on RGB is
optional [Address 02h, Bit 4].
Three 8-bit registers at Address 16h, 17h, 18h are used to program
the output color of the internal HD test pattern generator, whether
it is the lines of the cross hatch pattern or the uniform field test
pattern. They are not functional as color controls on external
pixel data input. For this purpose, the RGB matrix is used.
The standard used for the values for Y and the color difference
signals to obtain white, black, and the saturated primary and
complementary colors conforms to the ITU-R BT.601–4 standard.
Table VIII shows sample color values to be programmed into
the color registers when Output Standard Selection is set to
EIA 770.2.
GY at Addresses 03h and 05h control the output levels on the
green signal, BU at 04h and 08h control the blue signal output
levels, and RV at 04h and 09h control the red output levels. To
control YPrPb output levels, YUV output should be enabled
[Address 02h, Bit 5]. In this case GY [Address 05h; Address 03,
Bit 0–1] is used for the Y output, RV [Address 09; Address 04,
Bit 0–1] is used for the Pr output and BU [Address 08h; Address
04h, Bit 2–3] is used for the Pb output.
If RGB output is selected the RGB matrix scaler uses the following equations:
G = GY Y + GU Pb + GV Pr
B = GY Y + BU Pb
R = GY Y + RV Pr
Table VIII. Sample Color Values for
EIA770.2 Output Standard Selection
Sample
Color
Color Y
Value
Color CR
Value
Color CB
Value
White
Black
Red
Green
Blue
Yellow
Cyan
Magenta
235 (EB)
16 (10)
81 (51)
145 (91)
41 (29)
210 (D2)
170 (AA)
106 (6A)
128 (80)
128(80)
240 (F0)
34 (22)
110 (6E)
146 (92)
16 (10)
222 (DE)
128 (80)
128 (80)
90 (5A)
54 (36)
240 (F0)
16 (10)
166 (A6)
202 (CA)
If YUV output is selected the following equations are used:
Y = GY Y
U = BU Pb
V = RV Pr
On power-up, the RGB matrix is programmed with default values:
Table IX. RGB Matrix Default Values
HD RGB Matrix
[Subaddress 03h–09h]
When the programmable RGB matrix is disabled [Address 02h,
Bit 3], the internal RGB matrix takes care of all YCrCb to YUV
or RGB scaling according to the input standard programmed
into the device.
When the programmable RGB matrix is enabled, the color
components are converted according to the 1080i standard
[SMPTE 274M]:
Y' = 0.2126R' + 0.7152 G' + 0.0722 B'
CR' = [0.5/(1 – 0.0722)] (B'–Y')
CR' = [0.5/(1 – 0.2126)] (R'–Y')
This is reflected in the preprogrammed values for GY = 138Bh,
GU = 93h, GV = 3B, BU = 248h, RV = 1F0.
If another input standard is used, the scale values for GY, GU,
GV, BU, and RV have to be adjusted according to this input
standard. The user must consider that the color component
conversion might use different scale values. For example,
SMPTE 293M uses the following conversion:
Y' = 0.299 R' + 0.587 G' + 0.114 B'
CB' = [0.5 / (1 – 0.114)] (B'–Y')
CR' = [0.5 / (1 – 0.299)] (R'–Y')
The programmable RGB matrix can be used to control the HD
output levels in cases where the video output does not conform
to standard due to altering the DAC output stages such as termination resistors. The programmable RGB matrix is used for
external HD data and is not functional when the HD test pattern
is enabled.
Address
Default
03h
04h
05h
06h
07h
08h
09h
03h
F0h
4Eh
0Eh
24h
92h
7Ch
When the programmable RGB matrix is not enabled, the
ADV7314 automatically scales YCrCb inputs to all standards
supported by this part.
SD Luma and Color Control
[Subaddresses 5Ch, 5Dh, 5Eh, 5Fh]
SD Y scale, SD Cr scale, and SD Cb scale are 10-bit control
registers to scale the Y, U, and V output levels.
Each of these registers represents the value required to scale the
U or V level from 0.0 to 2.0 and Y level from 0.0 to 1.5 of its
initial level. The value of these 10 bits is calculated using the
following equation:
Y, U, or V Scalar Value = Scale Factor 512
For example:
Scale Factor = 1.18
Y, U, or V Scale Value = 1.18 512 = 665.6
Y, U, or V Scale Value = 665 (rounded to the nearest integer)
Y, U, or V Scale Value = 1010 0110 01b
Address 5Ch, SD LSB Register = 15h
Address 5Dh, SD Y Scale Register = A6h
Address 5Eh, SD V Scale Register = A6h
Address 5Fh, SD U Scale Register = A6h
–46–
REV. 0
ADV7314
Standard: PAL.
To add –7 IRE brightness level, write 72h to Address 61h, SD
brightness.
SD Hue Adjust Value
[Subaddress 60h]
The hue adjust value is used to adjust the hue on the composite
and chroma outputs.
[ IRE Value ¥ 2.015631] =
These eight bits represent the value required to vary the hue of
the video data, i.e., the variance in phase of the subcarrier during
active video with respect to the phase of the subcarrier during
the color burst. The ADV7314 provides a range of ± 22.5∞ increments of 0.17578125∞. For normal operation (zero adjustment),
this register is set to 80h. FFh and 00h represent the upper and
lower limit (respectively) of adjustment attainable.
(Hue Adjust) [∞] = 0.17578125∞ (HCRd –128), for positive
hue adjust value.
Ê
ˆ
4
Á 0.17578125 ˜ + 128 = 151d * = 97h
Ë
¯
*Rounded to the nearest integer.
To adjust the hue by –4∞, write 69h to the hue adjust value
register:
[7 ¥ 2.015631] = [14.109417] = 0001110b
[0001110]into twos complement = [1110010]B = 72h
Table X. Brightness Control Values*
Setup
Level In
NTSC with
Pedestal
Setup
Level In
NTSC No
Pedestal
Setup
Level In
PAL
SD
Brightness
22.5 IRE
15 IRE
7.5 IRE
0 IRE
15 IRE
7.5 IRE
0 IRE
–7.5 IRE
15 IRE
7.5 IRE
0 IRE
–7.5 IRE
1Eh
0Fh
00h
71h
*Values in the range from 3Fh to 44h might result in an invalid output signal.
Ê
ˆ
-4
Á 0.17578125 ˜ + 128 = 105d * = 69h
Ë
¯
SD Brightness Detect
[Subaddress 7Ah]
The ADV7314 allows monitoring of the brightness level of the
incoming video data. Brightness detect is a read-only register.
*Rounded to the nearest integer.
SD Brightness Control
[Subaddress 61h]
Double Buffering
[Subaddress 13h, Bit 7; Subaddress 48h, Bit 2]
The brightness is controlled by adding a programmable setup
level onto the scaled Y data. This brightness level may be added
onto the scaled Y data. For NTSC with pedestal, the setup can
vary from 0 IRE to 22.5 IRE. For NTSC without pedestal and
PAL, the setup can vary from –7.5 IRE to +15 IRE.
Double buffered registers are updated once per field on the
falling edge of the VSYNC signal. Double buffering improves
the overall performance since modifications to register settings
will not be made during active video, but take effect on the start
of the active video.
The brightness control register is an 8-bit register. Seven bits of
this 8-bit register are used to control the brightness level. This
brightness level can be a positive or negative value. For example:
Standard: NTSC with pedestal.
To add +20 IRE brightness level, write 28h to Address 61h, SD
brightness.
[ SD BrightnessValue] H =
[ IREValue ¥ 2.015631] H =
[ 20 ¥ 2.015631] H = [ 40.31262] H = 28 H
Double buffering can be activated on the following HD registers:
HD Gamma A and Gamma B curves and HD CGMS registers.
Double buffering can be activated on the following SD registers: SD Gamma A and Gamma B curves, SD Y scale, SD U
scale, SD V scale, SD brightness, SD closed captioning, and
SD Macrovision Bits 5–0.
NTSC WITHOUT PEDESTAL
+7.5 IRE
100 IRE
0 IRE
–7.5 IRE
NO SETUP
VALUE ADDED
POSITIVE SETUP
VALUE ADDED
NEGATIVE SETUP
VALUE ADDED
Figure 38. Examples for Brightness Control Values
REV. 0
–47–
ADV7314
PROGRAMMABLE DAC GAIN CONTROL
DACs A, B, and C are controlled by Register 0A.
DACs D, E, and F are controlled by Register 0B.
The I2C control registers will adjust the output signal gain up or
down from its absolute level.
CASE A
GAIN PROGRAMMED IN DAC O/P LEVEL
REGISTERS, SUBADDRESS 0Ah, 0Bh
700mV
In case B, the video output signal is reduced. The absolute
level of the sync tip and blanking level both decrease with respect
to the reference video output signal. The overall gain of the signal
is reduced from the reference signal.
The range of this feature is specified for ± 7.5% of the nominal
output from the DACs. For example, if the output current of
the DAC is 4.33 mA, the DAC tune feature can change this
output current from 4.008 mA (–7.5%) to 4.658 mA (+7.5%).
The reset value of the vid_out_ctrl registers is 00h –> nominal
DAC output current. Table XI is an example of how the output
current of the DACs varies for a nominal 4.33 mA output current.
Table XI.
Register
0Ah or 0Bh
DAC
Current
(mA)
% Gain
0100 0000 (40h)
0011 1111 (3Fh)
0011 1110 (3Eh)
...
...
0000 0010 (02h)
0000 0001 (01h)
0000 0000 (00h)
4.658
4.653
4.648
...
...
4.43
4.38
4.33
7.5000
7.3820
7.3640
...
...
0.0360
0.0180
0.0000
1111 1111 (FFh)
1111 1110 (FEh)
...
...
1100 0010 (C2h)
1100 0001 (C1h)
1100 0000 (C0h)
4.25
4.23
...
...
4.018
4.013
4.008
–0.0180
–0.0360
...
...
–7.3640
–7.3820
–7.5000
300mV
CASE B
700mV
NEGATIVE GAIN PROGRAMMED IN
DAC OUTPUT LEVEL REGISTERS,
SUBADDRESS 0Ah, 0Bh
300mV
Figure 39. Programmable DAC Gain—Positive
and Negative Gain
(I2C Reset Value,
Nominal)
In case A, the video output signal is gained. The absolute level
of the sync tip and blanking level both increase with respect to
the reference video output signal. The overall gain of the
signal is increased from the reference signal.
–48–
REV. 0
ADV7314
Gamma Correction
[Subaddress 24h–37h for HD, Subaddress 66h–79h for SD]
For the length of 16 to 240, the gamma correction curve has to
be calculated as follows:
y = x
Gamma correction is available for SD and HD video. For each
standard there are 20 8-bit registers. They are used to program
the gamma correction curves A and B. HD gamma curve A is
programmed at Addresses 24h–2Dh, HD gamma curve B at
2Eh–37h. SD gamma curve A is programmed at addresses
66h–6Fh, and SD gamma curve B at Addresses 70h–79h.
where:
y = gamma corrected output.
x = linear input signal.
= gamma power factor.
To program the gamma correction registers, the seven values for
y have to be calculated using the following formula:
Generally, gamma correction is applied to compensate for the
nonlinear relationship between signal input and brightness level
output (as perceived on the CRT). It can also be applied wherever nonlinear processing is used.
g
È x(n –16) ˘
yn = Í
˙ ¥ (240 - 16) + 16
ÍÎ (240 - 16) ˙˚
Gamma correction uses the function
SignalOUT = (Signal IN )
g
where:
where = gamma power factor.
x(n–16) = value for x along x-axis at points.
Gamma correction is performed on the luma data only. The
user has the choice to use two different curves, curve A or curve
B. At any time, only one of these curves can be used.
n = 24, 32, 48, 64, 80, 96, 128, 160, 192, or 224.
The response of the curve is programmed at 10 predefined
locations. In changing the values at these locations, the gamma
curve can be modified. Between these points linear interpolation
is used to generate intermediate values. Considering the curve
to have a total length of 256 points, the 10 locations are at 24,
32, 48, 64, 80, 96, 128, 160, 192, and 224. Location 0, 16,
240, and 255 are fixed and cannot be changed.
For example:
y24 = [(8 / 224)0.5 224] + 16 = 58*
y32 = [(16 / 224)0.5 224] + 16 = 76*
y48 = [(32 / 224)0.5 224] + 16 = 101*
y64 = [(48 / 224)0.5 224] + 16 =120*
y80 = [(64 / 224)0.5 224] + 16 =136*
y96 = [(80 / 224)0.5 224] + 16 = 150*
y128 = [(112 / 224)0.5 224] + 16 = 174*
y160 = [(144 / 224)0.5 224] + 16 = 195*
y192 = [(176 / 224)0.5 224] + 16 = 214*
y224 = [(208 / 224)0.5 224] + 16 = 232*
GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT
250
*rounded to the nearest integer
SIGNAL OUTPUT
The gamma curves in Figure 41 are examples only; any user
defined curve is acceptable in the range of 16 to 240.
200
0.5
150
100
SIGNAL INPUT
50
0
GAMMA CORRECTION BLOCK TO A RAMP INPUT FOR
VARIOUS GAMMA VALUES
300
GAMMA CORRECTED AMPLITUDE
GAMMA CORRECTED AMPLITUDE
300
yn = value for y along the y-axis, which has to be written into
the gamma correction register.
0
50
100
150
LOCATION
200
250
Figure 40. Signal Input (Ramp) and
Signal Output for Gamma 0.5
250
0.3
200
0.5
150
T
PU
100
L
NA
IN
1.5
G
SI
1.8
50
0
0
50
100
150
LOCATION
200
Figure 41. Signal Input (Ramp) and
Selectable Gamma Output Curves
REV. 0
–49–
250
ADV7314
The derivative of the incoming signal is compared to the three
programmable threshold values: HD adaptive filter threshold
A, B, C. The recommended threshold range is from 16 to 235
although any value in the range of 0 to 255 can be used.
HD Sharpness Filter Control and Adaptive Filter Control
[Subaddress 20h, 38h–3Dh]
There are three Filter modes available on the ADV7314:
sharpness filter mode and two adaptive filter modes.
HD Sharpness Filter Mode
To enhance or attenuate the Y signal in the frequency ranges
shown in Figure 42, the following register settings must be used:
HD sharpness filter must be enabled and HD adaptive filter
enable must be disabled.
To select one of the 256 individual responses, the according gain
values for each filter, which range from –8 to +7, must be programmed into the HD sharpness filter gain register at Address 20h.
HD Adaptive Filter Mode
The HD adaptive filter threshold A, B, C registers, the HD
adaptive filter gain 1, 2, 3 registers, and the HD sharpness filter
gain register are used in adaptive filter mode. To activate the
adaptive filter control, HD sharpness filter must be enabled and
HD adaptive filter gain must be enabled.
1. Mode A is used when adaptive filter mode is set to 0. In this
case, Filter B (LPF) will be used in the adaptive filter block.
Also, only the programmed values for Gain B in the HD
sharpness filter gain, HD adaptive filter gain 1, 2, 3 are applied
when needed. The Gain A values are fixed and cannot be
changed.
2. Mode B is used when adaptive filter gain is set to 1. In this
mode, a cascade of Filter A and Filter B is used. Both settings for Gain A and Gain B in the HD sharpness filter gain,
HD adaptive filter gain 1, 2, 3 become active when needed.
SHARPNESS AND ADAPTIVE FILTER CONTROL BLOCK
1.5
1.4
1.3
1.3
1.2
1.2
1.1
1.0
0.9
1.1
1.0
0.9
0.8
0.8
0.7
0.7
0.6
0.6
0.5
1.6
MAGNITUDE RESPONSE (Linear Scale)
1.4
MAGNITUDE
INPUT SIGNAL:
STEP
MAGNITUDE
1.5
The edges can then be attenuated with the settings in HD adaptive
filter gain 1, 2, 3 registers and HD sharpness filter gain register.
According to the settings of the HD adaptive filter mode control, there are two adaptive filter modes available:
0.5
1.5
1.4
1.3
1.2
1.1
1.0
FREQUENCY (MHz)
FREQUENCY (MHz)
FILTER A RESPONSE (Gain Ka)
FILTER B RESPONSE (Gain Kb)
0
2
4
6
8
10
FREQUENCY (MHz)
12
FREQUENCY RESPONSE IN SHARPNESS
FILTER MODE WITH Ka = 3 AND Kb = 7
Figure 42. Sharpness and Adaptive Filter Control Block Frequency Response in
Sharpness Filter Mode with Ka = +3 and Kb = +7
–50–
REV. 0
ADV7314
The effect of the sharpness filter can also be seen when using
the internally generated cross hatch pattern.
HD Sharpness Filter and Adaptive Filter Application Examples
HD Sharpness Filter Application
The HD sharpness filter can be used to enhance or attenuate
the Y video output signal. The following register settings were
used to achieve the results shown in the figures below. Input
data was generated by an external signal source.
Table XIII.
Table XII.
Address
Register
Setting
00h
01h
02h
10h
11h
20h
20h
20h
20h
20h
20h
FCh
10h
20h
00h
81h
00h
08h
04h
40h
80h
22h
Reference in
Figure 43
Address
Register Setting
00h
01h
02h
10h
11h
20h
FCh
10h
20h
00h
85h
99h
In toggling the sharpness filter enable bit [Address 11h, Bit 7],
it can be seen that the line contours of the cross hatch pattern
change their sharpness.
a
b
c
d
e
f
d
a
R2
1
e
b
R4
R1
f
c
1
R2
CH1 500mV
REF A
500mV 4.00s
1
M 4.00s
9.99978ms
CH1
ALL FIELDS
CH1 500mV
REF A
500mV 4.00s
1
M 4.00s
9.99978ms
CH1
ALL FIELDS
Figure 43. HD Sharpness Filter Control with Different Gain Settings for HS Sharpness Filter Gain Value
REV. 0
–51–
ADV7314
Adaptive Filter Control Application
Figures 44 and 45 show a typical signal to be processed by the
adaptive filter control block.
When changing the adaptive filter mode to Mode B, [Address
15h, Bit 6], the following output can be obtained:
: 674mV
@: 446mV
: 332ns
@: 12.8ms
: 692mV
@: 446mV
: 332ns
@: 12.8ms
Figure 46. Output Signal from Adaptive Filter Control
Figure 44. Input Signal to Adaptive Filter Control
: 692mV
@: 446mV
: 332ns
@: 12.8ms
The adaptive filter control can also be demonstrated using the
internally generated cross hatch test pattern and toggling the
adaptive filter control bit [Address 15h, Bit 7].
Table XV.
Figure 45. Output Signal after Adaptive Filter Control
The following register settings were used to obtain the results
shown in Figure 45, i.e., to remove the ringing on the Y signal.
Input data was generated by an external signal source.
Address
Register Setting
00h
01h
02h
10h
11h
15h
20h
38h
39h
3Ah
3Bh
3Ch
3Dh
FCh
38h
20h
00h
85h
80h
00h
ACh
9Ah
88h
28h
3Fh
64h
Table XIV.
Address
Register Setting
00h
01h
02h
10h
11h
15h
20h
38h
39h
3Ah
3Bh
3Ch
3Dh
FCh
38h
20h
00h
81h
80h
00h
ACh
9Ah
88h
28h
3Fh
64h
*All other registers at normal settings.
–52–
REV. 0
ADV7314
SD DIGITAL NOISE REDUCTION
[Subaddress 63h, 64h, 65h]
The digital noise reduction registers are three 8-bit registers.
They are used to control the DNR processing.
DNR is applied to the Y data only. A filter block selects the high
frequency, low amplitude components of the incoming signal
[DNR input select]. The absolute value of the filter output is
compared to a programmable threshold value [DNR threshold
control]. There are two DNR modes available: DNR mode and
DNR sharpness mode.
Coring Gain Border [Address 63h, Bits 3–0]
In DNR mode, if the absolute value of the filter output is smaller
than the threshold, it is assumed to be noise. A programmable
amount [coring gain border, coring gain data] of this noise
signal will be subtracted from the original signal.
In DNR sharpness mode, if the absolute value of the filter output is less than the programmed threshold, it is assumed to be
noise, as before. Otherwise, if the level exceeds the threshold,
now being identified as a valid signal, a fraction of the signal
[coring gain border, coring gain data] will be added to the original signal in order to boost high frequency components and to
sharpen the video image.
In MPEG systems, it is common to process the video information
in blocks of 8 pixels 8 pixels for MPEG2 systems, or 16 pixels
16 pixels for MPEG1 systems [block size control]. DNR can
be applied to the resulting block transition areas that are known
to contain noise. Generally, the block transition area contains
two pixels. It is possible to define this area to contain four pixels
[border area].
These four bits are assigned to the gain factor applied to
border areas.
In DNR mode, the range of gain values is 0–1, in increments of
1/8. This factor is applied to the DNR filter output, which lies
below the set threshold range. The result is then subtracted
from the original signal.
In DNR sharpness mode the range of gain values is 0–0.5, in
increments of 1/16. This factor is applied to the DNR filter
output which lies above the threshold range. The result is added
to the original signal.
Coring Gain Data [Address 63h, Bits 7-4]
These four bits are assigned to the gain factor applied to the
luma data inside the MPEG pixel block.
In DNR mode the range of gain values is 0–1, in increments of
1/8. This factor is applied to the DNR filter output, which lies
below the set threshold range. The result is then subtracted
from the original signal.
In DNR sharpness mode, the range of gain values is 0–0.5, in
increments of 1/16. This factor is applied to the DNR filter
output, which lies above the threshold range. The result is added
to the original signal.
APPLY DATA
CORING GAIN
It is also possible to compensate for variable block positioning
or differences in YCrCb pixel timing with the use of the [DNR
block offset].
DNR MODE
APPLY BORDER
CORING GAIN
OXXXXXXOOXXXXXXO
OXXXXXXOOXXXXXXO
DNR CONTROL
BLOCK SIZE CONTROL
BORDER AREA
BLOCK OFFSET
DNR27 – DNR24 = 01H
OFFSET CAUSED
BY VARIATIONS IN
INPUT TIMING
OXXXXXXOOXXXXXXO
GAIN
NOISE
SIGNAL PATH
CORING GAIN DATA
CORING GAIN BORDER
Figure 48. DNR Block Offset Control
DNR Threshold [Address 64h, Bits 5–0]
These six bits are used to define the threshold value in the range
of 0 to 63. The range is an absolute value.
INPUT FILTER
BLOCK
FILTER
OUTPUT
< THRESHOLD ?
Y DATA
INPUT
FILTER OUTPUT
> THRESHOLD
SUBTRACT SIGNAL
IN THRESHOLD
RANGE FROM
ORIGINAL SIGNAL
–
+
DNR OUT
MAIN SIGNAL PATH
DNR
SHARPNESS
MODE
Border Area [Address 64h, Bit 6]
In setting this bit to a Logic 1, the block transition area can be
defined to consist of four pixels. If this bit is set to a Logic 0,
the border transition area consists of two pixels, where one pixel
refers to two clock cycles at 27 MHz.
720485 PIXELS
(NTSC)
DNR CONTROL
BLOCK SIZE CONTROL
BORDER AREA
BLOCK OFFSET
2 PIXEL
BORDER DATA
GAIN
NOISE
SIGNAL PATH
CORING GAIN DATA
CORING GAIN BORDER
INPUT FILTER
BLOCK
Y DATA
INPUT
88 PIXEL BLOCK
FILTER
OUTPUT
> THRESHOLD ?
FILTER OUTPUT
< THRESHOLD
ADD SIGNAL
ABOVE THRESHOLD
RANGE FROM
ORIGINAL SIGNAL
Figure 49. DNR Border Area
+
+
DNR OUT
MAIN SIGNAL PATH
Figure 47. DNR Block Diagram
REV. 0
88 PIXEL BLOCK
–53–
ADV7314
Block Size Control [Address 64h, Bit 7]
DNR Mode Control [Address 65h, Bit 4]
This bit is used to select the size of the data blocks to be processed.
Setting the block size control function to a Logic 1 defines a
16 pixel ¥ 16 pixel data block; a Logic 0 defines an 8 pixel ¥
8 pixel data block, where one pixel refers to two clock cycles at
27 MHz.
This bit controls the DNR mode selected. A Logic 0 selects
DNR mode; a Logic 1 selects DNR sharpness mode.
DNR Input Select Control [Address 65h, Bit 2–0]
In DNR mode, it is possible to subtract a fraction of the signal
that lies below the set threshold, assumed to be noise, from the
original signal. The threshold is set in DNR Register 1.
Three bits are assigned to select the filter that is applied to the
incoming Y data. The signal that lies in the pass band of the
selected filter is the signal that will be DNR processed. Figure 50
shows the filter responses selectable with this control.
1.0
FILTER D
When DNR sharpness mode is enabled, it is possible to add a
fraction of the signal that lies above the set threshold to the
original signal, since this data is assumed to be valid data and
not noise. The overall effect is that the signal will be boosted
(similar to using extended SSAF filter).
Block Offset Control [Address 65h, Bits 7–4]
0.8
MAGNITUDE
DNR works on the principle of defining low amplitude, high
frequency signals as probable noise and subtracting this noise
from the original signal.
Four bits are assigned to this control, which allows a shift of the
data block of 15 pixels maximum. Consider the coring gain
positions fixed. The block offset shifts the data in steps of one
pixel such that the border coring gain factors can be applied at the
same position regardless of variations in input timing of the data.
FILTER C
0.6
0.4
FILTER B
0.2
FILTER A
0
0
1
2
3
4
FREQUENCY (Hz)
5
6
Figure 50. DNR Input Select
–54–
REV. 0
ADV7314
SD ACTIVE VIDEO EDGE
[Subaddress 42h, Bit 7]
SAV/EAV Step Edge Control
The ADV7314 can control fast rising and falling signals at the
start and end of active video to minimize ringing.
When the active video edge is enabled, the first three pixels and
the last three pixels of the active video on the luma channel are
scaled in such a way that maximum transitions on these pixels
are not possible. The scaling factors are ¥1/8, ¥1/2, ¥7/8. All
other active video passes through unprocessed.
An algorithm monitors SAV and EAV and governs when the
edges are too fast. The result will be reduced ringing at the start
and end of active video for fast transitions.
Subaddress 42h, Bit 7 = 1 enables this feature.
LUMA CHANNEL WITH
ACTIVE VIDEO EDGE
DISABLED
LUMA CHANNEL WITH
ACTIVE VIDEO EDGE
ENABLED
100 IRE
100 IRE
87.5 IRE
50 IRE
12.5 IRE
0 IRE
0 IRE
Figure 51. Example for Active Video Edge Functionality
VOLTS
IRE:FLT
100
0.5
50
0
0
F2
L135
–50
0
2
4
6
8
10
12
Figure 52. Address 42h, Bit 7 = 0
VOLTS
IRE:FLT
100
0.5
50
0
0
F2
L135
–50
–2
REV. 0
0
2
4
6
8
Figure 53. Address 42h, Bit 7 = 1
–55–
10
12
ADV7314
BOARD DESIGN AND LAYOUT CONSIDERATIONS
DAC OUTPUT
3
DAC Termination and Layout Considerations
300
The ADV7314 contains an on-board voltage reference. The
ADV7314 can be used with an external VREF (AD1580).
BNC OUTPUT
1
1.8k
Figure 54. Example for Output Filter for SD,
16 Oversampling
0
An optional analog reconstruction low-pass filter (LPF) may be
required as an anti-imaging filter if the ADV7314 is connected
to a device that requires this filtering. The filter specifications
vary with the application.
16n
–5
–15
14n
12n
–90
PHASE (Deg)
10n
–20
–120
8n
–25
–150
6n
–180
4n
GROUP DELAY (sec)
–210
2n
–35
Cutoff
Frequency Attenuation
Application Oversampling (MHz)
–50 dB @ (MHz)
–30
–60
–10
–30
Table XVI. External Filter Requirements
0
CIRCUIT FREQUENCY RESPONSE
MAGNITUDE (dB)
GAIN (dB)
Output buffering on all six DACs is necessary in order to drive
output devices, such as SD or HD monitors. Analog Devices
produces a range of suitable op amps for this application, for
example the AD8061. More information on line driver buffering
circuits is given in the relevant op amp data sheets.
>6.5
>6.5
>12.5
>12.5
>30
>30
75
300
600
Video Output Buffer and Optional Output Filter
2¥
16¥
1¥
8¥
1¥
2¥
22pF
4
The RSET resistors are connected between the RSET pins and
AGND and are used to control the full-scale output current and
therefore the DAC voltage output levels. For full-scale output,
RSET must have a value of 3040 W. The RSET values should not
be changed. RLOAD has a value of 150 W with a 4 gain stage
for full-scale output.
SD
SD
PS
PS
HDTV
HDTV
2.2H
–40
1M
10M
FREQUENCY (Hz)
100M
–240
0
Figure 55. Filter Plot for Output Filter for SD,
16 Oversampling
20.5
209.5
14.5
203.5
44.25
118.5
–56–
REV. 0
ADV7314
DAC OUTPUT
3.3H
22pF
300
198
20n
BNC OUTPUT
300
22pF
CIRCUIT FREQUENCY RESPONSE
0
3
158
–6
1
75
18n
118
–12
4
16n
77.6
–18
14n
1.8k
GAIN (dB)
600
Figure 56. Example for Output Filter for PS,
8¥ Oversampling
–36
–48
1
300
4
75
470nH
220nH
33pF
82pF
12n
MAGNITUDE (dB)
–30
–42
DAC OUTPUT
3
37.6
GROUP DELAY (sec)
–24
PHASE (Deg)
–54
3
BNC OUTPUT
75
–60
1M
1
4
10M
100M
FREQUENCY (Hz)
0
10n
–42.4
8n
–82.4
6n
–122
4n
–162
2n
–202
0
1G
Figure 58. Filter Plot for Output Filter for PS,
8¥ Oversampling
500
500
Figure 57. Example for Output Filter for HDTV,
2¥ Oversampling
CIRCUIT FREQUENCY RESPONSE
0
Table XVII shows possible output rates from the ADV7314.
18n
360
MAGNITUDE (dB)
–10
Table XVII.
480
15n
240
Input Mode
Address 01h, Bit 6–4
PLL
Output
Address 00h, Bit 1 Rate
SD Only
Off
On
GAIN (dB)
–20
27 MHz (2¥)
216 MHz (16¥)
12n
GROUP DELAY (sec)
120
–30
9n
0
–40
6n
PHASE (Deg)
PS Only
Off
On
27 MHz (1¥)
216 MHz (8¥)
–50
HDTV Only
Off
On
74.25 MHz (1¥)
148.5 MHz (2¥)
–60
1M
–120
3n
10M
100M
FREQUENCY (Hz)
Figure 59. Example for Output Filter HDTV,
2¥ Oversampling
REV. 0
–57–
–240
0
1G
ADV7314
PC BOARD LAYOUT CONSIDERATIONS
Supply Decoupling
The ADV7314 is optimally designed for lowest noise performance, for both radiated and conducted noise. To complement
the excellent noise performance of the ADV7314, it is imperative that great care be given to the PC board layout.
Noise on the analog power plane can be further reduced by the
use of decoupling capacitors.
Optimum performance is achieved by the use of 10 nF and
0.1 mF ceramic capacitors. Each of group of VAA, VDD, or VDD_IO
pins should be individually decoupled to ground. This should
be done by placing the capacitors as close as possible to the
device with the capacitor leads as short as possible, thus minimizing lead inductance.
The layout should be optimized for lowest noise on the ADV7314
power and ground lines. This can be achieved by shielding the
digital inputs and providing good decoupling. The lead length
between groups of VAA and AGND, VDD and DGND, and
VDD_IO and GND_IO pins should be kept as short as possible to
minimized inductive ringing.
A 1 mF tantalum capacitor is recommended across the VAA supply
in addition to a 10 nF ceramic capacitor. See Figure 60.
It is recommended that a 4-layer printed circuit board is used
with power and ground planes separating the layer of the signal
carrying traces of the components and solder side layer. Component placement should be carefully considered in order to
separate noisy circuits, such as crystal clocks, high speed logic
circuitry, and analog circuitry.
Digital Signal Interconnect
The digital signal lines should be isolated as much as possible
from the analog outputs and other analog circuitry. Digital
signal lines should not overlay the analog power plane.
Due to the high clock rates used, long clock lines to the ADV7314
should be avoided to minimize noise pickup.
There should be a separate analog ground plane and a separate
digital ground plane.
Power planes should encompass a digital power plane and an
analog power plane. The analog power plane should contain the
DACs and all associated circuitry, VREF circuitry. The digital
power plane should contain all logic circuitry.
The analog and digital power planes should be individually connected to the common power plane at one single point through a
suitable filtering device, such as a ferrite bead.
DAC output traces on a PCB should be treated as transmission
lines. It is recommended that the DACs be placed as close as
possible to the output connector, with the analog output traces
being as short as possible (less than 3 inches). The DAC termination resistors should be placed as close as possible to the
DAC outputs and should overlay the PCB’s ground plane. As
well as minimizing reflections, short analog output traces will
reduce noise pickup due to neighboring digital circuitry.
Any active pull-up termination resistors for the digital inputs
should be connected to the digital power plane and not to the
analog power plane.
Analog Signal Interconnect
The ADV7314 should be located as close as possible to the
output connectors, thus minimizing noise pickup and reflections
due to impedance mismatch.
For optimum performance, the analog outputs should each be
source and load terminated, as shown in Figure 60. The termination resistors should be as close as possible to the ADV7314
to minimize reflections.
For optimum performance, it is recommended that all decoupling
and external components relating to the ADV7314 be located on
the same side of the PCB and as close as possible to the ADV7314.
Any unused inputs should be tied to ground.
To avoid crosstalk between the DAC outputs, it is recommended
to leave as much space as possible between the tracks of the
individual DAC output pins. The addition of ground tracks
between outputs is also recommended.
–58–
REV. 0
ADV7314
POWER SUPPLY DECOUPLING FOR
EACH POWER SUPPLY GROUP
VAA
1F
10nF
ADV7314
VAA
VDD
VAA
10, 56
0.1F
10nF
0.1F
VDD_IO
10nF
5k
0.1F
VAA
VDD_ IO
0.1F
1.1k
COMP1 COMP2 VAA VDD VDD_ IO
I2C
VREF
S0–S9
RECOMMENDED EXTERNAL
AD1580 FOR OPTIMUM
PERFORMANCE
100nF
DAC A
150
S_HSYNC
DAC B
S_VSYNC
150
S BLANK
DAC C
150
C0–C9
DAC D
150
Y0–Y9
DAC E
150
CLKIN_B
VDD_ IO
P_HSYNC
DAC F
VDD_ IO
150
P_VSYNC
VAA
100
SCLK
P_BLANK
4.7k
100
SDA
RESET
4.7F
VDD_ IO
ALSB
VAA
CLKIN_A
5k
RSET2
820pF
3040
EXT_LF
GND_IO AGND DGND
680
3.9nF
RSET1
SELECTION HERE
DETERMINES
DEVICE ADDRESS
3040
11, 57
UNUSED INPUTS SHOULD BE GROUNDED.
Figure 60. ADV7314 Circuit Layout
REV. 0
5k
5k
–59–
MPU
BUS
ADV7314
APPENDIX 1—COPY GENERATION
MANAGEMENT SYSTEM
CGMS Functionality
PS CGMS Data Registers 2–0
[Subaddress 21h, 22h, 23h]
PS CGMS is available in 525p mode conforming to CGMS-A
EIA-J CPR1204-1, transfer method of video ID information using
vertical blanking interval (525p system), March 1998, and
IEC61880, 1998, Video systems (525/60)—video and accompanied data using the vertical blanking interval—analog
interface.
When PS CGMS is enabled [Subaddress 12h, Bit 6 = 1],
CGMS data is inserted on line 41. The PS CGMS data registers
are at Addresses 21h, 22h, and 23h.
If SD CGMS CRC [Address 59h, Bit 4] or PS/HD CGMS CRC
[Subaddress 12h, Bit 7] is set to a Logic 1, the last six bits,
C19–C14, which comprise the 6-bit CRC check sequence, are
calculated automatically on the ADV7314 based on the lower
14 bits (C0–C13) of the data in the data registers and output
with the remaining 14 bits to form the complete 20 bits of the
CGMS data. The calculation of the CRC sequence is based on
the polynomial x6 + x + 1 with a preset value of 111111. If SD
CGMS CRC [Address 59h, Bit 4] or PS/HD CGMS CRC [Address 12h, Bit 7] is set to a Logic 0, all 20 bits (C0–C19) are
output directly from the CGMS registers (no CRC calculated,
must be calculated by the user).
SD CGMS Data Registers 2–0
[Subaddress 59h, 5Ah, 5Bh]
Table XVIII.
The ADV7314 supports Copy Generation Management System
(CGMS), conforming to the standard. CGMS data is transmitted on Line 20 of the odd fields and Line 283 of even fields.
Bits C/W05 and C/W06 control whether or not CGMS data is
output on odd and even fields. CGMS data can be transmitted
only when the ADV7314 is configured in NTSC mode. The
CGMS data is 20 bits long, and the function of each of these bits
is as shown in Table XVIII. The CGMS data is preceded by a
reference pulse of the same amplitude and duration as a CGMS
bit; see Figure 62.
HD/PS CGMS [Address 12h, Bit 6]
The ADV7314 supports Copy Generation Management System
(CGMS) in HDTV mode (720p and 1080i) in accordance
with EIAJ CPR-1204-2.
Bit
Function
WORD0
B1
B2
B3
Aspect ratio
Display format
Undefined
WORD0
B4, B5, B6
WORD1
B7, B8, B9, B10
WORD2
B11, B12, B13, B14
The HD CGMS data registers can be found at Address 021h,
22h, 23h.
1
16:9
Letterbox
0
4:3
Normal
Identification information about video
and other signals (e.g., audio)
Identification signal incidental to Word 0
Identification signal and information
incidental to Word 0
Function of CGMS Bits
Word 0–6 bits; Word 1–4 bits; Word 2–6 bits; CRC 6 bits
CRC polynomial = x6 + x + 1 (preset to 111111)
720p System
CGMS data is applied to Line 24 of the luminance vertical
blanking interval.
1080i System
CGMS data is applied to Line 19 and on Line 582 of the luminance vertical blanking interval.
–60–
REV. 0
ADV7314
CRC SEQUENCE
+700mV
REF
70% 10%
BIT 1 BIT 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .BIT 20
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0mV
–300mV
21.2s 0.22s
22T
5.8s 0.15s
6T
T = 1/(fH 33) = 963ns
fH = HORIZONTAL SCAN FREQUENCY
T 30ns
Figure 61. Progressive Scan CGMS Waveform
+100 IRE
CRC SEQUENCE
REF
+70 IRE
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0 IRE
–40 IRE
49.1s 0.5s
11.2s
2.235s 20ns
Figure 62. Standard Definition CGMS Waveform
CRC SEQUENCE
+700mV
REF
70% 10%
BIT 1 BIT 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .BIT 20
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0mV
–300mV
T 30ns
17.2s 160ns
22T
4T
3.128s 90ns
T = 1/(fH 1650/58) = 781.93ns
fH = HORIZONTAL SCAN FREQUENCY
1H
Figure 63. HDTV 720P CGMS Waveform
CRC SEQUENCE
+700mV
REF
70% 10%
BIT 1 BIT 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .BIT 20
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0mV
–300mV
T 30ns
4T
4.15s 60ns
22.84s 210ns
22T
T = 1/(fH 2200/77) = 1.038s
fH = HORIZONTAL SCAN FREQUENCY
1H
Figure 64. HDTV 1080i CGMS Waveform
REV. 0
–61–
ADV7314
APPENDIX 2—SD WIDE SCREEN SIGNALING
[Subaddress 59h, 5Ah, 5Bh]
The ADV7314 supports wide screen signaling (WSS) conforming
to the standard. WSS data is transmitted on Line 23. WSS data
can be transmitted only when the ADV7314 is configured in PAL
mode. The WSS data is 14 bits long, and the function of each of
these bits is as shown in Table XIX. The WSS data is preceded
by a run-in sequence and a start code (see Figure 65). If SD
WSS [Address 59h, Bit 7] is set to a Logic 1, it enables the WSS
data to be transmitted on Line 23. The latter portion of Line 23
(42.5 ms from the falling edge of HSYNC) is available for the
insertion of video.
It is possible to blank the WSS portion of Line 23 with Subaddress
61h, Bit 7.
Table XIX. Function of WSS Bits
Bit
Description
Bit
Description
Bit 0–Bit 2
Aspect Ratio/Format/Position Bits
Bit 3
IS Odd Parity Check of Bit 0–Bit 2
B0, B1, B2, B3
0 0 0 1
1 0 0 0
0 1 0 0
Aspect Ratio
4:3
14:9
14:9
Format
Full Format
Letterbox
Letterbox
Position
Not applicable
Center
Top
B6
0
1
No Helper
Modulated Helper
1
0
1
0
1
16:9
16:9
>16:9
14:9
16:9
Letterbox
Letterbox
Letterbox
Full Format
N/A
Center
Top
Center
Center
N/A
1
0
0
1
1
0
1
1
1
1
1
0
1
1
0
B4
0
1
Camera Mode
Film Mode
B5
0
1
Standard Coding
Motion Adaptive Color Plus
B7
B9
0
1
0
1
Reserved
B10
0
0
1
1
No Open Subtitles
Subtitles in Active Image Area
Subtitles out of Active Image Area
Reserved
B11
0
1
No Surround Sound Information
Surround Sound Mode
B12
Reserved
B13
Reserved
500mV
RUN-IN
SEQUENCE
START
CODE
W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13
ACTIVE
VIDEO
11.0s
38.4s
42.5s
Figure 65. WSS Waveform Diagram
–62–
REV. 0
ADV7314
FCC Code of Federal Regulations (CFR) 47 section 15.119
and EIA608 describe the closed captioning information for
Lines 21 and 284.
APPENDIX 3—SD CLOSED CAPTIONING
[Subaddress 51h–54h]
The ADV7314 supports closed captioning conforming to the
standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active
line time of Line 21 of the odd fields and Line 284 of even fields.
Closed captioning consists of a 7-cycle sinusoidal burst that is
frequency- and phase-locked to the caption data. After the clock
run-in signal, the blanking level is held for two data bits and is
followed by a Logic Level 1 start bit. 16 bits of data follow the
start bit. These consist of two 8-bit bytes, seven data bits, and
one odd parity bit. The data for these bytes is stored in the SD
closed captioning registers [Address 53h–54h].
The ADV7314 also supports the extended closed captioning
operation, which is active during even fields and is encoded on
Scan Line 284. The data for this operation is stored in the SD
closed captioning registers [Address 51h–52h].
All clock run-in signals and timing to support closed captioning
on Lines 21 and 284 are generated automatically by the ADV7314.
All pixels inputs are ignored during Lines 21 and 284 if closed
captioning is enabled.
10.5 0.25s
The ADV7314 uses a single buffering method. This means that
the closed captioning buffer is only one byte deep, therefore
there will be no frame delay in outputting the closed captioning
data unlike other two byte deep buffering systems. The data
must be loaded one line before (Line 20 or Line 283) it is output on Line 21 and Line 284. A typical implementation of this
method is to use VSYNC to interrupt a microprocessor, which
in turn will load the new data (two bytes) every field. If no new
data is required for transmission, 0s must be inserted in both
data registers, which is called nulling. It is also important to load
control codes, all of that are double bytes on Line 21 or a television will not recognize them. If there is a message like Hello
World that has an odd number of characters, it is important
to pad it out to even in order to get end-of-caption 2-byte
control code to land in the same field.
12.91s
7 CYCLES OF
0.5035MHz
CLOCK RUN-IN
TWO 7-BIT + PARITY
ASCII CHARACTERS
(DATA)
S
T
A
R
T
50 IRE
P
A
R
I
T
Y
D0–D6
D0–D6
BYTE 0
40 IRE
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = FSC = 3.579545MHz
AMPLITUDE = 40 IRE
10.003s
27.382s
33.764s
Figure 66. Closed Captioning Waveform, NTSC
REV. 0
–63–
BYTE 1
P
A
R
I
T
Y
ADV7314
APPENDIX 4—TEST PATTERNS
The ADV7314 can generate SD and HD test patterns.
T
T
2
2
CH2 200mV
M 10.0s
A CH2
30.6000s
T
1.20V
CH2 100mV
Figure 67. NTSC Color Bars
M 10.0s
CH2
1.82600ms
T
EVEN
Figure 70. PAL Black Bar (–21 mV, 0 mV, 3.5 mV,
7 mV, 10.5 mV, 14 mV, 18 mV, 23 mV)
T
T
2
2
CH2 200mV
M 10.0s
A CH2
30.6000s
T
1.21V
CH2 200mV
Figure 68. PAL Color Bars
M 4.0s
CH2
1.82944ms
T
EVEN
Figure 71. 525p Hatch Pattern
T
T
2
2
CH2 100mV
M 10.0s
CH2
1.82600ms
T
CH2 200mV
EVEN
Figure 69. NTSC Black Bar (–21 mV, 0 mV, 3.5 mV,
7 mV, 10.5 mV, 14 mV, 18 mV, 23 mV)
M 4.0s
CH2
1.84208ms
T
EVEN
Figure 72. 625p Hatch Pattern
–64–
REV. 0
ADV7314
T
T
2
2
CH2 200mV
M 4.0s
CH2
1.82872ms
T
EVEN
CH2 100mV
Figure 73. 525p Field Pattern
M 4.0s
CH2
1.82936ms
T
EVEN
Figure 75. 625p Field Pattern
T
T
2
2
CH2 200mV
M 4.0s
CH2
1.84176ms
T
EVEN
CH2 100mV
M 4.0s
CH2
1.84176ms
T
EVEN
Figure 74. 525p Black Bar (–35 mV, 0 mV, 7 mV,
14 mV, 21 mV, 28 mV, 35 mV)
Figure 76. 625p Black Bar (–35 mV, 0 mV, 7 mV,
14 mV, 21 mV, 28 mV, 35 mV)
The following register settings are used to generate an SD NTSC
CVBS output on DAC A.
For PAL black bar pattern output on DAC A, the same settings
are used except that subaddress = 40h and register setting = 11h.
Subaddress
Register
Setting
00h
40h
42h
44h
4Ah
80h
10h
40h
40h
08h
The following register settings are used to generate a 525p hatch
pattern on DAC D.
*All other registers are set to default/normal settings.
For PAL CVBS output on DAC A, the same settings are used
except that Subaddress 40h is changed to 11h.
The following register settings are used to generate an SD NTSC
black bar pattern output on DAC A.
Register
Setting
00h
01h
10h
11h
16h
17h
18h
80h
10h
40h
05h
A0h
80h
80h
*All other registers are set to default/normal settings.
Subaddress
Register
Setting
For 625p hatch pattern on DAC D, the same register settings
are used except that subaddress = 10h and register setting = 50h.
00h
02h
40h
42h
44h
4Ah
80h
04h
10h
40h
40h
08h
For a 525p black bar pattern output on DAC D, the same settings
are used as for a 525p hatch pattern except that subaddress = 02h
and register setting = 24h.
*All other registers are set to default/normal settings.
REV. 0
Subaddress
For 625p black bar pattern output on DAC D, the same settings
are used as for a 625p hatch pattern except that subaddress = 02h
and register setting = 24h; and subaddress = 10h and register
setting = 50h.
–65–
ADV7314
APPENDIX 5—SD TIMING MODES
[Subaddress 4Ah]
Mode 0 (CCIR-656)—Slave Option
(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7314 is controlled by the SAV (start active video) and
EAV (end active video) time codes in the pixel data. All timing
information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and
after each line during active picture and retrace. S_VSYNC,
S_HSYNC, and S_BLANK (if not used) pins should be tied
high during this mode. Blank output is available.
ANALOG
VIDEO
EAV CODE
INPUT PIXELS
C
F 0 0 X 8 1 8 1
Y
Y
r
F 0 0 Y 0 0 0 0
4 CLOCK
SAV CODE
0 F F A A A
0 F F B B B
C
C
8 1 8 1 F 0 0 X C Y C Y C
Y r Y b
b
0 0 0 0 F 0 0 Y b
r
ANCILLARY DATA
(HANC)
1440 CLOCK
4 CLOCK
4 CLOCK
PAL SYSTEM
(625 LINES/50Hz)
4 CLOCK
268 CLOCK
NTSC/PAL M SYSTEM
(525 LINES/60Hz)
280 CLOCK
1440 CLOCK
START OF ACTIVE
VIDEO LINE
END OF ACTIVE
VIDEO LINE
Figure 77. SD Slave Mode 0
–66–
REV. 0
ADV7314
Mode 0 (CCIR-656)—Master Option
(Timing Register 0 TR0 = X X X X X 0 0 1)
The ADV7314 generates H, V, and F signals required for the
SAV (start active video) and EAV (end active video) time
codes in the CCIR656 standard. The H bit is output on
S_HSYNC, the V bit is output on S_BLANK, and the F bit is
output on S_VSYNC pin.
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
1
2
3
4
6
5
7
8
9
10
11
20
21
22
H
V
EVEN FIELD
F
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
260
261
262
263
264
265
266
267
268
269
270
271
272
273
283
274
284
285
H
V
ODD FIELD
F
EVEN FIELD
Figure 78. SD Master Mode 0 (NTSC)
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
5
6
7
21
22
23
H
V
EVEN FIELD
F
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
317
318
319
H
V
F
ODD FIELD
EVEN FIELD
Figure 79. SD Master Mode 0 (PAL)
REV. 0
–67–
320
334
335
336
ADV7314
ANALOG
VIDEO
H
V
F
Figure 80. SD Master Mode 0, Data Transitions
Mode 1—Slave Option
(Timing Register 0 TR0 = X X X X X 0 1 0)
In this mode, the ADV7314 accepts horizontal SYNC and
odd/even field signals. A transition of the field input when HSYNC
is low indicates a new frame, i.e., vertical retrace. The BLANK
signal is optional. When the BLANK input is disabled, the
ADV7314 automatically blanks all normally blank lines as per
CCIR-624. HSYNC is input on HSYNC, BLANK on S_BLANK,
and FIELD on S_VSYNC.
DISPLAY
DISPLAY
522
523
VERTICAL BLANK
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
260
261
VERTICAL BLANK
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
HSYNC
BLANK
FIELD
ODD FIELD
EVEN FIELD
Figure 81. SD Slave Mode 1 (NTSC)
–68–
REV. 0
ADV7314
Mode 1—Master Option
(Timing Register 0 TR0 = X X X X X 0 1 1)
In this mode, the ADV7314 can generate horizontal sync and odd/
even field signals. A transition of the field input when HSYNC is
low indicates a new frame i.e., vertical retrace. The BLANK
signal is optional. When the BLANK input is disabled, the
ADV7314 automatically blanks all normally blank lines as per
CCIR-624. Pixel data is latched on the rising clock edge following
the timing signal transitions. HSYNC is output on the S_HSYNC,
BLANK on S_BLANK, and FIELD on S_VSYNC.
DISPLAY
DISPLAY
622
623
VERTICAL BLANK
624
625
1
2
3
4
5
6
7
21
22
23
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
317
318
319
320
334
335
HSYNC
BLANK
ODD FIELD
FIELD
EVEN FIELD
Figure 82. SD Slave Mode 1 (PAL)
HSYNC
FIELD
PAL = 12 CLOCK/2
NTSC = 16 CLOCK/2
BLANK
PIXEL
DATA
Cb
Y
PAL = 132 CLOCK/2
NTSC = 122 CLOCK/2
Figure 83. SD Timing Mode 1—Odd/Even Field Transitions Master/Slave
REV. 0
–69–
Cr
Y
336
ADV7314
Mode 2—Slave Option
(Timing Register 0 TR0 = X X X X X 1 0 0)
In this mode, the ADV7314 accepts horizontal and vertical sync
signals. A coincident low transition of both HSYNC and VSYNC
inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field.
The BLANK signal is optional. When the BLANK input is
disabled the ADV7314 automatically blanks all normally blank
lines as per CCIR-624. HSYNC is input S_HSYNC, BLANK
on S_BLANK, and VSYNC on S_VSYNC.
DISPLAY
522
DISPLAY
VERTICAL BLANK
523
524
525
1
2
3
4
6
5
7
8
10
9
20
11
21
22
HSYNC
BLANK
VSYNC
ODD FIELD
EVEN FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
260
261
262
263
264
265
266
267
268
269
270
271
272
273
283
274
284
285
HSYNC
BLANK
VSYNC
EVEN FIELD
ODD FIELD
Figure 84. SD Slave Mode 2 (NTSC)
DISPLAY
622
623
DISPLAY
VERTICAL BLANK
624
625
1
2
3
4
5
6
7
21
22
23
HSYNC
BLANK
VSYNC
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
309
310
VERTICAL BLANK
311
312
313
314
315
316
317
318
319
320
334
335
336
HSYNC
BLANK
VSYNC
ODD FIELD
EVEN FIELD
Figure 85. SD Slave Mode 2 (PAL)
–70–
REV. 0
ADV7314
Mode 2—Master Option
(Timing Register 0 TR0 = X X X X X 1 0 1)
In this mode, the ADV7314 can generate horizontal and vertical
sync signals. A coincident low transition of both HSYNC and
VSYNC inputs indicates the start of an odd field. A VSYNC low
transition when HSYNC is high indicates the start of an even
field. The BLANK signal is optional. When the BLANK input is
disabled, the ADV7314 automatically blanks all normally blank
lines as per CCIR-624. HSYNC is output on S_HSYNC, BLANK
on S_BLANK, and VSYNC on S_VSYNC.
HSYNC
VSYNC
BLANK
PAL = 12 CLOCK/2
NTSC = 16 CLOCK/2
PIXEL
DATA
Cb
Y
PAL = 132 CLOCK/2
NTSC = 122 CLOCK/2
Figure 86. SD Timing Mode 2 Even-to-Odd Field Transition Master/Slave
HSYNC
VSYNC
BLANK
PAL = 12 CLOCK/2
NTSC = 16 CLOCK/2
PAL = 864 CLOCK/2
NTSC = 858 CLOCK/2
PIXEL
DATA
Cb
Y
Cr
Y
Cb
PAL = 132 CLOCK/2
NTSC = 122 CLOCK/2
Figure 87. SD Timing Mode 2 Odd-to-Even Field Transition Master/Slave
REV. 0
–71–
Cr
Y
ADV7314
Mode 3—Master/Slave Option
(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)
In this mode, the ADV7314 accepts or generates horizontal
sync and odd/even field signals. A transition of the field input
when HSYNC is high indicates a new frame i.e., vertical retrace. The BLANK signal is optional. When the BLANK input
is disabled, the ADV7314 automatically blanks all normally
blank lines as per CCIR-624. HSYNC is output in master mode
and input in slave mode on S_HSYNC, BLANK on S_BLANK,
and VSYNC on S_VSYNC.
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
1
2
3
4
6
5
7
8
9
10
20
11
21
22
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
260
DISPLAY
VERTICAL BLANK
261
262
263
264
265
266
267
268
269
270
271
272
273
283
274
284
285
HSYNC
BLANK
FIELD
ODD FIELD
EVEN FIELD
Figure 88. SD Timing Mode 3 (NTSC)
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
5
6
7
21
22
23
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
317
318
319
320
334
335
336
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
Figure 89. SD Timing Mode 3 (PAL)
–72–
REV. 0
ADV7314
APPENDIX 6—HD TIMING
DISPLAY
FIELD 1
VERTICAL BLANKING INTERVAL
1124
1125
1
2
3
4
5
6
7
8
20
21
22
560
P_VSYNC
P_HSYNC
DISPLAY
FIELD 2
VERTICAL BLANKING INTERVAL
561
562
563
564
565
566
567
568
569
570
583
P_VSYNC
P_HSYNC
Figure 90. 1080i HSYNC and VSYNC Input Timing
REV. 0
–73–
584
585
1123
ADV7314
APPENDIX 7—VIDEO OUTPUT LEVELS
HD YPrPb Output Levels
INPUT CODE
EIA-770.2, STANDARD FOR Y
OUTPUT VOLTAGE
INPUT CODE
940
EIA-770.3, STANDARD FOR Y
OUTPUT VOLTAGE
940
700mV
700mV
64
64
300mV
EIA-770.2, STANDARD FOR Pr/Pb
300mV
EIA-770.3, STANDARD FOR Pr/Pb
OUTPUT VOLTAGE
OUTPUT VOLTAGE
960
960
600mV
512
700mV
512
700mV
64
64
Figure 93. EIA 770.3 Standard Output Signals
(1080i, 720p)
Figure 91. EIA 770.2 Standard Output Signals
(525p/625p)
INPUT CODE
EIA-770.1, STANDARD FOR Y
INPUT CODE
OUTPUT VOLTAGE
782mV
Y–OUTPUT LEVELS FOR
FULL INPUT SELECTION
OUTPUT VOLTAGE
1023
940
700mV
714mV
64
64
300mV
286mV
EIA-770.1, STANDARD FOR Pr/Pb
INPUT CODE
OUTPUT VOLTAGE
Pr/Pb–OUTPUT LEVELS FOR
FULL INPUT SELECTION
OUTPUT VOLTAGE
1023
960
700mV
512
700mV
64
300mV
64
Figure 92. EIA 770.1 Standard Output Signals
(525p/625p)
Figure 94. Output Levels for Full Input Selection
–74–
REV. 0
ADV7314
RGB Output Levels
700mV
550mV
700mV
300mV
300mV
700mV
550mV
300mV
700mV
550mV
700mV
550mV
300mV
700mV
550mV
300mV
300mV
Figure 95. HD RGB Output Levels
700mV
Figure 97. SD RGB Output Levels—RGB Sync Disabled
550mV
700mV
300mV
300mV
0mV
0mV
700mV
550mV
300mV
300mV
0mV
0mV
700mV
550mV
300mV
300mV
0mV
0mV
Figure 96. HD RGB Output Levels—RGB Sync Enabled
REV. 0
550mV
550mV
700mV
550mV
700mV
550mV
Figure 98. SD RGB Output Levels—RGB Sync Enabled
–75–
ADV7314
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
332mV
YELLOW
WHITE
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
YPrPb Output Levels
2150mV
280mV
200mV
220mV
1260mV
1000mV
160mV
900mV
110mV
60mV
140mV
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
WHITE
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
YELLOW
Figure 102. U Levels—PAL
Figure 99. U Levels—NTSC
332mV
280mV
220mV
300mV
160mV
110mV
60mV
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
WHITE
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
Figure 100. U Levels—PAL
YELLOW
Figure 103. Y Levels—NTSC
2150mV
200mV
1260mV
300mV
1000mV
900mV
Figure 104. Y Levels—PAL
140mV
Figure 101. U Levels—NTSC
–76–
REV. 0
ADV7314
VOLTS
IRE:FLT
100
0.5
50
0
0
–50
0
F1
L76
10
20
APL = 44.5%
525 LINE NTSC
SLOW CLAMP TO 0.00V AT 6.72s
30
40
50
60
MICROSECONDS
PRECISION MODE OFF
SYNCHRONOUS
SYNC = A
FRAMES SELECTED 1 2
Figure 105. NTSC Color Bars 75%
VOLTS
0.4
IRE:FLT
50
0.2
0
0
–0.2
–50
–0.4
F1
L76
0
10
NOISE REDUCTION: 15.05dB
APL NEEDS SYNC-SOURCE!
525 LINE NTSC NO FILTERING
SLOW CLAMP TO 0.00 AT 6.72s
20
30
40
50
60
MICROSECONDS
PRECISION MODE OFF
SYNCHRONOUS
SYNC = B
FRAMES SELECTED 1 2
Figure 106. NTSC Chroma
REV. 0
–77–
ADV7314
VOLTS
IRE:FLT
0.6
0.4
50
0
0.2
0
0
–0.2
F2
L238
10
20
30
40
50
60
MICROSECONDS
PRECISION MODE OFF
SYNCHRONOUS
SYNC = SOURCE
FRAMES SELECTED 1 2
NOISE REDUCTION: 15.05dB
APL = 44.3%
525 LINE NTSC NO FILTERING
SLOW CLAMP TO 0.00 AT 6.72s
Figure 107. NTSC Luma
VOLTS
0.6
0.4
0.2
0
–0.2
L608
0
10
NOISE REDUCTION: 0.00dB
APL = 39.1%
625 LINE NTSC NO FILTERING
SLOW CLAMP TO 0.00 AT 6.72s
20
30
40
50
60
MICROSECONDS
PRECISION MODE OFF
SYNCHRONOUS
SOUND-IN-SYNC OFF
FRAMES SELECTED 1 2 3 4
Figure 108. PAL Color Bars 75%
–78–
REV. 0
ADV7314
VOLTS
0.5
0
–0.5
L575
10
20
APL NEEDS SYNC SOURCE!
625 LINE PAL NO FILTERING
SLOW CLAMP TO 0.00 AT 6.72s
30
40
50
60
MICROSECONDS
NO BUNCH SIGNAL
PRECISION MODE OFF
SYNCHRONOUS
SOUND-IN-SYNC OFF
FRAMES SELECTED 1
Figure 109. PAL Chroma
VOLTS
0.5
0
L575
0
10
APL NEEDS SYNC SOURCE!
625 LINE PAL NO FILTERING
SLOW CLAMP TO 0.00 AT 6.72s
20
30
40
50
60
70
MICROSECONDS
NO BUNCH SIGNAL
PRECISION MODE OFF
SYNCHRONOUS
SOUND-IN-SYNC OFF
FRAMES SELECTED 1
Figure 110. PAL Luma
REV. 0
–79–
ADV7314
APPENDIX 8—VIDEO STANDARDS
0HDATUM
SMPTE 274M
ANALOG WAVEFORM
DIGITAL HORIZONTAL BLANKING
*1
4T
272T
4T
1920T
EAV CODE
ANCILLARY DATA
(OPTIONAL) OR BLANKING CODE
SAV CODE
DIGITAL
ACTIVE LINE
F
F
INPUT PIXELS
0
0
0 F
0 V
H*
F
F
4 CLOCK
SAMPLE NUMBER
2112
C
0 F C
0 V b Y r
H*
0
0
C
Y
r
4 CLOCK
0
2199
2116 2156
44
188
192
2111
FVH* = FVH AND PARITY BITS
SAV/EAV: LINE 1–562: F = 0
SAV/EAV: LINE 563–1125: F = 1
SAV/EAV: LINE 1–20; 561–583; 1124–1125: V = 1
SAV/EAV: LINE 21–560; 584–1123: V = 0
FOR A FIELD RATE OF 30Hz: 40 SAMPLES
FOR A FIELD RATE OF 25Hz: 480 SAMPLES
Figure 111. EAV/SAV Input Data Timing Diagram—SMPTE 274M
SMPTE 293M
ANALOG WAVEFORM
ANCILLARY DATA
(OPTIONAL)
EAV CODE
F
F
INPUT PIXELS
0
0
F
0 V
0 H*
F
F
4 CLOCK
SAMPLE NUMBER
719
DIGITAL
ACTIVE LINE
SAV CODE
0
0
F
0
V
0
H*
C
C
b Y r
C
Y r
Y
4 CLOCK
723 736
0HDATUM
799
853
857
0
719
DIGITAL HORIZONTAL BLANKING
FVH* = FVH AND PARITY BITS
SAV: LINE 43–525 = 200H
SAV: LINE 1–42 = 2AC
EAV: LINE 43–525 = 274H
EAV: LINE 1–42 = 2D8
Figure 112. EAV/SAV Input Data Timing Diagram—SMPTE 293M
–80–
REV. 0
ADV7314
ACTIVE
VIDEO
522
523
ACTIVE
VIDEO
VERTICAL BLANK
524
525
1
2
5
6
7
8
9
12
13
14
15
16
42
43
44
Figure 113. SMPTE 293M (525p)
ACTIVE
VIDEO
622
623
ACTIVE
VIDEO
VERTICAL BLANK
624
625
1
2
4
5
6
7
8
9
10
11
12
13
43
44
45
Figure 114. ITU-R BT.1358 (625p)
DISPLAY
VERTICAL BLANKING INTERVAL
747
748
749
750
1
2
3
4
5
6
7
8
25
26
27
744
745
Figure 115. SMPTE 296M (720p)
DISPLAY
VERTICAL BLANKING INTERVAL
FIELD 1
1124
1125
1
2
3
4
5
6
7
8
20
21
22
560
DISPLAY
VERTICAL BLANKING INTERVAL
FIELD 2
561
562
563
564
565
566
567
568
569
570
Figure 116. SMPTE 274M (1080i)
REV. 0
–81–
583
584
585
1123
ADV7314
OUTLINE DIMENSIONS
64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64)
Dimensions shown in millimeters
0.75
0.60
0.45
12.00 BSC
SQ
1.60
MAX
64
49
1
48
SEATING
PLANE
PIN 1
10.00
BSC SQ
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.15
0.05
10
6
2
SEATING
PLANE
0.20
0.09
VIEW A
7
3.5
0
0.10 MAX
COPLANARITY
16
33
32
17
0.50
BSC
VIEW A
ROTATED 90 CCW
0.27
0.22
0.17
COMPLIANT TO JEDEC STANDARDS MS-026BCD
–82–
REV. 0
–83–
–84–
C03749–0–8/03(0)