Anpec APW7074KE-TUL Synchronous buck pwm controller Datasheet

APW7074
Synchronous Buck PWM Controller
Features
General Description
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The APW7074 uses fixed 300KHz switching frequency,
Single 12V Power Supply Required
voltage mode, synchronous PWM controller which
0.8V Reference with 1% Accuracy
drives dual N-channel MOSFETs. The device integrates
Shutdown and Soft-start Function
all of the control, monitoring and protecting functions
300KHz Fixed Switching Frequency
into a single package, provides one controlled power
Voltage Mode PWM Control Design
output with under-voltage and over-current protections.
Up to 100% Duty Cycle
The APW7074 provides excellent regulation for
Under-Voltage Protection
output load variation. The internal 0.8V temperature-
Over-Current Protection
compensated reference voltage is designed to meet
the requirement of low output voltage applications.
SOP-14 Package
The APW7074 with excellent protection functions:
Lead Free Available (RoHS Compliant)
POR, OCP and UVP. The Power-On-Reset (POR) circuit can monitor the VCC, EN, and OCSET voltage to
make sure the supply voltage exceeds their
Applications
threshold voltage while the controller is running.
The Over-Current Protection (OCP) monitors the out-
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put current by using the voltage drop across the upper
Graphic Cards
and lower MOSFET’s RDS(ON). When the output current reaches the trip point, the controller will run the
soft-start function until the fault events are removed.
The Under-Voltage Protection (UVP) monitors the voltage at FB pin (VFB) for short-circuit protection, when
the VFB is less 50% VREF, the controller will shutdown
the IC directly.
Pin Outs
NC
1
14
V CC
OCSET
2
13
PV CC
SS
3
12
LGA TE
COMP
4
11
PGND
FB
5
10
BOOT
EN
6
9
UGA TE
GND
7
8
PHASE
SOP-14
TOP V IEW
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Feb., 2006
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APW7074
Ordering and Marking Information
Package Code
K : SOP - 14
Temp. Range
E : -20 to 70°C
Handling Code
TU : Tube
Lead Free Code
L : Lead Free Device
APW7074
Lead Free Code
Handling Code
Temp. Range
Package Code
APW7074
XXXXX
APW7074 K :
TR : Tape & Reel
Blank : Original Device
XXXXX- Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate
termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldering
operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C for
MSL classification at lead-free peak reflow temperature.
Block Diagram
OCSET
VCC
GND
BOOT
IOCSET
200uA
Power-On
Reset
EN
UGATE
O.C.P
Comparator
PHASE
VCC
ISS
10uA
0.27V
Soft Start
O.C.P
Comparator
SS
U.V.P
Comparator
50%VREF
:2
PVCC
PWM
Comparator
Gate Control
LGATE
Error Amp
PGND
VREF
Oscillator
Sawtooth
Wave
FOSC
300KHz
FB
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Feb., 2006
COMP
2
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APW7074
Absolute Maximum Ratings
Symbol
Rating
Unit
VCC, PVCC to GND
-0.3 to +16
V
BOOT
BOOT to PHASE
-0.3 to +16
V
UGATE
UGATE to PHASE <400ns pulse width
>400ns pulse width
-5 to BOOT+5
-0.3 to BOOT +0.3
V
LGATE to PGND
-5 to PVCC+5
-0.3 to BOOT +0.3
-5 to +21
-0.3 to 16
VCC+0.3
VCC, PVCC
LGATE
PHASE
OCSET
FB, COMP
PGND
TJ
Parameter
PHASE to GND
<400ns pulse width
>400ns pulse width
<400ns pulse width
>400ns pulse width
OCSET to GND
FB, COMP to GND
V
V
V
-0.3 to 7
V
PGND to GND
-0.3 to +0.3
V
Junction Temperature Range
-20 to +150
°C
-65 ~ 150
°C
TSTG
Storage Temperature
TSDR
Soldering Temperature (10 Seconds)
300
°C
VESD
Minimum ESD Rating
±2
KV
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Symbol
VCC, PVCC
VIN
Parameter
Rating
Unit
IC Supply Voltage
10.8 to 13.2
V
Converter Input Voltage
2.2 to 13.2
V
VOUT
Converter Output Voltage
0.8 to 5
V
IOUT
Converter Output Current
0 to 25
A
TA
Ambient Temperature Range
-20 to 70
°C
TJ
Junction Temperature Range
-20 to 125
°C
Electrical Characteristics
Unless otherwise specified, these specifications apply over VCC=12V, and TA =-20~70°C. Typical values are at
TA=25°C.
Symbol
Parameter
Test Conditions
APW7074
Min
Unit
Typ
Max
0.5
1
mA
5
10
mA
INPUT SUPPLY CURRENT
ICC
VCC Supply Current
(Shutdown mode)
UGATE, LGATE and EN = GND
VCC Supply Current
UGATE and LGATE Open
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Feb., 2006
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APW7074
Electrical Characteristics (Cont.)
Unless otherwise specified, these specifications apply over VCC=12V, and TA =-20~70°C. Typical values are at
TA=25°C.
Symbol
Parameter
Test Conditions
APW7074
Unit
Min
Typ
Max
Rising VCC Threshold
9
9.5
10.0
V
Falling VCC Threshold
7.5
8
8.5
V
POWER-ON RESET
Rising VOCSET Threshold
1.3
V
VOCSET Hysteresis Voltage
0.1
V
Rising EN threshold Voltage
1.3
V
EN Hysteresis Voltage
0.1
V
OSCILLATOR
FOSC
Oscillator Frequency
VOSC
Ramp Amplitude
Duty
Duty Cycle Range
255
(nominal 1.35V to 2.95V)
300
345
1.6
0
kHz
V
100
%
REFERENCE
VREF
Reference Voltage
0.80
Reference Voltage Tolerance
-1
V
+1
%
PWM ERROR AMPLIFIER
Gain
Open Loop Gain
RL = 10k, CL = 10pF (Note3)
88
dB
RL = 10k, CL = 10pF (Note3)
15
MHz
Slew Rate
RL = 10k, CL = 10pF (Note3)
6
V/us
FB Input Current
VFB = 0.8V
GBWP Open Loop Bandwidth
SR
0.1
1
uA
VCOPM COMP High Voltage
5.5
V
VCOPM COMP Low Voltage
0
V
ICOMP COMP Source Current
VCOMP = 2V
5
mA
ICOMP COMP Sink Current
VCOMP = 2V
5
mA
GATE DRIVERS
IUGATE Upper Gate Source Current
BOOT = 12V, VUGATE -VPHASE = 2V
2.6
A
IUGATE Upper Gate Sink Current
BOOT = 12V, VUGATE -VPHASE = 2V
1.05
A
ILGATE Lower Gate Source Current
PVCC = 12V, VLGATE = 2V
4.9
A
ILGATE Lower Gate Sink Current
PVCC = 12V, VLGATE = 2V
1.4
A
RUGATE Upper Gate Source Impedance BOOT = 12V, IUGATE = 0.1A
RUGATE Upper Gate Sink Impedance
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Feb., 2006
BOOT = 12V, IUGATE = 0.1A
4
2
3
Ω
1.6
2.4
Ω
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APW7074
Electrical Characteristics (Cont.)
Unless otherwise specified, these specifications apply over VCC=12V, and TA =-20~70°C. Typical values are
at TA=25°C.
Symbol
Parameter
APW7074
Test Conditions
Min
Typ
Max
Unit
GATE DRIVERS (Cont.)
RLGATE
Lower Gate Source Impedance
PVCC = 12V, ILGATE = 0.1A
1.3
1.95
Ω
RLGATE
Lower Gate Sink Impedance
PVCC = 12V, ILGATE = 0.1A
1.25
1.88
Ω
TD
20
Dead Time
nS
PROTECTION
45
50
55
%
OCSET Source Current (Hi-Side) VOCSET = 11.5V
150
200
250
uA
OCP Voltage (Low-Side)
230
270
310
mV
8
10
12
uA
UVFB
FB Under Voltage Level
IOCSET
VOCP
Percent of VREF
SOFT START
ISS
Soft-Start Charge Current
Note 3:Guaranteed by design.
Typical Application Circuit
1uF
12V
VIN
1N4148
1nF
PVCC VCC OCSET
ON
1uH
1uF
EN
2.37K
470uFx2
470uF
BOOT
OFF
0.1uF
SS
UGATE
22nF
APM2509
2.2uH
PHASE
VOUT
1.5nF
APM2506
COMP
LGATE
FB
33nF
SCD24
1000uFx2
7.5R
PGND
GND
8.2nF
2.7K
1K
2K
18R
68nF
Copyright  ANPEC Electronics Corp.
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APW7074
Function Pin Descriptions
VCC (Pin14)
UGATE (Pin9)
Power supply input pin. Connect a nominal 12V power
This pin is the gate driver for the upper MOSFET of
supply to this pin. The power-on reset function
PWM output.
monitors the input voltage by this pin. It is recommended
LGATE (Pin12)
that a decoupling capacitor (1 to 10uF) be connected
This pin is the gate driver for the lower MOSFET of
to GND for noise decoupling.
PWM output.
PVCC (Pin13)
SS (Pin3)
This pin provides a supply voltage for the lower gate
Connect a capacitor to GND and a 10uA current source
drive, connect this pin to VCC pin in normal use.
charges this capacitor to set the soft-start time.
BOOT (Pin10)
OCSET (Pin2)
This pin provides the bootstrap voltage to the upper
This pin serves two functions: a shutdown control and
gate driver for driving the N-channel MOSFET.
the setting of over current limit threshold. Pulling this
PHASE (Pin8)
pin below 1.3V will shutdown the controller, forcing
This pin is the return path for the upper gate driver.
the UGATE and LGATE signals to be low.
Connect this pin to the upper MOSFET source. This
A resistor (Rocset) connected between this pin and
pin is also used to monitor the voltage drop across the
the drain of the high side MOSFET will determine the
MOSFET for over-current protection.
over current limit. An internal 200uA current source
GND (Pin7)
will flow through this resistor, creating a voltage drop,
This pin is the signal ground pin. Connect the GND pin
which will be compared with the voltage across the
to a good ground plane.
high side MOSFET. The threshold of the over current
limit is therefore given by:
PGND (Pin11)
IPEAK =
This pin is the power ground pin for the lower gate
driver. It should be tied to GND pin on the board.
IOCSET (200uA ) × R OCSET
R DS(ON)
COMP (Pin4)
EN (Pin6)
This pin is the output of PWM error amplifier. It is used
Pull this pin above 1.3V to enable the device and pull
to set the compensation components.
this pin below 1.2V to disable the device. In shutdown,
the SS is discharged and the UGATE and LGATE pins
FB (Pin5)
are held low. Note that don’t leave this pin open.
This pin is the inverting input of the PWM error amplifier.
It is used to set the output voltage and the compensation
components. This pin is also monitored for undervoltage protection; if the FB voltage is under 50% of
reference voltage, the device will be shut down.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Feb., 2006
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APW7074
Typical Characteristics
Power Off
Power On
CH1
VCC=12V, Vin=12V
Vo=1.5V, L=1uH
VCC=12V, Vin=12V
Vo=1.5V, L=1uH
CH2
CH1
CH2
CH3
CH3
CH1: Vcc (5V/div)
CH2: SS (2V/div)
CH3: Vo (1V/div)
Time: 2ms/div
CH1: Vcc (5V/div)
CH2: SS (2V/div)
CH3: Vo (1V/div)
Time: 10ms/div
EN (EN=Vcc)
Shutdown (EN=GND)
CH1
VCC=12V, Vin=12V
Vo=1.5V, L=1uH
VCC=12V, Vin=12V
Vo=1.5V, L=1uH
CH1
CH2
CH2
CH3
CH3
CH1: EN (5V/div)
CH2: SS (5V/div)
CH3: Vo (1V/div)
Time: 10ms/div
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Feb., 2006
CH1: EN (5V/div)
CH2: SS (5V/div)
CH3: Vo (1V/div)
Time: 10ms/div
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APW7074
Typical Characteristics
UGATE Falling
UGATE Rising
VCC=12V, Vin=12V
Vo=1.5V, L=1uH
CH1
VCC=12V, Vin=12V
Vo=1.5V, L=1uH
CH1
CH2
CH2
CH3
CH3
CH1: Ug (20V/div)
CH2: Lg (5V/div)
CH3: Phase (10V/div)
Time: 50ms/div
CH1: Ug (20V/div)
CH2: Lg (5V/div)
CH3: Phase (10V/div)
Time: 50ns/div
Load Transient Response
Under Voltage Protection
VCC=12V, Vin=12V
Vo=1.5V, L=1uH
CH1
VCC=12V, Vin=12V
Vo=1.5V, L=1uH
CH1
CH2
CH3
CH4
CH2
CH1: SS (5V/div)
CH2: Io (5A/div)
CH3: Vo (1V/div)
CH4: Ug (10V/div)
Time: 50ms/div
CH1: Vo (500mV/div)
CH2:Io (5A/div)
Time: 200us/div
Copyright  ANPEC Electronics Corp.
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APW7074
Typical Characteristics
Short Test
Over Current Protection
CH1
Vcc=12V, Vin=12V
Vo=1.5V, L=1uH
CH1
Vcc=12V, Vin=12V,Vo=1.5V, L=1uH
Rocset=1KΩ , Rds(on)=8mΩ
CH2
CH3
CH2
CH3
CH4
CH4
CH1: SS (5V/div)
CH2: IL (10A/div)
CH3: Vo (1V/div)
CH4:Ug (20V/div)
Time: 10ms/div
CH1: SS (5V/div)
CH2: IL (10A/div)
CH3: Vo (1V/div)
CH4:Ug (20V/div)
Time: 10ms/div
Reference Voltage vs. Junction Temperature
310
0.804
305
0.802
Reference Voltage(V)
Switching Frequency(KHz)
Switching Frequency vs. Junction Temperature
300
295
290
285
280
275
-40
-20
0
20
40
60
80
0.798
0.796
0.794
0.792
-40
100 120
Junction Temperature ( °C)
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Feb., 2006
0.8
-20
0
20
40
60
80
100
120
Junction Temperature ( °C)
9
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APW7074
Typical Characteristics
UGATE Sink current vs. UGATE Voltage
UGATE Source current vs. UGATE Voltage
3.5
3
VBOOT=12V
VBOOT=12V
2.5
UGATE Sink Current (A)
UGATE Source Current (A)
3
2.5
2
1.5
1
0.5
0
1.5
1
0.5
0
0
2
4
6
8
10
0
12
2
4
6
8
10
UGATE Voltage (V)
UGATE Voltage (V)
LGATE Source current vs. LGATE Voltage
LGATE Sink current vs. LGATE Voltage
6
12
3.5
PVCC=12V
5
PVCC=12V
3
LGATE Sink Current (A)
LGATE Source Current (A)
2
4
3
2
1
0
2.5
2
1.5
1
0.5
0
0
2
4
6
8
10
0
12
LGATE Voltage (V)
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Feb., 2006
2
4
6
8
10
12
LGATE Voltage (V)
10
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APW7074
Function Descriptions
Power On Reset (POR)
Voltage
The Power-On Reset (POR) function of APW7074
continually monitors the input supply voltage (VCC),
VSS
the enable (EN) pin and OCSET pin. The supply
4.2V
voltage (VCC) must exceed its rising POR threshold
voltage. The voltage at OCSET pin is equal to VIN less
a fixed voltage drop (Vocset = VIN- VROCSET). EN pin can
be pulled high with connecting a resistor to VCC. The
VOUT
POR function initiates soft-start operation after VCC,
1.8V
EN and OCSET voltages exceed their POR thresholds.
For operation with a single +12V power source, VIN
and VCC are equivalent and the +12V power source
t0
must exceed the rising VCC threshold. The POR
t1
Time
t2
Figure 1. Soft-Start Internal
function inhibits operation at disabled status (EN pin
low). With both input supplies above their POR
Over-Current Protection (monitor upper MOSFET)
thresholds, the device initiates a soft-start interval.
The APW7074 provides two manners to protect the
Soft-Start/EN
converter from abnormal output load; one monitors
The SS/EN pins control the soft-start and enable or
the voltage across the upper MOSFET and use the
disable the controller. Connect a soft-start capacitor
OCSET pin to set the over-current trip point, the other
from SS pin to GND to set the soft-start interval. Figure1.
monitors the voltage across the lower MOSFET by
shows the soft-start interval. When VCC reaches its
comparing with an internal reference voltage (0.27V).
Power-On-Reset threshold (9.5V), internal 10uA current
A resistor (ROCSET) connected between OCSET pin and
source starts to charge the capacitor. When the SS
the drain of the upper MOSFET will determine the over
reaches the enabled threshold about 1.8V, the inter-
current limit. An internal 200uA current source will flow
nal 0.8V reference starts to rise and follows the SS;
through this resistor, creating a voltage drop, which
the error amplifier output (COMP) suddenly raises to 1.
will be compared with the voltage across the upper
35V, which is the valley of the triangle wave of the
MOSFET. When the voltage across the upper
oscillator, leads the VOUT to start up. Until the SS
MOSFET exceeds the voltage drop across the R OCSET,
reaches about 4.2V, the internal reference completes
an over-current will be detected. The threshold of the
the soft-start interval and reaches to 0.8V; then VOUT
over current limit is therefore given by:
is in regulation. The SS still rises to 5.5V and then
stops.
C
TSoft − Start = t 2 − t 1 = SS ⋅ 2.4 V
ISS
ILIMIT =
IOCSET × R OCSET
R DS (ON )
For the over-current is never occurred in the normal
Where:
CSS = external Soft-Start capacitor
operating load range; the variation of all parameters in
ISS = Soft-Start current=10uA
the above equation should be determined.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Feb., 2006
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APW7074
Function Descriptions (Cont.)
Over-Current Protection (Cont.)
MOSFET’s RDS(ON) and this voltage drop will be com-
- The MOSFET’RDS(ON) is varied by temperature
pared with the internal 0.27V reference voltage. If the
and gate to source voltage, the user should determine
voltage drop across the lower MOSFET’s RDS(ON) is
the maximum RDS(ON) in manufacturer’s datasheet.
larger than 0.27V, an over-current condition is detected.
- The minimum IOCSET (170uA) and minimum ROCSET
The threshold of the over current limit is given by:
should be used in the above equation.
ILIMIT =
- Note that the ILIMIT is the current flow through the
upper MOSFET; ILIMIT must be greater than maximum
0.27V
R DS(ON)
For the over-current is never occurred in the normal
output current add the half of inductor ripple current.
operating load range; the parameters RDS(ON) and ILIMIT
An over current condition will shut down the device
in the above equation also have the same notices as
and discharge the CSS with a 10uA sink current and
the previous section.
then initiate the soft-start sequence. If the over current
Under Voltage Protection
condition is not removed during the soft-start interval,
the device will be shut down while the over current is
The FB pin is monitored during converter operation by
detected and the SS still rises to 4V to complete its
their own Under Voltage (UV) comparator. If the FB
cycle. The soft start function will be cycled until the
voltage drops below 50% of the reference voltage (50%
over current condition is removed. Both over-current
of 0.8V = 0.4V), a fault signal is internally generated,
protections have the same behavior while an over
and the device turns off both high-side and low-side
current condition is detected.
MOSFET and the converter’s output is latched to be
floating.
Over-Current Protection (monitor lower MOSFET)
The other over-current protection monitors the output
current by using the voltage drop across the lower
Application Information
Output Voltage Selection
Output Inductor Selection
The output voltage can be programmed with a resistive
The inductor value determines the inductor ripple
divider. Use 1% or better resistors for the resistive
current and affects the load transient response. Higher
divider is recommended. The FB pin is the inverter
inductor value reduces the inductor’s ripple current and
input of the error amplifier, and the reference voltage
induces lower output ripple voltage. The ripple current
is 0.8V. The output voltage is determined by:
and ripple voltage can be approximated by:

R
VOUT = 0.8 ×  1 + OUT
R GND




IRIPPLE =
Where ROUT is the resistor connected from VOUT to FB
∆VOUT = IRIPPLE × ESR
and RGND is the resistor connected from FB to GND.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Feb., 2006
VIN − VOUT VOUT
×
FS × L
VIN
12
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APW7074
Application Information (Cont.)
Output Inductor Selection (Cont.)
Input Capacitor Selection
where Fs is the switching frequency of the regulator.
The input capacitor is chosen based on the voltage
Although increase of the inductor value and frequency
rating and the RMS current rating. For reliable
reduces the ripple current and voltage, a tradeoff will
operation, select the capacitor voltage rating to be at
exist between the inductor’s ripple current and the
least 1.3 times higher than the maximum input voltage.
regulator load transient response time.
The maximum RMS current rating requirement is
approximately IOUT/2, where IOUT is the load current.
A smaller inductor will give the regulator a faster load
During power up, the input capacitors have to handle
transient response at the expense of higher ripple
large amount of surge current. If tantalum capacitors
current. Increasing the switching frequency (FS) also
are used, make sure they are surge tested by the
reduces the ripple current and voltage, but it will
manufactures. If in doubt, consult the capacitors
increase the switching loss of the MOSFET and the
manufacturer. For high frequency decoupling, a ceramic
power dissipation of the converter. The maximum ripple
capacitor 1uF can be connected between the drain of
current occurs at the maximum input voltage. A good
upper MOSFET and the source of lower MOSFET.
starting point is to choose the ripple current to be
approximately 30% of the maximum output current.
MOSFET Selection
Once the inductance value has been chosen, select
The selection of the N-channel power MOSFETs are
an inductor that is capable of carrying the required
determined by the RDS(ON), reverse transfer capacitance
peak current without going into saturation. In some
(CRSS) and maximum output current requirement. There
types of inductors, especially core that is made of
are two components of loss in the MOSFETs:
ferrite, the ripple current will increase abruptly when it
conduction loss and transition loss. For the upper
saturates. This will result in a larger output ripple
and lower MOSFET, the losses are approximately
voltage.
given by the following:
Output Capacitor Selection
PUPPER = IOUT (1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FS
Higher capacitor value and lower ESR reduce the
PLOWER = IOUT (1+ TC)(RDS(ON))(1-D)
output ripple and the load transient drop. Therefore,
Where IOUT is the load current
selecting high performance low ESR capacitors is
TC is the temperature dependency of RDS(ON)
intended for switching regulator applications. In some
FS is the switching frequency
applications, multiple capacitors have to be parallel to
tSW is the switching interval
achieve the desired ESR value. A small decoupling
D is the duty cycle
capacitor in parallel for bypassing the noise is also
recommended, and the voltage rating of the output
Note that both MOSFETs have conduction loss while
capacitors also must be considered. If tantalum
the upper MOSFET include an additional transition
capacitors are used, make sure they are surge tested
loss. The switching internal, tSW , is a function of the
by the manufactures. If in doubt, consult the capacitors
reverse transfer capacitance C RSS. The (1+TC) term is
manufacturer.
to factor in the temperature dependency of the RDS(ON)
and can be extracted from the “RDS(ON) vs Temperature”
curve of the power MOSFET.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Feb., 2006
13
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APW7074
Application Information (Cont.)
PWM Compensation
The PWM modulator is shown in Figure 4. The input
is the output of the error amplifier and the output is the
The output LC filter of a step down converter introduces
PHASE node. The transfer function of the PWM
a double pole, which contributes with -40dB/decade
modulator is given by:
gain slope and 180 degrees phase shift in the control
loop. A compensation network among COMP, FB and
GAIN PWM =
VOUT should be added. The compensation network is
VIN
∆ V OSC
shown in Fig. 5. The output LC filter consists of the
V IN
output inductor and output capacitors. The transfer
function of the LC filter is given by:
GAIN
LC
OSC
ΔV OSC
1 + s × ESR × C OUT
= 2
s × L × C OUT + s × ESR × C OUT + 1
PWM
Comparator
PHASE
Output of
Error Amplifier
The poles and zero of this transfer functions are:
1
FLC =
2 × π × L × C OUT
FESR =
Driver
Driver
1
2 × π × ESR × C OUT
Figure 4. The PWM Modulator
The FLC is the double poles of the LC filter, and FESR is
The compensation network is shown in Figure 5. It
the zero introduced by the ESR of the output capacitor.
provides a close loop transfer function with the highest
PHASE
L
OUTPUT
zero crossover frequency and sufficient phase margin.
The transfer function of error amplifier is given by:
C OUT
GAIN
ESR
1
1 

//  R2 +

sC1 
sC2 
=
1 

R1//  R3 +

sC3 


1
1

 

s +
 × s +
(
R2 × C2  
R1 + R3 ) × C3 
R1 + R3

=
×
C1 + C2  
1
R1 × R3 × C1


s s +
 × s +

R2 × C1 × C2  
R3 × C3 

Figure 2. The Output LC Filter
F LC
-40dB/dec
GAIN (dB)
AMP
V
= COMP
V OUT
The poles and zeros of the transfer function are:
F ESR
-20dB/dec
F Z1 =
1
2 × π × R2 × C2
F Z2 =
1
2 × π × (R1 + R3 ) × C3
FP1 =
FP2 =
Frequency(Hz)
1
 C1 × C2 
2 × π × R2 × 

 C1 + C2 
1
2 × π × R3 × C3
Figure 3. The LC Filter GAIN and Frequency
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Feb., 2006
14
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APW7074
Application Information (Cont.)
5.Set the second pole FP2 at the half of the switching
PWM Compensation (Cont.)
frequency and also set the second zero FZ2 at the
C1
R3
C3
R2
output LC filter double pole FLC. The compensation
C2
gain should not exceed the error amplifier open loop
gain, check the compensation gain at FP2 with the
V OUT
R1
FB
capabilities of the error amplifier.
V COMP
FP2 = 0.5 X FS
V REF
Figure 5. Compensation Network
FZ2 = FLC
The closed loop gain of the converter can be written
Combine the two equations will get the following
as:
component calculations:
GAINLC X GAINPWM X GAINAMP
Figure 6. shows the asymptotic plot of the closed loop
R3 =
R1
FS
−1
2 × FLC
C3 =
1
π × R3 × FS
converter gain, and the following guidelines will help
to design the compensation network. Using the below
guidelines should give a compensation similar to the
curve plotted. A stable closed loop has a -20dB/ decade
slope and a phase margin greater than 45 degree.
F Z1 F Z2
1.Choose a value for R1, usually between 1K and 5K.
GAIN (dB)
2.Select the desired zero crossover frequency FO:
(1/5 ~ 1/10) X FS >FO>FESR
Use the following equation to calculate R2:
∆ VOSC FO
R2 =
×
× R1
VIN
FLC
F P1
20log
(R2/R1)
F P2
20log
(V IN /Δ V OSC )
Compensation
Gain
F LC
3.Place the first zero FZ1 before the output LC filter
F ESR
double pole frequency FLC.
Converter
Gain
PWM & Filter
Gain
FZ1 = 0.75 X FLC
Frequency(Hz)
Calculate the C2 by the equation:
1
C2 =
2 × π × R2 × FLC × 0.75
Layout Considerations
4.Set the pole at the ESR zero frequency FESR:
In any high switching frequency converter, a correct
Figure 6. Converter Gain and Frequency
FP1 = FESR
layout is important to ensure proper operation of the
regulator. With power devices switching at 300KHz,
Calculate the C1 by the equation:
C1 =
the resulting current transient will cause voltage spike
C2
2 × π × R2 × C2 × FESR − 1
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Feb., 2006
across the interconnecting impedance and parasitic
15
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APW7074
Application Information (Cont.)
Layout Considerations (Cont.)
near the drain).
circuit elements. As an example, consider the turn-off
- The input capacitor should be near the drain of
transition of the PWM MOSFET. Before turn-off, the
the upper MOSFET; the output capacitor should
MOSFET is carrying the full load current. During
be near the loads. The input capacitor GND should
turn-off, current stops flowing in the MOSFET and is
be close to the output capacitor GND and the lower
free-wheeling by the lower MOSFET and parasitic
MOSFET GND.
diode. Any parasitic inductance of the circuit generates
- The drain of the MOSFETs (VIN and Phase nodes)
a large voltage spike during the switching interval. In
should be a large plane for heat sinking.
general, using short, wide printed circuit traces
should minimize interconnecting impedances and
APW7074
the magnitude of voltage spike. And signal and power
grounds are to be kept separate till combined using
V IN
VCC
PVCC
ground plane construction or single point grounding.
Figure 7. illustrates the layout, with bold lines indicating
BOOT
high current paths; these traces must be short and
wide. Components along the bold lines should be
L
O
A
D
UGATE
placed lose together. Below is a checklist for your
PHASE
layout:
V OUT
LGATE
- Keep the switching nodes (UGATE, LGATE and
PHASE) away from sensitive small signal nodes
since these nodes are fast moving signals.
Figure 7.Layout Guidelines
Therefore, keep traces to these nodes as short as
possible.
- The traces from the gate drivers to the MOSFETs
(UG, LG) should be short and wide.
- Place the source of the high-side MOSFET and
the drain of the low-side MOSFET as close
possible. Minimizing the impedance with wide
layout plane between the two pads reduces the
voltage bounce of the node.
- Decoupling capacitor, compensation component,
the resistor dividers, boot capacitors, and SS
capacitors should be close their pins. (For
example, place the decoupling ceramic capacitor
near the drain of the high-side MOSFET as close
as possible. The bulk capacitors are also placed
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Feb., 2006
16
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APW7074
Package Information
0.015 x 45
E
H
SOP – 14 (150mil)
C
D
A
Dim
A
A1
B
C
D
E
e
H
L
θ°
B
0.010
e
GAUGE PLANE
SEATING PLANE
A1
Millimeters
Min.
1.477
0.102
0.331
0.191
8.558
3.82
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Feb., 2006
L
Inches
Max.
1.732
0.255
0.509
0.2496
8.762
3.999
Min.
0.058
0.004
0.013
0.0075
0.336
0.150
6.215
1.274
8°
0.228
0.015
0°
1.274
5.808
0.382
0°
θ
Max.
0.068
0.010
0.020
0.0098
0.344
0.157
0.050
17
0.244
0.050
8°
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APW7074
Physical Specifications
Terminal Material
Lead Solderability
Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn
Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition
(IR/Convection or VPR Reflow)
tp
TP
Critical Zone
T L to T P
Temperature
Ramp-up
TL
tL
Tsmax
Tsmin
Ramp-down
ts
Preheat
25
t 25 °C to Peak
Tim e
Classification Reflow Profiles
Profile Feature
Average ramp-up rate
(TL to TP)
Preheat
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
Time maintained above:
- Temperature (TL)
- Time (tL)
Peak/Classificatioon Temperature (Tp)
Time within 5°C of actual
Peak Temperature (tp)
Ramp-down Rate
Sn-Pb Eutectic Assembly
Pb-Free Assembly
3°C/second max.
3°C/second max.
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
183°C
60-150 seconds
217°C
60-150 seconds
See table 1
See table 2
10-30 seconds
20-40 seconds
6°C/second max.
6°C/second max.
6 minutes max.
8 minutes max.
Time 25°C to Peak Temperature
Notes: All temperatures refer to topside of the package .Measured on the body surface.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Feb., 2006
18
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APW7074
Classification Reflow Profiles(Cont.)
Table 1. SnPb Entectic Process – Package Peak Reflow Temperatures
3
3
Package Thickness
Volum e m m
Volume mm
<350
≥350
<2.5 m m
240 +0/-5°C
225 +0/-5°C
≥2.5 m m
225 +0/-5°C
225 +0/-5°C
Table 2. Pb-free Process – Package Classification Reflow Temperatures
3
3
3
Package Thickness
Volume mm
Volume mm
Volume mm
<350
350-2000
>2000
<1.6 m m
260 +0°C*
260 +0°C*
260 +0°C*
1.6 m m – 2.5 m m
260 +0°C*
250 +0°C*
245 +0°C*
≥2.5 m m
250 +0°C*
245 +0°C*
245 +0°C*
*Tolerance: The device manufacturer/supplier shall assure process compatibility up to and
including the stated classification temperature (this means Peak reflow temperature +0°C.
For example 260°C+0°C) at the rated MSL level.
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TST
ESD
Latch-Up
Method
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B,A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
Description
245°C, 5 SEC
1000 Hrs Bias @125°C
168 Hrs, 100%RH, 121°C
-65°C~150°C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms, 1 tr > 100mA
Carrier Tape & Reel Dimensions
t
D
P
Po
E
P1
Bo
F
W
Ko
Ao
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Feb., 2006
D1
19
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APW7074
Carrier Tape & Reel Dimensions(Cont.)
T2
J
C
A
B
T1
Application
SOP-14
(150mil)
A
B
C
330REF
100REF
F
D
13.0 + 0.5
- 0.2
D1
7.5
φ0.50 +
0.1
φ1.50
(MIN)
J
T1
T2
W
P
E
2 ± 0.5
16.5REF
2.5 ± 025
16.0 ± 0.3
8
1.75
Po
P1
Ao
Ko
t
4.0
2.0
6.5
2.10
0.3±0.05
(mm)
Cover Tape Dimensions
Application
SOP- 14
Carrier Width
24
Cover Tape Width
21.3
Devices Per Reel
2500
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Feb., 2006
20
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