2.1 Ω On Resistance, ±15 V/+12 V/±5 V iCMOS SPDT Switch ADG1419 FEATURES FUNCTIONAL BLOCK DIAGRAM 2.1 Ω on resistance 0.5 Ω maximum on resistance flatness at 25°C Up to 390 mA continuous current Fully specified at +12 V, ±15 V, ±5 V No VL supply required 3 V logic-compatible inputs Rail-to-rail operation 8-lead MSOP and 8-lead 3 mm × 2 mm LFCSP packages ADG1419 LFCSP SA D SB EN IN SWITCHES SHOWN FOR A LOGIC 0 INPUT. 08485-001 DECODER Figure 1. 8-Lead LFCSP Functional Block Diagram APPLICATIONS Automatic test equipment Data acquisition systems Battery-powered systems Relay replacements Sample-and-hold systems Audio signal routing Video signal routing Communication systems ADG1419 MSOP SA D SB SWITCHES SHOWN FOR A LOGIC 0 INPUT. 08485-002 IN Figure 2. 8-Lead MSOP Functional Block Diagram GENERAL DESCRIPTION The ADG1419 is a monolithic iCMOS® device containing a single-pole/double-throw (SPDT) switch. An EN input on the LFCSP package is used to enable or disable the device. When disabled, all channels are switched off. The iCMOS (industrial CMOS) modular manufacturing process combines high voltage, complementary metal-oxide semiconductor (CMOS) and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no other generation of high voltage parts has achieved. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. The ADG1419 exhibits break-before-make switching action for use in multiplexer applications. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. 2.4 Ω maximum on resistance at 25°C. Minimum distortion. 3 V logic-compatible digital inputs: VINH = 2.0 V, VINL = 0.8 V. No VL logic power supply required. 8-lead MSOP and 8-lead, 3 mm × 2 mm LFCSP packages. The on resistance profile is very flat over the full analog input range ensuring excellent linearity and low distortion when switching audio signals. The iCMOS construction ensures ultralow power dissipation, making the part ideally suited for portable and battery-powered instruments. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. ADG1419 TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................7 Applications ....................................................................................... 1 Thermal Resistance .......................................................................7 Functional Block Diagram .............................................................. 1 ESD Caution...................................................................................7 General Description ......................................................................... 1 Pin Configuration and Function Descriptions..............................8 Product Highlights ........................................................................... 1 Typical Performance Characteristics ..............................................9 Revision History ............................................................................... 2 Test Circuits ..................................................................................... 12 Specifications..................................................................................... 3 Terminology .................................................................................... 14 ±15 V Dual Supply ....................................................................... 3 Outline Dimensions ....................................................................... 15 +12 V Single Supply ..................................................................... 4 Ordering Guide .......................................................................... 15 ±5 V Dual Supply ......................................................................... 5 Continuous Current Per Channel, S or D ................................. 6 REVISION HISTORY 10/09—Revision 0: Initial Version Rev. 0 | Page 2 of 16 ADG1419 SPECIFICATIONS ±15 V DUAL SUPPLY VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On Resistance Match Between Channels, ∆RON On Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25°C −40°C to +85°C −40°C to +125°C VDD to VSS 2.1 2.4 0.05 0.2 0.4 0.5 ±0.1 ±0.5 ±0.2 ±0.6 ±0.2 ±1 2.8 3.2 0.25 0.3 0.6 0.65 ±2 ±75 ±3 ±100 ±3 ±100 2.0 0.8 0.005 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION 4 Unit V Ω typ Ω max Ω typ Ω max Ω typ Ω max nA typ nA max nA typ nA max nA typ nA max V min V max μA typ μA max pF typ Break-Before-Make Time Delay, tD 130 155 85 110 115 140 15 Charge Injection −16 ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ Off Isolation −64 dB typ Channel-to-Channel Crosstalk −64 dB typ Total Harmonic Distortion + Noise 0.016 % typ −3 dB Bandwidth Insertion Loss 135 0.16 MHz typ dB typ CS (Off ) CD (Off ) CD, CS (On) 19 44 114 pF typ pF typ pF typ tON (EN) tOFF (EN) 190 220 125 140 160 180 8 Rev. 0 | Page 3 of 16 Test Conditions/Comments VS = ±10 V, IS = −10 mA; see Figure 22 VDD = +13.5 V, VSS = −13.5 V VS = ±10 V, IS = −10 mA VS = ±10 V, IS = −10 mA VDD = +16.5 V, VSS = −16.5 V VS = ±10 V, VS = ±10 V; see Figure 23 VS = ±10 V, VS = ±10 V; see Figure 23 VS = VD = ±10 V; see Figure 24 VIN = VGND or VDD RL = 300 Ω, CL = 35 pF VS = +10 V; see Figure 25 RL = 300 Ω, CL = 35 pF VS = 10 V; see Figure 27 RL = 300 Ω, CL = 35 pF VS = 10 V; see Figure 27 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 10 V; see Figure 26 VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 28 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 29 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 30 RL = 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz; see Figure 32 RL = 50 Ω, CL = 5 pF; see Figure 31 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 31 f = 1 MHz; VS = 0 V f = 1 MHz; VS = 0 V f = 1 MHz; VS = 0 V ADG1419 Parameter POWER REQUIREMENTS IDD 25°C −40°C to +85°C −40°C to +125°C 0.002 1.0 IDD, 8-Lead MSOP 58 IDD, 8-Lead LFCSP 120 95 190 ISS 0.002 1.0 ±4.5/±16.5 VDD/VSS 1 Unit μA typ μA max μA typ μA max μA typ μA max μA typ μA max V min/max Test Conditions/Comments VDD = +16.5 V, VSS = −16.5 V Digital inputs = 0 V or VDD Digital inputs = 5 V Digital inputs = 5 V Digital inputs = 0 V, 5 V or VDD Ground = 0 V Guaranteed by design, not subject to production test. +12 V SINGLE SUPPLY VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On Resistance Match Between Channels, ∆RON On Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25°C −40°C to +85°C −40°C to +125°C 0 V to VDD 4 4.6 0.08 0.25 1.2 1.5 ±0.1 ±0.5 ±0.2 ±0.6 ±0.2 ±1 5.5 6.2 0.3 0.35 1.75 1.9 ±2 ±75 ±3 ±100 ±3 ±100 2.0 0.8 0.005 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION 4 Break-Before-Make Time Delay, tD 200 255 145 190 130 170 55 Charge Injection Off Isolation 13 −60 tON (EN) tOFF (EN) 265 370 220 245 205 220 33 Rev. 0 | Page 4 of 16 Unit V Ω typ Ω max Ω typ Ω max Ω typ Ω max nA typ nA max nA typ nA max nA typ nA max V min V max μA typ μA max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ Test Conditions/Comments VS = 0 V to 10 V, IS = −10 mA; see Figure 22 VDD = +10.8 V, VSS = 0 V VS = 0 V to 10 V, IS = −10 mA VS = 0 V to 10 V, IS = −10 mA VDD = +13.2 V, VSS = 0 V VS = 1 V/10 V, VD = 10 V/1 V; see Figure 23 VS = 1 V/10 V, VD = 10 V/1 V; see Figure 23 VS = VD = 1 V or 10 V; see Figure 24 VIN = VGND or VDD RL = 300 Ω, CL = 35 pF VS = 8 V; see Figure 25 RL = 300 Ω, CL = 35 pF VS = 8 V; see Figure 27 RL = 300 Ω, CL = 35 pF VS = 8 V; see Figure 27 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 8 V; see Figure 26 VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 28 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 29 ADG1419 Parameter Channel-to-Channel Crosstalk 25°C −60 −3 dB Bandwidth Insertion Loss CS (Off ) CD (Off ) CD, CS (On) POWER REQUIREMENTS IDD 95 0.3 32 72 123 −40°C to +85°C −40°C to +125°C MHz typ dB typ pF typ pF typ pF typ 0.001 1.0 IDD, 8-Lead MSOP 58 95 IDD, 8-Lead LFCSP 120 190 5/16.5 VDD 1 Unit dB typ μA typ μA max μA typ μA max μA typ μA max V min/max Test Conditions/Comments RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 30 RL = 50 Ω, CL = 5 pF; see Figure 31 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 31 f = 1 MHz; VS = 6 V f = 1 MHz; VS = 6 V f = 1 MHz; VS = 6 V VDD = 13.2 V Digital inputs = 0 V or VDD Digital inputs = 5 V Digital inputs = 5 V Ground = 0 V, VSS = 0 V Guaranteed by design, not subject to production test. ±5 V DUAL SUPPLY VDD = +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted. Table 3. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On Resistance Match Between Channels, ∆RON On Resistance Flatness, RFLAT (ON) 25°C −40°C to +85°C −40°C to +125°C VDD to VSS 4.5 5.2 0.1 0.3 1.3 1.6 6.2 7 0.35 0.4 1.85 2 Unit V Ω typ Ω max Ω typ Ω max Ω typ Ω max Test Conditions/Comments VS = ±4.5V, IS = −10 mA; see Figure 22 VDD = +4.5 V, VSS = −4.5 V VS = ±4.5V, IS = −10 mA VS = ±4.5 V, IS = −10 mA LEAKAGE CURRENTS Source Off Leakage, IS (Off ) ±0.1 ±2 ±75 Drain Off Leakage, ID (Off ) ±0.5 ±0.1 nA max nA typ ±0.6 ±0.1 ±1 ±3 ±100 VS = VD = ±4.5 V; see Figure 24 ±3 ±100 nA max nA typ nA max V min V max μA typ μA max pF typ VIN = VGND or VDD Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH VDD = +5.5 V, VSS = −5.5 V nA typ 2.0 0.8 0.001 ±0.1 Digital Input Capacitance, CIN 4 Rev. 0 | Page 5 of 16 VS = ±4.5 V, VD = ∓4.5 V; see Figure 23 VS = ±4.5 V, VD = ∓4.5 V; see Figure 23 ADG1419 Parameter DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION 25°C −40°C to +85°C −40°C to +125°C 495 560 355 390 335 365 Test Conditions/Comments RL = 300 Ω, CL = 35 pF VS = 3 V; see Figure 25 RL = 300 Ω, CL = 35 pF VS = 3 V; see Figure 27 RL = 300 Ω, CL = 35 pF VS = 3 V; see Figure 27 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 3 V; see Figure 26 VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 28 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 29 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 30 RL = 10 kΩ, 5 V p-p, f = 20 Hz to 20 kHz; see Figure 32 RL = 50 Ω, CL = 5 pF; see Figure 31 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 31 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = +5.5 V, VSS = −5.5 V Digital inputs = 0 V or VDD Break-Before-Make Time Delay, tD 310 410 230 305 220 290 65 Charge Injection 59 ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ Off Isolation −60 dB typ Channel-to-Channel Crosstalk −60 dB typ Total Harmonic Distortion + Noise 0.04 % typ −3 dB Bandwidth Insertion Loss 105 0.28 MHz typ dB typ 26 62 128 pF typ pF typ pF typ tON (EN) tOFF (EN) 31 CS (Off ) CD (Off ) CD, CS (On) POWER REQUIREMENTS IDD 0.001 1.0 ISS 0.001 1.0 ±4.5/±16.5 VDD/VSS 1 Unit μA typ μA max μA typ μA max V min/max Digital inputs = 0 V or VDD Ground = 0 V Guaranteed by design, not subject to production test. CONTINUOUS CURRENT PER CHANNEL, S OR D Table 4. Parameter CONTINUOUS CURRENT PER CHANNEL 1 ±15 V Dual Supply 8-Lead MSOP (θJA = 206°C/W) 8-Lead LFCSP (θJA = 50.8°C/W) +12 V Single Supply 8-Lead MSOP (θJA = 206°C/W) 8-Lead LFCSP (θJA = 50.8°C/W) ±5 V Dual Supply 8-Lead MSOP (θJA = 206°C/W) 8-Lead LFCSP (θJA = 50.8°C/W) 1 25°C 85°C 125°C Unit 215 390 135 215 80 100 mA maximum mA maximum 175 320 115 185 70 95 mA maximum mA maximum 165 310 110 180 70 95 mA maximum mA maximum Test Conditions/Comments VDD = +13.5 V, VSS = −13.5 V VDD = 10.8 V, VSS = 0 V VDD = +4.5 V, VSS = −4.5 V Guaranteed by design, not subject to production test. Rev. 0 | Page 6 of 16 ADG1419 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 5. Table 6. Thermal Resistance Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs1 Digital Inputs1 Peak Current, S or D (Pulsed at 1 ms, 10% Duty-Cycle Maximum) 8-Lead MSOP (4-Layer Board) 8-Lead LFCSP Continuous Current per Channel, S or D Operating Temperature Range Industrial Storage Temperature Range Junction Temperature Reflow Soldering Peak Temperature, Pb Free 1 Rating 35 V −0.3 V to +25 V +0.3 V to −25 V VSS − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first GND − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first Package Type 8-Lead MSOP (4-Layer Board) 8-Lead LFCSP ESD CAUTION 400 mA 600 mA Data in Table 4 + 15% mA −40°C to +125°C −65°C to +150°C 150°C 260°C Over voltages at IN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 7 of 16 θJA 206 50.8 θJC 44 Unit °C/W °C/W ADG1419 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 8 SB SA 2 ADG1419 7 VSS GND 3 TOP VIEW (Not to Scale) 6 IN D 1 5 EN NOTES 1. EXPOSED PAD TIED TO SUBSTRATE, VSS. ADG1419 GND 3 TOP VIEW (Not to Scale) VDD 4 08485-003 VDD 4 SA 2 8 SB 7 VSS 6 IN 5 NC NC = NO CONNECT Figure 3. 8-Lead LFCSP Pin Configuration 08485-004 D 1 Figure 4. 8-Lead MSOP Pin Configuration Table 7. 8-Lead LFCSP Pin Function Descriptions Table 9. 8-Lead MSOP Pin Function Descriptions Pin No. 1 Mnemonic D Pin No. 1 Mnemonic D 2 SA 2 SA 3 4 5 GND VDD EN 3 4 5 6 7 8 GND VDD NC IN VSS SB 6 7 8 IN VSS SB EPAD Description Drain Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Ground (0 V) Reference. Most Positive Power Supply Potential. Active High Digital Input. When this pin is low, the device is disabled and all switches are turned off. When this pin is high, the IN logic input determines which switch is turned on. Logic Control Input. Most Negative Power Supply Potential. Source Terminal. This pin can be an input or output. Exposed pad tied to substrate, VSS. Table 10. 8-Lead MSOP Truth Table IN 0 1 Table 8. 8-Lead LFCSP Truth Table EN 0 1 1 IN X 0 1 Switch A Off On Off Description Drain Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Ground (0 V) Reference. Most Positive Power Supply Potential. No Connect. Logic Control Input. Most Negative Power Supply Potential. Source Terminal. This pin can be an input or output. Switch B Off Off On Rev. 0 | Page 8 of 16 Switch A On Off Switch B Off On ADG1419 TYPICAL PERFORMANCE CHARACTERISTICS 4.0 3.5 VDD = +15V VSS = –15V TA = 25°C 3.5 3.0 3.0 ON RESISTANCE (Ω) ON RESISTANCE (Ω) VDD = +10V VSS = –10V VDD = +12V VSS = –12V 2.5 VDD = +13.5V VSS = –13.5V 2.0 TA = +125°C 2.5 TA = +85°C 2.0 TA = +25°C 1.5 TA = –40°C 1.0 1.5 VDD = +16.5V VSS = –16.5V –11.5 –6.5 –1.5 3.5 VS, VD (V) 8.5 13.5 0 –15 –5 0 5 10 15 VS, VD (V) Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures, ±15 V Dual Supply Figure 5. On Resistance as a Function of VD (VS) for Dual Supply 6 9 TA = 25°C 8 VDD = 15V VSS = 0V 5 7 VDD = 10.8V VSS = 0V 6 VDD = 8V VSS = 0V 5 ON RESISTANCE (Ω) ON RESISTANCE (Ω) –10 08485-015 1.0 –16.5 0.5 08485-018 VDD = +15V VSS = –15V VDD = 12V VSS = 0V VDD = 13.2V VSS = 0V VDD = 15V VSS = 0V 4 TA= +125°C 4 TA= +85°C TA= +25°C 3 TA= –40°C 2 1 3 0 2 4 6 8 10 12 0 08485-017 2 14 VS, VD (V) 0 4 6 8 10 12 VS, VD (V) Figure 9. On Resistance as a Function of VD (VS) for Different Temperatures, +12 V Single Supply Figure 6. On Resistance as a Function of VD (VS) for Single Supply 7 5.0 TA = 25°C VDD = +5V VSS = –5V 4.5 6 VDD = +4.5V VSS = –4.5V 4.0 ON RESISTANCE (Ω) 3.5 3.0 2.5 2.0 VDD = +5V VSS = –5V 1.5 VDD = +5.5V VSS = –5.5V 1.0 VDD = +7V VSS = –7V 5 TA = +125°C TA = +85°C 4 TA = +25°C 3 TA = –40°C 2 1 0 –7 –5 –3 –1 1 3 5 7 VS, VD (V) Figure 7. On Resistance as a Function of VD (VS) for Dual Supply 0 –5 –4 –3 –2 –1 0 1 VS, VD (V) 2 3 4 5 08485-012 0.5 08485-016 ON RESISTANCE (Ω) 2 08485-013 VDD = 12V VSS = 0V Figure 10. On Resistance as a Function of VD (VS) for Different Temperatures, ±5 V Dual Supply Rev. 0 | Page 9 of 16 ADG1419 70 60 IDD PER CHANNEL TA = 25°C 80 70 50 60 40 ID (OFF) – + ID (OFF) + – ID, IS (ON) + + IS (OFF) + – IS (OFF) – + ID, IS (ON) – – 30 20 IDD (µA) LEAKAGE CURRENT (nA) 90 VDD = +15V VSS = –15V VBIAS = ±10V 50 40 VDD = +15V VSS = –15V VDD = +12V VSS = 0V 30 20 10 VDD = +5V VSS = –5V 10 0 20 40 60 80 100 120 TEMPERATURE (°C) –10 08485-019 0 0 2 4 12 14 16 TA = 25°C 400 VDD = +5V VSS = –5V 300 50 CHARGE INJECTION (pC) LEAKAGE CURRENT (nA) 10 500 VDD = 12V VSS = 0V VBIAS = 1V/10V 60 8 Figure 14. IDD vs. Logic Level Figure 11. Leakage Currents as a Function of Temperature, ±15 V Dual Supply 70 6 LOGIC LEVEL, IN (V) 08485-011 0 –10 40 ID (OFF) – + ID (OFF) + – ID, IS (ON) + + ID, IS (ON) – – IS (OFF) + – IS (OFF) – + 30 20 10 200 100 0 VDD = +12V VSS = 0V VDD = +15V VSS = –15V –100 –200 –300 0 20 40 60 80 100 120 TEMPERATURE (°C) –500 08485-032 0 –5 0 5 10 15 Figure 15. Charge Injection vs. Source Voltage 500 VDD = +5V VSS = –5V VBIAS = ±4.5V 50 –15 VS (V) Figure 12. Leakage Currents as a Function of Temperature, +12 V Single Supply 60 –10 08485-008 –400 –10 450 350 ID (OFF) – + ID (OFF) + – IS (OFF) + – IS (OFF) – + ID,IS (ON) + + ID,IS (ON) – – 30 20 TIME (ns) VDD = +5V VSS = –5V 300 250 VDD = +12V VSS = 0V 200 150 10 100 VDD = +15V VSS = –15V 0 10 0 20 40 60 80 TEMPERATURE (°C) 100 120 08485-020 50 Figure 13. Leakage Currents as a Function of Temperature, ±5 V Dual Supply Rev. 0 | Page 10 of 16 0 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 16. tTRANSITION Times vs. Temperature 120 08485-010 LEAKAGE CURRENT (nA) 400 40 ADG1419 0.06 RL = 110Ω TA = 25°C 0 0.05 VDD = +5V VSS = –5V VS = 5V p-p 0.04 –40 THD + N (%) OFF ISOLATION (dB) –20 TA = 25°C VDD = +15V VSS = –15V –60 0.03 0.02 –80 VDD = +15V VSS = –15V VS = 10V p-p 0.01 –100 100k 1M 10M 100M 1G FREQUENCY (Hz) 0 08485-006 10k 15k 20k Figure 20. THD + N vs. Frequency 0 0 TA = 25°C –10 VDD = +15V VSS = –15V TA = 25°C VDD = +15V VSS = –15V –10 –20 –20 NO DECOUPLING CAPACITORS –30 ACPSRR (dB) –30 –40 –50 –60 –40 –50 DECOUPLING CAPACITORS –60 –70 –70 –80 –80 –90 –90 100k 1M 10M 100M 1G FREQUENCY (Hz) 08485-033 –100 10k –100 Figure 18. Crosstalk vs. Frequency 0 –1.0 –1.5 –2.0 –2.5 –3.0 –3.5 –4.0 100k 1M 10M 100M FREQUENCY (Hz) 1G 08485-005 –4.5 –5.0 10k 10k 100k 1M FREQUENCY (Hz) Figure 21. ACPSRR vs. Frequency TA = 25°C VDD = +15V VSS = –15V –0.5 1k Figure 19. On Response vs. Frequency Rev. 0 | Page 11 of 16 10M 08485-007 CROSSTALK (dB) 10k FREQUENCY (Hz) Figure 17. Off Isolation vs. Frequency INSERTION LOSS (dB) 5k 08485-009 0 –120 1k ADG1419 TEST CIRCUITS V ID (ON) S D NC S D A 08485-021 VS Figure 22. On Resistance A Figure 24. On Leakage ID (OFF) S D A VS 08485-022 IS (OFF) VD NC = NO CONNECT 08485-023 IDS VD Figure 23. Off Leakage VDD VSS VDD VS 0.1µF 50% 50% VIN 50% 50% VSS SB D VOUT SA RL 300Ω IN VIN VIN CL 35pF 90% 90% VOUT GND tON tOFF 08485-024 0.1µF Figure 25. Switching Times, tON and tOFF 0.1µF VS VDD VSS VDD VSS SB 0.1µF VIN D VOUT SA RL 300Ω IN VOUT CL 35pF 80% tBBM tBBM VIN 08485-025 GND Figure 26. Break-Before-Make Time Delay 3V ENABLE DRIVE (VIN) 50% VDD VSS VDD VSS INx 50% SA VS SB 0V ADG1419 tOFF (EN) 0.9VO OUTPUT OUTPUT 0.9VO D EN VIN 50Ω GND 300Ω 35pF 08485-026 tON (EN) Figure 27. Enable Delay, tON (EN), tOFF (EN) Rev. 0 | Page 12 of 16 ADG1419 VDD VSS VDD VSS 0.1µF VIN (NORMALLY CLOSED SWITCH) ON SB VS D VOUT SA CL 1nF IN VIN OFF NC VIN (NORMALLY OPEN SWITCH) VOUT GND ΔVOUT QINJ = CL × ΔVOUT 08485-027 0.1µF Figure 28. Charge Injection VDD VSS 0.1µF VDD NETWORK ANALYZER VSS NC SA SB 0.1µF VDD NC 50Ω 50Ω SA IN VS SB VS D D VIN RL 50Ω VOUT VOUT VIN GND 08485-028 GND OFF ISOLATION = 20 log VOUT VS INSERTION LOSS = 20 log Figure 29. Off Isolation VDD NETWORK ANALYZER VOUT WITH SWITCH VOUT WITHOUT SWITCH Figure 31. Bandwidth VSS 0.1µF 0.1µF VOUT NETWORK ANALYZER VSS VDD VDD VSS VSS 0.1µF 0.1µF SA RL 50Ω AUDIO PRECISION VDD SB D R 50Ω VSS RS S IN IN VS GND VIN VOUT VS RL 10kΩ GND 08485-030 CHANNEL-TO-CHANNEL CROSSTALK = 20 log VS V p-p D Figure 32. THD + N Figure 30. Channel-to-Channel Crosstalk Rev. 0 | Page 13 of 16 VOUT 08485-031 IN VSS 0.1µF 08485-029 VDD 0.1µF ADG1419 TERMINOLOGY tON (EN) Delay time between the 50% and 90% points of the digital input and switch on condition. See Figure 27. IDD The positive supply current. ISS The negative supply current. tOFF (EN) Delay time between the 50% and 90% points of the digital input and switch off condition. See Figure 27. VD (VS) The analog voltage on Terminal D and Terminal S. RON The ohmic resistance between Terminal D and Terminal S. RFLAT (ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. IS (Off) The source leakage current with the switch off. TBBM Off time measured between the 80% point of both switches when switching from one address state to another. See Figure 26. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. See Figure 28. ID (Off) The drain leakage current with the switch off. Off Isolation A measure of unwanted signal coupling through an off switch. See Figure 29. ID, IS (On) The channel leakage current with the switch on. VINL The maximum input voltage for Logic 0. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. See Figure 30. VINH The minimum input voltage for Logic 1. IINL (IINH) The input current of the digital input. CS (Off) The off switch source capacitance, measured with reference to ground. CD (Off) The off switch drain capacitance, measured with reference to ground. CD, CS (On) The on switch capacitance, measured with reference to ground. CIN The digital input capacitance. tTRANSITION Delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. Bandwidth The frequency at which the output is attenuated by 3 dB. See Figure 31. On Response The frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. See Figure 31. THD + N The ratio of the harmonic amplitude plus noise of the signal to the fundamental. See Figure 32. AC Power Supply Rejection Ratio (ACPSRR) ACPSRR measures the ability of a part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on the output to the amplitude of the modulation is the ACPSRR. See Figure 21. Rev. 0 | Page 14 of 16 ADG1419 OUTLINE DIMENSIONS 3.20 3.00 2.80 8 3.20 3.00 2.80 5.15 4.90 4.65 5 1 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 6° 0° 0.40 0.25 0.80 0.55 0.40 0.23 0.09 100709-B 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 33. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 1.75 1.65 1.50 2.00 BSC 5 3.00 BSC 8 1.90 1.80 1.65 EXPOSED PAD 0.20 MIN 4 INDEX AREA 0.50 0.40 0.30 TOP VIEW 0.80 0.75 0.70 0.30 0.25 0.20 0.50 COPLANARITY 0.08 0.05 MAX 0.02 NOM PIN 1 INDICATOR BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 081806-A SEATING PLANE 0.15 REF SIDE VIEW 1 Figure 34. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm × 2 mm Body, Very Very Thin, Dual Lead (CP-8-4) Dimensions shown in millimeters ORDERING GUIDE Model ADG1419BRMZ1 ADG1419BRMZ-REEL71 ADG1419BCPZ-REEL71 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 8-Lead Mini Small Outline Package [MSOP] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Lead Frame Chip Scale Package [LFCSP_WD] Z = RoHS Compliant Part. Rev. 0 | Page 15 of 16 Package Option RM-8 RM-8 CP-8-4 Branding S1L S1L 1C ADG1419 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08485-0-10/09(0) Rev. 0 | Page 16 of 16