Cypress CY7C1061BV33-10ZXI 16-mbit (1m x 16) static ram Datasheet

CY7C1061BV33
16-Mbit (1M x 16) Static RAM
Features
Low Enable (BLE) is LOW, then data from I/O pins (I/O0
through I/O7), is written into the location specified on the
address pins (A0 through A19). If Byte High Enable (BHE) is
LOW, then data from I/O pins (I/O8 through I/O15) is written into
the location specified on the address pins (A0 through A19).
• High speed
— tAA = 10 ns
• Low active power
— 990 mW (max.)
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Available in Pb-free and non Pb-free 54-pin TSOP II
package
Functional Description
The CY7C1061BV33 is a high-performance CMOS Static
RAM organized as 1,048,576 words by 16 bits.
Writing to the device is accomplished by enabling the chip (CE
LOW) while forcing the Write Enable (WE) input LOW. If Byte
Reading from the device is accomplished by enabling the chip
by taking CE LOW while forcing the Output Enable (OE) LOW
and the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is
LOW, then data from the memory location specified by the
address pins will appear on I/O0 to I/O7. If Byte High Enable
(BHE) is LOW, then data from memory will appear on I/O8 to
I/O15. See the truth table at the back of this data sheet for a
complete description of Read and Write modes.
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a Write operation
(CE LOW and WE LOW).
The CY7C1061BV33 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout.
Pin Configurations[1, 2]
Logic Block Diagram
54-pin TSOP II (Top View)
I/O12
VCC
I/O13
I/O14
VSS
I/O15
A4
A3
A2
A1
A0
BHE
CE
VCC
WE
DNU/VCC
A19
A18
A17
A16
A15
I/O0
VCC
I/O1
I/O2
VSS
I/O3
1M x 16
ARRAY
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
ROW DECODER
INPUT BUFFER
I/O0–I/O7
I/O8–I/O15
A10
A11
A 12
A 13
A 14
A15
A16
A17
A18
A19
COLUMN
DECODER
BHE
WE
CE
OE
BLE
1
2
3
54
53
4
52
51
5
6
50
49
7
8
9
10
11
12
48
47
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
I/O11
VSS
I/O10
I/O9
VCC
I/O8
A5
A6
A7
A8
A9
NC
OE
VSS
DNU/VSS
BLE
A10
A11
A12
A13
A14
I/O7
VSS
I/O6
I/O5
VCC
I/O4
Notes:
1. DNU/VCC Pin (#16) has to be left floating or connected to VCC and DNU/VSS Pin (#40) has to be left floating or connected to VSS to ensure proper application.
2. NC – No Connect Pins are not connected to the die
Cypress Semiconductor Corporation
Document #: 38-05693 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 3, 2006
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CY7C1061BV33
Selection Guide
–10
Maximum Access Time
–12
Unit
10
12
ns
Maximum Operating Current
Commercial
275
260
mA
Industrial
275
260
Maximum CMOS Standby Current
Commercial/Industrial
50
50
mA
DC Input Voltage[3] ................................ –0.5V to VCC + 0.5V
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Operating Range
Storage Temperature ................................. –65°C to +150°C
Range
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Ambient Temperature
VCC
0°C to +70°C
3.3V ± 0.3V
Commercial
Industrial
Supply Voltage on VCC to Relative GND[3] –0.5V to +4.6VDC
Voltage Applied to Outputs
in High-Z State[3] ....................................–0.5V to VCC + 0.5V
–40°C to +85°C
DC Electrical Characteristics Over the Operating Range
–10
Test Conditions
Min.
VOH
Parameter
Output HIGH Voltage
Description
VCC = Min., IOH = –4.0 mA
2.4
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
–12
Max.
Min.
Max.
Unit
2.4
V
0.4
0.4
V
VIH
Input HIGH Voltage
2.0
VCC + 0.3
2.0
VCC + 0.3
V
VIL
Input LOW Voltage[3]
–0.3
0.8
–0.3
0.8
V
IIX
Input Leakage Current
GND < VI < VCC
–1
+1
–1
+1
µA
IOZ
Output Leakage Current
GND < VOUT < VCC, Output Disabled
–1
+1
–1
+1
µA
ICC
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
ISB1
ISB2
Commercial
275
260
mA
Industrial
275
260
mA
Automatic CE
Power-down Current
—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or VIN < VIL, f = fMAX
70
70
mA
Automatic CE
Power-down Current
—CMOS Inputs
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
50
50
mA
Commercial/
Industrial
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
I/O Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, VCC = 3.3V
Max.
Unit
6
pF
8
pF
Thermal Resistance[4]
Parameter
ΘJA
ΘJC
Description
Test Conditions
Thermal Resistance (Junction to Ambient) Test conditions follow standard test
methods and procedures for
Thermal Resistance (Junction to Case)
measuring thermal impedance, per
EIA/JESD51.
54-pin TSOP-II
Unit
49.95
°C/W
3.34
°C/W
Notes:
3. VIL (min.) = –2.0V and VIH(max) = VCC + 0.5V for pulse durations of less than 20 ns.
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05693 Rev. *B
Page 2 of 9
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CY7C1061BV33
AC Test Loads and Waveforms[5]
R1 317 Ω
50Ω
3.3V
VTH = 1.5V
OUTPUT
Z0 = 50Ω
30 pF*
(a)
OUTPUT
* Capacitive Load consists of all components of the test environment.
5 pF*
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
R2
351Ω
(b)
3.3V
90%
90%
10%
GND
10%
Fall time: > 1V/ns
Rise time > 1V/ns
(c)
AC Switching Characteristics Over the Operating Range[6]
–10
Parameter
Description
Min.
–12
Max.
Min.
Max.
Unit
Read Cycle
tpower
VCC(typical) to the first access[7]
1
tRC
Read Cycle Time
10
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
1
ms
12
10
3
ns
12
3
ns
ns
tACE
CE LOW to Data Valid
10
12
ns
tDOE
OE LOW to Data Valid
5
6
ns
tLZOE
OE LOW to Low-Z
tHZOE
OE HIGH to
tLZCE
CE LOW to Low-Z[8]
CE HIGH to
High-Z[8]
CE LOW to
Power-Up[9]
tPD
CE HIGH to
Power-Down[9]
tDBE
Byte Enable to Data Valid
tLZBE
Byte Enable to Low-Z
tHZBE
Byte Disable to High-Z
tHZCE
tPU
1
High-Z[8]
1
5
3
ns
6
3
5
0
ns
ns
6
0
ns
ns
10
12
ns
5
6
ns
1
1
5
ns
6
ns
Notes:
5. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1ms (Tpower) after reaching the
minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage.
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and specified transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise.
7. This part has a voltage regulator which steps down the voltage from 3V to 2V internally. tpower time has to be provided initially before a Read/Write operation is
started.
8. tHZOE, tHZCE, tHZWE, tHZBE and tLZOE, tLZCE, t\LZWE, tLZBE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV from steady-state
voltage.
9. These parameters are guaranteed by design and are not tested.
10. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Chip enables must be active and WE and byte enables must be LOW to
initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge
of the signal that terminates the Write.
11. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05693 Rev. *B
Page 3 of 9
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CY7C1061BV33
AC Switching Characteristics Over the Operating Range[6] (continued)
–10
Parameter
Write
Description
Min.
–12
Max.
Min.
Max.
Unit
Cycle[10, 11]
tWC
Write Cycle Time
10
12
ns
tSCE
CE LOW to Write End
7
8
ns
tAW
Address Set-up to Write End
7
7
ns
tSA
Address Set-up to Write Start
0
0
ns
tPWE
WE Pulse Width
7
8
ns
tSD
Data Set-up to Write End
5.5
6
ns
tHD
Data Hold from Write End
0
0
ns
tLZWE
WE HIGH to Low-Z[8]
3
3
ns
tHZWE
WE LOW to
High-Z[8]
tBW
Byte Enable to End of Write
7
8
ns
tHA
Address Hold from Write End
0
0
ns
5
6
ns
Data Retention Waveform
DATA RETENTION MODE
3.0V
VCC
VDR > 2V
3.0V
tR
tCDR
CE
Switching Waveforms
Read Cycle No. 1[12, 13]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Notes:
12. Device is continuously selected. OE, CE, BHE and/or BHE = VIL.
13. WE is HIGH for Read cycle.
Document #: 38-05693 Rev. *B
Page 4 of 9
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CY7C1061BV33
Switching Waveforms (continued)
Read Cycle No. 2 (OE Controlled)[13, 14]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
BHE, BLE
tLZOE
tHZCE
tDBE
tLZBE
DATA OUT
tHZBE
HIGH IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
IICC
CC
50%
50%
ISB
Write Cycle No. 1 (CE Controlled)[15, 16]
tWC
ADDRESS
CE
tSA
tSCE
tAW
tHA
tPWE
WE
tBW
BHE, BLE
tSD
tHD
DATAI/O
Notes:
14. Address valid prior to or coincident with CE transition LOW.
15. Data I/O is high-impedance if OE or BHE and/or BLE = VIH.
16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05693 Rev. *B
Page 5 of 9
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CY7C1061BV33
Switching Waveforms (continued)
Write Cycle No. 2 (BLE or BHE Controlled)
tWC
ADDRESS
tSA
BHE, BLE
tBW
tAW
tHA
tPWE
WE
tSCE
CE
tSD
tHD
DATAI/O
Write Cycle No. 3 (WE Controlled, OE LOW)[15, 16]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE, BLE
tHZWE
tSD
tHD
DATA I/O
tLZWE
Document #: 38-05693 Rev. *B
Page 6 of 9
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CY7C1061BV33
Truth Table
CE
OE
WE
BLE
BHE
I/O0–I/O7
I/O8–I/O15
Mode
Power
H
X
X
X
X
High-Z
High-Z
Power-down
Standby (ISB)
L
L
H
L
L
Data Out
Data Out
Read All Bits
Active (ICC)
L
L
H
L
H
Data Out
High-Z
Read Lower Bits Only
Active (ICC)
L
L
H
H
L
High-Z
Data Out
Read Upper Bits Only
Active (ICC)
L
X
L
L
L
Data In
Data In
Write All Bits
Active (ICC)
L
X
L
L
H
Data In
High-Z
Write Lower Bits Only
Active (ICC)
L
X
L
H
L
High-Z
Data In
Write Upper Bits Only
Active (ICC)
L
H
H
X
X
High-Z
High-Z
Selected, Outputs Disabled
Active (ICC)
Ordering Information
Speed
(ns)
10
12
Ordering Code
CY7C1061BV33-10ZC
CY7C1061BV33-10ZI
CY7C1061BV33-10ZXC
CY7C1061BV33-10ZXI
CY7C1061BV33-12ZC
CY7C1061BV33-12ZI
CY7C1061BV33-12ZXC
CY7C1061BV33-12ZXI
Document #: 38-05693 Rev. *B
Package
Name
51-85160
Package Type
54-pin TSOP II
54-pin TSOP II (Pb-free)
54-pin TSOP II
54-pin TSOP II (Pb-free)
Operating Range
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Page 7 of 9
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CY7C1061BV33
Package Diagram
54-pin TSOP II (51-85160)
51-85160-**
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05693 Rev. *B
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CY7C1061BV33
Document History Page
Document Title: CY7C1061BV33 16-Mbit (1M x 16) Static RAM
Document Number: 38-05693
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
283950
See ECN
RKF
New data sheet
*A
309453
See ECN
RKF
Final data sheet
*B
492137
See ECN
NXR
Removed 8 ns speed bin
Changed the description of IIX from Input Load Current to Input Leakage
Current in DC Electrical Characteristics table
Updated the Ordering Information Table
Document #: 38-05693 Rev. *B
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