Plerow APL0405 PLL Module Features Description TM The plerow PLL synthesizer module was designed for use in wireless and wireline systems in a wide range of frequency from 50 MHz to 6 GHz. ASB’s PLL provides exceptionally low spurious and phase noise performance with fast locking time and low current consumption. All products are available in a surface-mount type package. · +5 dBm Output Level at 405 MHz · Channel Step Size : 20 kHz · 2 nd Harmonic : < -25 dBc · Spurious Level : < -70 dBc · Lock Time : < 10 ms · 20 mA Current Consumption Specifications Unit Min. Typical Max. Frequency Range MHz 400 405 410 Output Power dBm 4 5 6 Supply Voltage V 4.7 5.0 5.3 30 Tel: (82) 42-528-7220 Fax: (82) 42-528-7222 ASB, Inc., 4th Fl. Venture Town Bldg, KT HRDC, 367-17 Goijeong-Dong, Seo-Gu, Daejeon, 302-716, Korea Parameter Current Consumption mA 20 Channel Step Size kHz 20 2nd Harmonics dBc -35 -25 Spurious Level dBc -78 -70 Lock Time ms 3 10 Reference Frequency MHz 10 Reference Input Level dBm -5 0 5 More Information Website: www.asb.co.kr E-mail: [email protected] Phase Noise (C / N) @ 10 kHz dBc/Hz -110 -107 -104 @ 100 kHz dBc/Hz -124 -121 -118 Output Impedance Ω Operating Temp. Range °C Package Type & Size mm 50 -40 25 85 SMT, 19.0W×19.0L×5.8H 1) Measurement conditions are as follows: T = 25°C, VCC = 5 V, Freq. = 405 MHz, 50 ohm system. Outline Drawing Top View Bottom View D A E F I H G C Pin Configuration Dimension (mm) CLOCK A 19.0 B 19.0 C 5.8 D 1.5 E 0.5 F 1.75 G 1.35 H 15.0 I 0.9 Tolerance: ± 0.2 1 2 3 4 9 13 15 16 Others DATA ENABLE OSC IN VCC (VCO) RF OUT VCP (PLL) LOCK DETECT Ground B Side View 1/1 www.asb.co.kr March 2004