Fractional-N Frequency Synthesizer ADF4153 FEATURES GENERAL DESCRIPTION RF bandwidth 500 MHz to 4 GHz 2.7 V to 3.3 V power supply Separate VP allows extended tuning voltage Programmable dual-modulus prescaler 4/5, 8/9 Programmable charge pump currents 3-wire serial interface Analog and digital lock detect Power-down mode Pin compatible with the ADF4110/ADF4111/ADF4112/ADF4113 and ADF4106 Programmable modulus on fractional-N synthesizer Trade-off noise versus spurious performance The ADF4153 is a fractional-N frequency synthesizer that implements local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a Σ-Δ based fractional interpolator to allow programmable fractional-N division. The INT, FRAC, and MOD registers define an overall N divider (N = (INT + (FRAC/MOD))). In addition, the 4-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a voltage controlled oscillator (VCO). APPLICATIONS CATV equipment Base stations for mobile radio (GSM, PCS, DCS, CDMA, WCDMA) Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANs Communications test equipment Control of all on-chip registers is via a simple 3-wire interface. The device operate with a power supply ranging from 2.7 V to 3.3 V and can be powered down when not in use. FUNCTIONAL BLOCK DIAGRAM AVDD DVDD VP SDVDD RSET ADF4153 REFERENCE 4-BIT R COUNTER ×2 DOUBLER REFIN + PHASE FREQUENCY DETECTOR – VDD HIGH Z CHARGE PUMP DGND LOCK DETECT MUXOUT CP OUTPUT MUX CURRENT SETTING VDD RDIV RFCP3 RFCP2 RFCP1 NDIV N-COUNTER RFINA RFINB THIRD ORDER FRACTIONAL INTERPOLATOR CLOCK DATA MODULUS REG INTEGER REG 03685-A-001 LE FRACTION REG 24-BIT DATA REGISTER AGND DGND CPGND Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. ADF4153 TABLE OF CONTENTS Specifications..................................................................................... 3 R Divider Register, R1................................................................ 17 Timing Characteristics..................................................................... 5 Control Register, R2 ................................................................... 17 Absolute Maximum Ratings............................................................ 6 Noise and Spur Register, R3 ...................................................... 18 ESD Caution.................................................................................. 6 Reserved Bits............................................................................... 18 Pin Configuration and Pin Function Descriptions...................... 7 RF Synthesizer: A Worked Example ........................................ 18 Typical Performance Characteristics ............................................. 8 Modulus....................................................................................... 19 Circuit Description......................................................................... 10 Reference Doubler and Reference Divider ............................. 19 Reference Input Section............................................................. 10 12-Bit Programmable Modulus................................................ 19 RF Input Stage............................................................................. 10 Spurious Optimization and Fastlock ....................................... 19 RF INT Divider........................................................................... 10 Phase Resync and Spur Consistency ....................................... 19 INT, FRAC, MOD, and R Relationship.................................... 10 Spurious Signals—Predicting Where They Will Appear....... 20 RF R COUNTER ........................................................................ 10 Filter Design—ADIsimPLL....................................................... 20 Phase Frequency Detector (PFD) and Charge Pump............ 11 Interfacing ................................................................................... 20 MUXOUT and LOCK Detect................................................... 11 PCB Design Guidelines for Chip Scale Package .................... 21 Input Shift Registers ................................................................... 11 Outline Dimensions ....................................................................... 22 Program Modes .......................................................................... 11 Ordering Guide .......................................................................... 22 N Divider Register, R0 ............................................................... 17 REVISION HISTORY 1/04—Data Sheet Changed from a REV. 0 to a REV. A Renumbered Figures and Tables.............................. UNIVERSAL Changes to Specifications ............................................................... 3 Changes to Pin Function Description .......................................... 7 Changes to RF Power-Down section .......................................... 17 Changes to PCB Design Guidelines for Chip Scale Package section .............................................................................. 21 Updated Outline Dimensions ...................................................... 22 Updated Ordering Guide.............................................................. 22 7/03—Revision 0: Initial Version Rev. A | Page 2 of 24 ADF4153 SPECIFICATIONS1 AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 Ω. Table 1. Parameter RF CHARACTERISTICS (3 V) RF Input Frequency (RFIN)2 REFERENCE CHARACTERISTICS REFIN Input Frequency2 REFIN Input Sensitivity REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency3 CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy RSET Range ICP Three-State Leakage Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD, SDVDD VP IDD4 Low Power Sleep Mode NOISE CHARACTERISTICS Phase Noise Figure of Merit5 ADF4153 Phase Noise Floor6 Phase Noise Performance7 1750 MHz Output8 See footnotes on next page. B Version Unit 0.5/4.0 GHz min/max 1.0/4.0 GHz min/max 10/250 MHz min/max 0.7/AVDD 0 to AVDD 10 ±100 V p-p min/max V max pF max µA max 32 MHz max 5 312.5 2.5 1.5/10 1 2 2 2 mA typ µA typ % typ kΩ min/max nA typ % typ % typ % typ 1.4 0.6 ±1 10 V min V max µA max pF max 1.4 0.4 V min V max 2.7/3.3 AVDD AVDD/5.5 24 1 V min/V max V min/V max mA max µA typ −217 −147 −143 dBc/Hz typ dBc/Hz typ dBc/Hz typ −106 dBc/Hz typ Rev. A | Page 3 of 24 Test Conditions/Comments See Figure 17 for input circuit. −8 dBm/0 dBm min/max. For lower frequencies, ensure slew rate (SR) > 396 V/µs. −10 dBm/0 dBm min/max. See Figure 16 for input circuit. For f < 10 MHz, use a dc-coupled CMOS compatible square wave, slew rate > 21 V/µs. AC-coupled. CMOS compatible. Programmable. See Table 5. With RSET = 5.1 kΩ. With RSET = 5.1 kΩ. Sink and source current. 0.5 V < VCP < VP – 0.5. 0.5 V < VCP < VP – 0.5. VCP = VP/2. Open-drain 1 kΩ pull-up to 1.8 V. IOL = 500 µA. 20 mA typical. @ 10 MHz PFD frequency. @ 26 MHz PFD frequency. @ VCO output. @ 1 kHz offset, 26 MHz PFD frequency. ADF4153 1 Operating temperature is B version: −40°C to +80°C. Use a square wave for frequencies below fMIN. 3 Guaranteed by design. Sample tested to ensure compliance. 4 AC coupling ensures AVDD/2 bias. See Figure 16 for typical circuit. 5 This figure can be used to calculate phase noise for any application. Use the formula –217 + 10log(fPFD) + 20logN to calculate in-band phase noise performance as seen at the VCO output. The value given is the lowest noise mode. 6 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value). The value given is the lowest noise mode. 7 The phase noise is measured with the EVAL-ADF4153EB1 evaluation board and the HP8562E spectrum analyzer. 8 fREFIN = 26 MHz; fPFD = 10 MHz; offset frequency = 1 kHz; RFOUT = 1750 MHz; N = 175; loop B/W = 20 kHz; lowest noise mode. 2 Rev. A | Page 4 of 24 ADF4153 TIMING CHARACTERISTICS1 AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 Ω. Table 2. Parameter t1 t2 t3 t4 t5 t6 t7 Unit ns min ns min ns min ns min ns min ns min ns min Test Conditions/Comments LE Setup Time DATA to CLOCK Setup Time DATA to CLOCK Hold Time CLOCK High Duration CLOCK Low Duration CLOCK to LE Setup Time LE Pulse Width Guaranteed by design but not production tested. t4 t5 CLOCK t2 DATA DB23 (MSB) t3 DB22 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t7 LE t1 t6 04414-0-002 1 Limit at TMIN to TMAX (B Version) 20 10 10 25 25 10 20 LE Figure 2. Timing Diagram Rev. A | Page 5 of 24 ADF4153 ABSOLUTE MAXIMUM RATINGS1, 2, 3, 4 TA = 25°C, unless otherwise noted. Table 3. Parameter VDD to GND VDD to VDD VP to GND VP to VDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN, RFIN to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature TSSOP θJA Thermal Impedance LFCSP θJA Thermal Impedance (Paddle Soldered) LFCSP θJA Thermal Impedance (Paddle Not Soldered) Lead Temperature, Soldering Vapor Phase (60 sec) Infrared Rating −0.3 V to +4 V −0.3 V to +0.3 V −0.3 V to +5.8 V −0.3 V to +5.8 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −40°C to +85°C −65°C to +150°C 150°C 150.4°C/W 122°C/W 216°C/W 215°C 220°C 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 This device is a high performance RF integrated circuit with an ESD rating of < 2 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly. 3 GND = AGND = DGND = 0 V. 4 VDD = AVDD = DVDD = SDVDD. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 6 of 24 ADF4153 20 19 18 17 16 CP RSET VP DVDD DVDD PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS CP 2 CPGND 3 16 VP 15 DVDD CPGND AGND AGND RFINB RFINA 14 MUXOUT ADF4153 13 LE TOP VIEW RFINB 5 (Not to Scale) 12 DATA 11 CLK RFIINA 6 10 SDVDD 9 DGND PIN 1 INDICATOR ADF4153 TOP VIEW 15 14 13 12 11 MUXOUT LE DATA CLK SDVDD AVDD 6 AVDD 7 REFIN 8 DGND 9 DGND 10 AVDD 7 REFIN 8 03685-A-002 AGND 4 1 2 3 4 5 Figure 3. TSSOP Pin Configuration 03685-A-003 RSET 1 Figure 4. LFCSP Pin Configuration Table 4. Pin Function Descriptions TSSOP 1 LFCSP 19 Mnemonic RSET Description Connecting a resistor between this pin and ground sets the maximum charge pump output current. The relation ship between ICP and RSET is I CP max = 2 20 CP 3 4 5 1 2, 3 4 CPGND AGND RFINB 6 7 5 6, 7 RFINA AVDD 8 8 REFIN 9 10 9, 10 11 DGND SDVDD 11 12 CLK 12 13 DATA 13 14 LE 14 15 MUXOUT 15 16, 17 DVDD 16 18 VP 25.5 RSET With RSET = 5.1 kΩ, ICPmax = 5 mA. Charge Pump Output. When enabled, this provides ±ICP to the external loop filter, which in turn drives the external VCO. Charge Pump Ground. This is the ground return path for the charge pump. Analog Ground. This is the ground return path of the prescaler. Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a small bypass capacitor, typically 100 pF (see Figure 17). Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO. Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. AVDD has a value of 3 V ± 10%. AVDD must have the same voltage as DVDD. Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of 100 kΩ (see Figure 16). This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled. Digital Ground. ∑-∆ Power. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. SDVDD has a value of 3 V ± 10%. SDVDD must have the same voltage as DVDD. Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the shift register on the CLK rising edge. This input is a high impedance CMOS input. Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high impedance CMOS input. Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the control bits. This multiplexer output allows either the RF lock detect, the scaled RF, or the scaled reference frequency to be accessed externally. Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. DVDD has a value of 3 V ± 10%. DVDD must have the same voltage as AVDD. Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, it can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V. Rev. A | Page 7 of 24 ADF4153 TYPICAL PERFORMANCE CHARACTERISTICS Figure 5 to Figure 10: RFOUT = 1.722 GHz, PFD Freq = 26 MHz, INT = 66, Channel Spacing = 200 kHz, Modulus = 130, Fraction = 1/130, and ICP = 5 mA. Loop Bandwidth = 20 kHz, Reference = Fox 10 MHz TCXO, VCO = Vari-L VCO190-1750T, Eval Board = Eval-ADF4153EB1, measurements taken on HP8562E spectrum analyzer. 0 0 REFERENCE LEVEL = –4dBm OUTPUT POWER (dB) –20 –30 –40 VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 26MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz LOWEST NOISE MODE N = 66 1/130 RBW = 10Hz –10 –20 OUTPUT POWER (dB) –10 –50 –60 –70 REFERENCE LEVEL = –4.2dBm –30 –40 VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 26MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz LOWEST NOISE MODE N = 66 1/130 RBW = 10Hz –50 –60 –71dBc@200kHz –70 –102dBc/Hz 03685-A-004 –90 –100 –2kHz –1kHz 1.722GHz 1kHz –90 –100 –400kHz 2kHz Figure 5. Phase Noise (Lowest Noise Mode) 200kHz 400kHz –40 –50 –10 –20 –60 –95dBc/Hz –70 –30 –40 –74dBc@200kHz VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 26MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz LOW NOISE AND SPUR MODE N = 66 1/130 RBW = 10Hz –50 –60 –70 –90 –100 –2kHz –1kHz 1.722GHz 1kHz 03685-A-008 –80 03685-A-005 –80 REFERENCE LEVEL = –4.2dBm –90 –100 –400kHz 2kHz Figure 6. Phase Noise (Low Noise Mode and Spur Mode) –200kHz 1.722GHz 200kHz 400kHz Figure 9. Spurs (Low Noise and Spur Mode) 0 0 –30 –40 –10 –50 –60 REFERENCE LEVEL = –4.2dBm –20 OUTPUT POWER (dB) REFERENCE LEVEL = –4.2dBm VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 26MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz LOWEST SPUR MODE N = 66 1/130 RBW = 10Hz –90dBc/Hz –70 –40 –50 –60 –70 –80 03685-A-006 –80 –30 VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 26MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz LOWEST SPUR NOISE N = 66 1/130 RBW = 10Hz –90 –100 –2kHz –1kHz 1.722GHz 1kHz 03685-A-009 OUTPUT POWER (dB) –30 VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 26MHz CHANNEL STEP = 200kHz LOOP BANDWIDTH = 20kHz LOW NOISE AND SPUR MODE N = 66 1/130 RBW = 10Hz OUTPUT POWER (dB) REFERENCE LEVEL = –4.2dBm –20 OUTPUT POWER (dB) 1.722GHz 0 –10 –20 –200kHz Figure 8. Spurs (Lowest Noise Mode) 0 –10 03685-A-007 –80 –80 –90 –100 –400kHz 2kHz Figure 7. Phase Noise (Lowest Spur Mode) –200kHz 1.722GHz 200kHz Figure 10. Spurs (Lowest Spur Mode) Rev. A | Page 8 of 24 400kHz ADF4153 –130 –80 PHASE NOISE (dBc/Hz) –150 –90 –95 –100 –160 –170 100 1000 10000 –110 100000 03685-A-013 –105 03685-A-010 PHASE NOISE (dBc/Hz) –85 –140 0 5 10 PHASE DETECTOR FREQUENCY (kHz) Figure 11. PFD Noise Floor vs. PFD Frequency (Lowest Noise Mode) 15 20 RSET VALUE (kΩ) 25 30 35 Figure 14. Phase Noise vs. RSET 5 –90 0 –92 P = 4/5 –15 –20 –30 –35 03685-A-011 –25 P = 8/9 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 –94 –96 –98 –100 –102 4.5 –104 –60 FREQUENCY (GHz) 03685-A-014 –10 PHASE NOISE (dBc/Hz) AMPLITUDE (dBm) –5 –40 –20 0 20 40 TEMPERATURE(°C) 60 Figure 12. RF Input Sensitivity Figure 15. Phase Noise vs. Temperature 6 5 4 3 2 0 –1 –2 –3 –4 03685-A-012 ICP(mA) 1 –5 –6 0 1 2 3 4 5 VCP(V) Figure 13. Charge Pump Output Characteristics Rev. A | Page 9 of 24 80 100 ADF4153 CIRCUIT DESCRIPTION REFERENCE INPUT SECTION INT, FRAC, MOD, AND R RELATIONSHIP The reference input stage is shown in Figure 16. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. The INT, FRAC, and MOD values, in conjunction with the R counter, make it possible to generate output frequencies that are spaced by fractions of the phase frequency detector (PFD). See the RF Synthesizer: A Worked Example section for more information. The RF VCO frequency (RFOUT) equation is RFOUT = FPFD × (INT + (FRAC MOD )) POWER-DOWN CONTROL where RFOUT is the output frequency of external voltage controlled oscillator (VCO). 100kΩ NC SW2 TO R COUNTER REFIN NC FPFD = REFIN × (1 + D ) R BUFFER 04414-0-010 SW1 SW3 NO (1) (2) where: Figure 16. Reference Input Stage REFIN is the reference input frequency. RF INPUT STAGE The RF input stage is shown in Figure 17. It is followed by a 2-stage limiting amplifier to generate the current mode logic (CML) clock levels needed for the prescaler. AVDD 2kΩ R is the preset divide ratio of binary 4-bit programmable reference counter (1 to 15). INT is the preset divide ratio of binary 9-bit counter (31 to 511). 1.6V BIAS GENERATOR D is the REFIN doubler bit. MOD is the preset modulus ratio of binary 12-bit programmable FRAC counter (2 to 4095). 2kΩ FRAC is the preset fractional ratio of binary 12-bit programmable FRAC counter (0 to MOD). RFINA RF R COUNTER The 4-bit RF R counter allows the input reference frequency (REFIN) to be divided down to produce the reference clock to the PFD. Division ratios from 1 to 15 are allowed. AGND 03685-A-015 RFINB RF N DIVIDER FROM RF INPUT STAGE Figure 17. RF Input Stage TO PFD N-COUNTER THIRD ORDER FRACTIONAL INTERPOLATOR RF INT DIVIDER INT REG MOD REG FRAC VALUE 03685-A-016 The RF INT CMOS counter allows a division ratio in the PLL feedback counter. Division ratios from 31 to 511 are allowed. N = INT + FRAC/MOD Figure 18. A and B Counters Rev. A | Page 10 of 24 ADF4153 PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP INPUT SHIFT REGISTERS The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. Figure 19 is a simplified schematic. The PFD includes a fixed delay element that sets the width of the antibacklash pulse, which is typically 3 ns. This pulse ensures that there is no dead zone in the PFD transfer function, and gives a consistent reference spur level. HI D1 Q1 UP The ADF4153 digital section includes a 4-bit RF R counter, a 9bit RF N counter, a 12-bit FRAC counter, and a 12-bit modulus counter. Data is clocked into the 24-bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of four latches on the rising edge of LE. The destination latch is determined by the state of the two control bits (C2 and C1) in the shift register. These are the 2 LSBs, DB1 and DB0, as shown in Figure 2. The truth table for these bits is shown in Table 5. Table 6 shows a summary of how the latches are programmed. U1 +IN PROGRAM MODES CLR1 DELAY Table 5 through Table 10 show how to set up the program modes in the ADF4153. CP The ADF4153 programmable modulus is double buffered. This means that two events have to occur before the part uses a new modulus value. First, the new modulus value is latched into the device by writing to the R divider register. Second, a new write must be performed on the N divider register. Therefore, any time that the modulus value has been updated, the N divider register must be written to after this, to ensure that the modulus value is loaded correctly. CLR2 DOWN D2 Q2 03685-A-017 HI CHARGE PUMP U3 U2 –IN Figure 19. PFD Simplified Schematic MUXOUT AND LOCK DETECT The output multiplexer on the ADF4153 allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2, and M1 (see Table 8). Figure 20 shows the MUXOUT section in block diagram form. The N-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10 kΩ nominal. When lock has been detected, it is high with narrow low-going pulses. Table 5. C2 and C1 Truth Table Control Bits C2 C1 0 0 0 1 1 0 1 1 DVDD THREE-STATE OUTPUT LOGIC LOW DIGITAL LOCK DETECT R COUNTER OUTPUT MUX MUXOUT CONTROL N COUNTER OUTPUT LOGIC HIGH DGND 03685-A-018 ANALOG LOCK DETECT Figure 20. MUXOUT Schematic Rev. A | Page 11 of 24 Register N Divider Register R Divider Register Control Register Noise and Spur Register ADF4153 Table 6. Register Summary FASTLOCK N DIVIDER REG 9-BIT INTEGER VALUE (INT) DB23 DB22 FL1 N9 DB21 DB20 N8 N7 DB19 DB18 N6 N5 DB17 N4 CONTROL BITS 12-BIT FRACTIONAL VALUE (FRAC) DB16 DB15 DB14 N3 N2 N1 DB13 DB12 DB11 F12 F11 F10 DB10 DB9 DB8 F9 F8 F7 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 F6 F5 F4 F3 F2 F1 C2 (0) C1 (0) R3 R2 R1 M12 M11 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 M10 M8 M7 M6 M5 M4 M3 M2 M1 M9 DB1 DB0 C2 (0) C1 (1) CONTROL REG RESYNC DB15 DB14 DB13 S4 S3 S2 DB12 DB11 DB10 S1 U6 CP3 CONTROL BITS DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 CP2 CP1 CP0 U5 U4 U3 U2 U1 CP CURRENT SETTING DB0 C2 (1) C1 (0) NOISE AND SPUR REG NOISE AND SPUR MODE RESERVED DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 T9 T8 T7 T6 T5 T4 T3 T2 T1 Rev. A | Page 12 of 24 CONTROL BITS DB1 C2 (1) DB0 C1 (1) 03685-A-019 R4 DB12 COUNTER RESET P1 DB13 NOISE AND SPUR MODE P2 DB14 CP THREE-STATE M1 DB16 DB15 POWERDOWN M2 DB17 LDP M3 DB19 DB18 PD POLARITY P3 DB21 DB20 CP/2 DB22 CONTROL BITS 12-BIT INTERPOLATOR MODULUS VALUE (MOD) RESERVED DB23 4-BIT R COUNTER REFERENCE DOUBLER MUXOUT PRESCALER RESERVED LOAD CONTROL R DIVIDER REG ADF4153 FAST LOCK Table 7. N Divider Register Map DB23 DB22 FL1 N9 N8 N7 DB19 DB18 N6 DB17 N5 N4 DB16 DB15 N3 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 N1 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 C2 (0) C1 (0) N2 F12 F11 F10 F3 F2 F1 FRACTIONAL VALUE (FRAC) 0 0 0 0 . . . 1 0 0 0 0 . . . 1 0 0 0 0 . . . 1 .......... .......... .......... .......... .......... .......... .......... .......... 0 0 0 0 . . . 1 0 0 1 1 . . . 0 0 1 0 1 . . . 0 0 1 2 3 . . . 4092 1 1 1 .......... 1 0 1 4093 1 1 1 .......... 1 1 0 4094 1 1 1 .......... 1 1 1 4095 N9 N8 N7 N6 N5 N4 N3 N2 N1 INTEGER VALUE (INT) 0 0 0 0 . . . 1 0 0 0 0 . . . 1 0 0 0 0 . . . 1 0 1 1 1 . . . 1 1 0 0 0 . . . 1 1 0 0 0 . . ... 1 1 0 0 0 . . . 1 1 0 0 1 . . . 0 1 0 1 0 . . . 1 31 32 33 34 . . . 509 1 1 1 1 1 1 1 1 0 510 1 1 1 1 1 1 1 1 1 511 FASTLOCK NORMAL OPERATION FAST LOCK ENABLED 03685-A-020 FL1 0 1 DB21 DB20 CONTROL BITS 12-BIT FRACTIONAL VALUE (FRAC) 9-BIT INTEGER VALUE (INT) Rev. A | Page 13 of 24 ADF4153 DB23 DB22 DB21 DB20 P3 P3 0 1 M3 M2 LOAD CONTROL NORMAL OPERATION LOAD RESYNC DB19 DB18 M1 P2 P1 0 1 P1 4-BIT R COUNTER DB17 DB16 DB15 DB14 DB13 R4 R2 R3 R1 PRESCALER 4/5 8/9 M12 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 M11 M8 M7 M6 M5 M4 M3 M2 M1 M10 M9 .......... .......... .......... .......... .......... .......... .......... 0 0 1 . . . 1 1 1 0 . . . 0 1 .......... 1 0 1 4093 1 1 .......... 1 1 0 4094 1 1 .......... 1 1 1 4095 0 0 0 . . . 1 0 0 0 . . . 1 0 0 0 . . . 1 1 1 1 1 R1 RF R COUNTER DIVIDE RATIO 0 0 0 0 . . . 1 0 0 0 1 . . . 1 0 1 1 0 . . . 0 1 0 1 0 . . . 0 1 2 3 4 . . . 12 1 1 0 1 13 1 1 1 0 14 1 1 1 1 15 M1 MUXOUT 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 THREE-STATE OUTPUT DIGITAL LOCK DETECT N DIVIDER OUTPUT LOGIC HIGH R DIVIDER OUTPUT ANALOG LOCK DETECT FASTLOCK SWITCH LOGIC LOW C2 (0) C1 (1) INTERPOLATOR M1 MODULUS VALUE (MOD) 0 2 1 3 0 4 . . . . . . 0 4092 M10 R2 M2 DB0 M2 M11 R3 0 0 0 0 1 1 1 1 DB1 M3 M12 R4 M3 CONTROL BITS 12-BIT INTERPOLATOR MODULUS VALUE (MOD) 03685-A-021 MUXOUT PRESCALER RESERVED LOAD CONTROL Table 8. R Divider Register Map Rev. A | Page 14 of 24 ADF4153 LDP POWERDOWN CP THREE-STATE COUNTER RESET CONTROL BITS DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CP3 CP2 CP1 CP0 U5 U4 U3 U2 U1 C2 (1) C1 (0) RESYNC DB15 DB14 DB13 S4 S3 S2 CP/2 REFERENCE DOUBLE PD POLARITY Table 9. Control Register Map DB12 DB11 S1 U6 CP CURRENT SETTING REFERENCE DOUBLER DISABLED ENABLED U6 0 1 S4 S3 S2 S1 RESYNC 0 0 0 . . . 1 1 1 0 0 0 . . . 1 1 1 0 1 1 . . . 0 1 1 1 0 1 . . . 1 0 1 1 2 3 . . . 13 14 15 U2 0 1 U1 COUNTER RESET 0 1 DISABLED ENABLED CP THREE-STATE DISABLED THREE-STATE U3 POWER-DOWN 0 1 NORMAL OPERATION POWER-DOWN ICP(mA) CP2 0 0 0 0 1 1 1 1 CP1 0 0 1 1 0 0 1 1 CP0 0 1 0 1 0 1 0 1 2.7kΩ 1.09 2.18 3.26 4.35 5.44 6.53 7.62 8.70 5.1kΩ 0.63 1.25 1.88 2.50 3.13 3.75 4.38 5.00 10kΩ 0.29 0.59 0.88 1.15 1.47 1.76 2.06 2.35 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0.54 1.10 1.64 2.18 2.73 3.27 3.81 4.35 0.31 0.63 0.94 1.25 1.57 1.88 2.19 2.50 0.15 0.30 0.44 0.588 0.74 0.88 1.03 1.18 Rev. A | Page 15 of 24 U4 0 1 U5 0 1 LDP 3 5 PD POLARITY NEGATIVE POSITIVE 03685-A-022 CP3 0 0 0 0 0 0 0 0 ADF4153 NOISE AND SPUR MODE NOISE AND SPUR MODE RESERVED Table 10. Noise and Spur Register RESERVED CONTROL BITS DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 T9 T8 T7 T6 T5 T4 T3 T2 T1 C2 (1) C1 (1) DB10, DB5, DB4, DB3 RESERVED 0 RESERVED DB9, DB8, DB7, DB6, DB2 NOISE AND SPUR SETTING 00000 11100 11111 LOWEST SPUR MODE LOW NOISE AND SPUR MODE LOWEST NOISE MODE Rev. A | Page 16 of 24 03685-A-023 THESE BITS MUST BE SET TO 0 FOR NORMAL OPERATION. ADF4153 takes the clock from the RF input stage and divides it down for the counters. It is based on a synchronous 4/5 core. When set to 4/5, the maximum RF frequency allowed is 2 GHz. Therefore, when operating the ADF4153 above 2 GHz, this must be set to 8/9. The prescaler limits the INT value. N DIVIDER REGISTER, R0 With R0[1, 0] set to [0, 0], the on-chip N divider register is programmed. Table 7 shows the input data format for programming this register. 9-Bit INT Value These nine bits control what is loaded as the INT value. This is used to determine the overall feedback division factor. It is used in Equation 1. With P = 4/5, NMIN = 31. 12-Bit FRAC Value The prescaler can also influence the phase noise performance. If INT < 91, a prescaler of 4/5 should be used. For applications where INT > 91, P = 8/9 should be used for optimum noise performance (see Table 8). These 12 bits control what is loaded as the FRAC value into the fractional interpolator. This is part of what determines the overall feedback division factor. It is used in Equation 1. The FRAC value must be less than or equal to the value loaded into the MOD register. Fastlock When set to logic high, this enables the fastlock. This sets the charge pump current to its maximum value. When set to logic low, the charge pump current is equal to the value programmed in the function register. R DIVIDER REGISTER, R1 With R1[1, 0] set to [0, 1], the on-chip R divider register is programmed. Table 8 shows the input data format for programming this register. With P = 8/9, NMIN = 91. 4-Bit RF R Counter The 4-bit RF R counter allows the input reference frequency (REFIN) to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 15 are allowed. 12-Bit Interpolator Modulus This programmable register sets the fractional modulus. This is the ratio of the PFD frequency to the channel step resolution on the RF output. Refer to the RF Synthesizer: A Worked Example section for more information. The ADF4153 programmable modulus is double buffered. This means that two events have to occur before the part uses a new modulus value. First, the new modulus value is latched into the device by writing to the R divider register. Second, a new write must be performed on the N divider register. Therefore, any time that the modulus value has been updated, the N divider register must be written to after this, to ensure that the modulus value is loaded correctly. Load Control When set to logic high, the value being programmed in the modulus is not loaded into the modulus. Instead, it sets the resync delay of the Σ-Δ. This is done to ensure phase resync when changing frequencies. See the Phase Resync and Spur Consistency section for more information and a worked example. CONTROL REGISTER, R2 MUXOUT With R2[1, 0] set to [0, 1], the on-chip control register is programmed. Table 9 shows the input data format for programming this register. The on-chip multiplexer is controlled by R1[22 ... 20] on the ADF4153. Table 8 shows the truth table. Digital Lock Detect RF Counter Reset The digital lock detect output goes high if there are 40 successive PFD cycles with an input error of less than 15 ns. It stays high until a new channel is programmed or until the error at the PFD input exceeds 30 ns for one or more cycles. If the loop bandwidth is narrow compared to the PFD frequency, the error at the PFD inputs may drop below 15 ns for 40 cycles around a cycle slip. Therefore, the digital lock detect may go falsely high for a short period until the error again exceeds 30 ns. In this case, the digital lock detect is reliable only as a loss-of-lock detector. Prescaler (P/P + 1) The dual-modulus prescaler (P/P + 1), along with the INT, FRAC, and MOD counters, determines the overall division ratio from the RFIN to the PFD input. Operating at CML levels, it DB3 is the RF counter reset bit for the ADF4153. When this is 1, the RF synthesizer counters are held in reset. For normal operation, this bit should be 0. RF Charge Pump Three-State This bit puts the charge pump into three-state mode when programmed to 1. It should be set to 0 for normal operation. RF Power-Down DB4 on the ADF4153 provides the programmable power-down mode. Setting this bit to 1 performs a power-down. Setting this bit to 0 returns the synthesizer to normal operation. While in software power-down mode, the part retains all information in its registers. Only when supplies are removed are the register contents lost. Rev. A | Page 17 of 24 ADF4153 When a power-down is activated, the following events occur: DB6 in the ADF4153 sets the phase detector polarity. When the VCO characteristics are positive, this should be set to 1. When they are negative, it should be set to 0. dither is enabled. This randomizes the fractional quantization noise so that it looks more like white noise rather than spurious noise. This means that the part is optimized for improved spurious performance. This operation would normally be used when the PLL closed-loop bandwidth is wide, for fast-locking applications. (Wide-loop bandwidth is seen as a loop bandwidth greater than 1/10 of the RFOUT channel step resolution (fRES)). A wide-loop filter does not attenuate the spurs to a level that a narrow-loop bandwidth would. When the low noise and spur setting is enabled, dither is disabled. This optimizes the synthesizer to operate with improved noise performance. However, the spurious performance is degraded in this mode compared to the lowest spurs setting. To further improve noise performance, the lowest noise setting option can be used, which reduces the phase noise. As well as disabling the dither, it also ensures that the charge pump is operating in an optimum region for noise performance. This setting is extremely useful where a narrow-loop filter bandwidth is available. The synthesizer ensures extremely low noise and the filter attenuates the spurs. The typical performance characteristics give the user an idea of the trade-off in a typical WCDMA setup for the different noise and spur settings. Charge Pump Current Setting RESERVED BITS DB7, DB8, and DB9 set the charge pump current setting. This should be set to the charge pump current that the loop filter is designed with (see Table 9). These bits should be set to 0 for normal operation. REFIN Doubler This equation governs how the synthesizer should be programmed. 1. All active dc current paths are removed. 2. The synthesizer counters are forced to their load state conditions. 3. The charge pump is forced into three-state mode. 4. The digital lock detect circuitry is reset. 5. The RFIN input is debiased. 6. The input register remains active and capable of loading and latching data. Lock Detect Precision (LDP) When this bit is programmed to 0, three consecutive reference cycles of 15 ns must occur before digital lock detect is set. When this bit is programmed to 1, five consecutive reference cycles of 15 ns must occur before digital lock detect is set. Phase Detector Polarity Setting this bit to 0 feeds the REFIN signal directly to the 4-bit RF R counter, disabling the doubler. Setting this bit to 1 multiplies the REFIN frequency by a factor of 2 before feeding into the 4-bit R counter. When the doubler is disabled, the REFIN falling edge is the active edge at the PFD input to the fractional synthesizer. When the doubler is enabled, both the rising and falling edges of REFIN become active edges at the PFD input. When the doubler is enabled and the lowest spur mode is chosen, the in-band phase noise performance is sensitive to the REFIN duty cycle. The phase noise degradation can be as much as 5 dB for the REFIN duty cycles outside a 45% to 55% range. The phase noise is insensitive to the REFIN duty cycle in the lowest noise mode and in the lowest noise and spur mode. The phase noise is insensitive to REFIN duty cycle when the doubler is disabled. RF SYNTHESIZER: A WORKED EXAMPLE [ ] RFOUT = INT + (FRAC MOD ) × [FPFD ] (3) where: RFOUT is the RF frequency output. INT is the integer division factor. FRAC is the fractionality. MOD is the modulus. [ FPFD = REFIN × (1 + D ) R ] where: REFIN is the reference frequency input. NOISE AND SPUR REGISTER, R3 D is the RF REFIN doubler bit. With R3[1, 0] set to 1, 1, the on-chip noise and spur register is programmed. Table 10 shows the input data format for programming this register. R is the RF reference division factor. Noise and Spur Mode Noise and spur mode allows the user to optimize a design either for improved spurious performance or for improved phase noise performance. When the lowest spur setting is chosen, Rev. A | Page 18 of 24 (4) ADF4153 Example: In a GSM 1800 system, where 1.8 GHz RF frequency output (RFOUT) is required, a 13 MHz reference frequency input (REFIN) is available and a 200 kHz channel resolution (fRES) is required on the RF output. MOD = REFIN f RES MOD = 13 MHz 200 kHz = 65 From Equation 4: [ ] FPFD = 13 MHz × (1 + 0 ) 1 = 13 MHz (5) 1.8 G = 13 MHz × (INT + FRAC 65) ≥ (6) INT = 138; ≥ FRAC = 30 MODULUS The choice of modulus (MOD) depends on the reference signal (REFIN) available and the channel resolution (fRES) required at the RF output. For example, a GSM system with 13 MHz REFIN would set the modulus to 65. This means that the RF output resolution (fRES) is the 200 kHz (13 MHz/65) necessary for GSM. REFERENCE DOUBLER AND REFERENCE DIVIDER The reference doubler on-chip allows the input reference signal to be doubled. This is useful for increasing the PFD comparison frequency. Making the PFD frequency higher improves the noise performance of the system. Doubling the PFD frequency usually results in an improvement in noise performance of 3 dB. It is important to note that the PFD cannot be operated above 32 MHz due to a limitation in the speed of the Σ-Δ circuit of the N divider. benefit. PDC requires 25 kHz channel step resolution, whereas GSM 1800 requires 200 kHz channel step resolution. A 13 MHz reference signal could be fed directly to the PFD. The modulus would be programmed to 520 when in PDC mode (13 MHz/ 520 = 25 kHz). The modulus would be reprogrammed to 65 for GSM 1800 operation (13 MHz/65 = 200 kHz). It is important that the PFD frequency remains constant (13 MHz). This allows the user to design one loop filter that can be used in both setups without running into stability issues. It is the ratio of the RF frequency to the PFD frequency that affects the loop design. Keeping this relationship constant, instead of changing the modulus factor, results in a stable filter. SPURIOUS OPTIMIZATION AND FASTLOCK As mentioned earlier, the part can be optimized for spurious performance. However, in fast locking applications, the loop bandwidth needs to be wide, and therefore the filter does not provide much attenuation of the spurs. The programmable charge pump can be used to get around this issue. The filter is designed for a narrow-loop bandwidth so that steady-state spurious specifications are met. This is designed using the lowest charge pump current setting. To implement fastlock during a frequency jump, the charge pump current is set to the maximum setting for the duration of the jump. This has the effect of widening the loop bandwidth, which improves lock time. When the PLL has locked to the new frequency, the charge pump is again programmed to the lowest charge pump current setting. This narrows the loop bandwidth to its original cutoff frequency to allow better attenuation of the spurs than the wide-loop bandwidth. PHASE RESYNC AND SPUR CONSISTENCY 12-BIT PROGRAMMABLE MODULUS Unlike most other fractional-N PLLs, the ADF4153 allows the user to program the modulus over a 12-bit range. This means that the user can set up the part in many different configurations for the application, when combined with the reference doubler and the 4-bit R counter. For example, here is an application that requires 1.75 GHz RF and 200 kHz channel step resolution. The system has a 13 MHz reference signal. One possible setup is feeding the 13 MHz directly to the PFD and programming the modulus to divide by 65. This would result in the required 200 kHz resolution. Another possible setup is using the reference doubler to create 26 MHz from the 13 MHz input signal. This 26 MHz is then fed into the PFD. The modulus is now programmed to divide by 130. This also results in 200 kHz resolution and offers superior phase noise performance over the previous setup. The programmable modulus is also very useful for multistandard applications. If a dual-mode phone requires PDC and GSM 1800 standards, the programmable modulus is a huge Setting the RESYNC bits [S4 ,S3, S2, and S1] enables the phase RESYNC feature. With a fractional denominator of MOD, a fractional-N PLL can settle with any one of (2 × π)/MOD valid phase offsets with respect to the reference input. This is different from integer-N where the RF output always settles to the same static phase offset with respect to the input reference, which is zero ideally. This is not an issue in applications that require only a consistent frequency lock. When RESYNC is enabled, it also ensures that spur levels remain consistent when the PLL returns to a certain frequency. This is due to the fact that the RESYNC function resets the Σ-Δ modulator. RESYNC is enabled by setting the S4 to S1 bits in R2 to a nonzero value. When the S4 to S1 bits are 0, 0, 0, and 0, RESYNC is disabled. For applications where a consistent phase relationship between the output and reference is required (i.e., digital beam forming), the ADF4153 can be used with the phase resync feature enabled. This ensures that if the user programs the PLL to jump from Frequency (and Phase) A to Frequency (and Phase) B and back again to Frequency A, the PLL returns to the original phase (Phase A). Rev. A | Page 19 of 24 ADF4153 When enabled, it activates every time the user programs Register R0 to set a new output frequency. However, if a cycle slip occurs in the settling transient after the phase RESYNC operation, the phase RESYNC is lost. This can be avoided by delaying the RESYNC activation until the locking transient is close to its final frequency. This is done by rewriting to R1 after R1 has been set up as normal. Setting load control [DB23] allows this. When set, instead of determining the fractional denominator, the MOD bits [M12 to M1] are used to set a time interval from when the new channel is programmed to the time the RESYNC is activated. This is called the delay. Its value should be programmed to set a time interval that is at least as long as the RF PLL lock time. INTERFACING For example, if REFIN = 26 MHz and MOD = 130 to give 200 kHz output steps (fRES), and the RF loop has a settling time of 150 µs, then delay should be programmed to 3,900, as 26 MHz × 150 µs = 3,900. ADuC812 Interface SPURIOUS SIGNALS—PREDICTING WHERE THEY WILL APPEAR Just as in integer-N PLLs, spurs appear at PFD frequency offsets from the carrier. In a fractional-N PLL, spurs also appear at frequencies equal to the RFOUT channel step resolution (fRES). The third-order fractional interpolator engine of the ADF4153 may also introduce subfractional spurs. If the fractional denominator (MOD) is divisible by 2, spurs appear at 1/2 fRES. If the fractional denominator (MOD) is divisible by 3, spurs appear at 1/3 fRES. Harmonics of all spurs mentioned will also appear. With the lowest spur mode enabled, the fractional and subfractional spurs is attenuated dramatically. The worst-case spurs appear when the fraction is programmed to (1/MOD). For example, in a GSM 900 MHz system with a 26 MHz PFD frequency and an RFOUT channel step resolution (fRES) of 200 kHz, the MOD = 130. PFD spurs appear at 26 MHz offset, and fractional spurs appear at 200 kHz offset. Since MOD is divisible by 2, subfractional spurs are also present at 100 kHz offset. The maximum allowable serial clock rate is 20 MHz. This means that the maximum update rate possible for the device is 909 kHz or one update every 1.1 µs. This is more than adequate for systems that have typical lock times in the hundreds of microseconds. Figure 21 shows the interface between the ADF4153 and the ADuC812 MicroConverter®. Since the ADuC812 is based on an 8051 core, this interface can be used with any 8051-based microcontroller. The MicroConverter is set up for SPI master mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF4153 needs a 24-bit word, which is accomplished by writing three 8-bit bytes from the MicroConverter to the device. After the third byte is written, the LE input should be brought high to complete the transfer. When operating in the mode described, the maximum SCLOCK rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the output frequency can be changed is 180 kHz. FILTER DESIGN—ADISIMPLL A filter design and analysis program is available to help the user to implement PLL design. Visit www.analog.com/pll for a free download of the ADIsimPLL software. The software designs, simulates, and analyzes the entire PLL frequency domain and time domain response. Various passive and active filter architectures are allowed. REV. #2 of ADIsimPLL allows analysis of the ADF4153. Rev. A | Page 20 of 24 ADuC812 SCLOCK MOSI ADF4153 SCLK SDATA LE I/O PORTS MUXOUT (LOCK DETECT) Figure 21. ADuC812 to ADF4153 Interface 03685-A-024 If the application requires the delay to be greater than 4095, the RESYNC bits should be increased. For example, if the lock time above is 1.5 ms, the delay should be programmed to 26 MHz × 1.5 ms = 39,000. In this case, program M12 to M1 to 3,900 and program S4 to S1 to 10. The delay is 3,900 × 10 = 39,000. The ADF4153 has a simple SPI® compatible serial interface for writing to the device. SCLK, SDATA, and LE control the data transfer. When LE (latch enable) is high, the 22 bits that have been clocked into the input register on each rising edge of SCLK are transferred to the appropriate latch. See Figure 2 for the timing diagram and Table 5 for the latch truth table. ADF4153 ADSP-2181 Interface Figure 22 shows the interface between the ADF4153 and the ADSP-21xx digital signal processor. As discussed previously, the ADF4153 needs a 24-bit serial word for each latch write. The easiest way to accomplish this using the ADSP-21xx family is to use the autobuffered transmit mode of operation with alternate framing. This provides a means for transmitting an entire block of serial data before an interrupt is generated. Set up the word length for eight bits and use three memory locations for each 24-bit word. To program each 24-bit latch, store the three 8-bit bytes, enable the autobuffered mode, and write to the transmit register of the DSP. This last operation initiates the autobuffer transfer. ADSP-21xx TFS I/O FLAGS SCLK SDATA LE MUXOUT (LOCK DETECT) 03685-A-025 DT The lands on the chip scale package (CP-20) are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land should be centered on the pad. This ensures that the solder joint size is maximized. The bottom of the chip scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. On the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. This ensures that shorting is avoided. Thermal vias may be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they should be incorporated in the thermal pad at 1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 oz. copper to plug the via. ADF4153 SCLOCK PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE The user should connect the printed circuit board thermal pad to AGND. Figure 22. ADSP-21xx to ADF4153 Interface Rev. A | Page 21 of 24 ADF4153 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.20 0.09 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153AB Figure 23. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters 0.60 MAX 4.0 BSC SQ 0.60 MAX PIN 1 INDICATOR 3.75 BSC SQ TOP VIEW 11 10 0.80 MAX 0.65 TYP 12° MAX 1.00 0.85 0.80 0.20 REF 2.25 2.10 SQ 1.95 6 5 0.25 MIN 0.30 0.23 0.18 0.05 MAX 0.02 NOM 0.50 BSC 20 1 BOTTOM VIEW 0.75 0.55 0.35 SEATING PLANE 16 15 COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1 Figure 24. 20-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body (CP-20) Dimensions shown in millimeters ORDERING GUIDE Model ADF4153BRU ADF4153BRU-REEL ADF4153BRU-REEL7 ADF4153BCP ADF4153BCP-REEL ADF4153BCP-REEL7 EVAL-ADF4153EB1 Description Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Lead Frame Chip Scale Package (LFCSP) Lead Frame Chip Scale Package (LFCSP) Lead Frame Chip Scale Package (LFCSP) Evaluation Board Rev. A | Page 22 of 24 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Option RU-16 RU-16 RU-16 CP-20 CP-20 CP-20 ADF4153 NOTES Rev. A | Page 23 of 24 ADF4153 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03685–0–1/04(A) Rev. A | Page 24 of 24