^lwNMNM= EZBuck™ 2A Simple Buck Regulator February 2006 General Description The AOZ1010 is a high efficiency, simple to use, 2A buck regulator. The AOZ1010 works from a 4.5V to 16V input voltage range, and provides up to 2A of continuous output current with an output voltage adjustable down to 0.8V. Features • 4.5V to 16V operating input voltage range • 130 m Ω internal PFET switch for high efficiency: up to 95% • Internal Schottky Diode • Internal soft start • Output voltage adjustable to 0.8V • 2A continuous output current • Fixed 500kHz PWM operation • Cycle-by-cycle current limit • Short-circuit protection • Thermal shutdown • Small size SO-8 package The AOZ1010 comes in an SO-8 package and is rated over a -40°C to +85°C ambient temperature range. Applications • Point of load dc/dc conversion • PCIe graphics cards • Set top boxes • DVD drives and HDD • LCD panels • Cable modems • Telecom/Networking/Datacom equipment Typical Application VIN C1 10uF VIN From uPC EN L1 AOZ1010 4.7uH VOUT LX COMP +3.3V Output @2A R1 RC FB AGND PGND R2 C2 47uF CC Figure 1. 3.3V/2A Buck Down Regulator February 2006 www.aosmd.com Page 1 of 16 ^lwNMNM Ordering Information Part Number AOZ1010AI Ambient Temperature Range -40°C to +85°C Package SO-8 Environmental RoHS Pin Configuration PGND 1 8 LX VIN 2 7 LX AGND 3 6 EN FB 4 5 COMP SO-8 Pin Description Pin Number 1 2 Pin Name PGND VIN 3 AGND 4 FB 5 6 COMP EN 7,8 LX Pin Function Power ground. Electrically needs to be connected to AGND. Supply voltage input. When VIN rises above the UVLO threshold the device starts up. Reference connection for controller section. Also used as thermal connection for controller section. Electrically needs to be connected to PGND. The FB pin is used to determine the output voltage via a resistor divider between the output and GND. External loop compensation pin. The enable pin is active high. Connect EN pin to VIN if not used. Do not leave the EN pin floating. PWM output connection to inductor. Thermal connection for output stage. Absolute Maximum Ratings(1) Parameter Supply Voltage (VIN) LX to AGND EN to AGND FB to AGND COMP to AGND PGND to AGND Junction Temperature (TJ) Storage Temperature (TS) ESD Rating(3) February 2006 Recommend Operating Ratings(2) Units 18V -0.7V to VIN+0.3V Parameter Supply Voltage (VIN) Output Voltage Range Units 4.5V to 16V 0.8V to VIN -0.3V to VIN+0.3V -0.3V to 6V -0.3V to 6V -0.3V to +0.3V +150°C -65°C to +150°C 2kV Ambient Temperature (TA) Package Thermal Resistance SO-8 (ΘJA) -40°C to +85°C 87° C/W www.aosmd.com Page 2 of 16 ^lwNMNM Electrical Characteristics TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified(4). Parameter Symbol Supply Voltage Input Under-Voltage Lockout Threshold VIN VUVLO Supply Current (Quiescent) IIN Shutdown Supply Current Feedback Voltage Load Regulation Line Regulation Feedback Voltage Input Current EN Input Threshold IOFF VFB EN Input Hysteresis Modulator Frequency Maximum Duty Cycle Minimum Duty Cycle Error Amplifier Voltage Gain Error Amplifier Transconductance Protection Current Limit Over-Temperature Shutdown Limit VHYS Soft Start Interval Output Stage High-Side Switch On-Resistance IFB VEN Conditions MIN TYP 4.5 VIN rising VIN falling IOUT = 0, VFB = 1.2V, VEN >2V VEN = 0V 4.00 3.70 2 0.782 Off threshold On threshold 3 0.8 0.5 1 MAX UNITS 16 V V V mA 3 20 0.818 200 0.6 2.0 100 fO DMAX DMIN 350 100 500 600 6 500 200 ILIM 2.5 TJ rising TJ falling 145 100 4 VIN = 12V VIN = 5V 97 166 tSS µA V % % nA V V mV kHz % % V/V µA/V 3.6 A °C °C ms 130 200 mΩ mΩ Notes: 1. Exceeding the Absolute Maximum ratings may damage the device. 2. The device is not guaranteed to operate beyond the Maximum Operating ratings. 3. Devices are inherently ESD sensitive, handling precautions are required. Human body model rating: 1.5KΩ in series with 100pF. 4. Specification in BOLD indicate an ambient temperature range of -40°C to +85°C. These specifications are guaranteed by design. February 2006 www.aosmd.com Page 3 of 16 ^lwNMNM Functional Block Diagram Vin UVLO & POR REFERENCE & BIAS 0.8V FB 5V LDO Internal +5V REGULATOR OTP + ISEN SOFTSTART Q1 ILIMIT + + EAMP - PWM PWM – COMP CONTROL LOGIC + LEVEL SHIFTER + FET DRIVER EN LX LX D1 COMP 500Khz OSCILLATOR AGND February 2006 www.aosmd.com PGND Page 4 of 16 ^lwNMNM Typical Performance Characteristics Circuit of figure 1. TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified. Full load (CCM) operation Light load (DCM) operation Vin ripple Vin ripple 0.1V/div 0.1V/div Vo ripple Vo ripple 20mV/div 20mV/div Iin 1A/div Iin 1A/div VLX 10V/div VLX 10V/div 1us/div 1us/div Start up to full load Full load to turn off Vin 5V/div Vin 5V/div Vo 1V/div Vo 1V/div Iin 0.5A/div Iin 0.5A/div 1ms/div 1ms/div Load transient Light load to turn off Vo Ripple Vin 5V/div 50mV/div Vo 1V/div Io 1A/div 100us/div February 2006 Iin 0.5A/div 1s/div www.aosmd.com Page 5 of 16 ^lwNMNM Short circuit protection Short circuit recovery Vo 2V/div Vo 2V/div IL 1A/div IL 1A/div 1ms/div 100us/div Efficiency (Vin=12V) vs. load current AOZ1010AI Efficiency 8.0V output Efficiency (%) 95% 5.0V output 90% 3.3V out 8 V out 5 V out 3.3V output 85% 80% 75% 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Load Current (A) February 2006 www.aosmd.com Page 6 of 16 ^lwNMNM Thermal de-rating curves for SO-8 package part under typical input and output condition Circuit of figure 1. 25ºC ambient temperature and natural convection (air speed<50LFM) unless otherwise specified. AOZ1010AI De-rating curves at 5V input De-rating Curve at 5V Input 2.5 3.3V output 5.0V output Output Current (Io) 2 1.8V output 1.5 1 0.5 0 25 35 45 55 65 75 85 Ambient Temperature (Ta) 1.8V output 3.3V output 5V output AOZ1010 De-rating curves at 12V input De-rating Curve at 12V Input 2.5 8.0V output 2 Output Current (Io) 5.0V output 1.5 3.3V output 1.8V output 1 0.5 0 25 35 45 55 65 75 85 Ambient Temperature (Ta) 1.8V output February 2006 3.3V output 5.0V output www.aosmd.com 8.0V output Page 7 of 16 ^lwNMNM Detailed Description The AOZ1010 is a current-mode step down regulator with integrated high side PMOS switch and a low side freewheeling Schottky diode. It operates from a 4.5V to 16V input voltage range and supplies up to 2A of load current. The duty cycle can be adjusted from 6% to 100% allowing a wide range of output voltage. Features include enable control, Power-On Reset, input under voltage lockout, fixed internal soft-start and thermal shut down. The AOZ1010 is available in SO-8 package. Enable and Soft Start The AOZ1010 has internal soft start feature to limit inrush current and ensure the output voltage ramps up smoothly to regulation voltage. A soft start process begins when the input voltage rises to 4.0V and voltage on EN pin is HIGH. In soft start process, the output voltage is ramped to regulation voltage in typically 4ms. The 4ms soft start time is set internally. The EN pin of the AOZ1010 is active high. Connect the EN pin to VIN if enable function is not used. Pull it to ground will disable the AOZ1010. Do not leave it open. The voltage on EN pin must be above 2.0 V to enable the AOZ1010. When voltage on EN pin falls below 0.6V, the AOZ1010 is disabled. If an application circuit requires the AOZ1010 to be disabled, an open drain or open collector circuit should be used to interface to EN pin. Steady-State Operation Under steady-state conditions, the converter operates in fixed frequency and Continuous-Conduction Mode (CCM). The AOZ1010 integrates an internal P-MOSFET as the high-side switch. Inductor current is sensed by amplifying the voltage drop across the drain to source of the high side power MOSFET. Output voltage is divided down by the external voltage divider at the FB pin. The difference of the FB pin voltage and reference is amplified by the internal transconductance error amplifier. The error voltage, which shows on the COMP pin, is compared against the current signal, which is sum of inductor current signal and ramp compensation signal, at PWM comparator input. If the current signal is less than the error voltage, the internal high-side switch is on. The inductor current flows from the input through the inductor to the output. When the current signal exceeds the error voltage, the high-side switch is off. The inductor current is freewheeling through the internal Schottky diode to output. February 2006 The AOZ1010 uses a P-Channel MOSFET as the high side switch. It saves the bootstrap capacitor normally seen in a circuit which is using an NMOS switch. It allows 100% turn-on of the upper switch to achieve linear regulation mode of operation. The minimum voltage drop from VIN to VO is the load current times DC resistance of MOSFET plus DC resistance of buck inductor. It can be calculated by equation below: VO _ MAX = VIN − I O × ( RDS ( ON ) + Rinductor ) Where VO_MAX is the maximum output voltage; VIN is the input voltage from 4.5V to 16V; IO is the output current from 0A to 2A; RDS(ON) is the on resistance of internal MOSFET, the value is between 97m Ω and 200m Ω depending on input voltage and junction temperature; Rinductor is the inductor DC resistance; Switching Frequency The AOZ1010 switching frequency is fixed and set by an internal oscillator. The actual switching frequency could range from 350kHz to 600kHz due to device variation. Output Voltage Programming Output voltage can be set by feeding back the output to the FB pin with a resistor divider network. In the application circuit shown in Figure 1. The resistor divider network includes R1 and R2. Usually, a design is started by picking a fixed R2 value and calculating the required R1 with equation below. VO = 0.8 × (1 + R1 ) R2 Some standard value of R1, R2 for most commonly used output voltage values are listed in Table 1. Table 1. Vo (V) 0.8 1.2 1.5 1.8 2.5 3.3 5.0 R1 (k Ω) 1.0 4.99 10 12.7 21.5 31.6 52.3 R2 (k Ω) open 10 11.5 10.2 10 10 10 Combination of R1 and R2 should be large enough to avoid drawing excessive current from the output, which will cause power loss. www.aosmd.com Page 8 of 16 ^lwNMNM Since the switch duty cycle can be as high as 100%, the maximum output voltage can be set as high as the input voltage minus the voltage drop on upper PMOS and inductor. Protection Features The AOZ1010 has multiple protection features to prevent system circuit damage under abnormal conditions. Over Current Protection (OCP) The sensed inductor current signal is also used for over current protection. Since the AOZ1010 employs peak current mode control, the COMP pin voltage is proportional to the peak inductor current. The COMP pin voltage is limited to be between 0.4V and 2.5V internally. The peak inductor current is automatically limited cycle by cycle. The cycle by cycle current limit threshold is set between 2.5A and 3.6A. When the load current reaches the current limit threshold, the cycle by cycle current limit circuit turns off the high side switch immediately to terminate the current duty cycle. The inductor current stop rising. The cycle by cycle current limit protection directly limits inductor peak current. The average inductor current is also limited due to the limitation on peak inductor current. When cycle by cycle current limit circuit is triggered, the output voltage drops as the duty cycle decreasing. The AOZ1010 has internal short circuit protection to protect itself from catastrophic failure under output short circuit conditions. The FB pin voltage is proportional to the output voltage. Whenever FB pin voltage is below 0.2V, the short circuit protection circuit is triggered. As a result, the converter is shut down and hiccups at a frequency equals to 1/8 of normal switching frequency. The converter will start up via a soft start once the short circuit condition disappears. In short circuit protection mode, the inductor average current is greatly reduced because of the low hiccup frequency. Application Information The basic AOZ1010 application circuit is shown in Figure 1. Component selection is explained below. Input capacitor The input capacitor must be connected to the VIN pin and PGND pin of the AOZ1010 to maintain steady input voltage and filter out the pulsing input current. The voltage rating of input capacitor must be greater than maximum input voltage plus ripple voltage. The input ripple voltage can be approximated by equation below: ∆VIN = Since the input current is discontinuous in a buck converter, the current stress on the input capacitor is another concern when selecting the capacitor. For a buck circuit, the RMS value of input capacitor current can be calculated by: I CIN _ RMS = I O × VO =m VIN The relation between the input capacitor RMS current and voltage conversion ratio is calculated and shown in Fig. 2 below. It can be seen that when VO is half of VIN, CIN is under the worst current stress. The worst current stress on CIN is 0.5·IO. 0.5 0.5 0.4 0.3 I CIN_RMS ( m) IO 0.2 0.1 0 0 February 2006 VO V (1 − O ) VIN VIN if let m equal the conversion ratio: Power-On Reset (POR) A power-on reset circuit monitors the input voltage. When the input voltage exceeds 4V, the converter starts operation. When input voltage falls below 3.7V, the converter will stop switching. Thermal Protection An internal temperature sensor monitors the junction temperature. It shuts down the internal control circuit and high side PMOS if the junction temperature exceeds 145ºC. The regulator will restart automatically under the control of soft-start circuit when the junction temperature decreases to 100ºC. IO V V × (1 − O ) × O f × C IN VIN VIN 0 0 0.5 m 1 1 Figure 2. ICIN vs. voltage conversion ratio For reliable operation and best performance, the input capacitors must have current rating higher than ICIN-RMS at worst operating conditions. Ceramic capacitors are www.aosmd.com Page 9 of 16 ^lwNMNM preferred for input capacitors because of their low ESR and high ripple current rating. Depending on the application circuits, other low ESR tantalum capacitor may also be used. When selecting ceramic capacitors, X5R or X7R type dielectric ceramic capacitors are preferred for their better temperature and voltage characteristics. Note that the ripple current rating from capacitor manufactures are based on certain amount of life time. Further de-rating may be necessary for practical design requirement. Inductor The inductor is used to supply constant current to output when it is driven by a switching voltage. For given input and output voltage, inductance and switching frequency together decide the inductor ripple current, which is, V V ∆I L = O × (1 − O ) f ×L VIN The peak inductor current is: I Lpeak = I O + ∆I L 2 High inductance gives low inductor ripple current but requires larger size inductor to avoid saturation. Low ripple current reduces inductor core losses. It also reduces RMS current through inductor and switches, which results in less conduction loss. Usually, peak to peak ripple current on inductor is designed to be 20% to 30% of output current. When selecting the inductor, make sure it is able to handle the peak current without saturation even at the highest operating temperature. The inductor takes the highest current in a buck circuit. The conduction loss on inductor needs to be checked for thermal and efficiency requirements. Surface mount inductors in different shape and styles are available from Coilcraft, Elytone and Murata. Shielded inductors are small and radiate less EMI noise. But they cost more than unshielded inductors. The choice depends on EMI requirement, price and size. Table below lists some inductors for typical output voltage design. Table 2. Vout L1 5.0 V Unshielded, 4.7uH LQH55DN4R7M03 Shielded, 4.7uH LQH66SN4R7M03 Shield, 5.8uH ET553-5R8 Un-shielded, 6.7uH DO3316P-682MLD 3.3 V Unshielded, 4.7uH LQH55DN3R3M03 Shield, 4.7uH LQH66SN3R3M03 Shield, 3.3uH ET553-3R3 Un-shielded, 4.7uH DO3316P-472MLD Un-shielded, 4.7uH DO1813P-472HC 1.8 V Unshielded, 2.2uH LQH55DN1R5M03 Shield, 2.2uH LQH66SN1R5M03 Shield, 2.2uH ET553-2R2 Un-shielded, 2.2uH DO3316P-222MLD Un-shielded, 2.2uH DO1813P-222HC Manufacture MURATA MURATA ELYTONE Coilcraft MURATA MURATA ELYTONE Coilcraft Coilcraft MURATA MURATA ELYTONE Coilcraft Coilcraft Output Capacitor The output capacitor is selected based on the DC output voltage rating, output ripple voltage specification and ripple current rating. The selected output capacitor must have a higher rated voltage specification than the maximum desired output voltage including ripple. De-rating needs to be considered for long term reliability. Output ripple voltage specification is another important factor for selecting the output capacitor. In a buck converter circuit, output ripple voltage is determined by inductor value, switching frequency, output capacitor value and ESR. It can be calculated by the equation below: ∆VO = ∆I L × ( ESRCO + 1 ) 8 × f × CO where CO is output capacitor value and ESRCO is the Equivalent Series Resistor of output capacitor. February 2006 www.aosmd.com Page 10 of 16 ^lwNMNM When low ESR ceramic capacitor is used as output capacitor, the impedance of the capacitor at the switching frequency dominates. Output ripple is mainly caused by capacitor value and inductor ripple current. The output ripple voltage calculation can be simplified to: ∆VO = ∆I L × If the impedance of ESR at switching frequency dominates, the output ripple voltage is mainly decided by capacitor ESR and inductor ripple current. The output ripple voltage calculation can be further simplified to: ∆VO = ∆I L × ESRCO For lower output ripple voltage across the entire operating temperature range, X5R or X7R dielectric type of ceramic, or other low ESR tantalum are recommended to be used as output capacitors. In a buck converter, output capacitor current is continuous. The RMS current of output capacitor is decided by the peak to peak inductor ripple current. It can be calculated by: ∆I L 12 Usually, the ripple current rating of the output capacitor is a smaller issue because of the low current stress. When the buck inductor is selected to be very small and inductor ripple current is high, output capacitor could be overstressed. Loop Compensation The AOZ1010 employs peak current mode control for easy use and fast transient response. Peak current mode control eliminates the double pole effect of the output L&C filter. It greatly simplifies the compensation loop design. With peak current mode control, the buck power stage can be simplified to be a one-pole and one-zero system in frequency domain. The pole is dominant pole and can be calculated by: f P1 = February 2006 1 2π × CO × RL f Z1 = 1 2π × CO × ESRCO Where CO is the output filter capacitor; RL is load resistor value; ESRCO is the equivalent series resistance of output capacitor; 1 8 × f × CO I CO _ RMS = The zero is a ESR zero due to output capacitor and its ESR. It is can be calculated by: The compensation design is actually to shape the converter close loop transfer function to get desired gain and phase. Several different types of compensation network can be used for AOZ1010. For most cases, a series capacitor and resistor network connected to the COMP pin sets the pole-zero and is adequate for a stable high-bandwidth control loop. In the AOZ1010, FB pin and COMP pin are the inverting input and the output of internal transconductance error amplifier. A series R and C compensation network connected to COMP provides one pole and one zero. The pole is: f P2 = G EA 2π × CC × GVEA Where GEA is the error amplifier transconductance, which is 200•10-6 A/V; GVEA is the error amplifier voltage gain, which is 500 V/V; CC is compensation capacitor; The zero given by the external compensation network, capacitor CC and resistor RC, is located at: fZ2 = 1 2π × CC × RC To design the compensation circuit, a target crossover frequency fC for close loop must be selected. The system crossover frequency is where control loop has unity gain. The crossover frequency is also called the converter bandwidth. Generally a higher bandwidth means faster response to load transient. However, the bandwidth should not be too high because of system stability concern. When designing the compensation loop, converter stability under all line and load condition must be considered. Usually, it is recommended to set the bandwidth to be less than 1/10 of switching frequency. The AOZ1010 www.aosmd.com Page 11 of 16 ^lwNMNM operates at a fixed switching frequency range from 350kHz to 600kHz. It is recommended to choose a crossover frequency less than 30kHz. f C = 30kHz The strategy for choosing RC and CC is to set the cross over frequency with RC and set the compensator zero with CC. Using selected crossover frequency, fC, to calculate RC: RC = f C × VO 2π × CO × VFB G EA × GCS capacitor, output capacitor, and PGND pin of the AOZ1010. In the AOZ1010 buck regulator circuit, the two major power dissipating components are the AOZ1010 and output inductor. The total power dissipation of converter circuit can be measured by input power minus output power. Ptotal _ loss = VIN ⋅ I IN − VO ⋅ I O The power dissipation of inductor can be approximately calculated by output current and DCR of inductor. Pindcutor _ loss = I O ⋅ Rinductor ⋅ 1.1 2 where fC is desired crossover frequency; VFB is 0.8V; GEA is the error amplifier transconductance, which is 200•10-6 A/V; GCS is the current sense circuit transconductance, which is 5.64 A/V; The compensation capacitor CC and resistor RC together make a zero. This zero is put somewhere close to the dominate pole fp1 but lower than 1/5 of selected crossover frequency. CC can is selected by: CC = 1.5 2π × RC × f P1 T junction = ( Ptotal _ loss − Pinductor _ loss ) ⋅ Θ JA The maximum junction temperature of AOZ1010 is 150ºC, which limits the maximum load current capability. Please see the thermal de-rating curves for the maximum load current of the AOZ1010 under different ambient temperature. The thermal performance of the AOZ1010 is strongly affected by the PCB layout. Extra care should be taken by users during design process to ensure that the IC will operate under the recommended environmental conditions. Equation above can also be simplified to: CC = The actual AOZ1010 junction temperature can be calculated with power dissipation in the AOZ1010 and thermal impedance from junction to ambient. CO × R L RC An easy-to-use application software which helps to design and simulate the compensation loop can be found at www.aosmd.com. Several layout tips are listed below for the best electric and thermal performance. The figure 3 below illustrates a PCB layout example as reference. Thermal management and layout consideration In the AOZ1010 buck regulator circuit, high pulsing current flows through two circuit loops. The first loop starts from the input capacitors, to the VIN pin, to the LX pins, to the filter inductor, to the output capacitor and load, and then return to the input capacitor through ground. Current flows in the first loop when the high side switch is on. The second loop starts from inductor, to the output capacitors and load, to the PGND pin of the AOZ1010, to the LX pins of the AZO1010. Current flows in the second loop when the low side diode is on. In PCB layout, minimizing the two loops area reduces the noise of this circuit and improves efficiency. A ground plane is strongly recommended to connect input February 2006 www.aosmd.com 1. Do not use thermal relief connection to the VIN and the PGND pin. Pour a maximized copper area to the PGND pin and the VIN pin to help thermal dissipation. 2. Input capacitor should be connected to the VIN pin and the PGND pin as close as possible. 3. A ground plane is preferred. If a ground plane is not used, separate PGND from AGND and connect them only at one point to avoid the PGND pin noise coupling to the AGND pin. 4. Make the current trace from LX pins to L to Co to the PGND as short as possible. 5. Pour copper plane on all unused board area and connect it to stable DC nodes, like VIN, GND or VOUT. Page 12 of 16 ^lwNMNM 6. The two LX pins are connected to internal PFET drain. They are low resistance thermal conduction path and most noisy switching node. Connected a copper plane to LX pin to help thermal dissipation. This copper plane should not be too larger otherwise switching noise may be coupled to other part of circuit. 7. Keep sensitive signal trace far away form the LX pins. 8. The AOZ1010-EVA document provides an example of proper layout techniques. Vo Vin L Cin PG LX Vin LX Cout GND AG EN FB CP GND Via to ground plane Figure 3. AOZ1010 PCB layout February 2006 www.aosmd.com Page 13 of 16 ^lwNMNM SO-8 Package Marking Description Z1010AI FAYWLT Note: Logo Z1010AI F&A Y W L&T February 2006 AOS logo Part number code Fab & Assembly location Year code Week code Assembly lot code www.aosmd.com Page 14 of 16 ^lwNMNM February 2006 www.aosmd.com Page 15 of 16 ^lwNMNM February 2006 www.aosmd.com Page 16 of 16