ON NCS325SN2T1G Zero-drift operational amplifier Datasheet

NCS325
50 mV Offset, 0.25 mV/5C,
35 mA, Zero-Drift
Operational Amplifier
Features
•
•
•
•
•
•
•
•
Low Offset Voltage: 14 mV typ, 50 mV max at 25°C
Zero Drift: 0.25 mV/°C max
Low Noise: 1 mVpp, 0.1 Hz to 10 Hz
Quiescent Current: 21 mA typ, 35 mA max at 25°C
Supply Voltage: 1.8 V to 5.5 V
Rail−to−Rail Input and Output
Internal EMI Filtering
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
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MARKING
DIAGRAM
TSOP−5
(SOT23−5)
SN SUFFIX
CASE 483
5
1
5
32A AYWG
G
1
A
= Assembly Location
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
OUT
1
VSS
2
IN+
3
5
VDD
4
IN−
+
−
The NCS325 is a CMOS operational amplifier providing precision
performance. The Zero−Drift architecture allows for continuous
auto−calibration, which provides very low offset, near−zero drift over
time and temperature, and near flat 1/f noise at only 35 mA (max)
quiescent current. These benefits make it ideal for precision DC
applications. The NCS325 provides rail−to−rail input and output
performance and is optimized for low voltage operation as low as
1.8 V and up to 5.5 V. The NCS325 is available in the space−saving
SOT23−5 package.
Typical Applications
•
•
•
•
•
•
Battery Powered Instruments
Temperature Measurements
Transducer Applications
Electronic Scales
Medical Instrumentation
Current Sensing
(Top View)
ORDERING INFORMATION
Device
Package
Shipping†
NCS325SN2T1G
TSOP−5
(Pb−Free)
3000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2014
June, 2014 − Rev. 1
1
Publication Order Number:
NCS325/D
NCS325
ABSOLUTE MAXIMUM RATINGS
Over operating free−air temperature, unless otherwise stated.
Parameter
Rating
Unit
6
V
Input Voltage (Note 1)
(VSS) − 0.3 to (VDD) +
0.3
V
Input Current (Note 1)
±10
mA
Supply Voltage
INPUT AND OUTPUT PINS
Output Short Circuit Current (Note 2)
Continuous
TEMPERATURE
Operating Temperature
−40 to +150
°C
Storage Temperature
−65 to +150
°C
Junction Temperature
−65 to +150
°C
Human Body Model (HBM)
4000
V
Machine Model (MM)
200
V
100
mA
ESD RATINGS (Note 3)
OTHER RATINGS
Latch−up Current (Note 4)
MSL
Level 1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Input terminals are diode−clamped to the power−supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should
be current limited to 10 mA or less
2. Short−circuit to ground.
3. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (JEDEC standard: JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (JEDEC standard: JESD22−A115)
4. Latch−up Current tested per JEDEC standard: JESD78.
THERMAL INFORMATION
Thermal Metric
Junction to Ambient (Note 5)
Symbol
SOT23−5
Unit
qJA
235
°C/W
5. As mounted on an 80x80x1.5 mm FR4 PCB with 650 mm2 and 2 oz (0.034 mm) thick copper heat spreader. Following JEDEC JESD/EIA
51.1, 51.2, 51.3 test guidelines
OPERATING CONDITIONS
Parameter
Supply Voltage (VDD − VSS)
Specified Operating Range
Input Common Mode Voltage Range
Symbol
Range
Unit
VS
1.8 to 5.5
V
TA
−40 to 125
°C
VICMR
VSS−0.1 to VDD+0.1
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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NCS325
ELECTRICAL CHARACTERISTICS: VS = 1.8 V to 5.5 V
At TA = +25°C, RL = 10 kW connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
Boldface limits apply over the specified temperature range, TA = −40°C to 125°C, guaranteed by characterization and/or design.
Parameter
Symbol
Conditions
VOS
DVOS/DT
Min
Typ
Max
Unit
VS = +5V
14
50
mV
TA = −40°C to 125°C
0.02
0.25
mV/°C
Input Characteristics
Offset Voltage
Offset Voltage Drift vs Temp
Input Bias Current
IIB
±50
pA
Input Offset Current
IOS
±100
pA
dB
Common Mode Rejection Ratio
CMRR
Input Resistance
RIN
Input Capacitance
CIN
VSS+0.3 < VCM < VDD − 0.3, VS = 1.8 V
85
108
VSS+0.3 < VCM < VDD − 0.3,
VS = 5.5 V
90
110
VSS−0.1 < VCM < VDD + 0.1, VS = 1.8 V
80
VSS−0.1 < VCM < VDD + 0.1, VS = 5.5 V
92
15
GW
Differential
1.8
pF
Common Mode
3.5
pF
12
100
mV
8
100
mV
OUTPUT CHARACTERISTICS
Output Voltage High
VOH
Output swing within VDD
Output Voltage Low
VOL
Output swing within VSS
Short Circuit Current
ISC
Open Loop Output Impedance
Capacitive Load Drive
Zout−OL
±5
mA
f = 350 kHz, IO = 0 mA, VS = 1.8 V
1.4
kW
f = 350 kHz, IO = 0 mA, VS = 5.5 V
2.7
CL
See Figure
NOISE PERFORMANCE
Voltage Noise Density
Voltage Noise
Current Noise Density
eN
fIN = 1 kHz
100
nV /
√Hz
eP−P
fIN = 0.01 Hz to 1 Hz
0.3
mVPP
fIN = 0.1 Hz to 10 Hz
1
mVPP
fIN = 10 Hz
0.3
pA /
√Hz
iN
Dynamic Performance
Open Loop Voltage Gain
AVOL
RL = 10 kW, VS = 5.5 V
114
dB
Gain Bandwidth Product
GBWP
CL = 100 pF, RL = 10 kW
350
kHz
Phase Margin
fM
CL = 100 pF
60
°
Gain Margin
AM
CL = 100 pF
20
dB
Slew Rate
SR
G = +1, CL = 100 pF, Vs = 1.8 V
0.10
V/ms
G = +1, CL = 100 pF, Vs = 5.5 V
0.16
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
100
TA = −40°C to 125°C
107
dB
ms
95
Turn−on Time
tON
VS = 5 V
100
Quiescent Current
IQ
No load
21
35
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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NCS325
100
VS = 5 V
VCM = midsupply
TA = 25°C
Sample size = 31
80
60
6
30
0
−30
0
−60
PHASE
−90
−40
−120
−60
−150
−80
0
0
3
6
9
12
15
18
21 24
27
30
10
100
1000
10k
100k
−180
1M
OFFSET VOLTAGE (mV)
FREQUENCY (Hz)
Figure 1. Offset Voltage Distribution
Figure 2. Gain and Phase vs. Frequency
100
100
TA = 25°C
90
VS = 5 V
RL = 10 kW
TA = 25°C
90
80
70
70
PSRR (dB)
80
60
50
40
30
60
50
40
30
20
20
VS = 1.8 V
VS = 5 V
10
0
10
100
10
1000
FREQUENCY (Hz)
0
10
100k
10k
VOH, VS = 5 V
400
VOH, VS = 1.8 V
0
VOL, VS = 1.8 V
−1
−2
VOL, VS = 5 V
1
2
3
4
5
6
10k
100k
1M
300
200
VS = 1.8 V
TA = 25°C
IIB+
IIB−
100
0
−100
−200
−300
−400
−500
−1 −0.8 −0.6 −0.4 −0.2
−3
0
1000
500
TA = 25°C
2
1
100
Figure 4. PSRR vs. Frequency
INPUT BIAS CURRENT (pA)
3
VSS
VDD
FREQUENCY (Hz)
Figure 3. CMRR vs. Frequency
OUTPUT SWING (V)
60
20
−20
4
2
CMRR (dB)
GAIN
40
8
GAIN (dB)
FREQUENCY
10
90
Gain, VS = 1.8 V
Gain, VS = 5.5 V
Phase, VS = 1.8 V
Phase, VS = 5.5 V
PHASE (°C)
12
7
8
9
10
0
0.2
0.4
0.6
0.8
OUTPUT CURRENT (mA)
COMMON MODE VOLTAGE (V)
Figure 5. Output Voltage Swing vs. Output
Current
Figure 6. Input Bias Current vs. Common
Mode Voltage, VS = 1.8 V
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1
NCS325
500
500
300
200
100
0
−100
−200
−300
300
200
100
0
−100
−200
−300
−400
−400
−500
−3 −2.5 −2 −1.5 −1
0
0.5
1
1.5
2
2.5
3
−500
−50
3.5
100
125
150
3
TA = 25°C
IIB+
IIB−
VS = 5.0 V
RL = 10 kW
CL = 10 pF
Av = 1 V/V
2
−0.25
−0.5
1
0
−1
−2
−0.75
−0.75
−0.5 −0.25
0
0.25
0.5
DIFFERENTIAL VOLTAGE (V)
0.75
−3
−200
1
−100
0
100
200
300
400
500
TIME (ms)
Figure 9. Input Bias Current vs. Input
Differential Voltage
Figure 10. Large Signal Step Response
0.2
3
VS = 5.0 V
RL = 10 kW
CL = 10 pF
Av = 1 V/V
0.1
0
1
0
−1
−0.1
−2
−100
0
100
200
300
400
Input
Output
2
VOLTAGE (V)
OUTPUT VOLTAGE (V)
70
TEMPERATURE (°C)
0
−0.2
−200
50
Figure 8. Input Bias Current vs. Temperature
0.25
−1
−1
25
0
COMMON MODE VOLTAGE (V)
OUTPUT VOLTAGE (V)
INPUT BIAS CURRENT (pA)
0.5
−25
Figure 7. Input Bias Current vs. Common
Mode Voltage, VS = 5.5 V
1.0
0.75
VS = 5.5 V
IIB+
IIB−
400
INPUT BIAS CURRENT (pA)
INPUT BIAS CURRENT (pA)
400
VS = 5.5 V
TA = 25°C
IIB+
IIB−
−3
−100
500
VS = 5.0 V
RL = 10 kW
CL = 10 pF
Av = −10 V/V
−50
0
50
100
150
TIME (ms)
TIME (ms)
Figure 11. Small Signal Step Response
Figure 12. Positive Over Voltage Recovery
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5
200
NCS325
3
700
Input
Output
SETTING TIME (ms)
VOLTAGE (V)
2
1
0
−1
VS = 5.0 V
RL = 10 kW
CL = 10 pF
Av = −10 V/V
−2
−3
−100
−50
VS = 5.0 V
RL = 10 kW
Output = 4 V Step
600
0
50
100
500
400
300
200
100
150
0
1
200
10
100
TIME (ms)
GAIN (dB)
Figure 13. Negative Over Voltage Recovery
Figure 14. Setting Time vs. Closed Loop Gain
70
VS = 1.8 V
VS = 5.5 V
VOLTAGE (500 nV/div)
OVERSHOOT (%)
60
50
40
30
20
10
RL = 10 kW
Input = 50 mV
0
10
100
1000
LOAD CAPACITANCE (pF)
TIME (1 s/div)
Figure 15. Small Signal Overshoot vs. Load
Capacitance
Figure 16. 0.1 Hz to 10 Hz Noise
1000
CURRENT NOISE (PA/√Hz)
VOLTAGE NOISE (nV/√Hz)
1000
100
10
1
10
VS = 1.8 V
VS = 5.5 V
100
VS = 1.8 V
VS = 5.5 V
100
10
1
0.1
0.01
0.1
1000
1
10
100
1000
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 17. Voltage Noise Spectral Density vs.
Frequency
Figure 18. Current Noise Spectral Density vs.
Frequency
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10k
NCS325
0.2
VS = 5.0 V
VIN = 5 VPP
SR+
0.16
0.12
RL = 10 kW
CL = 100 pF
Av = −10 V/V
VS = 1.8 V
VIN = 1.5 V
SR+
0.1
SR−
0.08
0.06
−40
−20
0
20
40
60
80
100
VS = 5.5 V
25
20
VS = 1.8 V
15
10
5
0
−40
120 140
−20
0
20
40
60
80
100
120 140
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 19. Slew Rate vs. Temperature
Figure 20. Quiescent Current vs. Temperature
6
VDD Pulse
5
4
3
Output
2
1
0
−1
−20
0
20
40
60
5
4.99
4.98
4.97
4.96
4.95
4.94
4.93
4.92
4.90
4.89
4.88
RL = 10 kW
4.87
TA = 25°C
4.86
80
100
120
TIME (ms)
Figure 21. Turn−on Response
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OUTPUT VOLTAGE (V)
0.14
QUIESCENT CURRENT (mA)
SR−
VDD VOLTAGE (V)
SLEW RATE (V/ms)
0.18
30
NCS325
APPLICATIONS INFORMATION
OFFSET CORRECTION
EMI SUSCEPTIBILITY AND INPUT FILTERING
The NCS325 uses an auto zero architecture to establish
low input offset voltage and noise. With an internal clock of
125 kHz, the amplifier offset is calibrated automatically
every 8 ms. The amplifier requires approximately 100 ms to
achieve the specified offset voltage.
Op amps have varying amounts of EMI susceptibility.
Semiconductor junctions can pick up and rectify EMI
signals, creating an EMI−induced voltage offset at the
output, adding another component to the total error. Input
pins are the most sensitive to EMI. The NCS325 integrates
a low−pass filter to decrease its sensitivity to EMI.
INPUT VOLTAGE
The NCS325 has a rail−to−rail common mode input
voltage range. The typical input bias current of the NCS325
is 50 pA. In an overdriven condition, the output is driven to
a supply rail. In this case, the feedback path cannot achieve
IN− = IN+. There are no clamp diodes between IN+ and IN−
to limit this differential voltage. Diodes between the inputs
and the supply rails keep the input voltage from exceeding
the rails.
APPLICATION CIRCUITS
Low−Side Current Sensing
The goal of low−side current sensing is to detect
over−current conditions or as a method of feedback control.
A sense resistor is placed in series with the load to ground.
Typically, the value of the sense resistor is less than 100 mW
to reduce power loss across the resistor. The op amp
amplifies the voltage drop across the sense resistor with a
gain set by external resistors R1, R2, R3, and R4 (where R1
= R2, R3 = R4). Precision resistors are required for high
accuracy, and the gain is set to utilize the full scale of the
ADC for the highest resolution.
VDD
10 kΩ
IN+
+
−
IN−
10 kΩ
VSS
Figure 22. Equivalent Input Circuit
R3
VLOAD
VDD
VDD
VDD
Load
R1
Microcontroller
+
ADC
RSENSE
control
−
R2
R4
Figure 23. Low−Side Current Sensing
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NCS325
Differential Amplifier for Bridged Circuits
produced is relatively small and needs to be amplified before
going into an ADC. Precision amplifiers are recommended
in these types of applications due to their high gain, low
noise, and low offset voltage.
Sensors to measure strain, pressure, and temperature are
often configured in a Wheatstone bridge circuit as shown in
Figure 24. In the measurement, the voltage change that is
VDD
VDD
−
+
Figure 24. Bridge Circuit Amplification
GENERAL LAYOUT GUIDELINES
the device pins. These techniques will reduce susceptibility
to electromagnetic interference (EMI). Thermoelectric
effects can create an additional temperature dependent
offset voltage at the input pins. To reduce these effects, use
metals with low thermoelectric−coefficients and prevent
temperature gradients from heat sources or cooling fans.
To ensure optimum device performance, it is important to
follow good PCB design practices. Place 0.1 mF decoupling
capacitors as close as possible to the supply pins. Keep traces
short, utilize a ground plane, choose surface−mount
components, and place components as close as possible to
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NCS325
PACKAGE DIMENSIONS
TSOP−5
CASE 483−02
ISSUE K
NOTE 5
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
D 5X
0.20 C A B
0.10 T
M
2X
0.20 T
B
5
1
4
2
S
3
K
B
DETAIL Z
G
A
A
TOP VIEW
DIM
A
B
C
D
G
H
J
K
M
S
DETAIL Z
J
C
0.05
H
SIDE VIEW
C
SEATING
PLANE
END VIEW
MILLIMETERS
MIN
MAX
3.00 BSC
1.50 BSC
0.90
1.10
0.25
0.50
0.95 BSC
0.01
0.10
0.10
0.26
0.20
0.60
0_
10 _
2.50
3.00
SOLDERING FOOTPRINT*
0.95
0.037
1.9
0.074
2.4
0.094
1.0
0.039
0.7
0.028
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NCS325/D