Dallas DS2746 Low-cost 2-wire battery monitor with ratiometric a/d input Datasheet

DS2746
Low-Cost 2-Wire Battery Monitor
with Ratiometric A/D Inputs
www.maxim-ic.com
GENERAL DESCRIPTION
FEATURES
The DS2746 provides system-side battery capacity
monitoring in cost-sensitive applications. Voltage,
bidirectional current, and accumulated current
measurement data is provided to the host processor
over a 2-wire interface. Offset bias and offset
blanking features greatly enhance the accuracy of
the coulomb counter. In addition, the DS2746 has
two auxiliary A/D inputs to sample the pack
identification resistor, thermistor, or other voltage
source. The results are reported as a ratiometric
fraction of the supply voltage eliminating error related
to the supply. The DS2746 reduces the total power
consumption of the measurement circuit by enabling
the resistor dividers, through the VOUT pin, only while
measurements are made. When the system is
inactive, a low power sleep mode reduces current
consumption while maintaining the coulomb count.
The tiny 3mm × 3mm TDFN package consumes only
9mm2 of PCB space.
ƒ
14-Bit Bidirectional Current Measurement
- 6.25μV LSB, ±51.2mV Dynamic Range
- 416.7μA LSB, ±3.4A Range (RSNS = 15mΩ)
Current Accumulation Register Resolution
- 6.25μVhr LSB, 409.6mVh Range
- 417μAhr LSB, 27.31Ah Range
11-Bit Battery Voltage Measurement
- 2.44mV LSB, 0V to 4.997V Input Range
- ±10mV Accuracy at 3.6V Input
Two 11-Bit Aux Input Voltage Measurements
- Ratiometric Inputs Eliminate Supply Error
- VOUT drives Dividers, Reduces Power
- ±8 LSB Accuracy
Low Power Consumption:
- Active Current: 70μA typical, 100μA max
- Sleep Current: 1μA typical, 3μA max
ƒ
ƒ
ƒ
ƒ
ORDERING INFORMATION
PART
TEMP RANGE
DS2746G+
-20ºC to +70ºC
DS2746G+T&R
-20ºC to +70ºC
APPLICATIONS
2.5G/3G Wireless Handsets
PDA/Smartphones
Digital Still and Video Cameras
Handheld Computers and Terminals
+ Denotes lead-free package.
TYPICAL OPERATING CIRCUIT
PIN CONFIGURATION
PIN-PACKAGE
10-Pin 3mm×3mm
TDFN
DS2746G+ in Tapeand-Reel
TOP VIEW
3mm × 3mm TDFN
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 080107
DS2746 Low-Cost 2-Wire Battery Monitor
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground
Operating Temperature Range
Storage Temperature Range
Soldering Temperature
-0.3V to +6V
-40°C to +85°C
-55°C to +125°C
See IPC/JEDECJ-STD-020A
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(VDD = 2.5V to 5.5V, TA = -20°C to +70°C.)
PARAMETER
Supply Voltage
Data I/O Pins
Programmable I/O Pin
VIN, AIN0, AIN1 Pin
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VDD
(Note 1)
+2.5
+5.5
V
SCL, SDA
(Note 1)
-0.3
+5.5
V
PIO
(Note 1)
-0.3
+5.5
V
VIN, AIN0,
AIN1
(Note 1)
-0.3
VDD + 0.3
V
DC ELECTRICAL CHARACTERISTICS
(VDD = 2.5V to 4.5V, TA = -20°C to +70°C.)
PARAMETER
SYMBOL
Active Current
IACTIVE
Sleep-Mode Current
ISLEEP
CONDITIONS
MIN
VDD = 5.5V
VDD = 2.0V,
SCL, SDA = Vss
SCL, SDA = Vss
TYP
MAX
UNITS
70
100
105
μA
0.5
1.0
1
3
μV
mV
Current Resolution
ILSB
Current Full-Scale Magnitude
IFS
(Note 1)
Current Offset
IOERR
(Note 2)
- 12.5
+ 12.5
Current Gain Error
IGERR
(Note 11)
- 1.5
+1.5
VDD = 3.6V at +25°C
Timebase Accuracy
tERR
-1
-2
-3
- 10
+1
+2
+3
+ 10
- 20
+ 20
Voltage Error
Input Resistance
VIN, AIN0, AIN1
AIN0, AIN1 Error
VOUT Output Drive
VOUT Precharge Time
Input Logic High:
SCL, SDA
Input Logic Low:
SCL, SDA
Output Logic Low:
SDA
Pulldown Current:
VGERR
6.25
TA = 0°C to +70°C
TA = -20°C to +70°C
VDD = VIN = 3.6V
RIN
AINGERR
μA
±51.2
15
μV
% of
reading
%
mV
MΩ
tPRE
(Note 10)
IO = 1mA
VODIS bit = 0
-8
VDD -0.1
13.3
VIH
(Note 1)
1.5
VIL
(Note 1)
0.6
V
VOL
IOL = 4mA, (Note 1)
0.4
V
IPD
VDD = 4.2V,
2 of 16
+8
14.2
LSB
V
ms
V
0.2
μA
DS2746 Low-Cost 2-Wire Battery Monitor
SCL, SDA
Input Capacitance:
SCL, SDA
Bus Low Timeout
VPIN = 0.4V
CBUS
tSLEEP
(Note 3)
1.5
50
pF
2.2
S
MAX
UNITS
400
KHz
DC ELECTRICAL CHARACTERISTICS: 2-WIRE INTERFACE
(VDD = 2.5V to 5.5V, TA = -20°C to +70°C.)
PARAMETER
SYMBOL
SCL Clock Frequency
fSCL
Bus Free Time Between a
STOP and START Condition
Hold Time (Repeated)
START Condition
tBUF
tHD:STA
CONDITIONS
(Note 4)
(Note 5)
MIN
TYP
0
1.3
µs
0.6
µs
Low Period of SCL Clock
tLOW
1.3
µs
High Period of SCL Clock
tHIGH
0.6
µs
Setup Time for a Repeated
START Condition
tSU:STA
0.6
µs
Data Hold Time
tHD:DAT
(Note 6, 7)
Data Setup Time
tSU:DAT
(Note 6)
Rise Time of Both SDA and
SCL Signals
Fall Time of Both SDA and
SCL Signals
Setup Time for STOP
Condition
Spike Pulse Widths
Suppressed by Input Filter
Capacitive Load for Each Bus
Line
SCL, SDA Input Capacitance
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
0
0.9
100
µs
ns
tR
20 + 0.1CB
300
ns
tF
20 + 0.1CB
300
ns
tSU:STO
0.6
tSP
(Note 8)
CB
(Note 9)
CBIN
0
µs
50
ns
400
pF
60
pF
All voltages are referenced to VSS.
Offset specified after auto-calibration cycle and Current Offset Bias register = 0x00.
The DS2746 enters the sleep mode 1.5s to 2.2s after ( SCL < Vil.) AND ( SDA < Vil ).
Timing must be fast enough to prevent the DS2746 from entering sleep mode due to bus low for period > tSLEEP.
fSCL must meet the minimum clock low time plus the rise/fall times.
The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
This device internally provides a hold time of at least 100ns for the SDA signal (referred to the VIHmin of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.
Cb – total capacitance of one bus line in pF.
The AINGERR spec is only valid when this equation is satisfied: (VAINx + 2VOUT) ≤ (11.6V - (TA - 25°C)10mV/°C). See Figure 1.
Accuracy specification valid for VSS - SNS ≥ ±2.5mV, below which offset error is dominant.
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DS2746 Low-Cost 2-Wire Battery Monitor
Figure 1. Valid Range for AINGERR Accuracy Specification
AINx Voltage
Measurement Error
Not Specified
C
0°
-2
°C
25
°C
70
AINx PIN VOLTAGE AS A PERCENTAGE
OF VOUT (%)
100%
67%
57%
48%
AINx Voltage Measurement Error
≤ AINGERR Specification
0%
2.5V
3.7
3.86
VOUT PIN VOLTAGE (V)
Figure 2. 2-Wire Bus Timing Diagram
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4.0
4.5V
DS2746 Low-Cost 2-Wire Battery Monitor
PIN DESCRIPTION
PIN
1
2
NAME
AIN1
AIN0
3
SCL
4
SDA
5
6
7
SNS
VSS
CTG
8
VOUT
9
VIN
10
VDD
PAD
PAD
FUNCTION
Aux Voltage Input Number 1.
Aux Voltage Input Number 0.
Serial Clock Input. Input only 2-wire clock line. Connect this pin to the CLOCK signal of
the 2-wire interface. This pin has a 0.2µA typical pulldown to sense disconnection.
Serial Data Input / Output. Open drain 2-wire data line. Connect this pin to the DATA
signal of the 2-wire interface. This pin has a 0.2µA typical pulldown to sense
disconnection.
Current-Sense Input. Connect to the handset side of the sense resistor.
Device Ground. Connect to the battery side of the sense resistor.
Connect to Ground. Connect to the battery side of the sense resistor.
Voltage Out. Supply for Aux input voltage Measurement dividers. Connect to high side of
resistor divider circuits.
Battery Voltage Input. The voltage of the cell pack is measured through this pin.
Power-Supply Input. 2.5V to 5.5V input range. Connect to system power through a
decoupling network.
Exposed Pad. Connect to VSS.
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DS2746 Low-Cost 2-Wire Battery Monitor
Figure 3. Block Diagram
DETAILED DESCRIPTION
The DS2746 operates either in active mode where cell voltage, system current, and auxiliary inputs are monitored,
or in a low power sleep mode to conserve energy when the system is idle. While in active mode, the DS2746
contantly measures current flow through an external sense resistor. Each current measurement is reported with
sign and magnitude in a two-byte Current register. Offset bias and offset blanking features remove offset error from
the current A/D to improve measurement accuracy. Each current measurement is integrated into the Accumulated
Current register (ACR) to maintain a sum of all charge entering and exiting the cell.
The DS2746 has two auxiliary inputs to allow voltage sampling of resistor divider circuits. These can be used to
measure a thermistor or an ID resistor located inside the battery pack. The VOUT output provides the pullup voltage
for the resistor divider networks. The DS2746 disables VOUT after measuring the auxiliary inputs to reduce power
use by the measurement system. VOUT operation can be disabled through software to further reduce power
consumption when the auxiliary inputs are not in use.
A dedicated voltage A/D measures voltage of the cell and the auxiliary inputs. A mux on the input to the A/D cycles
through the VIN, AIN0, and AIN1 pins repeatedly in that order. An internal reference is used to measure VIN voltage.
AIN0 and AIN1 are measured as a percentage of VOUT. This ratiometric measurement of the Auxiliary inputs
prevents noise in the supply from affecting accuracy of the readings
The DS2746 measurements can be used directly to provide accurate fuel gauging in typical use conditions, or
along with FuelPack™ algorithms to form a complete and accurate solution for estimating remaining capacity over
wide temperature and operating conditions.
Through its 2-Wire interface, the DS2746 allows a host system read/write access to the Status/Configuration
register and Measurement registers. If sleep mode operation is enabled, holding both interface lines low forces the
DS2746 into a low power sleep mode where A/D measurements are paused and the ACR register is maintained.
FuelPack is a trademark of Dallas Semiconductor.
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DS2746 Low-Cost 2-Wire Battery Monitor
Figure 4. APPLICATION EXAMPLE
System
VDD
Pack+
150
1K
VOUT
VIN
VDD
(1) 5.6V
Protection IC
(Li+/Polymer)
10nF
AIN0
PackID
1K
Therm
1K
SDA
AIN1
SCL
VSS
CTG
SNS
System
Serial
Bus
DS2746
RSNS
Pack-
1nF
1nF
(1) Optional for 8kV/15kV ESD
2.5V
(1)
System
VSS
POWER MODES
The DS2746 operates in one of two power modes: active and sleep. While in active mode, the DS2746 operates as
a high-precision battery monitor with voltage, auxiliary inputs, current and accumulated current measurements
acquired continuously and the resulting values updated in the measurement registers. Read and write access is
allowed to all registers. In sleep mode, the DS2746 operates in a low-power mode with no measurement activity.
The DS2746 operating mode transitions from SLEEP to ACTIVE when:
( SCL > VIH ) OR ( SDA > VIH )
The DS2746 operating mode transitions from ACTIVE to SLEEP when:
SMOD = 1 AND [ ( SCL < VIL ) AND ( SDA < VIL ) ] for tSLEEP
CAUTION: If SMOD = 1, a pull-up resistor is required on SCL and SDA in order to ensure that the DS2746
transitions from SLEEP to ACTIVE mode when the battery is charged. If the bus is not pulled up, the DS2746
remains in SLEEP and cannot accumulate the charge current.
MEASUREMENT SEQUENCE
The DS2746 uses seperate A/D converters to make voltage and current measurements. Each A/D converter
operates completely independent of the other, allowing measurements of voltage and current to be made in
parallel. Current Measurements are made at a resolution of 13 bits plus sign bit. The current register is updated
every 878ms with the average for that time period.
All Voltage Measurements are made at a resolution of 11 bits plus sign bit. The DS2746 continouly cycles through
measuring VIN, AIN0, and AIN1 in that order. Voltage measurement of each input requires 220ms to complete. A
full sequence of voltage measurements requires 660ms to complete. VOUT is active for a precharge time of tPRE
before the AIN0 measurement time occurs. The VOUT pin is enabled during the entire AIN0 and AIN1 measurement
sequence as long as the VODIS (VOUT Disable) bit is cleared. See Figure 5.
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DS2746 Low-Cost 2-Wire Battery Monitor
Figure 5. Measurement Timing
VOLTAGE MEASUREMENT
Battery voltage is measured at the VIN input with respect to VSS over a range of 0V to 4.997V and with a resolution
of 2.44mV. The result is updated every 660ms with the average voltage over the last 220ms and placed in the
VOLTAGE register in two’s compliment form. Voltages above the maximum register value are reported as 7FFFh.
Figure 6. Voltage Register Format
MSB—Address 0Ch
S
210
29
28
27
MSb
26
LSB—Address 0Dh
25
24
23
LSb
MSb
“S”: sign bit(s), “X”: reserved
22
21
20
X
X
X
X
LSb
Units: 2.44mV
The input impedance of VIN is sufficiently large (>15MΩ) to be connected to a high impedance voltage divider in
order to support multiple cell applications. The pack voltage should be divided by the number of series cells to
present a single cell average voltage to the VIN input.
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DS2746 Low-Cost 2-Wire Battery Monitor
AUXILARY INPUT MEASUREMENTS
The DS2746 allows for measuring two auxiliary measurement inputs, AIN0 and AIN1, with respect to VSS. These
inputs are designed for measuring resistor ratios, particularly useful for measuring thermistor or pack identification
resistors. At a time of tPRE prior to the beginning of a measurement cycle on AIN0 or AIN1, the VOUT pin puts out a
reference voltage in order to drive a resistive divider formed by a known resistor value, and the unknown resistance
to be measured. Making these measurements ratiometric with respect to VOUT removes reference tolerance from
the error calculations. Each auxiliary input measurement is updated every 660ms with the average voltage over the
220ms conversion period and placed in the AIN0 and AIN1 Registers in two’s complement form. The input
impedances of AIN0 and AIN1 are sufficiently large (>15MΩ) to be connected to a wide range of voltage divider
resistances.
Figure 7. Auxiliary Input Registers Format
MSB—Address 08h
AIN0
S
210
29
28
27
26
LSB—Address 09h
25
MSb
24
23
LSb
22
21
S
29
28
27
X
X
X
LSb
Units: 1LSB = VVOUT * 1/2047
MSB—Address 0Ah
210
X
MSb
“S”: sign bit, “X”: reserved
AIN1
20
26
LSB—Address 0Bh
25
MSb
24
23
LSb
22
21
20
X
X
X
MSb
X
LSb
“S”: sign bit, “X”: reserved
Units: 1LSB = VVOUT * 1/2047
CURRENT MEASUREMENT
In the active mode of operation, the DS2746 continually measures the current flow into and out of the battery by
measuring the voltage drop across a low-value current-sense resistor, RSNS, connected between the SNS and VSS
pins. The voltage sense range between SNS and VSS is ±51.2mV. Note that positive current values occur when
VSNS is less than VSS, and negative current values occur when VSNS is greater than VSS. Peak signal amplitudes up
to 102mV are allowed at the input as long as the continuous or average signal level does not exceed ±51.2mV over
the conversion period. The ADC samples the input differentially and updates the current register at the completion
of each conversion. The result is updated every 878ms with the average voltage and placed in the CURRENT
register in two’s compliment form. The current measurement register format is shown in Figure 8 and specifications
for several different sense resistor options are shown in Tables 1 and 2. Charge currents above the maximum
register value are reported at the maximum value (7FFFh = +51.2mV). Discharge currents below the minimum
register value are reported at the minimum value (8000h = -51.2mV).
Figure 8. Current Register Formats
MSB—Address 0Eh
S
212 211 210
MSb
“S”: sign bit
29
28
LSB—Address 0Fh
27
26
25
LSb
MSb
9 of 16
24
23
22
21
20
X
X
LSb
Units: 20 = 6.25μV/Rsns
DS2746 Low-Cost 2-Wire Battery Monitor
Table 1. Current Resolution for Various RSNS Values
CURRENT RESOLUTION (1 LSB)
VSS - VSNS
6.25μV
RSNS
20mΩ
312.5µA
15mΩ
416.7µA
10mΩ
625µA
5mΩ
1.25mA
10mΩ
±5.12A
5mΩ
±10.24A
Table 2. Current Range for Various RSNS Values
CURRENT INPUT RANGE
VSS - VSNS
±51.2mV
RSNS
20mΩ
±2.56A
15mΩ
±3.41A
Every 1024th conversion, the ADC measures its input offset to facilitate offset correction. Offset correction occurs
approximately once per hour. The resulting correction factor is applied to the subsequent 1023 measurements.
During the offset correction conversion, the ADC does not measure the SNS to VSS signal. A maximum error of
1/1024 in the accumulated current register (ACR) is possible, however, to reduce the error, the current
measurement just prior to the offset conversion is displayed in the current register and is substituted for the
dropped current measurement in the current accumulation process. The error due to offset correction is typically
much less than 1/1024 of the expected reading.
CURRENT ACCUMULATION
The Accumulated Current register (ACR) serves as an up/down counter holding a running count of charge stored in
the battery. Current measurement results, plus a programmable bias value are internally summed, or accumulated,
at the completion of each current measurement conversion period with the results displayed in the ACR. The ACR
has a range of 0mVh to +409.6mVh with an LSb of 6.25μVh. Additional registers hold fractional results of each
accumulation, however, these bits are not user accessible. The ACR count clamps at FFFFh when accumulating
charge values and at 0000h when accumulating discharge values.
Read and write access is allowed to the ACR. Whenever the ACR is written, fractional accumulation results are
cleared. A write to the ACR also forces the ADC to measure its offset and update the offset correction factor.
Current measurement and accumulation resume (using the new offset correction) with the second conversion
following the write to the ACR. Figure 9 describes the ACR address, format, and resolution. Table 3 shows the
ACR’s dynamic range for several different sense resistor options.
Figure 9. Accumulated Current Register Format
MSB—Address 10h
215 214 213 212 211 210
MSb
“S”: sign bit
LSB—Address 11h
29
28
LSb
27
MSb
10 of 16
26
25
24
23
22
21
20
LSb
Units: 6.25μVh/Rsns
DS2746 Low-Cost 2-Wire Battery Monitor
Table 3. Accumulated Current Range for Various RSNS Values
ACR RANGE
VSS - VSNS
409.6mVh
RSNS
20mΩ
20.48Ah
15mΩ
27.31Ah
10mΩ
40.96Ah
5mΩ
81.92Ah
CURRENT OFFSET BIAS
The Current Offset Bias register (COBR) allows a programmable offset value to be added to raw current
measurements. The result of the raw current measurement plus the COBR value is displayed as the current
measurement result in the CURRENT register, and is used for current accumulation. The COBR value can be used
to correct for a static offset error, or can be used to intentionally skew the current results and therefore the current
accumulation.
Read and write access is allowed to COBR. Whenever the COBR is written, the new value is applied to all
subsequent current measurements. COBR can be programmed in 1.56μV steps to any value between +198μV and
-200μV. The COBR value is stored as a two’s complement value in volatile memory, and must be initialized via the
interface on power-up. Figure 10 describes the COBR address, format, and resolution.
Figure 10. Current Offset Bias Register Format
Address 61h
S
26
MSb
“S”: sign bit
25
24
23
22
21
20
LSb
Units: 1.56μV/Rsns
CURRENT BLANKING
The Current Blanking feature modifies current measurement result prior to being accumulated in the ACR. Current
Blanking occurs conditionally when a current measurement (raw current + COBR) falls in one of two defined
ranges. The first range prevents charge currents less than 100μV/RSNS from being accumulated. The second range
prevents discharge currents less than 25μV/RSNS in magnitude from being accumulated. Charge current blanking is
always performed, however, discharge current blanking must be enabled by setting the NBEN bit in the
Status/Config register. See the register description for additional information.
ACCUMULATION BIAS
The Accumulation Bias register (ABR) allows a programmable offset value to be added to the current accumulation
process. The new ACR value results from the addition of the Current register value plus ABR plus the previous
ACR value. ABR can be used to intentionally skew the current accumulation to estimate system stand-by currents
that are too small to measure. ABR value is not subject to the Current Blanking thresholds.
Read and write access is allowed to the ABR. Whenever the ABR is written, the new value is applied to all
subsequent current measurements. ABR can be set to any value between +193.75μV and -200μV in 6.25μV steps.
The ABR value is stored as a two’s complement value in volatile memory, and must be initialized via the interface
on power-up. The lower two bits of the ABR register have no effect on the data. Figure 11 describes the ABR
address, format, and resolution.
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DS2746 Low-Cost 2-Wire Battery Monitor
Figure 1. Accumulation Bias Register Format
Address 62h
S
24
MSb
“S”: sign bit
23
22
21
20
X
X
LSb
Units: 6.25μVh/Rsns
MEMORY
The DS2746 has memory space with registers for instrumentation, status, and control. When the MSB of a twobyte register is read, both the MSB and LSB are latched and held for the duration of the read data command to
prevent updates during the read and ensure synchronization between the two register bytes. For consistent results,
always read the MSB and the LSB of a two-byte register during the same read data command sequence.
Table 4. Memory Map
ADDRESS (HEX)
00
01
02 to 07
08
09
0A
0B
0C
0D
0E
0F
10
11
12 to 60
61
62
63 to FF
DESCRIPTION
Reserved
Status/Config Register
Reserved
Auxiliary Input 0 Register MSB
Auxiliary Input 0 Register LSB
Auxiliary Input 1 Register MSB
Auxiliary Input 1 Register LSB
Voltage Register MSB
Voltage Register LSB
Current Register MSB
Current Register LSB
Accumulated Current Register MSB
Accumulated Current Register LSB
Reserved
Offset Bias Register
Accumulation Bias Register
Reserved
12 of 16
READ/WRITE
—
R/W
—
R
R
R
R
R
R
R
R
R/W
R/W
—
R/W
R/W
—
POR DEFAULT
X1110X00b
00h
00h
00h
00h
00h
00h
00h
00h
Undefined
Undefined
00h
00h
DS2746 Low-Cost 2-Wire Battery Monitor
STATUS/CONFIG REGISTER
The Status/Config register is read/write with individual bits designated as read only. Bit values indicate status as
well as program or select device functionality.
Figure 12. Status/Config Register Format
ADDRESS 01
BIT 7
X
BIT 6
PORF
BIT 5
SMOD
BIT 4
NBEN
BIT 3
VODIS
BIT 2
X
BIT 1
AIN1
BIT 0
AIN0
X — Reserved.
PORF — The Power-On-Reset Flag is set to indicate initial power-up. PORF is not cleared internally. The user
must write this flag value to a 0 in order to use it to indicate subsequent power-up events. If PORF indicates a
power-on-reset, the ACR could be misaligned with the actual battery state of charge. The system can request a
charge to full in order to synchronize the ACR with the battery charge state. PORF is read/write-to-zero.
SMOD — SLEEP Mode Enable. A value of 1 allows the DS2746 to enter sleep mode when SCL AND SDA are low
for tSLEEP. A value of 0 disables the transition to sleep mode. The power-up default is SMOD = 1.
NBEN — Negative Blanking Enable. A value of 1 enables blanking of negative current values up to 25µV. A value
of 0 disables blanking of negative currents. The power-up default is NBEN = 1.
VODIS – VOUT Disable. When set to 0 this output is driven tPRE before the AIN0 conversion begins, and disabled after
the AIN1 conversion ends. The power-up default is VODIS = 0, a value of 1 disables the VOUT output.
AIN1 – AIN1 Conversion Valid. This read only bit indicates that the VOUT output was enabled, and a conversion has
occurred on the AIN1 pin. When using the VODIS bit, before reading the AIN1 registers, read the AIN1 bit. Only once
the AIN1 bit is set, should the AIN1 register be read.
AIN0 – AIN0 Conversion Valid. This read only bit indicates that the VOUT output was enabled, and a conversion has
occurred on the AIN0 pin. When using the VODIS bit, before reading the AIN0 registers, read the AIN0 bit. Only once
the AIN0 bit is set, should the AIN0 register be read.
2-WIRE BUS SYSTEM
The 2-Wire bus system supports operation as a slave-only device in a single or multislave, and single or
multimaster system. The 2-wire interface consists of a serial data line (SDA) and serial clock line (SCL). SDA and
SCL provide bidirectional communication between the DS2746 slave device and a master device at speeds up to
400 kHz. The DS2746’s SDA pin operates bidirectionally, that is, when the DS2746 receives data, SDA operates
as an input, and when the DS2746 returns data, SDA operates as an open drain output, with the host system
providing a resistive pullup. The DS2746 always operates as a slave device, receiving and transmitting data under
the control of a master device. The master initiates all transactions on the bus and generates the SCL signal as
well as the START and STOP bits which begin and end each transaction.
Bit Transfer
One data bit is transferred during each SCL clock cycle, with the cycle defined by SCL transitioning low-to-high and
then high-to-low. The SDA logic level must remain stable during the high period of the SCL clock pulse. Any
change in SDA when SCL is high is interpreted as a START or STOP control signal.
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DS2746 Low-Cost 2-Wire Battery Monitor
Bus Idle
The bus is defined to be idle, or not busy, when no master device has control. Both SDA and SCL remain high
when the bus is idle. The STOP condition is the proper method to return the bus to the idle state.
START and STOP Conditions
The master initiates transactions with a START condition (S), by forcing a high-to-low transition on SDA while SCL
is high. The master terminates a transaction with a STOP condition (P), a low-to-high transition on SDA while SCL
is high. A REPEATED START condition (Sr) can be used in place of a STOP then START sequence to terminate
one transaction and begin another without returning the bus to the idle state. In multimaster systems, a
REPEATED START allows the master to retain control of the bus. The START and STOP conditions are the only
bus activities in which the SDA transitions when SCL is high.
Acknowledge Bits
Each byte of a data transfer is acknowledged with an Acknowledge bit (A) or a No Acknowledge bit (N). Both the
master and the DS2746 slave generate acknowledge bits. To generate an Acknowledge, the receiving device must
pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low until SCL
returns low. To generate a No Acknowledge (also called NAK), the receiver releases SDA before the rising edge of
the acknowledge-related clock pulse and leaves SDA high until SCL returns low. Monitoring the acknowledge bits
allows for detection of unsuccessful data transfers. An unsuccessful data transfer can occur if a receiving device is
busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication.
Data Order
A byte of data consists of 8 bits ordered most significant bit (msb) first. The least significant bit (lsb) of each byte is
followed by the Acknowledge bit. DS2746 registers composed of multibyte values are ordered most significant byte
(MSB) first. The MSB of multibyte registers is stored on even data memory addresses.
Slave Address
A bus master initiates communication with a slave device by issuing a START condition followed by a Slave
Address (SAddr) and the read/write (R/W) bit. When the bus is idle, the DS2746 continuously monitors for a
START condition followed by its slave address. When the DS2746 receives a slave address that matches its Slave
Address, it responds with an Acknowledge bit during the clock period following the R/W bit. The 7-bit Slave
Address is fixed.
DS2746 Slave Address
0110110
Read/Write Bit
The R/W bit following the slave address determines the data direction of subsequent bytes in the transfer. R/W = 0
selects a write transaction, with the following bytes being written by the master to the slave. R/W = 1 selects a read
transaction, with the following bytes being read from the stave by the master.
Bus Timing
The DS2746 is compatible with any bus timing up to 400kHz. No special configuration is required to operate at any
speed.
2-Wire Command Protocols
The command protocols involve several transaction formats. The simplest format consists of the master writing the
START bit, slave address, R/W bit, and then monitoring the acknowledge bit for presence of the DS2746. More
complex formats such as the Write Data, Read Data and Function command protocols write data, read data and
execute device specific operations. All bytes in each command format require the slave or host to return an
Acknowledge bit before continuing with the next byte. Each function command definition outlines the required
transaction format. The following key applies to the transaction formats.
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DS2746 Low-Cost 2-Wire Battery Monitor
Table 5. 2-Wire Protocol Key
KEY
S
SAddr
FCmd
MAddr
Data
A
N
DESCRIPTION
START bit
Slave Address (7-bit)
Function Command byte
Memory Address byte
Data byte written by master
Acknowledge bit - Master
No Acknowledge - Master
KEY
Sr
W
R
P
Data
A
N
DESCRIPTION
Repeated START
R/W bit = 0
R/W bit = 1
STOP bit
Data byte returned by slave
Acknowledge bit - Slave
No Acknowledge - Slave
Basic Transaction Formats
Write:
S SAddr W A MAddr A Data0 A P
A write transaction transfers one or more data bytes to the DS2746. The data transfer begins at the memory
address supplied in the MAddr byte. Control of the SDA signal is retained by the master throughout the transaction,
except for the Acknowledge cycles.
Read:
S SAddr W A MAddr A Sr SAddr R A Data0 N P
Write Portion
Read Portion
A read transaction transfers one or more bytes from the DS2746. Read transactions are composed of two parts, a
write portion followed by a read portion, and is therefore inherently longer than a write transaction. The write portion
communicates the starting point for the read operation. The read portion follows immediately, beginning with a
REPEATED START, Slave Address with R/W set to a 1. Control of SDA is assumed by the DS2746 beginning with
the Slave Address Acknowledge cycle. Control of the SDA signal is retained by the DS2746 throughout the
transaction, except for the Acknowledge cycles. The master indicates the end of a read transaction by responding
to the last byte it requires with a No Acknowledge. This signals the DS2746 that control of SDA is to remain with
the master following the Acknowledge clock.
Write Data Protocol
The write data protocol is used to write to register and shadow RAM data to the DS2746 starting at memory
address MAddr. Data0 represents the data written to MAddr, Data1 represents the data written to MAddr + 1 and
DataN represents the last data byte, written to MAddr + N. The master indicates the end of a write transaction by
sending a STOP or REPEATED START after receiving the last acknowledge bit.
S SAddr W A MAddr A Data0 A Data1 A … DataN A P
The msb of the data to be stored at address MAddr can be written immediately after the MAddr byte is
acknowledged. Because the address is automatically incremented after the least significant bit (lsb) of each byte is
received by the DS2746, the msb of the data at address MAddr + 1 is can be written immediately after the
acknowledgement of the data at address MAddr. If the bus master continues an auto-incremented write transaction
beyond address 4Fh, the DS2746 ignores the data. Data is also ignored on writes to read-only addresses and
reserved addresses, locked EEPROM blocks as well as a write that auto increments to the Function Command
register (address FEh). Incomplete bytes and bytes that are Not Acknowledged by the DS2746 are not written to
memory. As noted in the Memory Section, writes to unlocked EEPROM blocks modify the shadow RAM only.
Read Data Protocol
The Read Data protocol is used to read register and shadow RAM data from the DS2746 starting at memory
address specified by MAddr. Data0 represents the data byte in memory location MAddr, Data1 represents the data
from MAddr + 1 and DataN represents the last byte read by the master.
S SAddr W A MAddr A Sr SAddr R A Data0 A Data1 A … DataN N P
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DS2746 Low-Cost 2-Wire Battery Monitor
Data is returned beginning with the most significant bit (msb) of the data in MAddr. Because the address is
automatically incremented after the least significant bit (lsb) of each byte is returned, the msb of the data at
address MAddr + 1 is available to the host immediately after the acknowledgement of the data at address MAddr. If
the bus master continues to read beyond address FFh, the DS2746 outputs data values of FFh. Addresses labeled
“Reserved” in the memory map return undefined data. The bus master terminates the read transaction at any byte
boundary by issuing a No Acknowledge followed by a STOP or REPEATED START.
PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package
outline information, go to www.maxim-ic.com/DallasPackInfo.)
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