A4988 DMOS Microstepping Driver with Translator And Overcurrent Protection Features and Benefits Description ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ The A4988 is a complete microstepping motor driver with built-in translator for easy operation. It is designed to operate bipolar stepper motors in full-, half-, quarter-, eighth-, and sixteenth-step modes, with an output drive capacity of up to 35 V and ±2 A. The A4988 includes a fixed off-time current regulator which has the ability to operate in Slow or Mixed decay modes. Low RDS(ON) outputs Automatic current decay mode detection/selection Mixed and Slow current decay modes Synchronous rectification for low power dissipation Internal UVLO Crossover-current protection 3.3 and 5 V compatible logic supply Thermal shutdown circuitry Short-to-ground protection Shorted load protection Five selectable step modes: full, 1/2, 1/4, 1/8, and 1/16 The translator is the key to the easy implementation of the A4988. Simply inputting one pulse on the STEP input drives the motor one microstep. There are no phase sequence tables, high frequency control lines, or complex interfaces to program. The A4988 interface is an ideal fit for applications where a complex microprocessor is unavailable or is overburdened. Package: 28-contact QFN During stepping operation, the chopping control in the A4988 automatically selects the current decay mode, Slow or Mixed. In Mixed decay mode, the device is set initially to a fast decay for a proportion of the fixed off-time, then to a slow decay for the remainder of the off-time. Mixed decay current control results in reduced audible motor noise, increased step accuracy, and reduced power dissipation. with exposed thermal pad 5 mm × 5 mm × 0.90 mm (ET package) Continued on the next page… Approximate size Typical Application Diagram VDD 0.1 μF 0.1 μF 0.22 μF VREG ROSC 0.22 μF CP1 CP2 VCP VDD VBB2 5 kΩ Microcontroller or Controller Logic SLEEP STEP VBB1 OUT1A A4988 OUT1B SENSE1 MS1 MS2 MS3 OUT2A DIR OUT2B ENABLE SENSE2 RESET VREF 4988-DS, Rev. 4 GND GND 100 μF DMOS Microstepping Driver with Translator And Overcurrent Protection A4988 Description (continued) Internal synchronous rectification control circuitry is provided to improve power dissipation during PWM operation. Internal circuit protection includes: thermal shutdown with hysteresis, undervoltage lockout (UVLO), and crossover-current protection. Special power-on sequencing is not required. The A4988 is supplied in a surface mount QFN package (ES), 5 mm × 5 mm, with a nominal overall package height of 0.90 mm and an exposed pad for enhanced thermal dissipation. It is lead (Pb) free (suffix –T), with 100% matte tin plated leadframes. Selection Guide Part Number A4988SETTR-T Package Packing 28-contact QFN with exposed thermal pad 1500 pieces per 7-in. reel Absolute Maximum Ratings Characteristic Symbol Load Supply Voltage VBB Notes Rating Units 35 V Output Current IOUT ±2 A Logic Input Voltage VIN –0.3 to 5.5 V Logic Supply Voltage VDD –0.3 to 5.5 V –2.0 to 37 V VSENSE –0.5 to 0.5 V VREF 5.5 V –20 to 85 ºC Motor Outputs Voltage Sense Voltage Reference Voltage Operating Ambient Temperature Maximum Junction Storage Temperature TA Range S TJ(max) 150 ºC Tstg –55 to 150 ºC Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 DMOS Microstepping Driver with Translator And Overcurrent Protection A4988 Functional Block Diagram 0.1 MF 0.22 MF VREG VDD Current Regulator ROSC CP1 CP2 Charge Pump OSC VCP 0.1 MF DMOS Full Bridge REF DAC VBB1 OUT1A OUT1B PWM Latch Blanking Mixed Decay STEP OCP SENSE1 Gate Drive DIR RESET MS1 Translator Control Logic MS2 PWM Latch Blanking Mixed Decay ENABLE SLEEP DAC VBB2 RS1 OUT2A OCP MS3 DMOS Full Bridge OUT2B SENSE2 RS2 VREF Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A4988 DMOS Microstepping Driver with Translator And Overcurrent Protection ELECTRICAL CHARACTERISTICS1 at TA = 25°C, VBB = 35 V (unless otherwise noted) Characteristics Output Drivers Load Supply Voltage Range Logic Supply Voltage Range Output On Resistance Min. Typ.2 Max. Units 8 3.0 – – – – – – – – – – 320 320 – – – – – – 35 5.5 430 430 1.2 1.2 4 2 8 5 V V mΩ mΩ V V mA mA mA mA VIN(1) VDD0.7 – – V VIN(0) – – V –20 <1.0 VDD0.3 20 –20 <1.0 20 μA – – – 5 0.7 20 23 0 –3 – – – 100 100 50 100 11 1 30 30 – 0 – – – 475 – – – 19 1.3 40 37 4 3 ±15 ±5 ±5 800 kΩ kΩ kΩ % μs μs μs V μA % % % ns 2.1 – – 2.7 – – 165 15 2.8 90 – – – 2.9 – A °C °C V mV Symbol VBB VDD RDSON Body Diode Forward Voltage VF Motor Supply Current IBB Logic Supply Current IDD Test Conditions Operating Operating Source Driver, IOUT = –1.5 A Sink Driver, IOUT = 1.5 A Source Diode, IF = –1.5 A Sink Diode, IF = 1.5 A fPWM < 50 kHz Operating, outputs disabled fPWM < 50 kHz Outputs off Control Logic Logic Input Voltage Logic Input Current Microstep Select Logic Input Hysteresis Blank Time IIN(1) IIN(0) RMS1 RMS2 RMS3 VHYS(IN) tBLANK Fixed Off-Time tOFF Reference Input Voltage Range Reference Input Current VREF IREF Current Trip-Level Error3 errI Crossover Dead Time Protection Overcurrent Protection Threshold4 Thermal Shutdown Temperature Thermal Shutdown Hysteresis VDD Undervoltage Lockout VDD Undervoltage Hysteresis tDT IOCPST TTSD TTSDHYS VDDUVLO VDDUVLOHYS VIN = VDD0.7 VIN = VDD0.3 MS1 pin MS2 pin MS3 pin As a % of VDD OSC = VDD or GND ROSC = 25 kΩ VREF = 2 V, %ITripMAX = 38.27% VREF = 2 V, %ITripMAX = 70.71% VREF = 2 V, %ITripMAX = 100.00% VDD rising μA 1For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum limits. 3V ERR = [(VREF/8) – VSENSE] / (VREF/8). 4Overcurrent protection (OCP) is tested at T = 25°C in a restricted range and guaranteed by characterization. A 2Typical Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 DMOS Microstepping Driver with Translator And Overcurrent Protection A4988 THERMAL CHARACTERISTICS Characteristic Symbol Package Thermal Resistance RθJA Test Conditions* Value Units Four-layer PCB, based on JEDEC standard 32 ºC/W *Additional thermal information available on Allegro Web site. Power Dissipation versus Ambient Temperature 4.00 Power Dissipation, PD (W) 3.50 3.00 2.50 R QJ 2.00 A = 32 ºC /W 1.50 1.00 0.50 0 20 40 60 80 100 120 Temperature, TA (°C) 140 160 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 DMOS Microstepping Driver with Translator And Overcurrent Protection A4988 tA tB STEP tC tD MS1, MS2, MS3, RESET, or DIR Time Duration Symbol Typ. Unit STEP minimum, HIGH pulse width tA 1 μs STEP minimum, LOW pulse width tB 1 μs Setup time, input change to STEP tC 200 ns Hold time, input change to STEP tD 200 ns Figure 1. Logic Interface Timing Diagram Table 1. Microstepping Resolution Truth Table MS1 MS2 MS3 Microstep Resolution Excitation Mode L L L Full Step 2 Phase H L L Half Step 1-2 Phase L H L Quarter Step W1-2 Phase H H L Eighth Step 2W1-2 Phase H H H Sixteenth Step 4W1-2 Phase Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A4988 DMOS Microstepping Driver with Translator And Overcurrent Protection Functional Description Device Operation. The A4988 is a complete microstepping motor driver with a built-in translator for easy operation with minimal control lines. It is designed to operate bipolar stepper motors in full-, half-, quarter-, eighth, and sixteenth-step modes. The currents in each of the two output full-bridges and all of the N-channel DMOS FETs are regulated with fixed off-time PWM (pulse width modulated) control circuitry. At each step, the current for each full-bridge is set by the value of its external current-sense resistor (RS1 and RS2), a reference voltage (VREF), and the output voltage of its DAC (which in turn is controlled by the output of the translator). At power-on or reset, the translator sets the DACs and the phase current polarity to the initial Home state (shown in figures 8 through 12), and the current regulator to Mixed Decay Mode for both phases. When a step command signal occurs on the STEP input, the translator automatically sequences the DACs to the next level and current polarity. (See table 2 for the current-level sequence.) The microstep resolution is set by the combined effect of the MSx inputs, as shown in table 1. When stepping, if the new output levels of the DACs are lower than their previous output levels, then the decay mode for the active full-bridge is set to Mixed. If the new output levels of the DACs are higher than or equal to their previous levels, then the decay mode for the active full-bridge is set to Slow. This automatic current decay selection improves microstepping performance by reducing the distortion of the current waveform that results from the back EMF of the motor. Mixed Decay Operation. The bridge operates in Mixed decay mode, at power-on and reset, and during normal running according to the ROSC configuration and the step sequence, as shown in figures 8 through 12. During Mixed decay, when the trip point is reached, the A4988 initially goes into a fast decay mode for 31.25% of the off-time, tOFF . After that, it switches to Slow decay mode for the remainder of tOFF. A timing diagram for this feature appears on the next page. Typically, mixed decay is only necessary when the current in the winding is going from a higher value to a lower value as determined by the state of the translator. For most loads automatically-selected mixed decay is convenient because it minimizes ripple when the current is rising and prevents missed steps when the current is falling. For some applications where microstepping at very low speeds is necessary, the lack of back EMF in the winding causes the current to increase in the load quickly, resulting in missed steps. This is shown in figure 2. By pulling the ROSC pin to ground, mixed decay is set to be active 100% of the time, for both rising and falling currents, and prevents missed steps as shown in figure 3. If this is not an issue, it is recommended that automatically-selected mixed decay be used, because it will produce reduced ripple currents. Refer to the Fixed Off-Time section for details. Low Current Microstepping. Intended for applications where the minimum on-time prevents the output current from regulating to the programmed current level at low current steps. To prevent this, the device can be set to operate in Mixed decay mode on both rising and falling portions of the current waveform. This feature is implemented by shorting the ROSC pin to ground. Microstep Select (MSx). The microstep resolution is set by the voltage on logic inputs MSx, as shown in table 1. The MS1 and In this state, the off-time is internally set to 30 μs. MS3 pins have a 100 kΩ pull-down resistance, and the MS2 pin ¯ ). The R̄¯Ē¯S̄¯Ē¯T̄¯ input sets the translator has a 50 kΩ pull-down resistance. When changing the step mode Reset Input ( R̄¯Ē¯S̄¯Ē¯T̄ the change does not take effect until the next STEP rising edge. to a predefined Home state (shown in figures 8 through 12), and turns off all of the FET outputs. All STEP inputs are ignored until If the step mode is changed without a translator reset, and abso¯S̄¯Ē ¯T̄ ¯ input is set to high. the R̄¯Ē lute position must be maintained, it is important to change the step mode at a step position that is common to both step modes in Step Input (STEP). A low-to-high transition on the STEP order to avoid missing steps. When the device is powered down, or reset due to TSD or an over current event the translator is set to input sequences the translator and advances the motor one increthe home position which is by default common to all step modes. ment. The translator controls the input to the DACs and the direc- Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 DMOS Microstepping Driver with Translator And Overcurrent Protection A4988 Slow Decay Mixed Decay Slow Decay Mixed Decay Slow Decay Mixed Decay Slow Decay Mixed Decay Missed Step Voltage on ROSC terminal 2 V/div. Step input 10 V/div. t → , 1 s/div. Figure 2. Missed steps in low-speed microstepping Mixed Decay ILOAD 500 mA/div. Step input 10 V/div. No Missed Steps t → , 1 s/div. Figure 3. Continuous stepping using automatically-selected mixed stepping (ROSC pin grounded) Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 DMOS Microstepping Driver with Translator And Overcurrent Protection A4988 tion of current flow in each winding. The size of the increment is determined by the combined state of the MSx inputs. Direction Input (DIR). This determines the direction of rotation of the motor. Changes to this input do not take effect until the next STEP rising edge. Internal PWM Current Control. Each full-bridge is controlled by a fixed off-time PWM current control circuit that limits the load current to a desired value, ITRIP . Initially, a diagonal pair of source and sink FET outputs are enabled and current flows through the motor winding and the current sense resistor, RSx. When the voltage across RSx equals the DAC output voltage, the current sense comparator resets the PWM latch. The latch then turns off the appropriate source driver and initiates a fixed off time decay mode The maximum value of current limiting is set by the selection of RSx and the voltage at the VREF pin. The transconductance function is approximated by the maximum value of current limiting, ITripMAX (A), which is set by ITripMAX = VREF / ( 8 RS ) where RS is the resistance of the sense resistor (Ω) and VREF is the input voltage on the REF pin (V). The DAC output reduces the VREF output to the current sense comparator in precise steps, such that Itrip = (%ITripMAX / 100) × ITripMAX (See table 2 for %ITripMAX at each step.) It is critical that the maximum rating (0.5 V) on the SENSE1 and SENSE2 pins is not exceeded. Fixed Off-Time. The internal PWM current control circuitry uses a one-shot circuit to control the duration of time that the DMOS FETs remain off. The off-time, tOFF, is determined by the ROSC terminal. The ROSC terminal has three settings: ▪ ROSC through a resistor to ground — off-time is determined by the following formula, the decay mode is automatic Mixed decay for all step modes. tOFF ≈ ROSC ⁄ 825 Where tOFF is in μs. Blanking. This function blanks the output of the current sense comparators when the outputs are switched by the internal current control circuitry. The comparator outputs are blanked to prevent false overcurrent detection due to reverse recovery currents of the clamp diodes, and switching transients related to the capacitance of the load. The blank time, tBLANK (μs), is approximately tBLANK ≈ 1 μs Shorted-Load and Short-to-Ground Protection. If the motor leads are shorted together, or if one of the leads is shorted to ground, the driver will protect itself by sensing the overcurrent event and disabling the driver that is shorted, protecting the device from damage. In the case of a short-to-ground, the ¯Ē ¯Ē ¯P̄¯ input goes device will remain disabled (latched) until the S̄L̄ high or VDD power is removed. A short-to-ground overcurrent event is shown in figure 4. When the two outputs are shorted together, the current path is through the sense resistor. After the blanking time (≈1 μs) expires, the sense resistor voltage is exceeding its trip value, due to the overcurrent condition that exists. This causes the driver to go into a fixed off-time cycle. After the fixed off-time expires the driver turns on again and the process repeats. In this condition the driver is completely protected against overcurrent events, but the short is repetitive with a period equal to the fixed off-time of the driver. This condition is shown in figure 5. During a shorted load event it is normal to observe both a positive and negative current spike as shown in figure 3, due to the direction change implemented by the Mixed decay feature. This is shown in figure 6. In both instances the overcurrent circuitry is protecting the driver and prevents damage to the device. Charge Pump (CP1 and CP2). The charge pump is used to generate a gate supply greater than that of VBB for driving the source-side FET gates. A 0.1 μF ceramic capacitor, should be connected between CP1 and CP2. In addition, a 0.1 μF ceramic ▪ ROSC tied to VDD — off-time internally set to 30 μs, decay mode is automatic Mixed decay except when in full step where capacitor is required between VCP and VBB, to act as a reservoir for operating the high-side FET gates. decay mode is set to Slow decay ▪ ROSC tied directly to ground — off-time internally set to 30 μs, current decay is set to Mixed decay for both increasing and decreasing currents for all step modes. Capacitor values should be Class 2 dielectric ±15% maximum, or tolerance R, according to EIA (Electronic Industries Alliance) specifications. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 A4988 DMOS Microstepping Driver with Translator And Overcurrent Protection VREG (VREG). This internally-generated voltage is used to operate the sink-side FET outputs. The nominal output voltage of the VREG terminal is 7 V. The VREG pin must be decoupled with a 0.22 μF ceramic capacitor to ground. VREG is internally monitored. In the case of a fault condition, the FET outputs of the A4988 are disabled. 5 A / div. Fault latched Capacitor values should be Class 2 dielectric ±15% maximum, or tolerance R, according to EIA (Electronic Industries Alliance) specifications. Enable Input ( Ē¯N̄¯Ā¯B̄¯L̄¯Ē¯ ). This input turns on or off all of the FET outputs. When set to a logic high, the outputs are disabled. When set to a logic low, the internal control enables the outputs as required. The translator inputs STEP, DIR, and MSx, as well as the internal sequencing logic, all remain active, independent of the ¯N̄¯Ā¯B̄¯L̄ ¯Ē ¯ input state. Ē Shutdown. In the event of a fault, overtemperature (excess TJ) or an undervoltage (on VCP), the FET outputs of the A4988 are disabled until the fault condition is removed. At power-on, the UVLO (undervoltage lockout) circuit disables the FET outputs and resets the translator to the Home state. t→ Figure 4. Short-to-ground event 5 A / div. Fixed off-time Sleep Mode ( S̄¯L̄¯Ē¯Ē¯P̄¯ ). To minimize power consumption when the motor is not in use, this input disables much of the internal circuitry including the output FETs, current regulator, ¯Ē ¯Ē ¯P̄¯ pin puts the A4988 and charge pump. A logic low on the S̄L̄ into Sleep mode. A logic high allows normal operation, as well as start-up (at which time the A4988 drives the motor to the Home microstep position). When emerging from Sleep mode, in order to allow the charge pump to stabilize, provide a delay of 1 ms before issuing a Step command. Mixed Decay Operation. The bridge operates in Mixed Decay mode, depending on the step sequence, as shown in figures 8 through 12. As the trip point is reached, the A4988 initially goes into a fast decay mode for 31.25% of the off-time, tOFF. After that, it switches to Slow Decay mode for the remainder of tOFF. A timing diagram for this feature appears in figure 7. t→ Figure 5. Shorted load (OUTxA → OUTxB) in Slow decay mode 5 A / div. Fixed off-time Synchronous Rectification. When a PWM-off cycle is triggered by an internal fixed-off time cycle, load current recirculates according to the decay mode selected by the control logic. This synchronous rectification feature turns on the appropriate FETs during current decay, and effectively shorts out the body diodes with the low FET RDS(ON). This reduces power dissipation significantly, and can eliminate the need for external Schottky diodes in many applications. Synchronous rectification turns off when the load current approaches zero (0 A), preventing reversal of the load current. Fast decay portion (direction change) t→ Figure 6. Shorted load (OUTxA → OUTxB) in Mixed decay mode Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 DMOS Microstepping Driver with Translator And Overcurrent Protection A4988 VSTEP 100.00 70.71 See Enlargement A IOUT 0 –70.71 –100.00 Enlargement A toff IPEAK tFD tSD Slow Decay Mixed Decay IOUT Fa st De ca y t Symbol toff IPEAK Characteristic Device fixed off-time Maximum output current tSD Slow decay interval tFD Fast decay interval IOUT Device output current Figure 7. Current Decay Modes Timing Chart Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11 A4988 DMOS Microstepping Driver with Translator And Overcurrent Protection Application Layout Solder A4988 Trace (2 oz.) Signal (1 oz.) Ground (1 oz.) PCB Thermal (2 oz.) Thermal Vias RS1 RS2 ENABLE VBB1 SENSE1 NC OUT1A NC PAD DIR GND CP1 VCP STEP NC VDD C6 SLEEP GND REF ROSC CP2 RESET C4 A4988 MS3 C3 VBB C2 OUT1B OUT2B MS2 1 OUT2A VBB2 C9 SENSE2 C7 MS1 In order to minimize the effects of ground bounce and offset issues, it is important to have a low impedance single-point ground, known as a star ground, located very close to the device. By making the connection between the pad and the ground plane directly under the A4988, that area becomes an ideal location for a star ground point. A low impedance ground will prevent ground bounce during high current operation and ensure that the supply voltage remains stable at the input terminal. The two input capacitors should be placed in parallel, and as close to the device supply pins as possible. The ceramic capacitor (CIN1) should be closer to the pins than the bulk capacitor (CIN2). This is necessary because the ceramic capacitor will be responsible for delivering the high frequency current components. The sense resistors, RSx , should have a very low impedance path to ground, because they must carry a large current while supporting very accurate voltage measurements by the current sense comparators. Long ground traces will cause additional voltage drops, adversely affecting the ability of the comparators to accurately measure the current in the windings. The SENSEx pins have very short traces to the RSx resistors and very thick, low impedance traces directly to the star ground underneath the device. If possible, there should be no other components on the sense circuits. VREG Layout. The printed circuit board should use a heavy groundplane. For optimum electrical and thermal performance, the A4988 must be soldered directly onto the board. Pins 3 and 18 are internally fused, which provides a path for enhanced thermal dissipation. Theses pins should be soldered directly to an exposed surface on the PCB that connects to thermal vias are used to transfer heat to other layers of the PCB. R3 R2 VDD C1 C8 R6 R1 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12 DMOS Microstepping Driver with Translator And Overcurrent Protection A4988 Pin Circuit Diagrams VDD VBB VBB 8V GND GND SENSE GND CP2 GND GND GND GND GND VBB 10 V CP1 40 V PGND VREG VCP VREG DMOS Parasitic GND 8V MS1 MS2 MS3 DIR VREF ROSC SLEEP VBB OUT DMOS Parasitic 8V GND DMOS Parasitic GND GND Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 13 DMOS Microstepping Driver with Translator And Overcurrent Protection A4988 STEP STEP 100.00 100.00 70.71 70.71 Mixed* Slow –70.71 –100.00 100.00 Home Microstep Position 0.00 Phase 2 IOUT2A Direction = H (%) –100.00 100.00 70.71 Phase 2 IOUT2B Direction = H (%) 0.00 Slow Slow Mixed Mixed 0.00 –70.71 70.71 Slow Mixed Mixed* Slow Slow Mixed Home Microstep Position Phase 1 IOUT1A Direction = H (%) Home Microstep Position Slow Home Microstep Position Phase 1 IOUT1A Direction = H (%) Mixed Slow Slow Mixed 0.00 –70.71 –70.71 –100.00 –100.00 *With ROSC pin tied to GND DIR= H DIR= H Figure 8. Decay Mode for Full-Step Increments Figure 9. Decay Modes for Half-Step Increments STEP 100.00 92.39 70.71 Slow Mixed –38.27 –70.71 –92.39 –100.00 100.00 92.39 Slow Mixed* 70.71 Phase 2 IOUT2B Direction = H (%) Mixed Slow 0.00 Home Microstep Position Phase 1 IOUT1A Direction = H (%) Mixed* 38.27 38.27 Slow Mixed Slow Mixed Slow Mixed 0.00 –38.27 –70.71 –92.39 –100.00 *With ROSC pin tied to GND DIR= H Figure 10. Decay Modes for Quarter-Step Increments Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 14 DMOS Microstepping Driver with Translator And Overcurrent Protection A4988 STEP 100.00 92.39 83.15 70.71 55.56 Mixed* 38.27 19.51 Slow –19.51 –38.27 –55.56 –70.71 –83.15 –92.39 –100.00 100.00 92.39 83.15 70.71 55.56 Phase 2 IOUT2B Direction = H (%) Mixed Slow Mixed Mixed Slow 0.00 Home Microstep Position Phase 1 IOUT1A Direction = H (%) Mixed* 38.27 19.51 0.00 Mixed Slow –19.51 –38.27 –55.56 –70.71 –83.15 –92.39 –100.00 *With ROSC pin tied to GND DIR= H Figure 11. Decay Modes for Eighth-Step Increments Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 15 DMOS Microstepping Driver with Translator And Overcurrent Protection A4988 STEP 100.00 95.69 88.19 83.15 77.30 70.71 63.44 55.56 47.14 Mixed* 38.27 29.03 19.51 Phase 1 IOUT1A Direction = H (%) 9.8 Slow 0.00 Mixed Slow Mixed –9.8 –19.51 –29.03 Home Microstep Position –38.27 –47.14 –55.56 –63.44 –70.71 –77.30 –83.15 –88.19 –95.69 –100.00 100.00 95.69 88.19 83.15 77.30 70.71 63.44 55.56 47.14 Mixed* 38.27 29.03 19.51 Phase 2 IOUT2B Direction = H (%) 9.8 0.00 Slow Mixed Slow Mixed Slow –9.8 –19.51 –29.03 –38.27 –47.14 –55.56 –63.44 –70.71 –77.30 –83.15 –88.19 –95.69 –100.00 *With ROSC pin tied to GND DIR= H Figure 12. Decay Modes for Sixteenth-Step Increments Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 16 DMOS Microstepping Driver with Translator And Overcurrent Protection A4988 Table 2. Step Sequencing Settings Home microstep position at Step Angle 45º; DIR = H Full Step # Half Step # 1 1/4 Step # 1 2 2 3 5 6 4 7 8 (%) 100.00 (%) 0.00 2 99.52 9.80 5.6 98.08 19.51 11.3 4 95.69 29.03 16.9 5 92.39 38.27 22.5 6 88.19 47.14 28.1 7 83.15 55.56 33.8 8 77.30 63.44 39.4 9 70.71 70.71 45.0 3 5 10 63.44 77.30 50.6 11 55.56 83.15 56.3 12 47.14 88.19 61.9 13 38.27 92.39 67.5 14 29.03 95.69 73.1 15 19.51 98.08 78.8 16 9.80 99.52 84.4 9 17 0.00 100.00 90.0 18 –9.80 99.52 95.6 10 19 –19.51 98.08 101.3 20 –29.03 95.69 106.9 21 –38.27 92.39 112.5 22 –47.14 88.19 118.1 23 –55.56 83.15 123.8 24 –63.44 77.30 129.4 13 25 –70.71 70.71 135.0 26 –77.30 63.44 140.6 14 27 –83.15 55.56 146.3 28 –88.19 47.14 151.9 29 –92.39 38.27 157.5 30 –95.69 29.03 163.1 31 –98.08 19.51 168.8 32 –99.52 9.80 174.4 7 11 12 2 [% ItripMax] 3 8 3 [% ItripMax] Step Angle (º) 0.0 2 6 4 Phase 2 Current 1/16 Step # 1 4 1 Phase 1 Current 1/8 Step # 2 15 16 Full Step # Half Step # 5 1/4 Step # 9 10 6 11 12 13 14 8 15 16 [% ItripMax] Step Angle (%) 0.00 180.0 34 –99.52 –9.80 185.6 35 –98.08 –19.51 191.3 36 –95.69 –29.03 196.9 37 –92.39 –38.27 202.5 38 –88.19 –47.14 208.1 39 –83.15 –55.56 213.8 40 –77.30 –63.44 219.4 21 41 –70.71 –70.71 225.0 42 –63.44 –77.30 230.6 22 43 –55.56 –83.15 236.3 44 –47.14 –88.19 241.9 45 –38.27 –92.39 247.5 46 –29.03 –95.69 253.1 47 –19.51 –98.08 258.8 48 –9.80 –99.52 264.4 25 49 0.00 –100.00 270.0 50 9.80 –99.52 275.6 26 51 19.51 –98.08 281.3 52 29.03 –95.69 286.9 53 38.27 –92.39 292.5 54 47.14 –88.19 298.1 55 55.56 –83.15 303.8 56 63.44 –77.30 309.4 29 57 70.71 –70.71 315.0 58 77.30 –63.44 320.6 30 59 83.15 –55.56 326.3 60 88.19 –47.14 331.9 61 92.39 –38.27 337.5 62 95.69 –29.03 343.1 63 98.08 –19.51 348.8 64 99.52 –9.80 354.4 19 23 27 28 4 [% ItripMax] 18 24 7 Phase 2 Current 1/16 Step # 33 20 3 Phase 1 Current 1/8 Step # 17 31 32 (%) –100.00 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com (º) 17 DMOS Microstepping Driver with Translator And Overcurrent Protection A4988 22 VBB1 23 SENSE1 24 OUT1A 25 NC 26 OUT2A 27 SENSE2 28 VBB2 Pin-out Diagram OUT2B 1 21 OUT1B ENABLE 2 20 NC GND 3 CP1 4 CP2 5 17 REF VCP 6 16 STEP NC 7 15 VDD SLEEP 14 ROSC 13 18 GND RESET 12 MS3 11 9 MS1 MS2 10 8 VREG Terminal List Table 19 DIR PAD Name Number Description CP1 4 Charge pump capacitor terminal CP2 5 Charge pump capacitor terminal VCP 6 Reservoir capacitor terminal VREG 8 Regulator decoupling terminal MS1 9 Logic input MS2 10 Logic input MS3 11 Logic input ¯S̄¯Ē ¯T̄ ¯ R̄¯Ē 12 Logic input ROSC 13 Timing set S̄¯L̄¯Ē¯Ē¯P̄¯ 14 Logic input VDD 15 Logic supply STEP 16 Logic input REF 17 Gm reference voltage input GND 3, 18 Ground* DIR 19 Logic input OUT1B 21 DMOS Full Bridge 1 Output B VBB1 22 Load supply SENSE1 23 Sense resistor terminal for Bridge 1 OUT1A 24 DMOS Full Bridge 1 Output A OUT2A 26 DMOS Full Bridge 2 Output A SENSE2 27 Sense resistor terminal for Bridge 2 VBB2 28 Load supply OUT2B 1 DMOS Full Bridge 2 Output B ¯ Ē¯N̄¯Ā¯B̄¯L̄¯Ē 2 Logic input NC 7, 20, 25 PAD – No connection Exposed pad for enhanced thermal dissipation* *The GND pins must be tied together externally by connecting to the PAD ground plane under the device. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 18 DMOS Microstepping Driver with Translator And Overcurrent Protection A4988 ET Package, 28-Pin QFN with Exposed Thermal Pad 0.30 5.00 ±0.15 1.15 28 1 2 0.50 28 1 A 5.00 ±0.15 3.15 4.80 3.15 29X D SEATING PLANE 0.08 C C 4.80 C +0.05 0.25 –0.07 PCB Layout Reference View 0.90 ±0.10 0.50 For Reference Only; not for tooling use (reference JEDEC MO-220VHHD-1) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown 0.73 MAX A Terminal #1 mark area B 3.15 2 1 28 3.15 B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) C Reference land pattern layout (reference IPC7351 QFN50P500X500X100-29V1M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Coplanarity includes exposed thermal pad and terminals Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 19 DMOS Microstepping Driver with Translator And Overcurrent Protection A4988 Revision History Revision Revision Date Rev. 4 January 27, 2012 Description of Revision Update IOCPST Copyright ©2009-2012, Allegro MicroSystems, Inc. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 20