ON MC100E446 4-bit parallel/ serial converter Datasheet

SEMICONDUCTOR TECHNICAL DATA
The MC10E/100E446 is an integrated 4-bit parallel to serial data
converter. The device is designed to operate for NRZ data rates of up to
1.3Gb/s. The chip generates a divide by 4 and a divide by 8 clock for both
4-bit conversion and a two chip 8-bit conversion function. The conversion
sequence was chosen to convert the parallel data into a serial stream
from bit D0 to D3. A serial input is provided to cascade two E446 devices
for 8 bit conversion applications. Note that the serial output data clocks off
of the negative input clock transition.
•
•
•
•
•
•
•
•
4-BIT PARALLEL/
SERIAL CONVERTER
On Chip Clock ÷4 and ÷8
1.5 Gb/s Typical Data Rate Capability
Differential Clock and Serial Inputs
VBB Output for Single-ended Input Applications
Asynchronous Data Synchronization
Mode Select to Expand to 8 Bits
Internal 75kΩ Input Pulldown Resistors
Extended 100E VEE Range of -4.2V to -5.46V
The SYNC input will asynchronously reset the internal clock circuitry.
FN SUFFIX
This pin allows the user to reset the internal clock conversion unit and
PLASTIC PACKAGE
thus select the start of the conversion process.
CASE 776-02
The MODE input is used to select the conversion mode of the device.
With the MODE input LOW, or open, the device will function as a 4-bit
converter. When the mode input is driven HIGH the internal load clock will
change on every eighth clock cycle thus allowing for an 8-bit conversion scheme using two E446’s. When cascaded in an 8-bit
conversion scheme the devices will not operate at the 1.3Gb/s data rate of a single device. Refer to the applications section of
this data sheet for more information on cascading the E446.
For lower data rate applications a VBB reference voltage is supplied for single-ended inputs. When operating at clock rates
above 500MHz differential input signals are recommended. For single-ended inputs the VBB pin is tied to the inverting differential
input and bypassed via a 0.01µF capacitor. The VBB provides the switching reference for the input differential amplifier. The VBB
can also be used to AC couple an input signal, for more information on AC coupling refer to the interfacing section of the design
guide in the ECLinPS data book.
Pinout: 28-Lead PLCC (Top View)
PIN NAMES
Pin
Function
SIN
D0 – D3
SOUT, SOUT
CLK, CLK
CL/4, CL/4
CL/8, CL/8
MODE
SYNC
Differential Serial Data Input
Parallel Data Inputs
Differential Serial Data Output
Differential Clock Inputs
Differential ÷4 Clock Output
Differential ÷8 Clock Output
Conversion Mode 4-Bit/8-Bit
Conversion Synchronizing Input
FUNCTION TABLES
Mode
Conversion
L
H
4-Bit
8-Bit
D0
D1
D2
D3 MODE NC
NC
25
24
23
22
CLK
26
19
18
NC
CLK
27
17
NC
VBB
28
16
VCC
VEE
1
15
SOUT
SIN
2
14
SOUT
SIN
3
13
VCCO
SYNC
4
12
NC
5
6
7
8
21
9
20
10
11
VCCO CL/8 CL/8 VCCO CL/4 CL/4 VCCO
7/96
 Motorola, Inc. 1996
2–1
REV 2
MC10E446 MC100E446
LOGIC DIAGRAM
SIN
0
SIN
D
Q
1
D3
CLK
0
D
Q
1
D2
CLK
0
D
Q
1
D1
CLK
0
SOUT
D
Q
SOUT
1
D0
CLK
LOAD PULSE
GENERATOR
CL/8
Mode
0
1
CL/8
CLK
CLK
Delay
÷4
÷8
R
R
CL/4
CL/4
SYNC
MOTOROLA
2–2
ECLinPS and ECLinPS Lite
DL140 — Rev 4
MC10E446 MC100E446
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
150
85°C
Max
Min
Typ
150
Max
Unit
150
µA
IIH
Input HIGH Current
VOH
Output HIGH Voltage
10E (SOUT Only)
100E (SOUT Only)
–1020
–1025
–790
–830
–980
–1025
–760
–830
–910
–1025
–670
–830
VBB
Output Reference Voltage 10E
100E
–1.38
–1.38
–1.27
–1.26
–1.35
–1.38
–1.25
–1.26
–1.31
–1.38
–1.19
–1.26
V
IEE
Power Supply Current
151
174
mA
Condition
V
10E
100E
126
126
151
151
126
126
151
151
126
145
1
1
1. The maximum VOH limit was relaxed from standard ECL due to the high frequency output design. All other outputs are specified with the standard
10E and 100E VOH levels.
AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0°C
Symbol
Characteristic
Min
Typ
1.3
1.6
25°C
Max
Min
Typ
1.3
1.6
1020
650
800
650
1200
850
1050
850
85°C
Max
Min
Typ
1.3
1.6
1020
650
800
650
1200
850
1050
850
Max
Unit
FMAX
Max Conversion Frequency
tPLH
tPHL
Propagation Delay to Output
CLK to SOUT1
CLK to CL/4
CLK to CL/8
SYNC to CL/4, CL/8
1020
650
800
650
1200
850
1050
850
ts
Setup Time2
SIN, Dn
-200
-450
-200
–450
–200
–450
ps
th
Hold Time2
SIN, Dn
900
650
900
650
900
650
ps
tRR
Reset Recovery Time SYNC
500
300
500
300
500
300
ps
tPW
Min Pulse Width
CLK, MR
300
tr
tf
Rise/Fall Times
SOUT
Other
100
200
Condition
Gb/s
NRZ
ps
1480
1050
1300
1100
1480
1050
1300
1100
300
225
425
350
650
100
200
1480
1050
1300
1100
300
225
425
350
650
ps
100
200
225
425
D0–2
D1–2
350
650
ps
20% - 80%
1. Propagation delays measured from negative going clock edge.
2. Relative to negative clock edge.
Timing Diagrams
CLK
RESET
D0
D0–1
D0–2
D1
D1–1
D1–2
D2
D2–1
D2–2
D3
D3–1
D3–2
SOUT
D0–1
D1–1
D2–1
D3–1
D2–2
D3–2
CL/4
CL/8
Timing Diagram A. 4:1 Parallel to Serial Conversion
ECLinPS and ECLinPS Lite
DL140 — Rev 4
2–3
MOTOROLA
MC10E446 MC100E446
Applications Information
The MC10E/100E446 is an integrated 4:1 parallel to serial
converter. The chip is designed to work with the E445 device
to provide both transmission and receiving of a high speed
serial data path. The E446 can convert 4 bits of data into a
1.3Gb/s NRZ data stream. The device features a SYNC input
which allows the user to reset the internal clock circuitry and
restart the conversion sequence (see timing diagram A).
CLK
CLK
E446B
E446A
SOUT
SOUT
The E446 features a differential serial input and internal
divide by 8 circuitry to facilitate the cascading of two devices
to build a 8:1 multiplexer. Figure 1 illustrates the architecture
for a 8:1 multiplexer using two E446’s; the timing diagram for
this configuration can be found on the following page. Notice
the serial outputs (SOUT) of the lower order converter feed
the serial inputs of the the higher order device. This feed
through of the serial inputs bounds the upper end of the
frequency of operation. The clock to serial output
propagation delay plus the setup time of the serial input pins
must fit into a single clock period for the cascade architecture
to function properly. Using the worst case values for these
two parameters from the data sheet, TPD CLK to SOUT =
1480ps and tS for SIN = –200ps, yields a minimum period of
1280ps or a clock frequency of 780MHz.
SIN
SIN
Serial
Data
SOUT
SOUT
Q3 Q2 Q1 Q0
Q3 Q2 Q1 Q0
Q7 Q6 Q5 Q4
Q3 Q2 Q1 Q0
Parallel Data
1000ps
600ps
CLOCK
Tpd CLK
to SOUT
1000ps
The clock frequency is somewhat lower than that of a
single converter, to increase this frequency some games can
be played with the clock input of the higher order E446. By
delaying the clock feeding E446A relative to the clock of
E446B the frequency of operation can be increased.
1600ps
Figure 1. Cascaded 8:1 Converter Architecture
CLK
RESET
D0
D0–1
D0–2
D1
D1–1
D1–2
D2
D2–1
D2–2
D3
D3–1
D3–2
D4 (D0B)
D4–1
D4–2
D5 (D1B)
D5–1
D5–2
D6 (D2B)
D6–1
D6–2
D7 (D3B)
D7–1
D7–2
SOUT
D0–1
D1–1
D2–1
D3–1
D4–1
D5–1
D6–1
D7–1
D0–2
CL/4
CL/8
Timing Diagram B. 8:1 Parallel to Serial Conversion
MOTOROLA
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ECLinPS and ECLinPS Lite
DL140 — Rev 4
MC10E446 MC100E446
OUTLINE DIMENSIONS
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776–02
ISSUE D
0.007 (0.180)
B
Y BRK
-N-
T L –M
M
U
0.007 (0.180)
X
G1
M
S
N
T L –M
S
S
N
S
D
Z
-L-
-M-
D
W
28
V
1
C
A
0.007 (0.180)
M
R
0.007 (0.180)
M
T L –M
S
T L –M
S
N
S
N
S
H
S
N
S
0.007 (0.180)
M
T L –M
N
S
S
0.004 (0.100)
G
J
-T-
K
SEATING
PLANE
F
VIEW S
G1
T L –M
S
N
0.007 (0.180)
M
T L –M
S
N
S
VIEW S
S
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIM G1, TRUE POSITION TO BE MEASURED
AT DATUM -T-, SEATING PLANE.
3. DIM R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
ECLinPS and ECLinPS Lite
DL140 — Rev 4
T L –M
K1
E
S
S
VIEW D-D
Z
0.010 (0.250)
0.010 (0.250)
2–5
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.485 0.495
0.485 0.495
0.165 0.180
0.090 0.110
0.013 0.019
0.050 BSC
0.026 0.032
0.020
—
0.025
—
0.450 0.456
0.450 0.456
0.042 0.048
0.042 0.048
0.042 0.056
—
0.020
2°
10°
0.410 0.430
0.040
—
MILLIMETERS
MIN
MAX
12.32 12.57
12.32 12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
—
0.64
—
11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
—
0.50
2°
10°
10.42 10.92
1.02
—
MOTOROLA
MC10E446 MC100E446
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
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ECLinPS and ECLinPS Lite
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