TI1 LM833DR Dual high-speed audio operational amplifier Datasheet

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LM833
SLOS481B – JULY 2010 – REVISED OCTOBER 2014
LM833 Dual High-Speed Audio Operational Amplifier
1 Features
3 Description
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The LM833 device is a dual operational amplifier with
high-performance specifications for use in quality
audio and data-signal applications. Dual amplifiers
are utilized widely in audio circuits optimized for all
preamp and high level stages in PCM and HiFi
systems. The LM833 device is pin-for-pin compatible
with industry-standard dual operation amplifiers. With
addition of a preamplifier, the gain of the power stage
can be greatly reduced to improve performance.
1
Dual-Supply Operation: ±5 V to ±18 V
Low Noise Voltage: 4.5 nV/√Hz
Low Input Offset Voltage: 0.15 mV
Low Total Harmonic Distortion: 0.002%
High Slew Rate: 7 V/μs
High-Gain Bandwidth Product: 16 MHz
High Open-Loop AC Gain: 800 at 20 kHz
Large Output-Voltage Swing: –14.6 V to 14.1 V
Excellent Gain and Phase Margins
Available in 8-Terminal MSOP Package
(3.0 mm x 4.9 mm x 0.65 mm)
Device Information
PART NUMBER
LM833
2 Applications
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PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
PDIP (8)
9.81 mm × 6.35 mm
HiFi Audio System Equipment
Preamplification and Filtering
Set-Top Box
Microphone Preamplifier Circuit
General-Purpose Amplifier Applications
4 Typical Design Example Audio Pre-Amplifier
+VCC
750
47 µF
Audio
Input
0.1 µF
1000
1 µF
47 k
0.0022 µF
2.7 k
OUT1 VCC+
2.7 k
IN1±
0.001 µF
0.1 µF
OUT2
IN1+
IN2±
VCC±
IN2+
10 k
47 µF
750
±VEE
12 V / 1 W
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM833
SLOS481B – JULY 2010 – REVISED OCTOBER 2014
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Typical Design Example Audio Pre-Amplifier.....
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
4
5
5
6
Absolute Maximum Ratings .....................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram ....................................... 13
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 14
9
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Application ................................................. 15
9.3 Typical Application — Reducing Oscillation from
High-Capacitive Loads............................................. 18
10 Power Supply Recommendations ..................... 20
11 Layout................................................................... 20
11.1 Layout Guidelines ................................................. 20
11.2 Layout Example .................................................... 20
12 Device and Documentation Support ................. 22
12.1 Trademarks ........................................................... 22
12.2 Electrostatic Discharge Caution ............................ 22
12.3 Glossary ................................................................ 22
13 Mechanical, Packaging, and Orderable
Information ........................................................... 23
5 Revision History
Changes from Revision A (August 2010) to Revision B
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
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Deleted Ordering Information table. ....................................................................................................................................... 1
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Added Device Information table. ............................................................................................................................................ 1
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Added Pin Functions table. .................................................................................................................................................... 3
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Added Handling Ratings table. ............................................................................................................................................... 4
•
Added Thermal Information table. .......................................................................................................................................... 4
•
Added Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging,
and Orderable Information sections .................................................................................................................................... 20
Changes from Original (July 2010) to Revision A
•
2
Page
Changed data sheet status from Product Preview to Production Data. ................................................................................. 1
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6 Pin Configuration and Functions
D (SOIC), DGK (MSOP), OR P (PDIP) PACKAGE
(TOP VIEW)
OUT1
1
8
VCC+
IN1–
2
7
OUT2
IN1+
3
6
IN2–
VCC–
4
5
IN2+
Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
IN1+
3
Input
Noninverting input
IN1–
2
Input
Inverting Input
IN2+
5
Input
Noninverting input
IN2-
6
Input
Inverting Input
OUT1
1
Output
Output 1
OUT2
7
Output
Output 2
VCC+
8
—
Positive Supply
VCC–
4
—
Negative Supply
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VCC+
Supply voltage (2)
18
V
VCC–
Supply voltage
(2)
–18
V
VCC+ – VCC–
Supply voltage
36
V
VCC+
V
±10
mA
Input voltage, either input (2) (3)
Input current
VCC–
(4)
Duration of output short circuit (5)
TJ
(1)
(2)
(3)
(4)
(5)
Unlimited
Operating virtual junction temperature
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC–.
The magnitude of the input voltage must never exceed the magnitude of the supply voltage.
Excessive input current will flow if a differential input voltage in excess of approximately 0.6 V is applied between the inputs, unless
some limiting resistance is used.
The output may be shorted to ground or either power supply. Temperature and/or supply voltages must be limited to ensure the
maximum dissipation rating is not exceeded.
7.2 Handling Ratings
PARAMETER
Tstg
MIN
MAX
UNIT
°C
Storage temperature range
V(ESD)
(1)
(2)
DEFINITION
–65
150
Human-Body Model (HBM) (1)
0
2.5
Charged-Device Model (CDM) (2)
0
1.5
kV
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
VCC–
VCC+
TA
MIN
MAX
–5
–18
5
18
–40
85
Supply voltage
Operating free-air temperature range
UNIT
V
°C
7.4 Thermal Information
LM833
THERMAL METRIC (1)
D
DGK
P
UNIT
85
°C/W
8 PINS
RθJA
(1)
(2)
(3)
4
Junction-to-ambient thermal resistance (2) (3)
97
172
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA) / θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
The package thermal impedance is calculated in accordance with JESD 51-7.
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7.5 Electrical Characteristics
VCC– = –15 V, VCC+ = 15 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIO
Input offset voltage
VO = 0, RS = 10 Ω, VCM = 0
αVIO
Input offset voltage
temperature coefficient
VO = 0, RS = 10 Ω, VCM = 0
IIB
Input bias current
VO = 0, VCM = 0
IIO
Input offset current
VO = 0, VCM = 0
VICR
Common-mode input voltage
range
ΔVIO = 5 mV, VO = 0
AVD
Large-signal differential
voltage amplification
RL ≥ 2 kΩ, VO = ±10 V
Maximum output voltage
swing
TYP
MAX
0.15
2
TA = –40°C to 85°C
TA = –40°C to 85°C
mV
μV/°C
2
300
750
nA
800
TA = 25°C
25
150
TA = –40°C to 85°C
RL = 10,000 Ω
UNIT
3
TA = –40°C to 85°C
RL = 2000 Ω
VID = ±1 V
TA = 25°C
TA = 25°C
RL = 600 Ω
VOM
MIN
nA
175
±13
±14
TA = 25°C
90
110
TA = –40°C to 85°C
85
VOM+
10.7
VOM–
–11.9
VOM+
13.2
13.8
VOM–
–13.2
–13.7
VOM+
13.5
14.1
VOM–
V
dB
V
–14
–14.6
CMMR
Common-mode rejection ratio
VIN = ±13 V
80
100
dB
kSVR (1)
Supply-voltage rejection ratio
VCC+ = 5 V to 15 V, VCC– = –5 V to –15 V
80
105
dB
15
29
–20
–37
IOS
Output short-circuit current
|VID| = 1 V, Output to GND
ICC
Supply current (per channel)
VO = 0
(1)
Source current
Sink current
TA = 25°C
mA
2.05
2.5
TA = –40°C to 85°C
mA
2.75
Measured with VCC± differentially varied at the same time
7.6 Operating Characteristics
VCC– = –15 V, VCC+ = 15 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SR
Slew rate at unity gain
AVD = 1, VIN = –10 V to 10 V, RL = 2 kΩ, CL = 100 pF
GBW
Gain bandwidth product
f = 100 kHz
B1
Unity gain frequency
Open loop
CL = 0 pF
TYP MAX
UNIT
5
7
V/μs
10
16
MHz
9
MHz
–11
Gm
Gain margin
RL = 2 kΩ
Φm
Phase margin
RL = 2 kΩ
Amp-to-amp isolation
f = 20 Hz to 20 kHz
Power bandwidth
VO = 27 V(PP), RL = 2 kΩ, THD ≤ 1%
THD
Total harmonic distortion
VO = 3 Vrms, AVD = 1, RL = 2 kΩ, f = 20 Hz to 20 kHz
zo
Open-loop output impedance
VO = 0, f = 9 MHz
rid
Differential input resistance
Cid
Differential input capacitance
Vn
In
CL = 100 pF
–6
CL = 0 pF
55
CL = 100 pF
40
dB
degrees
–120
dB
120
kHz
0.002%
37
Ω
VCM = 0
175
kΩ
VCM = 0
12
pF
Equivalent input noise voltage
f = 1 kHz, RS = 100 Ω
4.5
nV/√Hz
Equivalent input noise current
f = 1 kHz
0.5
pA/√Hz
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7.7 Typical Characteristics
0.1 µF
100 kΩ
10 Ω
2.0 kΩ
4.3 kΩ
+
D.U.T.
22 µF
1/2
LM833
Scope
x1
RIN = 1.0 MΩ
−
4.7 µF
100 kΩ
Voltage Gain = 50,000
2.2 µF
24.3 kΩ
110 kΩ
0.1 µF
NOTE: All capacitors are non-polarized.
Figure 1. Voltage Noise Test Circuit (0.1 Hz to 10 Hz)
600
600
VCM = 0 V
VCC+ = 15 V
VCC– = –15 V
TA = 25°C
400
300
200
100
0
-15
6
TA = 25°C
500
IIB – Input Bias Current – nA
IIB – Input Bias Current – nA
500
400
300
200
100
0
-10
-5
0
5
10
5
15
6
7
8
9 10 11 12 13 14 15 16 17 18
VCM – Common Mode Voltage – V
VCC+/–VCC– – Supply Voltage – V
Figure 2. Input Bias Current vs Common-Mode Voltage
Figure 3. Input Bias Current vs Supply Voltage
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Typical Characteristics (continued)
1000
2
VCC– = –15 V
800
VCM = 0 V
VCC+ = 15 V
VCC– = –15 V
1.5
VIO – Input Offset Voltage – mV
IIB – Input Bias Current – nA
VCC+ = 15 V
900
700
600
500
400
300
200
VCM = 0 V
1
0.5
0
-0.5
-1
-1.5
100
0
-55 -35 -15
5
25
45
65
85
-2
-55 -35 -15
105 125
5
25
45
65
85
105 125
TA – Temperature – °C
TA – Temperature – °C
Figure 4. Input Bias Current vs Temperature
Figure 5. Input Offset Voltage vs Temperature
1.4
0
1.2
-0.2
VCC– = -3 V to -15 V
D VIO = 5 mV
-0.4
VO = 0 V
Input Common-Mode Voltage High
Proximity to V CC+ – V
Input Common-Mode Voltage Low
Proximity to V CC– – V
VCC+ = 3 V to 15 V
1
0.8
0.6
VCC+ = 3 V to 15 V
0.4
VCC– = -3 V to -15 V
D
è VIO = 5 mV
0.2
VO = 0 V
0
-55
-25
5
35
65
95
-0.6
-0.8
-1
-1.2
-1.4
-55
125
-25
TA – Temperature – °C
Figure 6. Input Common-Mode Voltage Low Proximity
to VCC– vs Temperature
35
65
95
125
Figure 7. Input Common-Mode Voltage High Proximity
to VCC+ vs Temperature
10
0
-1
9
TA = 125°C
-2
8
TA = 25°C
-3
Output Saturation Voltage
Proximity to V CC– – V
Output Saturation Voltage
Proximity to V CC+ – V
5
TA – Temperature – °C
TA = –55°C
-4
-5
-6
-7
-8
7
6
5
TA = 125°C
4
TA = 25°C
3
TA = –55°C
2
-9
1
-10
0
0.5
1
1.5
2
2.5
3
3.5
4
0
4.5
0
kW
RL – Load Resistance – kh
0.5
1
1.5
2
2.5
3
3.5
4
4.5
kW
RL – Load Resistance – k@
Figure 8. Output Saturation Voltage Proximity to VCC+
vs Load Resistance
Figure 9. Output Saturation Voltage Proximity to VCC–
vs Load Resistance
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Typical Characteristics (continued)
10
70
9
VCC– = –15 V
60
VID = 1 V
8
ICC – Supply Current – mA
IOS – Output Short-Circuit Current – mA
VCC+ = 15 V
50
40
Source
Sink
30
VCM = 0 V
RL = High Impedance
VO = 0 V
7
6
VCC± = ±15 V
5
4
VCC± = ±10 V
3
VCC± = ±5 V
2
20
1
10
-55
-35
-15
5
25
45
65
85
0
-55
105 125
-35
-15
TA – Temperature – °C
Figure 10. Output Short-Circuit Current vs Temperature
100
80
45
65
85
105 125
120
VCC+ = 15 V
VCC– = –15 V
TA = 25°C
110
100
90
80
60
PSRR – dB
CMMR – dB
70
25
Figure 11. Supply Current vs Temperature
VCC+ = 15 V
VCC– = –15 V
VCM = 0 V
DVCM = ±1.5 V
TA = 25°C
90
5
TA – Temperature – °C
50
40
70
T3P
60
50
T3N
40
30
30
20
20
10
10
0
100
10k
100k 1.0E+06
10M
1k
1M
1.0E+02
1.0E+03
1.0E+04
1.0E+05
1.0E+07
0
1.0E+02
1.0E+03
1.0E+04
1.0E+05
1.0E+07
100
10k
100k 1.0E+06
10M
1k
1M
f – Frequency – Hz
f – Frequency – Hz
Figure 12. CMRR vs Frequency
Figure 13. PSSR vs Frequency
30
GBW – Gain Bandwidth Product – MHz
GBW – Gaind Bandwidth Product – MHz
30
25
20
15
10
5
0
5
6
7
8
20
15
10
5
0
-55
9 10 11 12 13 14 15 16 17 18
VCC+/–VCC– – Supply Voltage – V
-35
-15
5
25
45
65
85
105
125
TA – Temperature – °C
Figure 14. Gain Bandwidth Product vs Supply Voltage
8
25
Figure 15. Gain Bandwidth Product vs Temperature
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Typical Characteristics (continued)
20
30
VCC+ = 15 V
VCC– = –15 V
RL = 2 kW
AV = 1
THD < 1%
TA = 25°C
15
25
VO – Output Voltage – V
VO – Output Voltage – V
RL = 10 kW
10
RL = 2 kW
5
0
-5
RL = 10 kW
-10
20
15
10
RL = 2 kW
5
-15
-20
5
6
7
8
0
100
10
10k
100k 1.E+06
10M
1k
1M
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+07
9 10 11 12 13 14 15 16 17 18
VCC+/–VCC– – Supply Voltage – V
f – Frequency – Hz
Figure 16. Output Voltage vs Supply Voltage
Figure 17. Output Voltage vs Frequency
120
110
115
AV – Open-Loop Gain – dB
AV – Open-Loop Gain – dB
105
100
95
90
RL = 2 kW
f < 10 Hz
DVO = 2/3(VCC+ – VCC–)
TA = 25°C
85
6
7
8
105
100
95
90
85
80
5
110
RL = 2 kW
f < 10 Hz
DVO = 2/3(VCC+ – VCC–)
TA = 25°C
80
-55
9 10 11 12 13 14 15 16 17 18
-35 -15
5
25
45
65
85
105 125
VCC+/–VCC– – Supply Voltage – V
TA – Temperature – °C
Figure 18. Open-Loop Gain vs Supply Voltage
Figure 19. Open-Loop Gain vs Temperature
200
50
VCC+ = 15 V
40
35
VCC– = –15 V
190
VO = 1 Vrms
180
TA = 25°C
Crosstalk Rejection – dB
ZO – Output Impedance – W
45
30
25
20
15
AV = 1000
10
AV = 100
AV = 10
160
150
140
130
120
AV = 1
5
0
1.0E+03
1k
170
Drive Channel
VCC+ = 15 V
VCC– = –15 V
RL = 2 kW
VO = 20 VPP
TA = 25°C
110
1.0E+04
10k
1.0E+05
100k
1.0E+06
1M
100
1.E+01
10
1.0E+07
10M
f – Frequency – Hz
1.E+02
100
1.E+03
1k
1.E+04
10k
1.E+05
100k
f – Frequency – Hz
Figure 20. Output Impedance vs Frequency
Figure 21. Crosstalk Rejection vs Frequency
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Typical Characteristics (continued)
AV = 1000
0.01
0.001
0.1
AV = 100
0.01
AV = 10
0.001
VCC+ = 15 V
VCC– = –15 V
f = 2 kHz
RL = 2 kW
TA = 25°C
AV = 1
0.0001
0.0001
10
1.E+01
100
1.E+02
1k
1.E+03
10k
1.E+04
0
100k
1.E+05
1
2
f – Frequency – Hz
Figure 22. Total Harmonic Distortion vs Frequency
10
9
9
7
Rising Edge
6
5
4 DV = 2/3(V – V )
IN
CC+
CC–
AV = 1
3 RL = 2 kW
TA = 25°C
2
5 6 7 8 9 10 11 12 13 14 15 16 17 18
SR – Slew Rate – V/µs
SR – Slew Rate – V/µs
8
Falling Edge
VCC+ = 15 V
VCC– = –15 V
DVIN = 20 V
AV = 1
RL = 2 kW
4
5
1.E+04
10k
Gain Margin – dB
-90
Gain, TA = 125°C
45
65
85
VCC+ = 15 V
VCC– = –15 V
VO = 0 V
1.E+06
1M
125
10
40
6
Phase, TA = 125°C
50
60
Phase, TA = 25°C
70
0
-180
1.E+07
10M
0
30
Phase, TA = –55°C
1.E+05
100k
105
20
Gain, TA = –55°C
3
-135
VCC+ = 15 V
VCC– = –15 V
RL = 2 kW
TA = 25°C
25
9
-45
Gain
0
1.E+03
1k
1
10
100
80
1000
Cout – Output Load Capacitance – pF
f – Frequency – Hz
Figure 26. Gain and Phase vs Frequency
10
-15
Figure 25. Slew Rate vs Temperature
12
Phase Shift – deg
Gain – dB
10
-35
TA – Temperature – °C
30
20
9
5
Gain, TA = 25°C
40
8
Rising Edge
70
50
7
6
2
-55
0
60
6
7
3
Figure 24. Slew Rate vs Supply Voltage
Phase
5
Falling Edge
VCC+/–VCC– – Supply Voltage – V
80
4
Figure 23. Total Harmonic Distortion vs Output Voltage
10
8
3
VO – Output Voltage – Vrms
Phase Margin – deg
0.1
1
VCC+ = 15 V
VCC– = –15 V
VO = 1 Vrms
AV = 1
RL = 2 kW
TA = 25°C
THD – Total Harmonic Distortion – %
THD – Total Harmonic Distortion – %
1
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Figure 27. Gain and Phase Margin
vs Output Load Capacitance
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Typical Characteristics (continued)
80
VCC+ = 15 V
VCC– = –15 V
VCC– = –15 V
VIN = 100 mVPP
TA = 25°C
Overshoot – %
70
60
50
40
TA = 125°C
30
20
10
VCC+ = 15 V
nV/ÖHz
Input Voltage Noise – nV/rtHz
90
TA = 25°C
10
pA/ÖHz
Input Current Noise – pA/rtHz
100
100
1
Input Voltage Noise
Input Current Noise
10
TA = –55°C
1
10
100
1000
10
100
Cout – Output Load Capacitance – pF
1k
1000
10k
10000
0.1
100k
100000
f – Frequency – Hz
Figure 28. Overshoot vs Output Load Capacitance
Figure 29. Input Voltage and Current Noise vs Frequency
16
1000
64
60
VCC– = –15 V
f = 1 Hz
TA = 25°C
14
56
52
12
48
Phase Margin
100
Gain Margin – dB
nV/ÖHz
Input Referred Noise Voltage – nV/rtHz
VCC+ = 15 V
10
44
10
40
Gain Margin
36
8
32
28
6
4
2
VCC+ = 15 V
24
VCC– = –15 V
20
AV = 100
16
VO = 0 V
12
TA = 25°C
8
Phase Margin – deg
0
4
0
1.E+02
100
1.E+03
1k
1.E+04
10k
1.E+05
100k
1.E+06
1M
1
00
Figure 30. Input Referred Noise Voltage
vs Source Resistance
55
45
0
45
-10
35
VCC+ = 15 V
VCC– = –15 V
AV = 1
RL = 2 kW
CL = 100 pF
TA = 25°C
-20
-30
5
-40
-5
-15
-2
2
6
10
14
18
VO – Output Voltage – V
10
VI – Input Voltage – V
VO – Output Voltage – V
Input
Output
101k
00
0
1010k
0 0 0 10100k
0000
Figure 31. Gain and Phase Margin
vs Differential Source Resistance
55
15
100
10
0
RSD – Differential Source Resistance – W
è
RS – Source Resistance – W
è
25
10
10
Input
10
0
35
25
15
-10
VCC+ = 15 V
VCC– = –15 V
AV = –1
RL = 2 kW
CL = 100 pF
TA = 25°C
Output
-20
-30
5
-40
-50
-5
-50
-60
-15
22
-60
-2
Time – µs
VI – Input Voltage – V
1
1.E+01
10
2
6
10
14
18
22
Time – µs
Figure 32. Large Signal Transient Response (AV = 1)
Figure 33. Large Signal Transient Response (AV = –1)
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Typical Characteristics (continued)
0.6
0.2
400
0.5
0.1
300
-0.1
0.3
VCC+ = 15 V
VCC– = –15 V
AV = 1
RL = 2 kW
CL = 100 pF
TA = 25°C
0.2
0.1
-0.2
-0.3
-0.4
0
Input Voltage Noise – nV
Input
VI – Input Voltage – V
VO – Output Voltage – V
200
0.0
0.4
Output
-0.2
-0.5
0.5
1.0
-200
T3
VCC+ = 15 V
-300
VCC– = –15 V
BW = 0.1 Hz to 10 Hz
TA = 25°C
-5
1.5
-4
-3
-2
-1
0
1
2
3
4
5
Time – s
Time – µs
Figure 34. Small Signal Transient Response
12
-100
-500
-0.6
0.0
0
-400
-0.5
-0.1
100
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Figure 35. Low-Frequency Noise
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8 Detailed Description
8.1 Overview
The LM833 device is a dual operational amplifier with high-performance specifications for use in quality audio
and data-signal applications. This device operates over a wide range of single- and dual-supply voltage with low
noise, high-gain bandwidth, and high slew rate. Additional features include low total harmonic distortion, excellent
phase and gain margins, large output voltage swing with no deadband crossover distortions, and symmetrical
sink/source performance. The dual amplifiers are utilized widely in circuit of audio optimized for all preamp and
high-level stages in PCM and HiFi systems. The LM833 device is pin-for-pin compatible with industry-standard
dual operation amplifiers' pin assignments. With addition of a preamplifier, the gain of the power stage can be
greatly reduced to improve performance.
8.2 Functional Block Diagram
VCC
INí
IN+
VOUT
VEE
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8.3 Feature Description
8.3.1 Operating Voltage
The LM833 operational amplifier is fully specified and ensured for operation from ±5 V to ±18 V. In addition,
many specifications apply from –40°C to 85°C. Parameters that vary significantly with operating voltages or
temperature are shown in Absolute Maximum Ratings .
8.3.2 High Gain Bandwidth Product
Gain bandwidth product is found by multiplying the measured bandwidth of an amplifier by the gain at which that
bandwidth was measured. The LM833 has a high gain bandwidth of 16 MHz which stays relatively stable over a
wide range of supply voltages. Parameters that vary significantly with temperature are shown in Figure 14.
8.3.3 Low Total Harmonic Distortion
Harmonic distortions to an audio signal are created by electronic components in a circuit. Total harmonic
distortion (THD) is a measure of harmonic distortions accumulated by a signal in an audio system. The LM833
has a very low THD of 0.002% meaning that the LM833 will add little harmonic distortion when used in audio
signal applications. More specific characteristics are shown in Figure 22.
8.4 Device Functional Modes
The LM833 is powered on when the supply is connected. It can be operated as a single supply operational
amplifier or dual supply amplifier depending on the application.
14
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
An application of the LM833 is the two stage RIAA Phono Preamplifier. A primary task of the phono preamplifier
is to provide gain (usually 30 to 40 dB at 1 kHz) and accurate amplitude and phase equalization to the signal
from a moving magnet or a moving coil cartridge. In addition to the amplification and equalization functions, the
phono preamp must not add significant noise or distortion to the signal from the cartridge. The circuit shown in
Figure 36 uses two amplifiers, fulfills these qualifications, and has greatly improved performance over a singleamplifier design.
9.2 Typical Application
VIN
47 k
CP
½ LM833
3 +
2
1
C4
2 PF
R3
2.37
4
C3
33 nF
-15 V
R1
80.6 k
15 V
R6
54.9 k
R2
8.45 k
R4
2k
R0
499
5 + 8
6
7
VOUT
½ LM833
R5
4.3 k
C1
39 nF
C0
200 PF
Figure 36. RIAA Phono Preamplifier
9.2.1 Design Requirements
• Supply Voltage = ±15 V
• Low-Frequency −3 dB corner of the first amplifier (f0) > 20 Hz (below audible range)
• Low-Frequency −3 dB corner of the second stage (fL) = 20.2 Hz
9.2.2 Detailed Design Procedure
9.2.2.1 Introduction to Design Method
Equation 1 through Equation 5 show the design equations for the preamplifier.
R1 = 8.058 R0A1
where
•
A1 is the 1 kHz voltage gain of the first amplifier
(1)
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Typical Application (continued)
C1 =
3.18 ´10-3
R1
(2)
R
R 2 = 1 - R0
9
C3 = 7.5 ´10-5
(3)
(R3 + R6 ) 7.5 ´10
=
R3 R 6
RP
-5
(4)
1
C4 =
2 p f L (R3 + R6 )
where
fL is the low-frequency −3 dB corner of the second stage
•
(5)
For standard RIAA preamplifiers, fL should be kept well below the audible frequency range. If the preamplifier is
to follow the IEC recommendation (IEC Publication 98, Amendment #4), fL should equal 20.2 Hz.
R
A V2 = 1 + 5
R4
where
•
AV2 is the voltage gain of the second amplifier
(6)
1
2 p f0 R0
C0 »
where
•
f0 is the low-frequency −3 dB corner of the first amplifier
(7)
This should be kept well below the audible frequency range.
A design procedure is shown below with an illustrative example using 1% tolerance E96 components for close
conformance to the ideal RIAA curve. Because 1% tolerance capacitors are often difficult to find except in 5% or
10% standard values, the design procedure calls for re-calculation of a few component values so that standard
capacitor values can be used.
9.2.2.2 RIAA Phono Preamplifier Design Procedure
A design procedure is shown below with an illustrative example using 1% tolerance E96 components for close
conformance to the ideal RIAA curve. Since 1% tolerance capacitors are often difficult to find except in 5% or
10% standard values, the design procedure calls for re-calculation of a few component values so that standard
capacitor values can be used.
Choose R0. R0 should be small for minimum noise contribution, but not so small that the feedback network
excessively loads the amplifier.
Example: Choose R0 = 500
Choose 1 kHz gain, AV1 of first amplifier. This will typically be around 20 dB to 30 dB.
Example: Choose AV1 = 26 dB = 20
Calculate R1 = 8.058 R0AV1
Example: R1 = 8.058 × 500 × 20 = 80.58 k
Calculate C1 =
Example : C1 =
3.18 ´10-3
R1
3.18 ´10-3
8.058 ´104
(8)
= 0.03946 mF
(9)
If C1 is not a convenient value, choose the nearest convenient value and calculate a new R1 from Equation 10.
16
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Typical Application (continued)
R1 =
3.18 ´10-3
C1
(10)
Example: New C1 = 0.039 μF.
New R1 =
3.18 ´10-3
3.9 ´10-8
= 81.54k
Use R1 = 80.6k
(11)
Calculate a new value for R0 from Equation 12.
R1
R0 =
8.058 A V1
(12)
4
Example: New R0 =
8.06 ´10
= 498.8
8.058 ´ 20
(13)
Use R0 = 499.
Calculate R2 =
R1
- R0
9
8.06 ´104
- 499 = 8456.56
9
Example : R2 =
(14)
Use R2 = 8.45 K.
Choose a convenient value for C3 in the range from 0.01 μF to 0.05 μF.
Example: C3 = 0.033 μF
Calculate RP =
Example: RP =
7.5 ´10-5
C3
7.5 ´10-5
3.3 ´10-8
= 2.273k
(15)
Choose a standard value for R3 that is slightly larger than RP.
Example: R3 = 2.37 k
Calculate R6 from 1 / R6 = 1 / RP − 1 / R3
Example: R6 = 55.36 k
Use 54.9 k
Calculate C4 for low-frequency rolloff below 1 Hz from design Equation 5.
Example: C4 = 2 μF. Use a good quality mylar, polystyrene, or polypropylene.
Choose gain of second amplifier.
Example: The 1 kHz gain up to the input of the second amplifier is about 26 dB for this example. For an
overall 1 kHz gain equal to about 36 dB we choose:
AV2 = 10 dB = 3.16
Choose value for R4.
Example: R4 = 2 k
Calculate R5 = (AV2 − 1) R4
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Typical Application (continued)
Example: R5 = 4.32 k
Use R5 = 4.3 k
Calculate C0 for low-frequency rolloff below 1 Hz from design Equation 7.
Example: C0 = 200 μF
9.2.3 Application Curves for Output Characteristics
The maximum observed error for the prototype was 0.1 dB.
Figure 37. Deviation from Ideal RIAA Response for
Circuit of Figure 36 Using 1% Resistors
The lower curve is for an output level of 300 mVrms and the upper curve is for an output level of 1 Vrms.
Figure 38. THD of Circuit in Figure 36 as a Function of Frequency
9.3 Typical Application — Reducing Oscillation from High-Capacitive Loads
While all the previously stated operating characteristics are specified with 100-pF load capacitance, the LM833
device can drive higher-capacitance loads. However, as the load capacitance increases, the resulting response
pole occurs at lower frequencies, causing ringing, peaking, or oscillation. The value of the load capacitance at
which oscillation occurs varies from lot-to-lot. If an application appears to be sensitive to oscillation due to load
capacitance, adding a small resistance in series with the load should alleviate the problem (see Figure 39).
9.3.1 Test Schematic
15 V
RO
VO
5V
–5 V
–15 V
CL
RL = 2 kΩ
Figure 39. Capacitive Load Testing Circuit
18
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Typical Application — Reducing Oscillation from High-Capacitive Loads (continued)
9.3.2 Output Characteristics
Figure 40 through Figure 45 demonstrate the effect adding this small resistance has on the ringing in the output
signal.
Maximum capacitance
before oscillation = 590 pF
0.25 V per Division
0.25 V per Division
Maximum capacitance
before oscillation = 380 pF
250 ns per Division
250 ns per Division
Figure 40. Pulse Response
(RL = 600 Ω, CL = 380 pF)
Figure 41. Pulse Response
(RL = 2 kΩ, CL = 560 pF)
0.25 V per Division
0.25 V per Division
Maximum capacitance
before oscillation = 590 pF
250 ns per Division
250 ns per Division
Figure 42. Pulse Response
(RL = 10 kΩ, CL = 590 pF)
0.25 V per Division
0.25 V per Division
Figure 43. Pulse Response
(RO = 0 Ω, CO = 1000 pF,
RL = 2 kΩ)
250 ns per Division
250 ns per Division
Figure 44. Pulse Response
(RO = 4 Ω, CO = 1000 pF,
RL = 2 kΩ)
Figure 45. Pulse Response
(RO = 35 Ω, CO = 1000 pF,
RL = 2 kΩ)
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10 Power Supply Recommendations
The LM833 is specified for operation from 10 to 36 V (±5 to ±18 V); many specifications apply from –40°C to
85°C. The Typical Characteristics section presents parameters that can exhibit significant variance with regard to
operating voltage or temperature.
CAUTION
Supply voltages larger than 36 V can permanently damage the device (see Absolute
Maximum Ratings ).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
section.
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the operational
amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to
Circuit Board Layout Techniques, (SLOA089).
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in Layout Example.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
11.2 Layout Example
VIN
RIN
RG
+
VOUT
RF
Figure 46. Operational Amplifier Schematic for Noninverting Configuration
20
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Layout Example (continued)
Place components close to
device and to each other to
reduce parasitic errors
Run the input traces as far
away from the supply lines
as possible
VS+
RF
OUT1
VCC+
GND
IN1í
OUT2
VIN
IN1+
IN2í
VCCí
IN2+
RG
GND
RIN
Use low-ESR, ceramic
bypass capacitor
Only needed for
dual-supply
operation
GND
VS(or GND for single supply)
Ground (GND) plane on another layer
Figure 47. Operational Amplifier Board Layout for Noninverting Configuration
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12 Device and Documentation Support
12.1 Trademarks
All trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
22
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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21-Jan-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM833D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LM833
LM833DGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
RSU
LM833DGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
RSU
LM833DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LM833
LM833P
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
LM833P
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
21-Jan-2014
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Jan-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
LM833DGKR
VSSOP
DGK
8
LM833DGKT
VSSOP
DGK
LM833DR
SOIC
D
LM833DR
SOIC
D
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2500
330.0
12.4
5.3
3.3
1.3
8.0
12.0
Q1
8
250
180.0
12.4
5.3
3.3
1.3
8.0
12.0
Q1
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Jan-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM833DGKR
VSSOP
DGK
8
2500
346.0
346.0
35.0
LM833DGKT
VSSOP
DGK
8
250
203.0
203.0
35.0
LM833DR
SOIC
D
8
2500
367.0
367.0
35.0
LM833DR
SOIC
D
8
2500
340.5
338.1
20.6
Pack Materials-Page 2
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
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