19-0393; Rev 0; 5/95 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs ____________________________Features ♦ ♦ ♦ ♦ ♦ ________________________Applications ________________Functional Diagram Single +5V Supply Simple 2-Wire Serial Interface I2C Compatible Output Buffer Amplifiers Swing Rail-to-Rail Space-Saving 8-pin DIP/SO Packages (MAX517/MAX518) ♦ Reference Input Range Includes Both Supply Rails (MAX517/MAX519) ♦ Power-On Reset Clears All Latches ♦ 4µA Power-Down Mode ______________Ordering Information TEMP. RANGE MAX517ACPA 0°C to +70°C 8 Plastic DIP 1 MAX517BCPA MAX517ACSA MAX517BCSA 0°C to +70°C 0°C to +70°C 0°C to +70°C 8 Plastic DIP 8 SO 8 SO 1.5 1 1.5 MAX517BC/D 0°C to +70°C Dice* 1.5 Ordering Information continued at end of data sheet. *Dice are specified at TA = +25°C, DC parameters only. **Contact factory for availability and processing to MIL-STD-883. Minimum Component Analog Systems Digital Offset/Gain Adjustment Industrial Process Control Automatic Test Equipment Programmable Attenuators VDD 7 REF OUTPUT LATCH 0 DAC0 INPUT LATCH 1 OUTPUT LATCH 1 DAC1 8 OUT1 (REF0) 7 VDD 6 AD0 5 AD1 SCL 3 MAX517 MAX518 SDA 4 SCL SDA 8 8-BIT SHIFT REGISTER ADDRESS COMPARATOR DECODE START/STOP DETECTOR OUT1 MAX518 3 4 DIP/SO ( ) ARE FOR MAX517 Pin Configurations continued at end of data sheet. OUT0 REF TOP VIEW GND 2 1 INPUT LATCH 0 _________________Pin Configurations OUT0 1 PIN-PACKAGE TUE (LSB) PART 6 AD0 5 AD1 2 GND ________________________________________________________________ Maxim Integrated Products Call toll free 1-800-998-8800 for free samples or literature. 1 MAX517/MAX518/MAX519 _______________General Description The MAX517/MAX518/MAX519 are 8-bit voltage output digital-to-analog converters (DACs) with a simple 2-wire serial interface that allows communication between multiple devices. They operate from a single 5V supply and their internal precision buffers allow the DAC outputs to swing rail-to-rail. The MAX517 is a single DAC and the MAX518/MAX519 are dual DACs. The MAX518 uses the supply voltage as the reference for both DACs. The MAX517 has a reference input for its single DAC and each of the MAX519’s two DACs has its own reference input. The MAX517/MAX518/MAX519 feature a serial interface and internal software protocol, allowing communication at data rates up to 400kbps. The interface, combined with the double-buffered input configuration, allows the DAC registers of the dual devices to be updated individually or simultaneously. In addition, the devices can be put into a low-power shutdown mode that reduces supply current to 4µA. Power-on reset ensures the DAC outputs are at 0V when power is initially applied. The MAX517/MAX518 are available in space-saving 8pin DIP and SO packages. The MAX519 comes in 16pin DIP and SO packages. MAX517/MAX518/MAX519 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V OUT_ ..........................................................-0.3V to (VDD + 0.3V) REF_ (MAX517, MAX519)...........................-0.3V to (VDD + 0.3V) AD_.............................................................-0.3V to (VDD + 0.3V) SCL, SDA to GND.....................................................-0.3V to +6V Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70°C) 8-Pin Plastic DIP (derate 9.09mW/°C above +70°C) ...727mW 8-Pin SO (derate 5.88mW/°C above +70°C)................471mW 8-Pin CERDIP (derate 8.00mW/°C above +70°C)........640mW 16-Pin Plastic DIP (derate 10.53mW/°C above +70°C)..842mW 16-Pin Narrow SO (derate 8.70mW/°C above +70°C) ...696mW 16-Pin CERDIP (derate 10.00mW/°C above +70°C) ......800mW Operating Temperature Ranges MAX51_C_ _ .......................................................0°C to +70°C MAX51_E_ _.....................................................-40°C to +85°C MAX51_MJB ..................................................-55°C to +125°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 5V ±10%, VREF_ = 4V (MAX517, MAX519), RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC ACCURACY Resolution 8 Total Unadjusted Error (Note 1) TUE Differential Nonlinearity (Note 1) DNL Zero-Code Error Zero-Code-Error Supply Rejection Zero-Code-Error Temperature Coefficient Full-Scale Error Full-Scale-Error Supply Rejection Full-Scale-Error Temperature Coefficient 2 ZCE Bits MAX51 _A ±1 MAX51 _B ±1.5 Guaranteed monotonic Code = 00 hex Code = 00 hex 18 MAX51 _E 20 MAX51 _BM 20 MAX51 _C ±1 MAX51 _E ±1 MAX51 _BM ±1 Code = 00 hex Code = FF hex, MAX518 unloaded MAX517, MAX519 Code = FF hex VDD = +5V ±10% Code = FF hex ±1 MAX51 _C ±10 MAX51 _E ±20 MAX51 _BM ±20 ±1 ±1 MAX51 _BM ±1 ±10 _______________________________________________________________________________________ mV µV/°C ±18 MAX51 _C LSB mV MAX51 _C MAX51 _E LSB mV mV µV/°C 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs (VDD = 5V ±10%, VREF_ = 4V (MAX517, MAX519), RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS REFERENCE INPUTS (MAX517, MAX519) Input Voltage Range Input Resistance 0 RIN Code = 55 hex (Note 2) 16 VDD 24 V kΩ Input Current Power-down mode Input Capacitance Code = FF hex (Note 3) 30 ±10 µA pF Channel-to-Channel Isolation (MAX519) (Note 4) -60 dB AC Feedthrough (Note 5) -70 dB DAC OUTPUTS Full-Scale Output Voltage 0 Output Load Regulation Output Leakage Current VDD OUT_ = 4V, 0mA to 2.5mA 0.25 MAX51 _C/E, REF_ = VDD (MAX517, MAX519), code = FF hex, 0µA to 500µA 1.5 MAX51 _M, REF_ = VDD (MAX517, MAX519), code = FF hex, 0µA to 500µA 2.0 V LSB OUT_ = 0V to VDD, power-down mode ±10 µA DIGITAL INPUTS SCL, SDA Input High Voltage VIH Input Low Voltage VIL Input Leakage Current IIN Input Hysteresis 0.7VDD 0V ≤ VIN ≤ VDD VHYST Input Capacitance CIN V 0.3VDD V ±10 µA 10 pF 0.05VDD V (Note 6) DIGITAL INPUTS AD0, AD1, AD2, AD3 Input High Voltage VIH Input Low Voltage VIL Input Leakage Current IIN 2.4 V 0.8 V VIN = 0V to VDD ±10 µA ISINK = 3mA 0.4 ISINK = 6mA 0.6 VIN = 0V to VDD ±10 µA 10 pF DIGITAL OUTPUT SDA (Note 7) Output Low Voltage Three-State Leakage Current Three-State Output Capacitance VOL IL COUT (Note 6) V DYNAMIC PERFORMANCE MAX51 _C MAX51 _E MAX51 _M 2.0 1.4 1.0 Voltage Output Slew Rate Positive and negative V/µs Output Settling Time To 1/2 LSB, 10kΩ and 100pF load (Note 8) 6 µs Digital Feedthrough Code = 00 hex, all digital inputs from 0V to VDD 5 nV-s _______________________________________________________________________________________ 3 MAX517/MAX518/MAX519 ELECTRICAL CHARACTERISTICS (continued) MAX517/MAX518/MAX519 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs ELECTRICAL CHARACTERISTICS (continued) (VDD = 5V ±10%, VREF_ = 4V (MAX517, MAX519), RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25°C.) PARAMETER SYMBOL Digital-Analog Glitch Impulse Signal to Noise + Distortion Ratio (MAX517, MAX519) SINAD Multiplying Bandwidth (MAX517, MAX519) CONDITIONS MIN TYP MAX UNITS Code 128 to 127 VREF_ = 4Vp-p at 1kHz, VDD = 5V, Code = FF hex 12 nV-s 87 dB VREF_ = 4Vp-p, 3dB bandwidth 1 MHz 60 µVRMS Wideband Amplifier Noise POWER REQUIREMENTS Supply Voltage VDD Supply Current IDD 4.5 Normal mode, output(s) unloaded, all digital inputs at 0V or VDD 5.5 MAX517C 1.5 3.0 MAX517E/M 1.5 3.5 MAX518C, MAX519C 2.5 5 MAX518E/M, MAX519E/M 2.5 6 4 20 Power-down mode V mA µA TIMING CHARACTERISTICS (VDD = 5V ±10%, TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25°C.) PARAMETER Serial Clock Frequency Bus Free Time Between a STOP and a START Condition Hold Time, (Repeated) Start Condition SYMBOL CONDITIONS MIN TYP MAX UNITS 400 kHz fSCL 0 tBUF 1.3 µs tHD, STA 0.6 µs Low Period of the SCL Clock tLOW 1.3 µs High Period of the SCL Clock tHIGH 0.6 µs Setup Time for a Repeated START Condition tSU, STA 0.6 Data Hold Time tHD, DAT Data Setup Time tSU, DAT (Note 9) 0 µs 0.9 100 µs ns Rise Time of Both SDA and SCL Signals, Receiving tR (Note 10) 20 + 0.1Cb 300 ns Fall Time of Both SDA and SCL Signals, Receiving tF (Note 10) 20 + 0.1Cb 300 ns Fall Time of SDA Transmitting (Note 7) tF ISINK ≤ 6mA (Note 10) 20 + 0.1Cb 250 ns 400 pF 50 ns Setup Time for STOP Condition tSU, STO Capacitive Load for Each Bus Line Cb Pulse Width of Spike Suppressed tSP 0.6 (Notes 6, 11) 0 µs Note 1: For the MAX518 (full-scale = VDD) the last three codes are excluded from the TUE and DNL specifications, due to the limited output swing when loaded with 10kΩ to GND. Note 2: Input resistance is code dependent. The lowest input resistance occurs at code = 55 hex. Note 3: Input capacitance is code dependent. The highest input capacitance occurs at code FF hex. Note 4: VREF_ = 4Vp-p, 10kHz. Channel-to-channel isolation is measured by setting the code of one DAC to FF hex and setting the code of all other DACs to 00 hex. Note 5: VREF_ = 4Vp-p, 10kHz, DAC code = 00 hex. Note 6: Guaranteed by design. Note 7: I2C compatible mode. Note 8: Output settling time is measured by taking the code from 00 hex to FF hex, and from FF hex to 00 hex. Note 9: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to bridge the undefined region of SCL’s falling edge. Note 10: Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3VDD and 0.7VDD. Note 11: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns. 4 _______________________________________________________________________________________ 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs 8 4 2 3.5 4.0 0 0.5 MAX518 SUPPLY CURRENT vs. TEMPERATURE DAC CODE = 1B HEX 1.5 DAC CODE = FF HEX 1.0 1.5 -55 -35 -15 5 25 45 65 25 45 65 85 105 125 MAX518 SUPPLY CURRENT vs. DAC CODE SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE VDD = 5.5V BOTH DACS SET 2.0 1.5 1.0 0 0 -55 -35 -15 5 2.0 0.5 DAC CODE = 00 HEX 0.5 MAX517, MAX519 DAC CODE = 00 HEX 6 VDD = 5.5V ALL DIGITAL INPUTS to VDD 5 4 3 2 1 0 32 0 85 105 125 64 96 128 160 192 224 256 -55 -35 -15 5 25 45 65 85 105 125 DAC CODE (DECIMAL) TEMPERATURE (°C) MAX517/MAX519 SUPPLY CURRENT vs. REFERENCE VOLTAGE MAX517/MAX519 REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE POSITIVE FULL-SCALE STEP RESPONSE 2.5 VDD = 5V DAC CODE(S) FF HEX MAX519 1.0 0 RELATIVE OUTPUT (dB) 2.0 MAX517-08 TEMPERATURE (°C) MAX517 -4 -12 -16 0 0.5 1 1.5 2 2.5 3 3.5 4 REFERENCE VOLTAGE (V) 4.5 5 OUT0 1V/div 4VP-P SINE 2VP-P SINE 1VP-P SINE 0.5VP-P SINE -8 0.5 0 MAX517-09 SUPPLY CURRENT (mA) 2.5 2.0 MAX517, DAC CODE = FF HEX TEMPERATURE (°C) 2.5 SUPPLY CURRENT (mA) VDD = 5.5V AD0, AD1 = VDD 3.0 1.0 3.0 MAX517-04 3.5 1.0 OUTPUT SINK CURRENT (mA) SHUTDOWN SUPPLY CURRENT (µA) 2.5 3.0 MAX517-05 1.5 2.0 MAX519, DAC CODE = FF HEX 1.5 0 0 0.5 1.0 2.0 0.5 OUTPUT SOURCE CURRENT (mA) SUPPLY CURRENT (mA) MAX517-02 4 2 0 VDD = 5.5V REF_ INPUTS = 0.6V ALL DIGITAL INPUTS to VDD 2.5 6 0 1.5 3.0 MAX517-07 6 VDD = VREF = 5V DAC CODE = 00 HEX LOAD to VDD SUPPLY CURRENT (mA) 8 10 MAX517-01 VDD = VREF = 5V DAC CODE = FF HEX LOAD TO AGND ZERO-CODE ERROR (LSB) FULL-SCALE ERROR (LSB) 10 MAX517/MAX519 SUPPLY CURRENT vs. TEMPERATURE ZERO-CODE ERROR vs. SINK CURRENT MAX517-03 FULL-SCALE ERROR vs. SOURCE CURRENT (VREF = VDD) MAX517/MAX518/MAX519 __________________________________________Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) VDD = 5V VREF = SINE WAVE CENTERED AT 2.5V 1k 10k 100k FREQUENCY (Hz) 1M 10M 1µs/div OUT0 LOADED WITH 10kΩ II 100pF REF0 = 4V (MAX517/MAX519) DAC CODE = 00 HEX to FF HEX _______________________________________________________________________________________ 5 MAX517/MAX518/MAX519 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs ______________________________Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) NEGATIVE FULL-SCALE STEP RESPONSE WORST-CASE 1LSB STEP CHANGE OUT0 20mV/div AC COUPLED OUT0 1V/div 1µs/div OUT0 LOADED WITH 10kΩ II 100pF REF0 = 4V (MAX517/MAX519) DAC CODE = FF HEX to 00 HEX 500ns/div REF0 = 5V (MAX517/MAX519) DAC CODE = 80 HEX to 7F HEX MAX517/MAX519 REFERENCE FEEDTHROUGH AT 1kHz CLOCK FEEDTHROUGH A A B B A = SCL, 400kHz, 5V/div B = OUT0, 5mV/div DAC CODE = 7F HEX REF0 = 5V (MAX517/MAX519) A = REF0, 1V/div (4VP-P) B = OUT0, 50µV/div, UNLOADED FILTER PASSBAND = 100Hz to 10kHz DAC CODE = 00 HEX MAX517/MAX519 REFERENCE FEEDTHROUGH AT 10kHz MAX517/MAX519 REFERENCE FEEDTHROUGH AT 100kHz A A B A = REF0, 1V/div (4VP-P) B = OUT0, 50µV/div, UNLOADED FILTER PASSBAND = 1kHz to 100kHz DAC CODE = 00 HEX 6 B A = REF0, 1V/div (4VP-P) B = OUT0, 50µV/div, UNLOADED FILTER PASSBAND = 10kHz to 1MHz DAC CODE = 00 HEX _______________________________________________________________________________________ 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs PIN NAME FUNCTION MAX517 MAX518 MAX519 1 1 1 OUT0 DAC0 Voltage Output 2 2 4 GND Ground — — 5 AD3 Address Input 3; sets IC’s slave address 3 3 6 SCL Serial Clock Input 4 4 8 SDA Serial Data Input — — 9 AD2 Address Input 2; sets IC’s slave address 5 5 10 AD1 Address Input 1; sets IC’s slave address 6 6 11 AD0 Address Input 0; sets IC’s slave address 7 7 12 VDD Power Supply, +5V; used as reference for MAX518 — — 13 REF1 Reference Voltage Input for DAC1 8 — 15 REF0 Reference Voltage Input for DAC0 — 8 16 OUT1 DAC1 Voltage Output — — 2, 3, 7, 14 N.C. No Connect—not internally connected. _______________Detailed Description VDD REF0 (REF1) Serial Interface INPUT LATCH 0 OUTPUT LATCH 0 DAC0 OUT0 INPUT LATCH 1 OUTPUT LATCH 1 DAC1 (OUT1) MAX519 ONLY 8-BIT SHIFT REGISTER ADDRESS COMPARATOR MAX517/MAX519 SCL SDA START/STOP DETECTOR DECODE AD0 (AD2) AD1 (AD3) GND ( ) ARE FOR MAX519 Figure 1. MAX517/MAX519 Functional Diagram The MAX517/MAX518/MAX519 use a simple 2-wire serial interface requiring only two I/O lines (2-wire bus) of a standard microprocessor (µP) port. Figure 2 shows the timing diagram for signals on the 2-wire bus. Figure 3 shows a typical application. The 2-wire bus can have several devices (in addition to the MAX517/ MAX518/MAX519) attached. The two bus lines (SDA and SCL) must be high when the bus is not in use. When in use, the port bits are toggled to generate the appropriate signals for SDA and SCL. External pull-up resistors are not required on these lines. The MAX517/MAX518/ MAX519 can be used in applications where pull-up resistors are required (such as in I2C systems) to maintain compatibility with existing circuitry. The MAX517/MAX518/MAX519 are receive-only devices and must be controlled by a bus master device. They operate at SCL rates up to 400kHz. A master device sends information to the devices by transmitting their address over the bus and then transmitting the desired information. Each transmission consists of a START condition, the MAX517/MAX518/MAX519’s programmable slave-address, one or more command-byte/output-byte pairs (or a command byte alone, if it is the last byte in the transmission), and finally, a STOP condition (Figure 4). _______________________________________________________________________________________ 7 MAX517/MAX518/MAX519 ______________________________________________________________Pin Description MAX517/MAX518/MAX519 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs SDA tSU, DAT tBUF tSU, STA tHD, STA tLOW tSU, STO tHD, DAT SCL tHIGH tHD, STA tR tF START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION Figure 2. Two-Wire Serial Interface Timing Diagram µC SDA DUAL DAC SCL RC 1k SCL SDA AD0 AD1 AD2 AD3 REF0 REF1 +1V +4V OUT0 OFFSET ADJUSTMENT OUT1 GAIN ADJUSTMENT MAX519 DUAL DAC MAX518 SCL SDA AD0 AD1 SINGLE DAC +5V SCL SDA AD0 AD1 OUT0 BRIGHTNESS ADJUSTMENT OUT1 CONTRAST ADJUSTMENT REF0 +2.5V OUT0 THRESHOLD ADJUSTMENT MAX517 Figure 3. MAX517/MAX518/MAX519 Application Circuit 8 The address byte and pairs of command and output bytes are transmitted between the START and STOP conditions. The SDA state is allowed to change only while SCL is low, with the exception of START and STOP conditions. SDA’s state is sampled, and therefore must remain stable while SCL is high. Data is transmitted in 8-bit bytes. Nine clock cycles are required to transfer the data bits to the MAX517/MAX518/MAX519. Set SDA low during the 9th clock cycle as the MAX517/MAX518/MAX519 pull SDA low during this time. RC (see Figure 3) limits the current that flows during this time if SDA stays high for short periods of time. The START and STOP Conditions When the bus is not in use, both SCL and SDA must be high. A bus master signals the beginning of a transmission with a START condition by transitioning SDA from high to low while SCL is high (Figure 5). When the master has finished communicating with the slave, it issues a STOP condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission. The Slave Address The MAX517/MAX518/MAX519 each have a 7-bit long slave address (Figure 6). The first three bits (MSBs) of the slave address have been factory programmed and are always 010. In addition, the MAX517 and MAX518 have the next two bits factory programmed to 1s. The logic state of the address inputs (AD0 and AD1 on the MAX517/MAX518; AD0, AD1, AD2, and AD3 on the MAX519) determine the LSB bits of the 7-bit slave address. These input pins may be connected to VDD or DGND, or they may be actively driven by TTL or CMOS logic levels. The MAX517/MAX518 have four possible slave addresses and therefore a maximum of four of _______________________________________________________________________________________ 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs COMMAND BYTE MAX517/MAX518/MAX519 SLAVE ADDRESS BYTE OUTPUT BYTE SDA MSB LSB ACK MSB LSB ACK MSB LSB ACK SCL STOP CONDITION START CONDITION Figure 4. A Complete Serial Transmission R2 R1 R0 RST SDA PD A0/0 X SDA MSB ACK X LSB SCL SCL STOP CONDITION START CONDITION R2, R1, R0: RESERVED BITS. SET TO 0. Figure 5. All communications begin with a START condition and end with a STOP condition, both generated by a bus master. 1 0 1 or AD3 1 or AD2 PD: POWER-DOWN BIT. SET TO 1 TO PLACE THE DEVICE IN THE 4µA SHUTDOWN MODE. SET TO 0 TO RETURN TO THE NORMAL OPERATIONAL STATE. A0: ADDRESS BIT. DETERMINES WHICH DAC'S INPUT LATCH RECEIVES THE 8 BITS OF DATA IN THE NEXT BYTE. SET TO 0 FOR MAX517. SLAVE ADDRESS 0 RST: RESET BIT, SET TO 1 TO RESET ALL DAC REGISTERS. AD1 AD0 0 ACK ACK: ACKNOWLEDGE BIT. THE MAX517/MAX518/MAX519 PULLS SDA LOW DURING THE 9TH CLOCK PULSE. X: DON’T CARE. SDA LSB Figure 7. Command Byte SCL SLAVE ADDRESS BITS AD0, AD1, AD2, AND AD3 CORRESPOND TO THE LOGIC STATE OF THE ADDRESS INPUT PINS. Figure 6. Address Byte these devices may share the bus. The MAX519 has 16 possible slave addresses. The eighth bit (LSB) in the slave address byte should be low when writing to the MAX517/MAX518/MAX519. The MAX517/MAX518/MAX519 monitor the bus continuously, waiting for a START condition followed by their slave address. When a device recognizes its slave address, it is ready to accept data. The Command Byte and Output Byte A command byte follows the slave address. Figure 7 shows the format for the command byte. A command byte is usually followed by an output byte unless it is the last byte in the transmission. If it is the last byte, all bits except PD (power-down) and RST (reset) are ignored. If an output byte follows the command byte, A0 of the command byte indicates the digital address of the DAC whose input data latch receives the digital output data. Set this bit to 0 when writing to the MAX517. The data is transferred to the DAC’s output latch during the STOP condition following the transmission. This allows both DACs of the MAX518/MAX519 to be updated simultaneously (Figure 8). Setting the PD bit high powers down the MAX517/ MAX518/MAX519 following a STOP condition (Figure 9a). If a command byte with PD set high is followed by an output byte, the addressed DAC’s input latch will be updated and the data will be transferred to the DAC’s output latch following the STOP condition (Figure 9b). _______________________________________________________________________________________ 9 MAX517/MAX518/MAX519 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs 0 1 1 1 or or 0 AD3 AD2AD1 AD0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 SDA ADDRESS BYTE START CONDITION COMMAND BYTE (ADDRESSING DAC0) ACK ACK STOP DAC0 INPUT LATCH CONDITION SET TO FULL SCALE DAC OUTPUT CHANGES HERE: DAC0 GOES TO FULL SCALE. OUTPUT BYTE (FULL SCALE) ACK ( ) ( ) Figure 8a. Setting One DAC Output (MAX517/MAX518/MAX519) 0 1 1 1 or or 0 AD3 AD2AD1 AD0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 SDA ADDRESS BYTE START CONDITION 1 1 1 1 1 COMMAND BYTE (ADDRESSING DAC0) ACK ACK OUTPUT BYTE (FULL SCALE) ACK ( 1 1 1 COMMAND BYTE (ADDRESSING DAC1) DAC0 INPUT LATCH SET TO FULL SCALE ACK ) 0 SDA ACK OUTPUT BYTE STOP (FULL SCALE) DAC1 INPUT LATCH CONDITION SET TO FULL SCALE DAC OUTPUTS CHANGE HERE: DAC0 AND DAC1 GO TO FULL SCALE. ( ) ( ) Figure 8b. Setting Both DAC Outputs (MAX518/MAX519) (a) 0 1 1 1 or or 0 AD3 AD2 AD1 AD0 0 0 (PD) 0 0 0 0 1 0 X SDA ADDRESS BYTE X X COMMAND BYTE ACK ACK STOP CONDITION START CONDITION (b) 0 1 1 1 or or 0 AD3 AD2 AD1AD0 0 0 0 0 0 0 (PD) 1 0 X SDA ADDRESS BYTE ACK START CONDITION NOTE: X = DON'T CARE 0 1 1 ( DEVICE ENTERS POWER-DOWN STATE 1 1 1 1 1 1 ) 0 X COMMAND BYTE (ADDRESSING DAC0) ACK OUTPUT BYTE (FULL SCALE) ( ACK STOP CONDITION DAC0 INPUT LATCH SET TO FULL SCALE. DEVICE ENTERS POWER-DOWN STATE. DAC0 OUTPUT LATCH SET TO FULL SCALE. ) ( Figure 9. Entering the Power-Down State 10 ______________________________________________________________________________________ ) 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs (a) 0 1 1 1 or or 0 AD3 AD2 AD1 AD0 0 I2C Compatibility The MAX517/MAX518/MAX519 are fully compatible with existing I 2 C systems. SCL and SDA are highimpedance inputs; SDA has an open drain that pulls the data line low during the 9th clock pulse. Figure 12 shows a typical I2C application. (PD) 0 0 0 0 0 0 0 X SDA ADDRESS BYTE following output byte is ignored. Subsequent pairs of command/output bytes overwrite the input latches (Figure 11b). All changes made during a transmission affect the MAX517/MAX518/MAX519’s outputs only when the transmission ends and a STOP has been recognized. The R0, R1, and R2 bits are reserved and must be set to zero. X X COMMAND BYTE ACK ACK STOP CONDITION START CONDITION (b) 0 1 1 1 or or 0 AD3 AD2AD1 AD0 0 0 0 0 0 (PD) 0 0 0 0 X SDA ADDRESS BYTE 0 DEVICE RETURNS TO NORMAL OPERATION 0 0 0 0 0 0 ) 0 X COMMAND BYTE (ADDRESSING DAC0) ACK START CONDITION 0 ( ACK OUTPUT BYTE STOP (SET TO 0) CONDITION DAC0 INPUT LATCH SET TO 0. DEVICE RETURNS TO NORMAL OPERATION. DAC0 SET TO 0. ACK ( NOTE: X = DON'T CARE ) ( ) Figure 10. Returning to Normal Operation from Power-Down (a) 0 1 1 1 or or 0 AD3 AD2 AD1AD0 0 0 (RST) 0 0 0 1 0 0 X SDA ADDRESS BYTE ( 0 1 1 1 or or 0 AD3 AD2 AD1 AD0 0 0 0 0 ACK ) ALL INPUT LATCHES SET TO 0. (RST) 0 1 0 ADDRESS BYTE START CONDITION NOTE: X = DON'T CARE ACK STOP CONDITION ( ALL OUTPUTS SET TO 0. ) 0 X SDA X COMMAND BYTE ACK START CONDITION (b) X X COMMAND BYTE ( X 0 X X X X X X X X "DUMMY" OUTPUT BYTE ACK ALL INPUT LATCHES SET TO 0. ) ACK ADDITIONAL COMMAND BYTE/ OUTPUT BYTE PAIRS ( STOP CONDITION ) DAC OUTPUTS SET TO 0 UNLESS CHANGED BY ADDITIONAL COMMAND BYTE/OUTPUT BYTE PAIRS. Figure 11. Resetting DAC Outputs ______________________________________________________________________________________ 11 MAX517/MAX518/MAX519 Furthermore if the transmission’s last command byte has PD high, the output latches are updated, but voltage outputs will not reflect the newly entered data because the DAC enters power-down mode when the STOP condition is detected. When in power-down, the DAC outputs float. In this mode, the supply current is a maximum of 20µA. A command byte with the PD bit low returns the MAX517/MAX518/MAX519 to normal operation following a STOP condition, with the voltage outputs reflecting the output-latch contents (Figures 10a and 10b). Because each subsequent command byte overwrites the previous PD bit, only the last command byte of a transmission affects the power-down state. Setting the RST bit high clears the DAC input latches. The DAC outputs remain unchanged until a STOP condition is detected (Figure 11a). If a reset is issued, the MAX517/MAX518/MAX519 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs µC latches with data that has not been transferred to the output latches (Figure 13). Only the currently addressed device will recognize a STOP condition and transfer data to its output latches. If the device is left with data in its input latches, the data can be transferred to the output latches the next time the device is addressed, as long as it receives at least one command byte and a STOP condition. 2 E PROM XICOR X24C04 SDA SCL SCL SDA Early STOP Conditions The addressed device recognizes a STOP condition at any point in a transmission. If the STOP occurs during a command byte, all previous uninterrupted command and output byte pairs are accepted, the interrupted command byte is ignored, and the transmission ends (Figure 14a). If the STOP occurs during an output byte, all previous uninterrupted command and output byte pairs are accepted, the final command byte’s PD and RST bits are accepted, the interrupted output byte is ignored, and the transmission ends (Figure 14b). DUAL DAC OUT0 SCL MAX518 OUT1 SDA AD0 AD1 SINGLE DAC OUT0 +5V SCL SDA AD0 AD1 Analog Section MAX517 DAC Operation The MAX518 and MAX519 contain two matched voltage-output DACs. The MAX517 contains a single DAC. The DACs are inverted R-2R ladder networks that convert 8-bit digital words into equivalent analog output voltages in proportion to the applied reference voltages. The MAX518 has both DAC’s reference inputs connected to VDD. Figure 15 shows a simplified diagram of one DAC. Figure 12. MAX517/MAX518/MAX519 Used in a Typical I2C Application Circuit Additional START Conditions It is possible to interrupt a transmission to a device with a new START (repeated start) condition (perhaps addressing another device), which leaves the input 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 MAX517/MAX519 Reference Inputs The MAX517 and MAX519 can be used for multiplying applications. The reference accepts a 0V to VDD volt- 1 1 1 1 1 1 1 1 0 0 1 0 1 1 0 1 0 0 SDA ADDRESS BYTE (DEVICE 0) START CONDITION ACK COMMAND BYTE ADDRESSING DAC0 OUTPUT BYTE (FULL SCALE) ACK ( 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ADDRESS BYTE (DEVICE 1) ACK DEVICE 0's DAC0 INPUT LATCH SET TO FULL SCALE. ) REPEATED START CONDITION 0 SDA COMMAND BYTE (ADDRESSING DAC0) ACK OUTPUT BYTE (FULL SCALE) ( ACK DEVICE 1's DAC0 INPUT LATCH SET TO FULL SCALE. )( STOP CONDITION ) ONLY DEVICE 1's DAC0 OUTPUT LATCH SET TO FULL SCALE. DEVICE 0's OUTPUT LATCH UNCHANGED. Figure 13. Repeated START Conditions 12 ______________________________________________________________________________________ ACK 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs 0 1 1 1 or or 0 AD3 AD2 AD1 AD0 0 0 MAX517/MAX518/MAX519 (a) (RST) (PD) 0 0 0 1 1 0 SDA ADDRESS BYTE ACK START CONDITION (b) 0 1 1 1 or or 0 AD3 AD2 AD1 AD0 0 0 0 INTERRUPTED COMMAND BYTE EARLY MAX517/MAX518/MAX519's STOP CONDITION STATE REMAINS UNCHANGED. ( 0 (PD) 0 RST 1 0 0 0 0 1 1 1 0 ) 0 X X SDA ADDRESS BYTE ACK START CONDITION COMMAND BYTE (POWER DOWN) INTERRUPTED OUTPUT BYTE ACK EARLY STOP CONDITION ( MAX517/MAX518/MAX519 POWER DOWN; INPUT LATCH UNCHANGED IF RST = 0, DAC OUTPUT(S) RESET IF RST = 1. ) Figure 14. Early STOP Conditions Table 1. Unipolar Code Table DAC CONTENTS ANALOG OUTPUT 11111111 255 + VREF (———) 256 10000001 129 + VREF (———) 256 10000000 128 VREF + VREF (———) = —— 256 2 01111111 127 + VREF (———) 256 00000001 1 + VREF (———) 256 00000000 0V R 2R R R OUT_ 2R 2R 2R 2R D0 D5 D6 D7 REF_* GND SHOWN FOR ALL 1s ON DAC *REF = VDD FOR THE MAX518 Figure 15. DAC Simplified Circuit Diagram age, both DC and AC signals. The voltage at each REF input sets the full-scale output voltage for its respective DAC. The reference voltage must be positive. The DAC’s input impedance is code dependent, with the lowest value occurring when the input code is 55 hex or 0101 0101, and the maximum value occurring when the input code is 00 hex. Since the REF input resistance (RIN) is code dependent, it must be driven by a circuit with low output impedance (no more than RIN ÷ 2000) to maintain output linearity. The REF input capacitance is also code dependent, with the maximum value occurring at code FF hex (typically 30pF). The output voltage for any DAC can be represented by a digitally programmable voltage source as: VOUT = (N x VREF) / 256, where N is the numerical value of the DAC’s binary input code. Output Buffer Amplifiers The DAC voltage outputs are internally buffered precision unity-gain followers that slew up to 1V/µs. The outputs can swing from 0V to VDD. With a 0V to 4V (or 4V to 0V) output transition, the amplifier outputs typically settle to 1/2LSB in 6µs when loaded with 10kΩ in parallel with 100pF. The buffer amplifiers are stable with any combination of resistive loads ≥2kΩ and capacitive loads ≤300pF. The MAX517/MAX518/MAX519 are designed for unipolar-output, single-quadrant multiplication where the output voltages and the reference inputs are positive with respect to AGND. Table 1 shows the unipolar code. ______________________________________________________________________________________ 13 MAX517/MAX518/MAX519 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs SYSTEM GND +5V OUT1 OUT0 REF0 N.C. N.C. N.C. REF1 GND 0.1µF VDD RF REF_ CF MAX517 MAX519 Figure 16. PC Board Layout for Minimizing MAX519 Crosstalk (bottom view) __________Applications Information Power-Supply Bypassing and Ground Management Bypass VDD with a 0.1µF capacitor, located as close to VDD and GND as possible. Careful PC board layout minimizes crosstalk among DAC outputs, reference inputs, and digital inputs. Figure 16 shows the suggested PC board layout to minimize crosstalk. When using the MAX518 (or the MAX517/MAX519 with VDD as the reference), you may want to add a noise filter to the VDD supply (Figure 17) or to the reference input(s) (Figure 18), especially in noisy environments. The reference input’s bandwidth exceeds 1MHz for AC signals, so disturbances on the reference input can easily affect the DAC output(s). The maximum input current for a single reference input is VREF/16kΩ = IREF (max). In Figure 17, choose RF so that changes in the reference input current will have little effect on the reference voltage. For example, with RF = 6Ω, the maximum output error due to RF is given by: 6Ω x IREF (max) = 1.9mV or 0.1LSB In Figure 18, there is a voltage drop across RF that adds to the TUE. This voltage drop is due to the sum of the reference input current (VREF/16kΩ maximum), supply current (6mA maximum), and the amplifier output current (VREF/RLOAD). Choose RF to limit this voltage drop to an acceptable value. For example, with a 10kΩ load, you can limit the error due to R F to 0.5LSB (9.8mV) by selecting RF so that: RF = VRF / IRF ≤ 9.8mV / (5V / 16kΩ + 6mA + 5V / 10kΩ) RF ≤ 1.4Ω 14 Figure 17. Reference Filter When Using VDD as a Reference +5V RF CF VDD MAX518 Figure 18. VDD Filter When Using VDD as a Reference ______________________________________________________________________________________ 0.1µF 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs ____________________Chip Topography TOP VIEW OUT0 OUT0 1 16 OUT1 N.C. 2 15 REF0 N.C. 3 14 N.C. GND 4 MAX519 OUT1 (MAX518/MAX519) REF0 (MAX517/ MAX519) REF1 (MAX519) 13 REF1 AD3 5 12 VDD SCL 6 11 AD0 N.C. 7 10 AD1 SDA 8 9 GND 0.135" (3.429mm) AD3 (MAX519) AD2 DIP/SO V DD __Ordering Information (continued) AD0 SCL TUE (LSB) PART TEMP. RANGE PIN-PACKAGE MAX517AEPA -40°C to +85°C 8 Plastic DIP 1 MAX517BEPA -40°C to +85°C 8 Plastic DIP 1.5 MAX517AESA -40°C to +85°C 8 SO 1 MAX517BESA -40°C to +85°C 8 SO 1.5 MAX517BMJA -55°C to +125°C 8 CERDIP** 1.5 MAX518ACPA 0°C to +70°C 8 Plastic DIP 1 MAX518BCPA MAX518ACSA MAX518BCSA 0°C to +70°C 0°C to +70°C 0°C to +70°C 8 Plastic DIP 8 SO 8 SO 1.5 1 1.5 MAX518BC/D MAX518AEPA MAX518BEPA MAX518AESA MAX518BESA MAX518BMJA MAX519ACPE MAX519BCPE MAX519ACSE MAX519BCSE MAX519BC/D MAX519AEPE MAX519BEPE MAX519AESE MAX519BESE MAX519BMJE 0°C to +70°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -55°C to +125°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -55°C to +125°C Dice* 8 Plastic DIP 8 Plastic DIP 8 SO 8 SO 8 CERDIP** 16 Plastic DIP 16 Plastic DIP 16 Narrow SO 16 Narrow SO Dice* 16 Plastic DIP 16 Plastic DIP 16 Narrow SO 16 Narrow SO 16 CERDIP** 1.5 1 1.5 1 1.5 1.5 1 1.5 1 1.5 1.5 1 1.5 1 1.5 1.5 SDA AD2 (MAX519) AD1 0.078" (1.981mm) TRANSISTOR COUNT: 1797 SUBSTRATE CONNECTED TO VDD *Dice are specified at TA = +25°C, DC parameters only. **Contact factory for availability and processing to MIL-STD-883. ______________________________________________________________________________________ 15 MAX517/MAX518/MAX519 _____Pin Configurations (continued) MAX517/MAX518/MAX519 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs ________________________________________________________Package Information D E DIM E1 A A1 A2 A3 B B1 C D1 E E1 e eA eB L A3 A A2 L A1 0° - 15° C e B1 eA B eB D1 Plastic DIP PLASTIC DUAL-IN-LINE PACKAGE (0.300 in.) INCHES MAX MIN 0.200 – – 0.015 0.175 0.125 0.080 0.055 0.022 0.016 0.065 0.045 0.012 0.008 0.080 0.005 0.325 0.300 0.310 0.240 – 0.100 – 0.300 0.400 – 0.150 0.115 PKG. DIM PINS P P P P P N D D D D D D 8 14 16 18 20 24 MILLIMETERS MIN MAX – 5.08 0.38 – 3.18 4.45 1.40 2.03 0.41 0.56 1.14 1.65 0.20 0.30 0.13 2.03 7.62 8.26 6.10 7.87 2.54 – 7.62 – – 10.16 2.92 3.81 INCHES MIN MAX 0.348 0.390 0.735 0.765 0.745 0.765 0.885 0.915 1.015 1.045 1.14 1.265 MILLIMETERS MIN MAX 8.84 9.91 18.67 19.43 18.92 19.43 22.48 23.24 25.78 26.54 28.96 32.13 21-0043A DIM D 0°-8° A 0.101mm 0.004in. e B A1 E C L Narrow SO SMALL-OUTLINE PACKAGE (0.150 in.) H A A1 B C E e H L INCHES MAX MIN 0.069 0.053 0.010 0.004 0.019 0.014 0.010 0.007 0.157 0.150 0.050 0.244 0.228 0.050 0.016 DIM PINS D D D 8 14 16 MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 3.80 4.00 1.27 5.80 6.20 0.40 1.27 INCHES MILLIMETERS MIN MAX MIN MAX 0.189 0.197 4.80 5.00 0.337 0.344 8.55 8.75 0.386 0.394 9.80 10.00 21-0041A Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 © 1995 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.