Rohm BD9673AEFJ-E2 Flexible step-down switching regulators with built-in power mosfet Datasheet

Datasheet
Single-chip Type with Built-in FET Switching Regulators
Flexible Step-down
Switching Regulators
with Built-in Power MOSFET
BD9673AEFJ
●General Description
Output 1.5A and below High Efficiency Rate Step-down
Switching Regulator Power MOSFET Internal Type
BD9673AEFJ mainly used as secondary side Power
supply, for example from fixed Power supply of 12V, 24V
etc, Step-down Output of 1.2V/1.8V/3.3V/5V, etc, can be
produced. This IC has external Coil/Capacitor
down-sizing through 300kHz Frequency operation,
inside Nch-FET SW for 45V “withstand-pressure”
commutation and also, high speed load response
through Current Mode Control is a simple external
setting phase compensation system, through a wide
range external constant, a compact Power supply can
be produced easily.
●Features
■ Internal 200 mΩ Nch MOSFET
■ Output Current 1.5A
■ Oscillation Frequency 300kHz
■ Synchronizes to External Clock ( 200kHz～
500kHz )
■ Feedback Voltage 1.0V±1.0%
■ Internal Soft Start Function
■ Internal Over Current Protect Circuit,
Low Input Error Prevention Circuit,
Heat Protect Circuit
■ ON/OFF Control through EN Pin
(Standby Current 0 A Typ.)
■ Package: HTSOP-J8 Package
●Key Specifications
■ Input Voltage
■ Ref. Precision (Ta=25℃)
■ Max Output Current
■ Operating Temperature
■ Max Junction Temperature
●Packages
HTSOP-J8
7V to 42V
±1.0%
1.5A (Max.)
-40℃ to 105℃
-55℃ to 150℃
4.90mm x 6.00mm x 1.00mm
HTSOP-J8
●Applications
■ For Household machines in general that have
12V/24V Lines, etc.
0.01µF
●Typical Application Circuits
15µH CDRH105R
(SUMIDA)
Lx
5V/1.0A VOUT
VCC
RB056L-40 (ROHM)
47µF/15V
GRM32EB31C476KE15 (murata)
BST
GND
R1
120kΩ
R2
30kΩ
C1
open
C2
R3
VC
EN
FB
SYNC
VCC 24V
10µF/35V
GRM31EB3YA106KA12L
(murata)
EN
ON/OFF
control
6800pF
SYNC
10kΩ
Figure 1. Typical Application Circuit
○Structure：Silicon Monolithic Integrated Circuit
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Datasheet
BD9673AEFJ
●Pin Configuration
8
7
6
5
Thermal Pad
1
2
3
4
Figure 2. Pin Configuration (TOP VIEW)
●Pin Description
Pin No.
Pin Name
Description
1
Lx
2
GND
3
VC
Error amplifier output
4
FB
Inverting node of the trans conductance error amplifier
5
SYNC
6
EN
Stand-by ON/OFF pin
7
BST
Voltage Supply pin for High Side FET Driver
8
VCC
Voltage input pin
Terminal for inductor
Ground pin
Input pin of an external signal for the device synchronized by external signal
●Block Diagram
ON/OF
E
VC
TSD
UVLO
Reference
REG
VREF
Current
Sense AMP
Shutdown
F
1.0V
+
+
Error
Σ
BS
Current
Comparator
R Q
+
S
200mΩ
LX
Soft
Start
10Ω
Oscillator
300kH
V
VOU
T
GN
SYN
Figure 3. Block Diagram
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Datasheet
BD9673AEFJ
●Description of Blocks
1.
Reference
This Block generates Error Amp Standard Voltage.
Standard Voltage is 1.0V.
2.
REG
This is a Gate Drive Voltage Generator and 5V Low Saturation regulator for internal Circuit Power supply.
3.
OSC
This is a precise wave Oscillation Circuit with Operation Frequency fixed to 300 kHz fixed (self-running mode).
To implement the synchronization feature connect a square wave (Hi Level: higher than 2V Low Level: lower than 0.8V )
to the SYNC pin. The synchronization frequency range is 200 kHz to 500 kHz.
After connecting the rising edge of LX will be synchronized to the falling edge of SYNC pin signal after 3 count.
At the synchronization remove the external clock, the device transitions self-running mode after 7 microseconds.
4.
Soft Start
A Circuit that does Soft Start to the Output Voltage of DC/DC Comparator, and prevents Rush Current during Start-up.
Soft Start Time is set at IC internal, after 10ms from starting-up EN Pin, Standard Voltage comes to 1.0V, and Output
Voltage becomes set Voltage.
5.
ERROR AMP
This is an Error amplifier what detects Output Signal, and outputs PWM Control Signal.
Internal Standard Voltage is set to 1.0V. Also, C and R are connected between the Output (VC) Pin GND of Error Amp
as Phase compensation elements. (See P.11)
6.
ICOMP
This is a Voltage-Pulse Width Converter that controls Output Voltage in response to Input Voltage.
This compares the Voltage added to the internal SLOPE waveform in response to the FET WS Current with Error
amplifier Output Voltage, controls the width of Output Pulse and outputs to Driver.
7.
Nch FET SW
This is an internal commutation SW that converts Coil Current of DC/DC Comparator.
It contains 45V” with stand pressure” 200mΩ SW.
Because the Current Rating of this FET is 2.0A included ripple current, please use at within 2.0A.
The device has the circuit of over current protection for protecting the FET from over current.
To detect OCP 2 times sequentially, the device will stop and after 13 msec restart.
8.
UVLO
This is a Low Voltage Error Prevention Circuit.
This prevents internal circuit error during increase of Power supply Voltage and during decline of Power supply Voltage.
It monitors VCC Pin Voltage and internal REG Voltage, And when VCC Voltage becomes 6.4V and below, it turns OFF
all Output FET and turns OFF DC/DC Comparator Output, and Soft Start Circuit resets.
Now this Threshold has Hysteresis of 200mV.
9.
TSD
This is a Heat Protect (Temperature Protect) Circuit.
When it detects an abnormal temperature exceeding Maximum Junction Temperature (Tj=150℃), it turns OFF all
Output FET, and turns OFF DC/DC Comparator Output. When Temperature falls, it has/with Hysteresis and
automatically returns.
10. EN
With the Voltage applied to EN Pin(6pin), IC ON/OFF can be controlled.
When a Voltage of 2.0V or more is applied, it turns ON, at Open or 0V application, it turns OFF.
About 550kΩ Pull-down Resistance is contained within the Pin.
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Datasheet
BD9673AEFJ
●Absolute Maximum Ratings
Item
VCC-GND Supply Voltage
BST-GND Voltage
Symbol
Ratings
Unit
VCC
45
V
VBST
50
V
⊿VBST
7
V
EN-GND Voltage
VEN
45
V
Lx-GND Voltage
VLX
45
V
FB-GND Voltage
VFB
7
V
VC
7
V
SYNC
7
V
BST-Lx Voltage
VC-GND Voltage
SYNC-GND Voltage
High-side FET Drain Current
IDH
3.5
A
Power Dissipation
Pd
3.76(*1)
W
Topr
-40～+105
℃
Storage Temperature
Tstg
-55～+150
℃
Junction Temperature
Tjmax
+150
℃
Operating Temperature
(*1)During mounting of 70×70×1.6t mm 4layer board (Copper area: 70mm×70mm).Reduce by 30.08mW for every 1℃ increase. (Above 25℃)
●Electrical Characteristics (Unless otherwise specified Ta=25℃, VCC=24V, Vo=5V,EN=3V )
Parameter
Symbol
Limits
Min.
Typ.
Max.
Unit
Conditions
【Circuit Current】
Stand-by current of VCC
Ist
－
0
10
µA
VEN=0V
Circuit current of VCC
Icc
－
1
2
mA
FB=1.2V
Vuv
6.1
6.4
6.7
V
Vuvhy
－
200
300
mV
fosc
270
300
330
kHz
Dmax
85
91
97
%
FB threshold voltage
VFB
0.990
1.000
1.010
V
Input bias current
IFB
-1.0
0
1.0
µA
Error amplifier DC gain
AVEA
700
7000
70000
V/V
Trans Conductance
GEA
110
220
440
µA/V
Soft Start Time
Tsoft
7
10
13
ms
GCS
5
10
20
A/V
Lx NMOS ON resistance
RonH
－
200
340
mΩ
Lx pre-charge NMOS ON resistance
RonL
－
10
17
Ω
【Under Voltage Lock Out (UVLO)】
Detect Voltage
Hysteresis width
【Oscillator】
Oscillating frequency
Max Duty Cycle
【Error Amp】
VFB=0V
IVC=±10µA,
VC=1.5V
【Current Sense Amp】
VC to switch current transconductance
【Output】
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Datasheet
BD9673AEFJ
Over Current Detect Current
Iocp
2
3.3
－
A
【CTL】
ON
VENON
2
－
VCC
V
OFF
VENOFF
-0.3
－
0.8
V
REN
2.7
5.5
11
µA
High
VSYNCH
2.0
－
5.5
V
Low
VSYNCL
-0.3
－
0.8
V
SYNC Pin input current
REN
6
12
24
µA
SYNC falling edge to LX rising edge delay
tdelay
200
400
600
ns
EN Pin Control voltage
EN Pin input current
VEN=3V
【SYNC】
SYNC Pin Control voltage
VSYNC=3V
◎Not designed to withstand radiation.
●Operating Ratings(Ta=25℃)
Item
Power Supply Voltage
Output Voltage
Symbol
Ratings
Typ
Max
7
－
42
V
－
VCC×0.7
V
VCC
VOUT
Unit
Min
(*2)
1.0
(*2)Restricted by minimum on pulse typ. 200ns
●Detailed Description
◇Synchronizes to External Clock
The SYNC pin can be used to synchronize the regulator to an external system clock. To implement the synchronization
feature connect a square wave to SYNC pin. The square wave amplitude must transition lower than 0.8V and higher than
2.0V on the SYNC pin and have an on time greater than 100ns and an off time greater than 100ns. The synchronization
frequency range is 200 kHz to 500 kHz. The rising edge of the LX will be synchronized to the falling edge of SYNC pin
signal after SYNC input pulse 3 count. At the synchronization, the external clock is removed, the device transitions
self-running mode after 7 microseconds.
SYNC
Set the latch for
synchronization
SYNC_LATCH
400nsec
about
7µsec
Lx
Figure 4. Timing chart at Synchronization
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Datasheet
BD9673AEFJ
◇The case of not using the function of synchronization
Although the SYNC pin is pulled down by resistor in this device, if the function of the synchronization is not used, it is
recommended to connect SYNC pin to ground.
Figure 5. the method to disposal the SYNC pin without
synchronization
◇SOFT START
The soft start time of BD9673AEFJ is determined by the DCDC operating frequency (self-run mode 300 kHz ⇒10ms).
If synchronization is used at the time of EN=ON, The soft start time is restricted by SYNC pin input pulse frequency.
SYNC pin input pulse frequency is fosc_ex kHz, the soft start time is expressed by below equation.
300
Tss
=
fosc_ex
× 10 [ms]
◇OCP operation
The device has the circuit of over current protection for protecting the FET from over current.
To detect OCP 2 times sequentially, the device will stop and after 13 msec restart.
OCP threshold
VC
VC voltage discharged
by OCP latch
VC voltage rising by
output connect to GND
force the High side FET OFF
by detecting OCP current
(pulse by pulse protection)
Lx
output connect to GND
VOUT
OCP
set the OCP latch by detecting
the OCP current 2 times sequencially
OCP latch reset after 13 msec
(300ｋHz 4000 counts)
OCP_LATCH
Figure 6. Timing chart at OCP operation
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Datasheet
BD9673AEFJ
●Reference Data (Unless otherwise specified, Ta=25℃, VCC=24V, Vo=5V, EN=3V)
2
1
0.9
0.8
1.5
VCC=42V
0.6
ICC[mA]
ICC[uA]
0.7
VCC=36
V
VCC=24V
0.5
0.4
VCC=12V
0.3
1
Temp=105℃
Temp=25℃
0.5
0.2
0.1
Temp=‐40℃
0
0
-60 -40 -20
0
20
40
60
0
80 100 120
5
10
15
Temp[℃ ]
20
25
30
35
40
45
VCC[V]
Figure 8. Standby Current
Temperature Characteristics
Figure 9. Circuit Current
Power supply Voltage Characteristics
8
2
7
UVLO threshold[V]
ICC[mA]
1.5
1
VCC=12V
VCC=24V
0.5
6
5
detect voltage
4
reset voltage
3
2
VCC=36V
1
VCC=42V
0
0
-60 -40 -20
0
20
40
60
80 100 120
-60 -40 -20
0
Temp[℃ ]
40
60
80 100 120
Temp[℃ ]
Figure 11.. UVLO Threshold
Temperature Characteristics
Figure 10.. Circuit Current
Temperature Characteristics
350
100
340
90
330
80
320
70
MAXDUTY[%]
FREQUENCY[kHz]
20
310
300
290
280
60
50
40
30
270
20
260
10
0
250
-60 -40 -20
0
20
40
60
-60 -40 -20
80 100 120
Temp[℃ ]
20
40
60
80 100 120
Temp[℃ ]
Figure 12. Oscillation Frequency
Temperature Characteristics
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Figure 13. Max Duty
Temperature Characteristics
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Datasheet
BD9673AEFJ
1.010
1.010
1.008
1.008
1.006
VCC=36V
1.004
VFB threshold[V]
VFB threshold[V]
1.006
VCC=42V
1.002
1.000
0.998
0.996
VCC=24V
VCC=12V
0.994
1.004
1.002
1.000
0.998
0.996
Temp=‐40℃
Temp=25℃
Temp=105℃
0.994
0.992
0.992
0.990
0.990
-60 -40 -20
0
20
40
60
80 100 120
0
5
10
Temp[℃ ]
30
35
40
45
VCC[V]
14
Soft Start Time[ms]
VC terminal current[uA]
25
16
Temp=105℃
Temp=25℃
Temp=‐40℃
12
10
8
6
VCC=12V
VCC=24V
4
VCC=36V
2
VCC=42V
0
0
0.5
1
1.5
2
-60 -40 -20
0
20
40
60
80 100 120
Temp[℃ ]
VFB[V]
Figure 16. FB Voltage - IVC
Current Characteristics
Figure 17. Soft Start Time
Temperature Characteristics
20
PRECHARGE FET RON [Ω]
300
HIGHSIDE FET RON [mΩ]
20
Figure 15. FB Threshold
Power supply Characteristics
Figure 14. FB Threshold Voltage
Temperature Characteristics
60
50
40
30
20
10
0
‐10
‐20
‐30
‐40
‐50
‐60
15
250
200
150
100
50
15
10
5
0
0
-60 -40 -20
0
20
40
60
-60 -40 -20
80 100 120
20
40
60
80 100 120
Temp[℃ ]
Temp[℃ ]
Figure 19. Pre-charge FET ON
Resistance Temperature Characteristics
Figure 18. Nch FET ON Resistance
Temperature Characteristics
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Datasheet
BD9673AEFJ
6
VC to SW Current
transconductance[A/V]
OCP_peak_current[A]
5
4
3
VCC=12V
VCC=24V
VCC=36V
VCC=42V
2
1
0
-60 -40 -20
0
20
40
60
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-60 -40 -20
80 100 120
Temp[℃ ]
0
20
40
60
80 100 120
Temp[℃ ]
Figure21. VC to SW current transconductance
Temperature characteristics
Figure 20. OCP Detect Current
Temperature Characteristics
2
EN Threshold[V]
1.5
1
0.5
0
-60 -40 -20
0
20
40
60
80 100 120
Temp[℃ ]
Figure 22. EN Threshold
Temperature Characteristics
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Datasheet
BD9673AEFJ
●Example of Reference Application Circuit (Input 24V, Output 5.0V)
0.01µF
15µH CDRH105R
(SUMIDA)
Lx
5V/1.0A VOUT
VCC
RB056L-40 (ROHM)
47µF/15V
GRM32EB31C476KE15 (murata)
GND
R1
120kΩ
R2
30kΩ
C2
C1
open
R3
BST
VC
EN
FB
SYNC
VCC 24V
10µF/35V
GRM31EB3YA106KA12L
(murata)
EN
ON/OFF
control
6800pF
SYNC
10kΩ
Figure 23. Reference Application Circuit
●Reference Application Data (Example of Reference Application Circuit)
Transformation Efficiency η[%]
100
90
80
70
60
Phase
Phase
Gain
Gain
VCC=12V
50
VCC=24V
40
VCC=36V
30
VCC=42V
20
10
0
0
500
1000
1500
LOAD CURRENT[mA]
Figure 25. Frequency Response
Characteristics (Io=0.5A)
Figure 24. Electric Power
Conversion Rate
Figure 26. Frequency Response
Characteristics (Io=1.0A)
VOUT：200mV/div (AC)
VOUT：200mV/div (AC)
IL：1A/div (DC)
IL：1A/div (DC)
Figure 28. Load Response Characteristics
(Io=1.5A→0A)
Figure 27. Load Response Characteristics
(Io=0A→1.5A)
EN：5V/div (DC)
LX：10V/div (DC
EN：5V/div (DC)
LX：10V/div (DC
IL：0.5A/div (DC)
VOUT：2V./div (DC)
IL：0.5A/div (DC)
VOUT：2V./div (DC)
Figure 30. Stop Waveform
Figure 29. startup Waveform
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Datasheet
BD9673AEFJ
●Example of Reference Application Circuit (Input 24V, Output 12V)
Figure 31. Reference Application Circuit
Transformation Efficiency η[%]
●Reference Application Data (Example of Reference Application Circuit)
100
90
80
70
60
50
40
30
20
10
0
VCC=7V
VCC=12V
VCC=24V
VCC=42V
0
500
1000
1500
LOAD CURRENT[mA]
Figure 32. Electric Power
Conversion Rate
Figure 33. Frequency Response
Characteristics (Io=0.5A)
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Figure 34. Frequency Response
Characteristics (Io=1.0A)
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BD9673AEFJ
●Example of Reference Application Circuit (Input 24V, Output 3.3V)
Figure 35. Reference Application Circuit
Transformation Efficiency η[%]
●Reference Application Data (Example of Reference Application Circuit)
100
90
80
70
60
50
40
30
20
10
0
VCC=24V
VCC=36V
VCC=42V
0
500
1000
1500
LOAD CURRENT[mA]
Figure 36. Electric Power
Conversion Rate
Figure 37. Frequency Response
Characteristics (Io=0.5A)
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Figure 38. Frequency Response
Characteristics (Io=3.0A)
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Datasheet
BD9673AEFJ
●Example of Reference Application Circuit (Input 24V, Output -12V)
Figure 39. Reference Application Circuit
Transformation Efficiency η[%]
●Reference Application Data (Example of Reference Application Circuit)
100
90
80
70
60
50
40
30
20
10
0
VCC=12V
0
VCC=24V
500
LOAD CURRENT[mA]
1000
Figure 40. Electric Power
Conversion Rate
Figure 41. Frequency Response
Characteristics (Io=0.5A)
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Figure 42. Frequency Response
Characteristics (Io=3.0A)
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Datasheet
BD9673AEFJ
●Evaluation Board Pattern (Reference)
Layout is a critical portion of good power supply design. There are several signals paths that conduct fast changing currents
or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies
performance. To help eliminate these problems, the VCC pin should be bypassed to ground with a low ESR ceramic bypass
capacitor with B dielectric. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the
VCC pin, and the anode of the catch diode. See Fig.28 for a PCB layout example. The GND pin should be tied directly to the
thermal pad under the IC and the thermal pad.
The thermal pad should be connected to any internal PCB ground planes using multiple VIAs directly under the IC. The LX
pin should be routed to the cathode of the catch diode and to the output inductor. Since the LX connection is the switching
node, the catch diode and output inductor should be located close to the LX pins, and the area of the PCB conductor
minimized to prevent excessive capacitive coupling. For operation at full rated load, the top side ground area must provide
adequate heat dissipating area. The additional external components can be placed approximately as shown. It may be
possible to obtain acceptable performance with alternate PCB layouts, however this layout has been shown to produce good
results and is meant as a guideline.
Figure 43. Evaluation Board Pattern
Figure 44. Reference Board Pattern
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Datasheet
BD9673AEFJ
●Power Dissipation
t
It is shown below reducing characteristics of power dissipation to mount 70mm×70mm×1.6mm PCB
Junction temperature must be designed not to exceed 150℃.
4000
④3760mW
HTSOP-J8 Package On 70mm×70mm×1.6mm t glass epoxy PCB
①1-layer board （Backside copper foil area 0mm×0mm）
②2-layer board ( Backside copper foil area 15mm×15mm)
③2-layer board （Backside copper foil area 70mm×70mm）
④4-layer board （Backside copper foil area 70mm×70mm）
POWER DISSIPATION - mW
3500
3000
2500
③2210mW
2000
②1100mW
1500
1000
①820mW
500
0
0
25
50
75
100
125
150
Ambient Temperature - ℃
t
Figure 45. Power Dissipation ( 70mm×70mm×1.6mm 1layer PCB)
●Power Dissipation Estimate
The following formulas show how to estimate the device power dissipation under continuous mode operations. They should
not be used if the device is working in the discontinuous conduction mode.
The device power dissipation includes:
2
1) Conduction loss： Pcon = IOUT × RonH × VOUT/VCC
–9
2
2) Switching loss: Psw = 1.25 × 10 × VCC × IOUT × fsw
–9
3) Gate charge loss： Pgc = 22.8 × 10 × fsw
4) Quiescent current loss： Pq = 1.0 × 10–3 × VCC
Where:
IOUT is the output current (A）, RonH is the on-resistance of the high-side MOSFET（Ω）, VOUT is the output voltage (V).
VCC is the input voltage (V), fsw is the switching frequency (Hz).
Therefore
Power dissipation of IC is the sum of above dissipation.
Pd = Pcon + Psw + Pgc + Pq
For given Tj, Tj =Ta + θja × Pd
Where:
Pd is the total device power dissipation (W), Ta is the ambient temperature (℃)
Tj is the junction temperature (℃), θja is the thermal resistance of the package (℃)
●Application Components Selection Method
(1) Inductor
Something of the shield Type that Fulfills the Current Rating (Current value Ipecac below), with low DCR (Direct Current
Resistance element) is recommended.
Value of Inductor influences Inductor Ripple Current and becomes the cause of Output Ripple.
In the same way as the formula below, this Ripple Current can be made small for as big as the L value of Coil or as high
as the Switching Frequency.
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BD9673AEFJ
Ipeak =Iout + ⊿IL/2 [A]
⊿IL=
Vin-Vout
(1)
Vout
×
Vin
L
Δ IL
1
×
f
[A]
(2)
Figure 46. Inductor Current
(η: Efficiency, ⊿IL: Output Ripple Current, f: Switching Frequency)
For design value of Inductor Ripple Current, please carry out design tentatively with about 20%～50% of Maximum Input
Current.
※When current that exceeds Coil rating flows to the coil, the Coil causes a Magnetic Saturation, and there are cases
wherein a decline in efficiency, oscillation of output happens. Please have sufficient margin and select so that Peak
Current does not exceed Rating Current of Coil.
(2) Output Capacitor
In order for Capacitor to be used in Output to reduce Output Ripple, Low Ceramic Capacitor of ESR is recommended.
Also, for Capacitor Rating, on top of putting into consideration DC Bias Characteristics, please use something whose
Maximum Rating has sufficient margin with respect to the Output Voltage.
Output Ripple Voltage is looked for using the following formula.
1
＋
Vpp=⊿IL×
2π×f×Co
⊿IL×RESR
[V]
・・・ (3)
Please design in a way that it is held within Capacity Ripple Voltage.
(3) Output Voltage Setting
ERROR AMP internal Standard Voltage is 1.0V. Output Voltage is determined as seen in (4) formula.
VOUT
ERROR AMP
R1
(R1+R2)
FB
Vo=
R2
×1.0 [V] ・・・ (4)
R2
VREF
1.0V
Figure 47.Voltage Return Resistance Setting Method
(4) Bootstrap Capacitor
Please connect from 0.01µF (Laminate Ceramic Capacitor) between BST Pin and Lx Pins.
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BD9673AEFJ
(5)
Schottky diode
Recommend selecting a diode which is satisfied with maximum input voltage of the application, and which is larger
than maximum current rating. If Vf of Schottky diode is large, there is a possibility that Vf of internal parasitic diode
and Vf of Schottky diode reverse and might cause IC error operation when increasing a difference in temperature with
IC. Recommend using a diode with smaller Vf as possible, and location is recommended to be nearest to the pin.
BD9673EFJ use below diode is recommended.
IO[A]
VF[V]
IR[mA]
品番
VRM[V]
RB050L-40
40
3
0.55
1
RB055L-30
30
3
0.55
3
(6) About Adjustment of DC/DC Comparator Frequency Characteristics
Role of Phase compensation element C1, C2, R3 (See P.7. Example of Reference Application Circuit)
Stability and Responsiveness of Loop are controlled through VC Pin which is the output of Error Amp.
The combination of zero and pole that determines Stability and Responsiveness is adjusted by the combination of
resistor and capacitor that are connected in series to the VC Pin.
DC Gain of Voltage Return Loop can be calculated for using the following formula.
Adc = Rl × Gcs × A EA ×
V FB
Vout
Here, VFB is Feedback Voltage (1.0V).AEA is Voltage Gain of Error amplifier (typ: 77dB),
Gcs is the Trans-conductance of Current Detect (typ: 10A/V), and Rl is the Output Load Resistance value.
There are 2 important poles in the Control Loop of this DC/DC.
The first occurs with/ through the output resistance of Phase compensation Capacitor (C1) and Error amplifier.
The other one occurs with/through the Output Capacitor and Load Resistor.
These poles appear in the frequency written below.
fp1 =
GEA
2π×C1×AEA
1
fp2 =
2π×COUT×Rl
Here, GEA is the trans-conductance of Error amplifier (typ: 220 µA/V).
Here, in this Control Loop, one zero becomes important. With the zero which occurs because of Phase compensation
Capacitor C1 and Phase compensation Resistor R3, the Frequency below appears.
1
fz 1 =
2 π × C1 × R3
Also, if Output Capacitor is big, and that ESR (RESR) is big, in this Control Loop, there are cases when it has an
important, separate zero (ESR zero).
This ESR zero occurs due to ESR of Output Capacitor and Capacitance, and exists in the Frequency below.
fzESR =
1
2π× COUT × RESR
(ESR zero)
In this case, the 3rd pole determined with the 2nd Phase compensation Capacitor (C2) and Phase Correction Resistor
(R3) is used in order to correct the ESR zero results in Loop Gain.
This pole exists in the frequency shown below.
1
fp 3 =
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BD9673AEFJ
The target of Phase compensation design is to create a communication function in order to acquire necessary band and
Phase margin.
Cross-over Frequency (band) at which Loop gain of Return Loop becomes “0” is important.
When Cross-over Frequency becomes low, Power supply Fluctuation Response, Load Response, etc worsens.
On the other hand, when Cross-over Frequency is too high, instability of the Loop can occur.
Tentatively, Cross-over Frequency is targeted to be made 1/20 or below of Switching Frequency.
Selection method of Phase Compensation constant is shown below.
1.
Phase Compensation Resistor (R3) is selected in order to set to the desired Cross-over Frequency.
Calculation of RC is done using the formula below.
R3 =
2 π × COUT × fc
GEA × GCS
×
Vout
VFB
Here, fc is the desired Cross-over Frequency. It is made about 1/20 and below of the Normal Switching Frequency (fs).
2.
Phase compensation Capacitor (C1) is selected in order to achieve the desired phase margin.
In an application that has a representative Inductance value (about several µH～20µH), by matching zero of
compensation to 1/4 and below of the Cross-over Frequency, sufficient Phase margin can be acquired. C1 can be
calculated using the following formula.
C1 ＞
4
2π × R3 × fc
RC is Phase compensation Resistor.
3.
Examination whether the second Phase compensation Capacitor C2 is necessary or not is done.
If the ESR zero of Output Capacitor exists in a place that is smaller than half of the Switching Frequency, a second
Phase compensation Capacitor is necessary. In other words, it is the case wherein the formula below happens.
1
fs
＜
2π× COUT × RESR 2
In this case, add the second Phase compensation Capacitor C2, and match the frequency of the third pole to the
Frequency fp3 of ESR zero.
C2 is looked for using the following formula.
COUT × RESR
C2 =
R3
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BD9673AEFJ
●I/O Equivalent Schematic
Pin.
Pin.
No
Name
1
Lx
Pin.
No
Pin Equivalent Schematic
Pin.
Name
BST
Pin Equivalent Schematic
SYNC
VC
2
GND
7
BST
8
VCC
5
SYNC
Lx
GND
GND
VC
EN
3
VC
6
VC
EN
GND
GND
FB
4
FB
GND
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Datasheet
BD9673AEFJ
●Ordering part number
B
D
9
6
7
Part Number
3
A
E
F
J
-
package
EFJ : HTSOP-J8
E2
Packaging and forming specification
E2: Embossed tape and reel
●External information
HTSOP-J8(TOP VIEW)
Part Number Marking
D 9 6 7 3 A
LOT Number
1PIN MARK
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Datasheet
Notice
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(Note 1)
, transport
intend to use our Products in devices requiring extremely high reliability (such as medical equipment
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Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific
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CLASSⅢ
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6.
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confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
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7.
De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta). When used in sealed area, confirm the actual
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8.
Confirm that operation temperature is within the specified range described in the product specification.
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Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used; if flow soldering method is preferred, please consult with the
ROHM representative in advance.
For details, please refer to ROHM Mounting specification
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Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
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[d] the Products are exposed to high Electrostatic
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