AD EVAL-ADV7171EBM Digital pal/ntsc video encoder Datasheet

Digital PAL/NTSC Video Encoder with 10-Bit
SSAF™ and Advanced Power Management
ADV7170/ADV7171
Programmable LUMA delay
Individual on/off control of each DAC
CCIR and square pixel operation
Integrated subcarrier locking to external video source
Color signal control/burst signal control
Interlaced/noninterlaced operation
Complete on-chip video timing generator
Programmable multimode master/slave operation
Macrovision® AntiTaping Rev. 7.1 (ADV7170 only) 3
Closed captioning support
Teletext insertion port (PAL-WST)
On-board color bar generation
On-board voltage reference
2-wire serial MPU interface (I2C®-compatible and Fast I2C)
Single supply 5 V or 3.3 V operation
Small 44-lead MQFP/TQFP packages
Industrial temperature grade = −40°C to +85°C 4
FEATURES
1
ITU-R BT601/656 YCrCb to PAL/NTSC video encoder
High quality 10-bit video DACs
SSAF (super sub-alias filter)
Advanced power management features
CGMS (copy generation management system)
WSS (wide screen signalling)
Simultaneous Y, U, V, C output format
NTSC M, PAL M/N 2 , PAL B/D/G/H/I, PAL60
Single 27 MHz clock required (×2 oversampling)
80 dB video SNR
32-bit direct digital synthesizer for color subcarrier
Multistandard video output support
Composite (CVBS)
Components S-Video (Y/C), YUV, and RGB
EuroSCART output (RGB + CVBS/LUMA)
Component YUV + CHROMA
Video input data port supports
CCIR-656 4:2:2 8-bit parallel input format
4:2:2 16-bit parallel input format
Programmable simultaneous composite and S-Video or RGB
(SCART)/YUV video outputs
Programmable luma filters (low-pass [PAL/NTSC]) notch,
extended (SSAF, CIF, and QCIF)
Programmable chroma filters (low-pass [0.65 MHz, 1.0 MHz,
1.2 MHz and 2.0 MHz], CIF and QCIF)
Programmable VBI (vertical blanking interval)
Programmable subcarrier frequency and phase
APPLICATIONS
High performance DVD playback systems, portable video
equipment including digital still cameras and laptop PCs,
video games, PC video/multimedia and digital
satellite/cable systems (set-top boxes/IRD)
1
ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced
CCIR recommendations).
2
Throughout the document N is referenced to PAL- Combination -N.
3
Protected by U.S. Patents 4,631,603;, 4,577,216, 4,819,098; and other intellectual
property rights. The Macrovision anticopy process is licensed for noncommercial
home use only, which is its sole intended use in the device. Please contact sales
office for latest Macrovision version available.
4
Refer to Table 8 for complete operating details.
VAA
POWER
MANAGEMENT
CONTROL
(SLEEP MODE)
TTX
10
CGMS AND WSS
INSERTION
BLOCK
TELETEXT
INSERTION
BLOCK
YUV TO
RGB
MATRIX
10
RESET
COLOR
DATA
P7–P0
P15–P8
HSYNC
FIELD/VSYNC
BLANK
10
8
Y 8
4:2:2 TO
8
4:4:4
INTERPOLATOR
8
YCrCb
TO
YUV U 8
MATRIX
V 8
VIDEO TIMING
GENERATOR
CLOCK
ADD
SYNC
9
8
ADD
BURST 8
INTERPOLATOR
8
INTERPOLATOR 8
SDATA
PROGRAMMABLE
LUMINANCE
FILTER
10
PROGRAMMABLE
CHROMINANCE 10
FILTER
REAL-TIME
CONTROL
CIRCUIT
I2C MPU PORT
SCLOCK
9
ALSB
SCRESET/RTC
10
M
U 10
L
T
I 10
P
L
E
X 10
E
R
10-BIT
DAC
DAC D (PIN 27)
10-BIT
DAC
DAC C (PIN 26)
10-BIT
DAC
DAC B (PIN 31)
10-BIT
DAC
DAC A (PIN 32)
U
10
V
10
10
SIN/COS
DDS BLOCK
ADV7170/ADV7171
VOLTAGE
REFERENCE
CIRCUIT
GND
VREF
RSET
COMP
00221-001
TTXREQ
Figure 1. Functional Block Diagram
Protected by U.S. Patents 5,343,196; 5,442,355; and other intellectual property rights.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
www.analog.com
Tel: 781.329.4700
Fax: 781.461.3113 ©2002–2009 Analog Devices, Inc. All rights reserved.
ADV7170/ADV7171
TABLE OF CONTENTS
Specifications..................................................................................... 4
Mode Register 1 MR1 (MR17 to MR10) ................................. 30
Dynamic Specifications ............................................................... 6
MR1 Bit Description .................................................................. 30
Timing Specifications .................................................................. 7
Mode Register 2 MR2 (MR27 to MR20) ................................. 30
Timing Diagrams.......................................................................... 9
MR2 Bit Description .................................................................. 30
Absolute Maximum Ratings.......................................................... 10
Mode Register 3 MR3 (MR37 to MR30) .................................... 32
Package Thermal Performance ................................................. 10
MR3 Bit Description.................................................................... 32
ESD Caution ................................................................................ 10
Mode Register 4 MR4 (MR47 to MR40) ................................. 33
Pin Configuration and Function Descriptions ........................... 11
MR4 Bit Description .................................................................. 33
General Description ....................................................................... 13
VSYNC_3H (MR43) .................................................................. 33
Data Path Description................................................................ 13
Timing Mode Register 0 (TR07 to TR00) ............................... 33
Internal Filter Response ............................................................. 14
TR0 Bit Description ................................................................... 34
Typical Performance Characteristics ........................................... 15
Timing Mode Register 1 (TR17 to TR10) ............................... 34
Features ............................................................................................ 18
TR1 Bit Description ................................................................... 34
Color Bar Generation ................................................................ 18
Subcarrier Frequency Registers 0 to 3 (FSC3 to FSC0)......... 35
Square Pixel Mode ...................................................................... 18
Subcarrier Phase Registers (FP7 to FP0)................................. 35
Color Signal Control .................................................................. 18
Closed Captioning Even Field Data Register 1 to 0 (CED15 to
CED0) .......................................................................................... 35
Burst Signal Control ................................................................... 18
NTSC Pedestal Control ............................................................. 18
Pixel Timing Description .......................................................... 18
Subcarrier Reset .......................................................................... 18
Closed Captioning Odd Field Data Registers 1 to 0 (CCD15
to CCD0) ..................................................................................... 35
NTSC Pedestal/PAL Teletext Control Registers 3 to 0 (PCE15
to PCE0, PCO15 to PCO0)/(TXE15 to TXE0, TXO15 to
TXO0) .......................................................................................... 36
Real-Time Control ..................................................................... 18
Teletext Request Control Register TC07 (TC07 to TC00) .... 36
Video Timing Description ........................................................ 18
CGMS_WSS Register 0 C/W0 (C/W07 to C/W00) .............. 36
Power-On Reset .......................................................................... 26
C/W0 Bit Description ................................................................ 36
SCH Phase Mode ........................................................................ 26
CGMS_WSS Register 1 C/W1 (C/W17 to C/W10) .............. 37
MPU Port Description ............................................................... 26
C/W1 Bit Description ................................................................ 37
Register Accesses ........................................................................ 27
CGMS Data Bits (C/W17 to C/W16) ...................................... 37
Register Programming ................................................................... 28
CGMS_WSS Register 2 C/W1 (C/W27 to C/W20) .............. 37
Subaddress Register (SR7 to SR0) ............................................ 28
C/W2 Bit Description ................................................................ 37
Register Select (SR5 to SR0) ...................................................... 28
Appendices ...................................................................................... 38
Mode Register 0 MR0 (MR07 to MR00) ................................. 28
Appendix 1—Board Design and Layout Considerations...... 38
MR0 Bit Description .................................................................. 28
Rev. C | Page 2 of 64
ADV7170/ADV7171
Appendix 2—Closed Captioning ..............................................40
Appendix 7—Optional Output Filter ....................................... 48
Appendix 3—Copy Generation Management System
(CGMS) ........................................................................................41
Appendix 8—Optional DAC Buffering ................................... 48
Appendix 4—Wide Screen Signaling .......................................42
Appendix 5—Teletext Insertion ................................................43
Appendix 6—Waveforms ...........................................................44
Appendix 9—Recommended Register Values ........................ 49
Appendix 10—Output Waveforms ........................................... 51
Outline Dimensions ........................................................................ 61
Ordering Guide ........................................................................... 62
REVISION HISTORY
3/09—Rev. B to Rev. C
Changes to Table 8 ..........................................................................10
Updated Outline Dimensions ........................................................61
Added Figure 103, Renumbered Figures Sequentially ...............61
Changes to Ordering Guide ...........................................................61
6/05—Rev. A to Rev. B
Updated Format.................................................................. Universal
Changes to Features Section ............................................................ 1
Changes to Table 8 ..........................................................................10
Changes to Square Pixel Mode Section ........................................18
Changes to Figure 37 ......................................................................29
Changes to Figure 42 ......................................................................33
Changes to Subcarrier Frequency Registers 3 to 0 Section .......35
Changes to Figure 45 ......................................................................35
Changes to Figure 82 ......................................................................48
Changes to Ordering Guide ...........................................................62
6/02—Starting Rev. A to Rev. B
Changes to Specifications ................................................................. 3
Changes to Package Thermal Performance section...9
Rev. C | Page 3 of 64
ADV7170/ADV7171
SPECIFICATIONS
VAA = 5 V ± 5% 1 , VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX 2 , unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN
DIGITAL OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Three-State Leakage Current
Three-State Output Capacitance
ANALOG OUTPUTS
Output Current 3
Output Current 4
DAC-to-DAC Matching
Output Compliance, VOC
Output Impedance, ROUT
Output Capacitance, COUT
VOLTAGE REFERENCE
Reference Range, VREF
POWER REQUIREMENTS 5
VAA
Normal Power Mode
IDAC (max) 6
IDAC (min)6
ICCT 7
Low Power Mode
IDAC (max)6
IDAC (min)6
ICCT7
Sleep Mode
IDAC 8
ICCT 9
Power Supply Rejection Ratio
1
Conditions1
Min
RSET = 300 Ω
Guaranteed monotonic
Typ
Max
Unit
10
Bits
±1
LSB
LSB
±0.6
2
0.8
±1
10
V
V
μA
pF
0.4
10
10
V
V
μA
pF
VIN = 0.4 V or 2.4 V
ISOURCE = 400 μA
ISINK = 3.2 mA
RSET = 150 Ω, RL = 37.5 Ω
RSET = 1041 Ω, RL = 262.5 Ω
2.4
3
34.7
5
1.5
0
37
30
mA
mA
%
V
kΩ
pF
+1.4
30
IOUT = 0 mA
IVREFOUT = 20 μA
RSET = 150 Ω, RL = 37.5 Ω
RSET = 1041 Ω, RL = 262.5 Ω
1.142
1.235
1.327
V
4.75
5.0
5.25
V
150
20
75
155
95
mA
mA
mA
95
mA
mA
mA
0.5
μA
μA
%/%
80
20
75
COMP = 0.1 μF
0.1
0.001
0.01
The min/max specifications are guaranteed over this range. The min/max values are typical over 4.75 V to 5.25 V.
Ambient temperature range TMIN to TMAX: −40°C to +85°C. The die temperature, TJ, must always be kept below 110°C.
3
Full drive into 37.5 Ω doubly terminated load.
4
Minimum drive current (used with buffered/scaled output load).
5
Power measurements are taken with clock frequency = 27 MHz. Max TJ = 110°C.
6
IDAC is the total current (min corresponds to 5 mA output per DAC; max corresponds to 37 mA output per DAC) to drive all four DACs. Turning off individual DACs
reduces IDAC correspondingly.
7
ICCT (circuit current) is the continuous current required to drive the device.
8
Total DAC current in sleep mode.
9
Total continuous current during sleep mode.
Rev. C | Page 4 of 64
2
ADV7170/ADV7171
VAA = 3.0 V to 3.6 V 1 , VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX 2 , unless otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE 3
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS3
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN3, 4
Input Capacitance, CIN
DIGITAL OUTPUTS3
Output High Voltage, VOH
Output Low Voltage, VOL
Three-State Leakage Current
Three-State Output Capacitance
ANALOG OUTPUTS3
Output Current4, 5
Output Current 6
DAC-to-DAC Matching
Output Compliance, VOC
Output Impedance, ROUT
Output Capacitance, COUT
POWER REQUIREMENTS3, 7
VAA
Normal Power Mode
IDAC (max) 8
IDAC (min)8
ICCT 9
Low Power Mode
IDAC (max)8
IDAC (min)8
ICCT9
Sleep Mode
IDAC 10
ICCT 11
Power Supply Rejection Ratio
Conditions1
Min
RSET = 300 Ω
Guaranteed monotonic
Typ
Max
Unit
10
Bits
±1
LSB
LSB
±0.6
2
VIN = 0.4 V or 2.4 V
0.8
±1
V
V
μA
pF
0.4
10
V
V
μA
pF
10
ISOURCE = 400 μA
ISINK = 3.2 mA
2.4
10
RSET = 150 Ω, RL = 37.5 Ω
RSET = 1041 Ω, RL = 262.5 Ω
33
34.7
5
2.0
30
mA
mA
%
V
kΩ
pF
3.3
3.6
V
150
20
35
155
mA
mA
mA
0
37
1.4
30
IOUT = 0 mA
3.0
RSET = 150 Ω, RL = 37.5 Ω
RSET = 1041 Ω, RL = 262.5 Ω
COMP = 0.1 μF
1
80
20
35
mA
mA
mA
0.1
0.001
0.01
μA
μA
%/%
0.5
The min/max specifications are guaranteed over this range. The min/max values are typical over 3.0 V to 3.6 V.
Ambient temperature range TMIN to TMAX: −40°C to +85°C. The die temperature, TJ, must always be kept below 110°C.
3
Guaranteed by characterization.
4
Full drive into 37.5 Ω load.
5
DACs can output 35 mA typically at 3.3 V (RSET = 150 Ω and RL = 37.5 Ω); optimum performance obtained at 18 mA DAC current (RSET = 300 Ω and RL = 75 Ω).
6
Minimum drive current (used with buffered/scaled output load).
7
Power measurements are taken with clock frequency = 27 MHz. Max TJ = 110°C.
8
IDAC is the total current (min corresponds to 5 mA output per DAC, max corresponds to 38 mA output per DAC) to drive all four DACs. Turning off individual DACs
reduces IDAC correspondingly.
9
ICCT (circuit current) is the continuous current required to drive the device.
10
Total DAC current in sleep mode.
11
Total continuous current during sleep mode.
2
Rev. C | Page 5 of 64
ADV7170/ADV7171
DYNAMIC SPECIFICATIONS
VAA = 5 V ± 5% 1 , VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX 2 , unless otherwise noted.
Table 3.
Parameter
Differential Gain 3, 4
Differential Phase3, 4
Differential Gain3, 4
Differential Phase3, 4
SNR3, 4(Pedestal)
SNR3, 4(Pedestal)
SNR3, 4(Ramp)
SNR3, 4(Ramp)
Hue Accuracy3, 4
Color Saturation Accuracy3, 4
Chroma Nonlinear Gain3, 4
Chroma Nonlinear Phase3 4
Chroma/Luma Intermod3, 4
Chroma/Luma Gain Inequality3, 4
Chroma/Luma Delay Inequality3, 4
Luminance Nonlinearity3, 4
Chroma AM Noise3, 4
Chroma PM Noise3, 4
Conditions1
Normal power mode
Normal power mode
Lower power mode
Lower power mode
RMS
Peak periodic
RMS
Peak periodic
Min
Typ
0.3
0.4
1.0
1.0
80
70
60
58
0.7
0.9
0.6
0.3
0.2
1.0
0.5
0.8
85
81
Referenced to 40 IRE
82
79
Max
0.7
0.7
2.0
2.0
1.2
1.4
0.5
0.4
1.4
2.0
1.4
Unit
%
Degrees
%
Degrees
dB rms
dB p-p
dB rms
dB p-p
Degrees
%
±%
±Degrees
±%
±%
ns
±%
dB
dB
1
The min/max specifications are guaranteed over this range. The min/max values are typical over 4.75 V to 5.25 V.
Ambient temperature range TMIN to TMAX: −40°C to +85°C. The die temperature, TJ, must always be kept below 110°C.
3
Guaranteed by characterization.
4
These specifications are for the low-pass filter only and are guaranteed by design.
2
VAA = 3.0 V to 3.6 V 1 , VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX 2 , unless otherwise noted.
Table 4.
Parameter
Differential Gain 3
Differential Phase3
Differential Gain3
Differential Phase3
SNR3 (Pedestal)
SNR3 (Pedestal)
SNR3 (Ramp)
SNR3 (Ramp)
Hue Accuracy3
Color Saturation Accuracy3
Luminance Nonlinearity3, 4
Chroma AM Noise3, 4
Chroma PM Noise3, 4
Chroma Nonlinear Gain3, 4
Chroma Nonlinear Phase3, 4
Chroma/Luma Intermod3, 4
Conditions1
Normal power mode
Normal power mode
Lower power mode
Lower power mode
RMS
Peak periodic
RMS
Peak periodic
Referenced to 40 IRE
1
Min
Typ
1.0
0.5
0.6
0.5
78
70
60
58
1.0
1.0
1.4
80
79
0.6
0.3
0.2
The min/max specifications are guaranteed over this range. The min/max values are typical over 4.75 V to 5.25 V.
Ambient temperature range TMIN to TMAX: −40°C to +85°C. The die temperature, TJ, must always be kept below 110°C.
3
Guaranteed by characterization.
4
These specifications are for the low-pass filter only and are guaranteed by design. For other internal filters, see Table 10.
2
Rev. C | Page 6 of 64
Max
0.5
0.4
Unit
%
Degrees
%
Degrees
dB rms
dB p-p
dB rms
dB p-p
Degrees
%
±%
dB
dB
±%
±Degrees
±%
ADV7170/ADV7171
TIMING SPECIFICATIONS
VAA = 4.75 V to 5.25 V 1 , VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX 2 , unless otherwise noted.
Table 5.
Parameter
MPU PORT 3, 4
SCLOCK Frequency
SCLOCK High Pulse Width, t1
SCLOCK Low Pulse Width, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
ANALOG OUTPUTS3, 5
Analog Output Delay
DAC Analog Output Skew
CLOCK CONTROL AND PIXEL PORT5, 6
fCLOCK
Clock High Time, t9
Clock Low Time, t10
Data Setup Time, t11
Data Hold Time, t12
Control Setup Time, t11
Control Hold Time, t12
Digital Output Access Time, t13
Digital Output Hold Time, t144
Pipeline Delay, t154
TELETEXT3, 4, 7
Digital Output Access Time, t16
Data Setup Time, t17
Data Hold Time, t18
RESET CONTROL3, 4
RESET Low Time
Conditions
Min
After this period the first clock is generated
Relevant for repeated start condition
Typ
0
0.6
1.3
0.6
0.6
100
Max
Unit
400
kHz
μs
μs
μs
μs
ns
ns
ns
μs
300
300
0.6
7
0
ns
ns
27
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock cycles
8
8
3.5
4
4
3
11
8
48
20
2
6
6
1
16
ns
ns
ns
ns
The min/max specifications are guaranteed over this range. The min/max values are typical over 4.75 V to 5.25 V range.
Ambient temperature range TMIN to TMAX: −40°C to +85°C. The die temperature, TJ, must always be kept below 110°C.
3
TTL input values are 0 V to 3 V, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Analog output load ≤ 10 pF.
4
Guaranteed by characterization
5
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6
Pixel port consists of the following:
Pixel inputs:
P15–P0
HSYNC, FIELD/VSYNC, BLANK
Pixel controls:
Clock input:
CLOCK
7
Teletext port consists of the following:
Teletext output: TTXREQ
Teletext input: TTX
2
Rev. C | Page 7 of 64
ADV7170/ADV7171
VAA = 3.0 V to 3.6 V 1 , VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX 2 , unless otherwise noted.
Table 6.
Parameter
MPU PORT 3, 4
SCLOCK Frequency
SCLOCK High Pulse Width, t1
SCLOCK Low Pulse Width, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
ANALOG OUTPUTS3, 5
Analog Output Delay
DAC Analog Output Skew
CLOCK CONTROL AND PIXEL PORT4, 5, 6
fCLOCK
Clock High Time, t9
Clock Low Time, t10
Data Setup Time, t11
Data Hold Time, t12
Control Setup Time, t11
Control Hold Time, t12
Digital Output Access Time, t13
Digital Output Hold Time, t14
Pipeline Delay, t15
TELETEXT3, 4, 7
Digital Output Access Time, t16
Data Setup Time, t17
Data Hold Time, t18
RESET CONTROL3, 4
RESET Low Time
Conditions
Min
After this period the first clock is generated
Relevant for repeated start condition
Typ
0
0.6
1.3
0.6
0.6
100
Max
Unit
400
kHz
μs
μs
μs
μs
ns
ns
ns
μs
300
300
0.6
7
0
ns
ns
27
12
8
48
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock cycles
23
2
6
ns
ns
ns
8
8
3.5
4
4
3
6
1
ns
The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V range.
Ambient temperature range TMIN to TMAX: −40°C to +85°C. The die temperature, TJ, must always be kept below 110°C.
TTL input values are 0 V to 3 V, with input rise/fall times ≤3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Analog output load ≤10 pF.
4
Guaranteed by characterization
5
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition
6
Pixel Port consists of the following:
Pixel inputs:
P15–P0
Pixel controls: HSYNC, FIELD/VSYNC, BLANK
Clock input:
CLOCK
7
Teletext port consists of the following:
Teletext output: TTXREQ
Teletext input: TTX
2
3
Rev. C | Page 8 of 64
ADV7170/ADV7171
TIMING DIAGRAMS
t3
t5
t3
SDATA
SCLOCK
t2
t4
t7
t8
00221-002
t1
t6
Figure 2. MPU Port Timing Diagram
CLOCK
t9
HSYNC,
FIELD/VSYNC,
BLANK
PIXEL INPUT
DATA
Cb
Y
Cr
Y
t11
CONTROL
O/PS
Cb
Y
t13
HSYNC,
FIELD/VSYNC,
BLANK
00221-003
CONTROL
I/PS
t12
t10
t14
Figure 3. Pixel and Control Data Timing Diagram
TTXREQ
t16
CLOCK
t17
t18
4 CLOCK
CYCLES
4 CLOCK
CYCLES
4 CLOCK
CYCLES
Figure 4. Teletext Timing Diagram
Rev. C | Page 9 of 64
3 CLOCK
CYCLES
4 CLOCK
CYCLES
00221-004
TTX
ADV7170/ADV7171
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter
VAA to GND
Voltage on Any Digital Input Pin
Storage Temperature (TS)
Junction Temperature (TJ)
Lead Temperature (Soldering, 10 sec)
Analog Outputs to GND 1
1
Rating
7V
GND − 0.5 V to VAA + 0.5 V
−65°C to +150°C
150°C
260°C
GND − 0.5 V to VAA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability. Only one absolute maximum rating may
be applied at any one time.
Analog output short circuit to any power supply or GND can be of an
indefinite duration.
PACKAGE THERMAL PERFORMANCE
The 44-MQFP package used for this device takes advantage of
an ADI patented thermal coastline lead frame construction.
This maximizes heat transfer into the leads and reduces the
package thermal resistance.
For the MQFP package, the junction-to-ambient (θJA) thermal
resistance in still air on a four-layer PCB is 35.5°C/W. The
junction-to-case thermal resistance (θJC) is 13.75°C/W. For the
TQFP package, θJA in still air on a four-layer PCB is 53.2°C/W.
θJC is 11.1°C/W. Junction Temperature = TJ = [VAA (Σ DAC
Output Current + ICCT) × θJA] + Ambient Temperature.
Table 8. Allowable Operating Conditions for KS and KSU
Package Options
Conditions
4 DAC ON Double 75R 1
4 DAC ON Low Power 2
4 DAC ON Buffering 3
3 DAC ON Double 75R
3 DAC ON Low Power
3 DAC ON Buffering
Yes
Yes
4 DAC ON Buffering
3V
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
KS, WBS
5V
+70°C max
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1
KSU
3V
+70°C max
Yes
Yes
Yes
Yes
Yes
Yes
5V
No
No
Yes
No
Yes
Yes
Yes
DAC ON Double 75R refers to a condition where the DACs are terminated
in a double 75R load and low power mode is disabled.
2
DAC ON Low Power refers to a condition where the DACs are terminated
in a double 75R load and low power mode is enabled.
3
DAC ON Buffering refers to a condition where the DAC current is reduced
to 5 mA and external buffers are used to drive the video load.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. C | Page 10 of 64
ADV7170/ADV7171
44 43 42 41 40 39 38
RSET
SCRESET/RTC
TTXREQ
TTX
P0
P1
P2
P3
P4
GND
CLOCK
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
37 36 35 34
VAA 1
33
VREF
32
DAC A
31
DAC B
30
VAA
29
GND
28
VAA
27
DAC D
P11 8
26
DAC C
P12 9
25
COMP
GND 10
24
SDATA
VAA 11
23
SCLOCK
PIN 1
P5 2
P6 3
ADV7170/ADV7171
P7 4
MQFP/TQFP
P8 5
P9 6
TOP VIEW
(Not to Scale)
P10 7
00221-005
RESET
GND
VAA
GND
ALSB
BLANK
FIELD/VSYNC
HSYNC
P15
P14
P13
12 13 14 15 16 17 18 19 20 21 22
Figure 5. Pin Configuration
Table 9. Pin Function Descriptions
Pin No.
1, 11, 20, 28, 30
2 to 9, 12 to 14,
38 to 42
10, 19, 21, 29, 43
15
Mnemonic
VAA
P15 to P0
Input/
Output
P
I
GND
HSYNC
G
I/O
16
FIELD/VSYNC
I/O
17
BLANK
I/O
18
22
ALSB
RESET
I
I
23
24
25
SCLOCK
SDATA
COMP
I
I/O
O
26
27
31
32
DAC C
DAC D
DAC B
DAC A
O
O
O
O
33
34
VREF
RSET
I/O
I
Description
Power Supply (3 V to 5 V).
8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7 to P0) or 16-Bit YCrCb Pixel Port (P15 to P0).
P0 represents the LSB.
Ground Pin.
HSYNC (Mode 1 and Mode 2) Control Signal. This pin may be configured to output (master
mode) or accept (slave mode) sync signals.
Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. This pin may be
configured to output (master mode) or accept (slave mode) these control signals.
Video Blanking Control Signal. The pixel inputs are ignored when this is Logic Level 0. This
signal is optional.
TTL Address Input. This signal sets up the LSB of the MPU address.
The input resets the on-chip timing generator and sets the ADV7170/ADV7171 into default
mode. This is NTSC operation, Timing Slave Mode 0, 8-bit operation, 2 × composite and
S-Video out, and DAC B powered on and DAC D powered off.
MPU Port Serial Interface Clock Input.
MPU Port Serial Data Input/Output.
Compensation Pin. Connect a 0.1 μF capacitor from COMP to VAA. For optimum dynamic
performance in low power mode, the value of the COMP capacitor can be lowered to as low
as 2.2 nF.
RED/S-Video C/V Analog Output.
GREEN/S-Video Y/Y Analog Output.
BLUE/Composite/U Analog Output.
PAL/NTSC Composite Video Output. Full-scale output is 180 IRE (1286 mV) for NTSC and
1300 mV for PAL.
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
A 150 Ω resistor connected from this pin to GND is used to control full-scale amplitudes
of the video signals.
Rev. C | Page 11 of 64
ADV7170/ADV7171
Pin No.
35
Mnemonic
SCRESET/RTC
Input/
Output
I
36
TTXREQ
O
37
TTX
I
44
CLOCK
I
Description
This pin can be configured as an input by setting MR22 and MR21 of Mode Register 2.
It can be configured as a subcarrier reset pin, in which case a low-to-high transition on this
pin resets the subcarrier to Field 0. Alternatively, it may be configured as a real-time control
(RTC) input.
Teletext Data Request Signal. Defaults to GND when teletext not selected. Enables
backward compatibility to ADV7175/ADV7176.
Teletext Data. Defaults to VAA when teletext not selected. Enables backward compatibility
to ADV7175/ADV7176.
TTL Clock Input. Requires a stable 27 MHz reference clock for standard operation.
Alternatively, a 24.5454 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel
operation.
Rev. C | Page 12 of 64
ADV7170/ADV7171
GENERAL DESCRIPTION
The ADV7170/ADV7171 are integrated digital video encoders
that convert digital CCIR-601 4:2:2 8- or 16-bit component
video data into a standard analog baseband television signal
compatible with worldwide standards.
The on-board SSAF (super sub-alias filter) with extended
luminance frequency response and sharp stop band attenuation
enables studio-quality video playback on modern TVs, giving
optimal horizontal line resolution.
An advanced power management circuit enables optimal
control of power consumption in both normal operating modes
and power-down or sleep modes.
The ADV7170/ADV7171 support both PAL and NTSC square
pixel operation. The parts also incorporate WSS and CGMS-A
data control generation.
The output video frames are synchronized with the incoming
data timing reference codes. Optionally, the encoder accepts
and can generate HSYNC, VSYNC, and FIELD timing signals.
These timing signals can be adjusted to change pulse width and
position while the part is in the master mode. The encoder
requires a single, two-times pixel rate (27 MHz) clock for
standard operation. Alternatively, the encoder requires a
24.5454 MHz clock for NTSC or 29.5 MHz clock for PAL
square pixel mode operation. All internal timing is generated
on-chip.
A separate teletext port enables the user to directly input teletext
data during the vertical blanking interval.
DATA PATH DESCRIPTION
For PAL B/D/G/H/I/M/N, and NTSC M and N modes, YcrCb
4:2:2 data is input via the CCIR-656 compatible pixel port at a
27 MHz data rate. The pixel data is demultiplexed to form three
data paths. Y typically has a range of 16 to 235; Cr and Cb
typically have a range of 128 ± 112. However, it is possible to
input data from 1 to 254 on Y, Cb, and Cr. The ADV7170/
ADV7171 support PAL (B, D, G, H, I, M, N) and NTSC (with
and without pedestal) standards. The appropriate SYNC,
BLANK, and burst levels are added to the YCrCb data.
Macrovision antitaping (ADV7170 only), closed-captioning,
and teletext levels are also added to Y, and the resultant data
is interpolated to a rate of 27 MHz. The interpolated data is
filtered and scaled by three digital FIR filters.
The U and V signals are modulated by the appropriate subcarrier sine/cosine phases and added together to make up the
chrominance signal. The luma (Y) signal can be delayed 1 to
3 luma cycles (each cycle is 74 ns) with respect to the chroma
signal. The luma and chroma signals are then added together to
make up the composite video signal. All edges are slew rate
limited.
The YCrCb data is also used to generate RGB data with
appropriate SYNC and BLANK levels. The RGB data is in
synchronization with the composite video output. Alternatively,
analog YUV data can be generated instead of RGB.
The four 10-bit DACs can be used to output the following:
Composite video + RGB video.
The ADV7170/ADV7171 modes are set up over a 2-wire, serial
bidirectional port (I2C-compatible) with two slave addresses.
Functionally, the ADV7170 and ADV7171 are the same with the
exception that the ADV7170 can output the Macrovision
anticopy algorithm.
The ADV7170/ADV7171 are packaged in a 44-lead MQFP
package and a 44-lead TQFP package.
Composite video + YUV video.
Two composite video signals + LUMA
and CHROMA (Y/C) signals.
Alternatively, each DAC can be individually powered off if not
required.
Video output levels are illustrated in Appendix 6—Waveforms.
Rev. C | Page 13 of 64
ADV7170/ADV7171
INTERNAL FILTER RESPONSE
The Y filter supports several different frequency responses, including two low-pass responses, two notch responses, an extended (SSAF)
response, a CIF response, and a QCIF response. The UV filter supports several different frequency responses, including four low-pass
responses, a CIF response, and a QCIF response that are shown in Table 10 and Table 11 and Figure 6 to Figure 18.
Table 10. Luminance Internal Filter Specifications
Filter Type
Low Pass (NTSC)
Low Pass (PAL)
Notch (NTSC)
Notch (PAL)
Extended (SSAF)
CIF
QCIF
Filter Selection
MR04 MR03 MR02
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
Pass-Band Ripple
(dB)
0.091
0.15
0.015
0.095
0.051
0.018
Monotonic
3 dB Bandwidth
(MHz)
4.157
4.74
6.54
6.24
6.217
3.0
1.5
Stop-Band
Cutoff (MHz)
7.37
7.96
8.3
8.0
8.0
7.06
7.15
Stop-Band Attenuation
(dB)
−56
−64
−68
−66
−61
−61
−50
Pass-Band Ripple
(dB)
0.084
Monotonic
Monotonic
0.0645
3 dB Bandwidth
(MHz)
1.395
0.65
1.0
2.2
Stop-Band
Cutoff (MHz)
3.01
3.64
3.73
5.0
Stop-Band Attenuation
(dB)
−45
−58.5
−49
−40
0.084
Monotonic
0.7
0.5
3.01
4.08
−45
−50
Table 11. Chrominance Internal Filter Specifications
Filter Type
1.3 MHz Low Pass
.65 MHz Low Pass
1.0 MHz Low Pass
2.0 MHz Low Pass
Reserved
CIF
QCIF
Filter Selection
MR07 MR06 MR05
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
Rev. C | Page 14 of 64
ADV7170/ADV7171
0
–10
–10
–20
–20
–30
–40
–30
–40
–50
–50
–60
–60
–70
0
2
4
6
8
10
00221-009
MAGNITUDE (dB)
0
00221-006
MAGNITUDE (dB)
TYPICAL PERFORMANCE CHARACTERISTICS
–70
0
12
2
4
10
12
0
0
–10
–10
–20
MAGNITUDE (dB)
–20
–30
–40
–30
–40
–50
–50
–60
00221-007
–60
–70
0
2
4
6
8
10
00221-010
MAGNITUDE (dB)
8
Figure 9. PAL Notch Luma Filter
Figure 6. NTSC Low-Pass Luma Filter
–70
0
12
2
4
6
8
10
12
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 10. Extended Mode (SSAF) Luma Filter
Figure 7. PAL Low-Pass Luma Filter
0
0
–10
–10
–20
MAGNITUDE (dB)
–20
–30
–40
–30
–40
–50
–50
–70
0
2
4
6
8
10
00221-011
–60
–60
00221-008
MAGNITUDE (dB)
6
FREQUENCY (MHz)
FREQUENCY (MHz)
–70
0
12
2
4
6
8
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 11. CIF Luma Filter
Figure 8. NTSC Notch Luma Filter
Rev. C | Page 15 of 64
10
12
0
–10
–10
–20
–20
–30
–40
–30
–40
–50
–50
–60
–60
–70
0
2
4
6
8
10
00221-015
MAGNITUDE (dB)
0
00221-012
MAGNITUDE (dB)
ADV7170/ADV7171
–70
0
12
2
4
FREQUENCY (MHz)
0
–10
–10
–20
–20
–30
–40
–40
–50
–60
–60
–70
6
8
10
–70
0
12
2
4
FREQUENCY (MHz)
–10
–20
–20
–30
–40
–40
–50
–60
–60
–70
8
12
–30
–50
6
10
10
00221-017
MAGNITUDE (dB)
–10
00221-014
MAGNITUDE (dB)
0
4
8
Figure 16. 2.0 MHz Low-Pass Chroma Filter
0
2
6
FREQUENCY (MHz)
Figure 13. 1.3 MHz Low-Pass Chroma Filter
0
12
–30
–50
4
10
00221-016
MAGNITUDE (dB)
0
2
8
Figure 15. 1.0 MHz Low-Pass Chroma Filter
00221-013
MAGNITUDE (dB)
Figure 12. QCIF Luma Filter
0
6
FREQUENCY (MHz)
–70
0
12
FREQUENCY (MHz)
2
4
6
8
FREQUENCY (MHz)
Figure 14. 0.65 MHz Low-Pass Chroma Filter
Figure 17. CIF Chroma Filter
Rev. C | Page 16 of 64
10
12
ADV7170/ADV7171
0
–10
–30
–40
–50
–60
00221-018
MAGNITUDE (dB)
–20
–70
0
2
4
6
8
10
12
FREQUENCY (MHz)
Figure 18. QCIF Chroma Filter
Rev. C | Page 17 of 64
ADV7170/ADV7171
FEATURES
COLOR BAR GENERATION
SUBCARRIER RESET
The ADV7170/ADV7171 can be configured to generate
100/7.5/75/7.5 color bars for NTSC or 100/0/75/0 color bars
for PAL. These are enabled by setting MR17 of Mode Register 1
to Logic Level 1.
Together with the SCRESET/RTC pin and Bit MR22 and
Bit MR21 of Mode Register 2, the ADV7170/ADV7171
can be used in subcarrier reset mode. The subcarrier resets
to Field 0 at the start of the following field when a low-to-high
transition occurs on this input pin.
SQUARE PIXEL MODE
The ADV7170/ADV7171 can be used to operate in square pixel
mode. For NTSC operation, an input clock of 24.5454 MHz is
required. Alternatively, for PAL operation, an input clock of 29.5
MHz is required. The internal timing logic adjusts accordingly
for square pixel mode operation. When the ADV7171 is
configured for PAL square pixel mode, it supports 768 active
pixels per line. NTSC square pixel mode supports 640 active
pixels per line.
COLOR SIGNAL CONTROL
The color information can be switched on and off the video
output using Bit MR24 of Mode Register 2.
BURST SIGNAL CONTROL
The burst information can be switched on and off the video
output using Bit MR25 of Mode Register 2.
REAL-TIME CONTROL
Together with the SCRESET/RTC pin and Bit MR22 and
Bit MR21 of Mode Register 2, the ADV7170/ADV7171 can be
used to lock to an external video source. The real-time control
mode allows the ADV7170/ADV7171 to automatically alter the
subcarrier frequency to compensate for line length variation.
When the part is connected to a device that outputs a digital
data stream in the RTC format (such as a ADV7185 video
decoder, shown in Figure 19), the part automatically changes to
the compensated subcarrier frequency on a line-by-line basis.
This digital data stream is 67 bits wide, and the subcarrier is
contained in Bit 0 to Bit 21. Each bit is 2 clock cycles long.
00Hex should be written into all four subcarrier frequency
registers when using this mode.
VIDEO TIMING DESCRIPTION
NTSC PEDESTAL CONTROL
The pedestal on both odd and even fields can be controlled on a
line-by-line basis using the NTSC pedestal control registers.
This allows the pedestals to be controlled during the vertical
blanking interval.
PIXEL TIMING DESCRIPTION
The ADV7170/ADV7171 operate in either 8-bit or 16-bit
YCrCb mode.
8-Bit YCrCb Mode
This default mode accepts multiplexed YCrCb inputs through
the P7 to P0 pixel inputs. The inputs follow the sequence Cb0,
Y0 Cr0, Y1 Cb1, Y2, and so on. The Y, Cb, and Cr data are input
on a rising clock edge.
16-Bit YCrCb Mode
This mode accepts Y inputs through the P7 to P0 pixel inputs
and multiplexed CrCb inputs through the P15 to P8 pixel
inputs. The data is loaded on every second rising edge of
CLOCK. The inputs follow the sequence Cb0, Y0 Cr0, Y1 Cb1,
Y2, and so on.
The ADV7170/ADV7171 are intended to interface to off-theshelf MPEG1 and MPEG2 decoders. Consequently, the
ADV7170/ADV7171 accept 4:2:2 YCrCb pixel data via a
CCIR-656 pixel port, and they have several video timing modes
of operation that allow them to be configured as either system
master video timing generators or as slaves to the system video
timing generator. The ADV7170/ADV7171 generate all of the
required horizontal and vertical timing periods and levels for
the analog video outputs.
The ADV7170/ADV7171 calculate the width and placement of
analog sync pulses, blanking levels, and color burst envelopes.
Color bursts are disabled on appropriate lines, and serration
and equalization pulses are inserted where required.
In addition, the ADV7170/ADV7171 support a PAL or NTSC
square pixel operation in slave mode. The part requires an input
pixel clock of 24.5454 MHz for NTSC and an input pixel clock of
29.5 MHz for PAL. The internal horizontal line counters place the
various video waveform sections in the correct location for the new
clock frequencies.
The ADV7170/ADV7171 have four distinct master and four
distinct slave timing configurations. Timing Control is established
with the bidirectional SYNC, BLANK, and FIELD/VSYNC pins.
Timing Mode Register 1 can also be used to vary the timing pulse
widths where they occur in relation to each other.
Rev. C | Page 18 of 64
ADV7170/ADV7171
CLOCK
COMPOSITE VIDEO
(FOR EXAMPLE,
VCR OR CABLE)
SCRESET/RTC
VIDEO
DECODER
(FOR EXAMPLE,
ADV7185)
GREEN/LUMA/Y
RED/CHROMA/V
P7–P0
BLUE/COMPOSITE/U
HSYNC
COMPOSITE
FIELD/VSYNC
ADV7170/ADV7171
H/LTRANSITION
COUNT START
SEQUENCE
RESERVED
BIT2 RESET
5 BITS
BIT3
RESERVED
4 BITS
RESERVED
LOW
128
13
14 BITS
RESERVED
0
FSCPLL INCREMENT1
21
0
RTC
TIME SLOT: 01
67 68
19
14
NOT USED IN
ADV7170/ADV7171
VALID
SAMPLE
INVALID
SAMPLE
8/LLC
NOTES:
1F PLL
SC
FSCPLL
00221-019
INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7170/ADV7171 FSC DDS REGISTER IS
INCREMENTS BITS 21:0 PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD
BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7170/ADV7171.
2SEQUENCE BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE
3RESET BIT
RESET ADV7170/ADV7171 DDS
Figure 19. RTC Timing and Connections
Vertical Blanking Data Insertion
Mode 0 (CCIR-656): Slave Option
It is possible to allow encoding of incoming YCbCr data on
those lines of VBI that do not bear line sync or pre-/postequalization pulses (see Figure 21 to Figure 32). This mode of
operation is called “partial blanking” and is selected by setting
MR32 to 1. It allows the insertion of any VBI data (opened VBI)
into the encoded output waveform. This data is present in the
digitized incoming YcbCr data stream (for example, WSS data,
CGMS, VPS, and so on). Alternatively, the entire VBI may be
blanked (no VBI data inserted) on these lines by setting MR32
to 0.
(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7170/ADV7171 are controlled by the SAV (start active
video) and EAV (end active video) time codes in the pixel data.
All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately
before and after each line during active picture and retrace.
Mode 0 is shown in Figure 20. The HSYNC, FIELD/VSYNC,
and BLANK (if not used) pins should be tied high during this
mode.
ANALOG
VIDEO
EAV CODE
4 CLOCK
0 F F A A A
0 F F B B B
C
C
8 1 8 1 F 0 0 X C Y C Y C
Y r Y b
b
0 0 0 0 F 0 0 Y b
r
ANCILLARY DATA
(HANC)
1440 CLOCK
4 CLOCK
4 CLOCK
PAL SYSTEM
(625 LINES/50Hz)
4 CLOCK
268 CLOCK
NTSC/PAL M SYSTEM
(525 LINES/60Hz)
280 CLOCK
1440 CLOCK
START OF ACTIVE
VIDEO LINE
END OF ACTIVE
VIDEO LINE
Figure 20. Timing Mode 0 (Slave Mode)
Rev. C | Page 19 of 64
00221-020
INPUT PIXELS
SAV CODE
C
F 0 0 X 8 1 8 1
Y
Y
r
F 0 0 Y 0 0 0 0
ADV7170/ADV7171
Mode 0 (CCIR-656): Master Option
(Timing Register 0 TR0 = X X X X X 0 0 1)
The ADV7170/ADV7171 generate H, V, and F signals required for the SAV (start active video) and EAV (end active video) time codes
in the CCIR656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin, and the F bit is output on the
FIELD/VSYNC pin. Mode 0 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL). The H, V, and F transitions relative to the video
waveform are illustrated in Figure 23.
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
H
V
F
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
H
F
ODD FIELD
00221-021
V
EVEN FIELD
Figure 21. Timing Mode 0 (NTSC Master Mode)
Rev. C | Page 20 of 64
ADV7170/ADV7171
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
5
6
7
21
22
23
H
V
EVEN FIELD
F
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
317
318
319
320
335
334
336
H
ODD FIELD
EVEN FIELD
Figure 22. Timing Mode 0 (PAL Master Mode)
ANALOG
VIDEO
H
F
00221-023
F
00221-022
V
V
Figure 23. Timing Mode 0 Data Transitions (Master Mode)
Rev. C | Page 21 of 64
ADV7170/ADV7171
Mode 1: Slave Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 0 1 0)
In this mode the ADV7170/ADV7171 accept horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input when
HSYNC is low indicates a new frame, that is, vertical retrace. The BLANK signal is optional. When the BLANK input is disabled,
the ADV7170/ADV7171 automatically blank all normally blank lines as per CCIR-624. Mode 1 is illustrated in Figure 24 (NTSC)
and Figure 25 (PAL).
DISPLAY
522
523
DISPLAY
VERTICAL BLANK
524
525
1
2
3
4
6
5
7
8
10
9
20
11
21
22
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
260
VERTICAL BLANK
261
262
263
264
265
266
267
268
269
270
271
272
273
283
274
284
285
HSYNC
FIELD
ODD FIELD
00221-024
BLANK
EVEN FIELD
Figure 24. Timing Mode 1 (NTSC)
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
6
5
7
21
22
23
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
309
310
VERTICAL BLANK
311
312
313
314
315
316
317
318
319
320
334
335
336
HSYNC
FIELD
ODD FIELD
00221-025
BLANK
EVEN FIELD
Figure 25. Timing Mode 1 (PAL)
Rev. C | Page 22 of 64
ADV7170/ADV7171
Mode 1: Master Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 0 1 1)
In this mode the ADV7170/ADV7171 can generate horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input when
HSYNC is low indicates a new frame, that is, vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the
ADV7170/ADV7171 automatically blank all normally blank lines as per CCIR-624. Pixel data is latched on the rising clock edge following
the timing signal transitions. Mode 1 is shown in Figure 24 (NTSC) and Figure 25 (PAL). Figure 26 illustrates the HSYNC, BLANK, and
FIELD for an odd or even field transition relative to the pixel data.
HSYNC
FIELD
PAL = 12 × CLOCK/2
NTSC = 16 × CLOCK/2
BLANK
Cb
Y
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Cr
Y
00221-026
PIXEL
DATA
Figure 26. Timing Mode 1 Odd/Even Field Transitions Master/Slave
Mode 2: Slave Option HSYNC, VSYNC, BLANK
(Timing Register 0 TR0 = X X X X X 1 0 0)
In this mode the ADV7170/ADV7171 accept horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and
VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The
BLANK signal is optional. When the BLANK input is disabled, the ADV7170/ADV7171 automatically blank all normally blank lines as
per CCIR-624. Mode 2 is illustrated in Figure 27 (NTSC) and Figure 28 (PAL).
DISPLAY
522
DISPLAY
VERTICAL BLANK
523
524
525
1
2
3
4
6
5
7
8
10
9
11
20
21
22
HSYNC
BLANK
EVEN FIELD
VSYNC
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
HSYNC
VSYNC
ODD FIELD
EVEN FIELD
Figure 27. Timing Mode 2 (NTSC)
Rev. C | Page 23 of 64
00221-027
BLANK
ADV7170/ADV7171
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
6
5
7
21
22
23
HSYNC
BLANK
VSYNC
ODD FIELD
EVEN FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
317
318
319
320
335
334
336
HSYNC
00221-028
BLANK
VSYNC
ODD FIELD
EVEN FIELD
Figure 28. Timing Mode 2 (PAL)
Mode 2: Master Option HSYNC, VSYNC, BLANK
(Timing Register 0 TR0 = X X X X X 1 0 1)
In this mode the ADV7170/ADV7171 can generate horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and
VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The
BLANK signal is optional. When the BLANK input is disabled, the ADV7170/ADV7171 automatically blank all normally blank lines as
per CCIR-624. Mode 2 is shown in Figure 27 (NTSC) and Figure 28 (PAL). Figure 29 shows the HSYNC, BLANK, and VSYNC for an
even-to-odd field transition relative to the pixel data. Figure 30 shows the HSYNC, BLANK, and VSYNC for an odd-to-even field
transition relative to the pixel data.
HSYNC
VSYNC
BLANK
PAL = 12 × CLOCK/2
NTSC = 16 × CLOCK/2
PIXEL
DATA
Y
Cr
Y
00221-029
Cb
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Figure 29. Timing Mode 2 Even-to-Odd Field Transition Master/Slave
HSYNC
VSYNC
PAL = 12 × CLOCK/2
NTSC = 16 × CLOCK/2
PAL = 864 × CLOCK/2
NTSC = 858 × CLOCK/2
BLANK
Y
Cr
Y
Cb
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Figure 30. Timing Mode 2 Odd-to-Even Field Transition Master/Slave
Rev. C | Page 24 of 64
00221-030
Cb
PIXEL
DATA
ADV7170/ADV7171
Mode 3: Master/Slave Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)
In this mode the ADV7170/ADV7171 accept or generate horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input
when HSYNC is high indicates a new frame, that is, vertical retrace. The BLANK signal is optional. When the BLANK input is disabled,
the ADV7170/ADV7171 automatically blank all normally blank lines as per CCIR-624. Mode 3 is shown in Figure 31 (NTSC) and Figure
32 (PAL).
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
1
2
3
4
6
5
7
8
9
10
11
20
21
22
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
260
VERTICAL BLANK
261
262
263
264
265
266
267
268
269
270
271
272
273
283
274
284
285
HSYNC
FIELD
ODD FIELD
00221-031
BLANK
EVEN FIELD
Figure 31. Timing Mode 3 (NTSC)
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
5
6
7
21
22
23
HSYNC
BLANK
EVEN FIELD
FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
317
318
319
320
334
335
336
HSYNC
FIELD
ODD FIELD
00221-032
BLANK
EVEN FIELD
Figure 32. Timing Mode 3 (PAL)
Rev. C | Page 25 of 64
ADV7170/ADV7171
1
After power-up, it is necessary to execute a reset operation.
A reset occurs on the falling edge of a high-to-low transition
on the RESET pin. This initializes the pixel port so that the pixel
inputs, P7 to P0, are selected. After reset, the ADV7170/
ADV7171 is automatically set up to operate in NTSC mode.
Subcarrier frequency code 21F07C16HEX is loaded into the
subcarrier frequency registers. All other registers, with the
exception of Mode Register 0, are set to 00H. All bits in
Mode Register 0 are set to Logic Level 0, except Bit MR44.
Bit MR44 of Mode Register 4 is set to Logic Level 1. This
enables the 7.5 IRE pedestal.
1
0
1
0
1
A1
X
ADDRESS
CONTROL
SET UP BY
ALSB
READ/WRITE
CONTROL
0
1
WRITE
READ
00221-033
POWER-ON RESET
Figure 33. ADV7170 Slave Address
0
1
0
1
0
1
A1
X
ADDRESS
CONTROL
SET UP BY
ALSB
SCH PHASE MODE
Resetting the SCH phase every four or eight fields avoids the
accumulation of SCH phase error and results in very minor
SCH phase jumps at the start of the four or eight field sequence.
Resetting the SCH phase should not be done if the video source
does not have stable timing or the ADV7170/ADV7171 are
configured in RTC mode (MR21 = 1 and MR22 = 1). Under
these conditions (unstable video), the subcarrier phase reset
should be enabled (MR22 = 0 and MR21 = 1) but no reset
applied. In this configuration the SCH phase is never reset,
which means the output video tracks the unstable input video.
The subcarrier phase reset, when applied, resets the SCH phase
to Field 0 at the start of the next field (for example, subcarrier
phase reset applied in Field 5 [PAL] on the start of the next field
SCH phase resets to Field 0).
MPU PORT DESCRIPTION
READ/WRITE
CONTROL
0
1
WRITE
READ
00221-034
The SCH phase is configured in default mode to reset every
four (NTSC) or eight (PAL) fields to avoid an accumulation of
SCH phase error over time. In an ideal system, zero SCH phase
error would be maintained forever, but in reality, this is
impossible to achieve due to clock frequency variations. This
effect is reduced by the use of a 32-bit DDS, which generates
this SCH.
Figure 34. ADV7171 Slave Address
To control the various devices on the bus, the following
protocol must be followed: first, the master initiates a data
transfer by establishing a start condition, defined by a high-tolow transition on SDATA while SCLOCK remains high. This
indicates that an address/data stream follows. All peripherals
respond to the start condition and shift the next eight bits
(7-bit address + R/RW bit). The bits transfer from MSB down to
LSB. The peripheral that recognizes the transmitted address
responds by pulling the data line low during the ninth clock
pulse. This is known as an acknowledge bit. All other devices
withdraw from the bus at this point and maintain an idle
condition. The idle condition is where the device monitors the
SDATA and SCLOCK lines waiting for the start condition and
the correct transmitted address. The R/RW bit determines the
direction of the data. A Logic Level 0 on the LSB of the first byte
means that the master writes information to the peripheral. A
Logic Level 1 on the LSB of the first byte means the master
reads information from the peripheral.
The ADV7170/ADV7171 support a 2-wire, serial (I2Ccompatible) microprocessor bus driving multiple peripherals.
Two inputs, serial data (SDATA), and serial clock (SCLOCK),
carry information between any devices connected to the bus.
Each slave device is recognized by a unique address. The
ADV7170/ADV7171 each have four possible slave addresses for
both read and write operations. These are unique addresses for
each device and are shown in Figure 33 and Figure 34.
The LSB sets either a read or write operation. Logic Level 1
corresponds to a read operation, while Logic Level 0 corresponds to a write operation. A 1 is set by setting the ALSB pin of
the ADV7170/ADV7171 to Logic Level 0 or Logic Level 1.
Rev. C | Page 26 of 64
ADV7170/ADV7171
REGISTER ACCESSES
The ADV7170/ADV7171 act as standard slave devices on the
bus. The data on the SDATA pin is eight bits long, supporting
the 7-bit addresses plus the R/RW bit. The ADV7170 has 48
subaddresses, and the ADV7171 has 26 subaddresses to enable
access to the internal registers. It therefore interprets the first
byte as the device address and the second byte as the starting
subaddress. The subaddresses’ auto-increment allows data to be
written to or read from the starting subaddress. A data transfer
is always terminated by a stop condition. The user can also
access any unique subaddress register on a one-by-one basis
without having to update all the registers. There is one
exception. The subcarrier frequency registers should be updated
in sequence, starting with Subcarrier Frequency Register 0. The
auto-increment function should then be used to increment and
access Subcarrier Frequency Register 1, Subcarrier Frequency
Register 2, and Subcarrier Frequency Register 3. The subcarrier
frequency registers should not be accessed independently.
The MPU can write to or read from all of the ADV7170/
ADV7171 registers except the subaddress register, which is a
write-only register. The subaddress register determines which
register the next read or write operation accesses. All communications with the part through the bus start with an access to
the subaddress register. A read/write operation is performed
from/to the target address, which then increments to the next
address until a stop command on the bus is performed.
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of
sequence with normal read and write operations, they cause an
immediate jump to the idle condition. During a given SCLOCK
high period, the user should issue only one start condition, one
stop condition, or a single stop condition followed by a single
start condition. If an invalid subaddress is issued by the user,
the ADV7170/ADV7171 do not issue an acknowledge, and they
return to the idle condition. If in auto-increment mode the user
exceeds the highest subaddress, the following action is taken:
In read mode, the highest subaddress register contents
continue to be output until the master device issues a noacknowledge. This indicates the end of a read. A noacknowledge condition is where the SDATA line is not pulled
low on the ninth pulse.
In write mode, the data for the invalid byte is not loaded into
any subaddress register, a no-acknowledge is issued by the
ADV7170/ADV7171, and the part returns to the idle
condition.
Figure 35 illustrates an example of data transfer for a read
sequence and the start and stop conditions.
Figure 36 shows bus write and read sequences.
SCLOCK
S
9
1–7
8
START ADDR R/W ACK
1–7
9
8
SUBADDRESS ACK
1–7
DATA
8
9
ACK
P
STOP
00221-035
SDATA
Figure 35. Bus Data Transfer
Rev. C | Page 27 of 64
ADV7170/ADV7171
REGISTER PROGRAMMING
MODE REGISTER 0 MR0 (MR07 TO MR00)
This section describes each register, including subaddress
register, mode registers, subcarrier frequency registers,
subcarrier phase register, timing registers, closed captioning
extended data registers, closed captioning data registers, and
NTSC pedestal control registers, in terms of its configuration.
(Address [SR4 to SR0] = 00H)
Figure 38 shows the various operations under the control of
Mode Register 0. This register can be read from as well as
written to.
SUBADDRESS REGISTER (SR7 TO SR0)
MR0 BIT DESCRIPTION
The communications register is an 8-bit, write-only register.
After the part has been accessed over the bus and a read/write
operation is selected, the subaddress is set up. The subaddress
register determines to/from which register the operation takes
place.
Output Video Standard Selection (MR01 to MR00)
These bits are used to set up the encode mode. The ADV7170/
ADV7171 can be set up to output NTSC, PAL B/D/G/H/I, and
PAL M/N standard video.
Luminance Filter Control (MR02 to MR04)
Figure 37 shows the various operations under the control of the
subaddress register. Zero should always be written to SR7 to SR6.
These bits specify which luma filter is to be selected. The filter
selection is made independent of whether PAL or NTSC is
selected.
REGISTER SELECT (SR5 TO SR0)
These bits are set up to point to the required starting address.
Chrominance Filter Control (MR05 to MR07)
These bits select the chrominance filter. A low-pass filter can be
selected with a choice of cutoff frequencies, 0.65 MHz,
1.0 MHz, 1.3 MHz, or 2 MHz, along with a choice of CIF
or QCIF filters.
S
SLAVE ADDR
A(S)
SUBADDR
A(S)
DATA
S
SLAVE ADDR A(S)
S = START BIT
P = STOP BIT
A(S) P
LSB = 1
LSB = 0
READ
SEQUENCE
DATA
A(S)
SUBADDR
A(S) S SLAVE ADDR
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
A(S)
DATA
A(M)
A (S) = NO-ACKNOWLEDGE BY SLAVE
A (M) = NO-ACKNOWLEDGE BY MASTER
Figure 36. Write and Read Sequences
Rev. C | Page 28 of 64
DATA
A(M) P
00221-036
WRITE
SEQUENCE
ADV7170/ADV7171
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
SR7–SR5 (000)
ZERO SHOULD BE WRITTEN
TO THESE BITS
ADV7171 SUBADDRESS REGISTER
ADV7170 SUBADDRESS REGISTER
SR5
MODE REGISTER 0
00
0
0
0
0
0
0
MODE REGISTER 0
00
MODE REGISTER 1
58
0
0
0
0
0
1
MODE REGISTER 1
58
0
MODE REGISTER 2
00
0
0
0
0
1
0
MODE REGISTER 2
00
1
1
MODE REGISTER 3
00
0
0
0
0
1
1
MODE REGISTER 3
00
1
0
0
MODE REGISTER 4
10
0
0
0
1
0
0
MODE REGISTER 4
10
0
1
0
1
RESERVED
00
0
0
0
1
0
1
RESERVED
00
0
0
1
1
0
RESERVED
00
0
0
0
1
1
0
RESERVED
00
0
0
0
1
1
1
TIMING MODE REGISTER 0
00
0
0
0
1
1
1
TIMING MODE REGISTER 0
00
0
0
1
0
0
0
TIMING MODE REGISTER 1
00
0
0
1
0
0
0
TIMING MODE REGISTER 1
00
0
0
1
0
0
1
SUBCARRIER FREQUENCY REGISTER 0
16*
0
0
1
0
0
1
SUBCARRIER FREQUENCY REGISTER 0
16*
0
0
1
0
1
0
SUBCARRIER FREQUENCY REGISTER 1
7C
0
0
1
0
1
0
SUBCARRIER FREQUENCY REGISTER 1
7C
0
0
1
0
1
1
SUBCARRIER FREQUENCY REGISTER 2
F0
0
0
1
0
1
1
SUBCARRIER FREQUENCY REGISTER 2
F0
0
0
1
1
0
0
SUBCARRIER FREQUENCY REGISTER 3
21
0
0
1
1
0
0
SUBCARRIER FREQUENCY REGISTER 3
21
0
0
1
1
0
1
SUBCARRIER PHASE REGISTER
00
0
0
1
1
0
1
SUBCARRIER PHASE REGISTER
00
0
0
1
1
1
0
CLOSED CAPTIONING EXTENDED DATA BYTE 0
00
0
0
1
1
1
0
CLOSED CAPTIONING EXTENDED DATA BYTE 0
00
0
0
1
1
1
1
CLOSED CAPTIONING EXTENDED DATA BYTE 1
00
0
0
1
1
1
1
CLOSED CAPTIONING EXTENDED DATA BYTE 1
00
0
1
0
0
0
0
CLOSED CAPTIONING DATA BYTE 0
00
0
1
0
0
0
0
CLOSED CAPTIONING DATA BYTE 0
00
0
1
0
0
0
1
CLOSED CAPTIONING DATA BYTE 1
00
0
1
0
0
0
1
CLOSED CAPTIONING DATA BYTE 1
00
0
1
0
0
1
0
NTSC PEDESTAL CONTROL REG 0/
PAL TTX CONTROL REG 0
00
0
1
0
0
1
0
NTSC PEDESTAL CONTROL REG 0/
PAL TTX CONTROL REG 0
00
0
1
0
0
1
1
NTSC PEDESTAL CONTROL REG 1/
PAL TTX CONTROL REG 1
00
0
1
0
0
1
1
NTSC PEDESTAL CONTROL REG 1/
PAL TTX CONTROL REG 1
00
0
NTSC PEDESTAL CONTROL REG 2/
PAL TTX CONTROL REG 2
00
0
1
0
1
0
0
NTSC PEDESTAL CONTROL REG 2/
PAL TTX CONTROL REG 2
00
00
SR4
SR3
SR2
SR1
SR0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
SR4
SR3
SR2
SR1
SR0
0
1
0
1
0
1
NTSC PEDESTAL CONTROL REG 3/
PAL TTX CONTROL REG 3
00
0
1
0
1
0
1
NTSC PEDESTAL CONTROL REG 3/
PAL TTX CONTROL REG 3
0
1
0
1
1
0
CGMS_WSS_0
00
0
1
0
1
1
0
CGMS_WSS_0
00
0
1
0
1
1
1
CGMS_WSS_1
00
0
1
0
1
1
1
CGMS_WSS_1
00
0
1
1
0
0
0
CGMS_WSS_2
00
0
1
1
0
0
0
CGMS_WSS_2
00
0
1
1
0
0
1
TELETEXT REQUEST CONTROL REGISTER
00
0
1
1
0
0
1
TELETEXT REQUEST CONTROL REGISTER
00
0
1
1
0
1
0
RESERVED
00
0
1
1
0
1
1
RESERVED
00
0
1
1
1
0
0
RESERVED
00
0
1
1
1
0
1
RESERVED
00
0
1
1
1
1
0
MACROVISION REGISTERS
00
0
1
1
1
1
1
MACROVISION REGISTERS
00
1
0
0
0
0
0
MACROVISION REGISTERS
00
1
0
0
0
0
1
MACROVISION REGISTERS
00
1
0
0
0
1
0
MACROVISION REGISTERS
00
1
0
0
0
1
1
MACROVISION REGISTERS
00
1
0
0
1
0
0
MACROVISION REGISTERS
00
1
0
0
1
0
1
MACROVISION REGISTERS
00
1
0
0
1
1
0
MACROVISION REGISTERS
00
1
0
0
1
1
1
MACROVISION REGISTERS
00
1
0
1
0
0
0
MACROVISION REGISTERS
00
1
0
1
0
0
1
MACROVISION REGISTERS
00
1
0
1
0
1
0
MACROVISION REGISTERS
00
1
0
1
0
1
1
MACROVISION REGISTERS
00
1
0
1
1
0
0
MACROVISION REGISTERS
00
1
0
1
1
0
1
MACROVISION REGISTERS
00
1
0
1
1
1
0
MACROVISION REGISTERS
00
1
0
1
1
1
1
MACROVISION REGISTERS
00
*SUBCARRIER FREQUENCY REGISTER 0 = 16 IS
INCORRECT ON POWER-UP FOR NTSC. THIS REGISTER
SHOULD BE PROGRAMMED TO 1F FOR ACCURATE FSC.
Figure 37. Subaddress Register Map
Rev. C | Page 29 of 64
00221-037
POWER-UP/
RESET VALUE
(HEX)
POWER-UP/
RESET VALUE
(HEX)
SR5
ADV7170/ADV7171
MR06
MR05
MR04
MR03
MR02
MR01
CHROMA FILTER SELECT
MR00
OUTPUT VIDEO
STANDARD SELECTION
MR07
MR06
MR05
0
0
0
1.3MHz LOW PASS FILTER
MR01
MR00
0
0
1
0.65MHz LOW PASS FILTER
0
0
NTSC
0
1
0
1.0MHz LOW PASS FILTER
0
1
PAL (B, D, G, H, I)
0
1
1
2.0MHz LOW PASS FILTER
1
0
PAL (M)
1
0
0
RESERVED
1
1
RESERVED
1
0
1
CIF
1
1
0
Q CIF
1
1
1
RESERVED
LUMA FILTER SELECT
MR04
MR03
MR02
0
0
0
LOW PASS FILTER (NTSC)
0
0
1
LOW PASS FILTER (PAL)
0
1
0
NOTCH FILTER (NTSC)
0
0
1
NOTCH FILTER (PAL)
1
0
0
EXTENDED MODE
1
0
1
CIF
1
1
0
Q CIF
1
1
1
RESERVED
00221-038
MR07
Figure 38. Mode Register 0
Color Bar Control (MR17)
MODE REGISTER 1 MR1 (MR17 TO MR10)
Figure 39 shows the various operations under the control of
Mode Register 1. This register can be read from as well as
written to.
This bit can be used to generate and output an internal color bar
test pattern. The color bar configuration is 100/7.5/75/7.5 for
NTSC and 100/0/75/0 for PAL. It is important to note that when
color bars are enabled, the ADV7170/ADV7171 are configured
in a master timing mode.
MR1 BIT DESCRIPTION
MODE REGISTER 2 MR2 (MR27 TO MR20)
Interlace Control (MR10)
(Address [SR4 to SR0] = 02H)
This bit is used to set up the output to interlaced or noninterlaced mode. This mode is only relevant when the part is in
composite video mode.
Mode Register 2 is an 8-bit-wide register.
(Address (SR4 to SR0) = 01H)
Closed Captioning Field Selection (MR12 to MR11)
These bits control the fields on which closed captioning data is
displayed. Closed captioning information can be displayed on
an odd field, even field, or both odd and even fields.
DAC Control (MR16 to MR13)
These bits can be used to power down the DACs. This can be
used to reduce the power consumption of the ADV7170/
ADV7171 if any of the DACs are not required in the
application.
Figure 40 shows the various operations under the control of
Mode Register 2. This register can be read from as well as
written to.
MR2 BIT DESCRIPTION
Square Pixel Control (MR20)
This bit is used to set up square pixel mode. This is available in
slave mode only. For NTSC, a 24.5454 MHz clock must be
supplied. For PAL, a 29.5 MHz clock must be supplied.
Rev. C | Page 30 of 64
ADV7170/ADV7171
MR16
MR15
MR14
MR16
NORMAL
POWER-DOWN
0
1
0
0
1
1
0
1
0
1
NO DATA OUT
ODD FIELD ONLY
EVEN FIELD ONLY
DATA OUT
(BOTH FIELDS)
DAC C
CONTROL
INTERLACE
CONTROL
MR13
MR15
DISABLE
ENABLE
MR10
MR12 MR11
0
1
DAC B
CONTROL
MR17
MR11
CLOSED CAPTIONING
FIELD SELECTION
MR14
NORMAL
POWER-DOWN
COLOR BAR
CONTROL
0
1
MR12
DAC D
CONTROL
DAC A
CONTROL
0
1
MR13
0
1
NORMAL
POWER-DOWN
MR10
NORMAL
POWER-DOWN
0
1
INTERLACED
NONINTERLACED
00221-039
MR17
Figure 39. Mode Register 1
MR26
MR25
MR23
DISABLE
ENABLE
0
1
MR27
MR20
GENLOCK CONTROL
ENABLE COLOR
DISABLE COLOR
x
0
0
1
1
1
DISABLE GENLOCK
ENABLE SUBCARRIER
RESET PIN
ENABLE RTC PIN
SQUARE PIXEL
CONTROL
ACTIVE VIDEO LINE
DURATION
BURST
CONTROL
RESERVED
MR21
MR22 MR21
MR24
MR26
MR22
CHROMINANCE
CONTROL
LOW POWER MODE
0
1
MR24
MR25
MR20
MR23
0
1
ENABLE BURST
DISABLE BURST
0
1
0
1
720 PIXELS
710 PIXELS/702 PIXELS
DISABLE
ENABLE
00221-040
MR27
Figure 40. Mode Register 2
MR36
MR35
TTXRQ BIT
MODE CONTROL
MR36
0
1
MR33
CHROMA OUTPUT
SELECT
MR34
NORMAL
BIT REQUEST
INPUT DEFAULT
COLOR
MR37
0
1
MR34
0
1
DISABLE
ENABLE
0
1
DISABLE
ENABLE
MR31
VBI_OPEN
MR32
0
1
DISABLE
ENABLE
TELETEXT
ENABLE
MR35
DISABLE
ENABLE
MR32
MR30
MR30
MR31
RESERVED
DAC OUTPUT
MR33
DAC A
DAC B
0
COMPOSITE
BLUE/COMP/U
1
GREEN/LUMA/Y BLUE/COMP/U
DAC C
RED/CHROMA/V
RED/CHROMA/V
DAC D
GREEN/LUMA/Y
COMPOSITE
00221-041
MR37
Figure 41. Mode Register 3
Genlock Control (MR22 to MR21)
These bits control the genlock feature of the ADV7170/
ADV7171. Setting MR21 to a Logic Level 1 configures the
SCRESET/RTC pin as an input. Setting MR22 to Logic Level 0
configures the SCRESET/RTC pin as a subcarrier reset input.
Therefore, the subcarrier resets to Field 0 following a low-tohigh transition on the SCRESET/RTC pin. Setting MR22 to
Logic Level 1 configures the SCRESET/RTC pin as a real-time
control input.
a 1 selects ITU-R.BT470 standard for active video duration
(710 pixels NTSC; 702 pixels PAL).
Chrominance Control (MR24)
This bit enables the color information to be switched on and off
the video output.
Burst Control (MR25)
This bit enables the burst information to be switched on and off the
video output.
Active Video Line Duration (MR23)
Low Power Mode (MR26)
This bit switches between two active video line durations.
A 0 selects CCIR REC601 (720 pixels PAL/NTSC), and
This bit enables the lower power mode of the ADV7170/
ADV7171, reducing the DAC current by 45%.
Rev. C | Page 31 of 64
ADV7170/ADV7171
Reserved (MR27)
DAC Output (MR33)
A Logic Level 0 must be written to this bit.
This bit is used to switch the DAC outputs from SCART to a
EUROSCART configuration. A complete table of all DAC output
configurations is shown in Table 12.
MODE REGISTER 3 MR3 (MR37 TO MR30)
(Address [SR4 to SR0] = 03H)
Chroma Output Select (MR34)
Mode Register 3 is an 8-bit-wide register. Figure 41 shows the
various operations under the control of Mode Register 3.
MR3 BIT DESCRIPTION
With this active high bit it is possible to output YUV data with a
composite output on the fourth DAC or a chroma output on the
fourth DAC (0 = CVBS; 1 = CHROMA).
Revision Code (MR30 to MR31)
Teletext Enable (MR35)
These bits are read-only and indicate the revision of the device.
This bit must be set to 1 to enable teletext data insertion on the
TTX pin.
VBI Open (MR32)
This bit determines whether or not data in the vertical blanking
interval (VBI) is output to the analog outputs or blanked. VBI
data insertion is not available in Slave Mode 0. Also, when both
BLANK input control and VBI-open are enabled, BLANK input
control has priority; that is, VBI data insertion does not work.
TTXREQ Bit Mode Control (MR36)
This bit enables switching of the teletext request signal from a
continuous high signal (MR36 = 0) to a bit wise request signal
(MR36 = 1).
Input Default Color (MR37)
This bit determines the default output color from the DACs for
zero input pixel data (or disconnected). A Logic Level 0 means that
the color corresponding to 00000000 is displayed. A Logic Level 1
forces the output color to black for 00000000 pixel input video data.
Table 12. DAC Output Configuration Matrix
MR34
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
MR40
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
MR41
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
MR33
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DAC A
CVBS
Y
CVBS
Y
CVBS
G
CVBS
Y
C
Y
C
Y
C
G
C
Y
DAC B
CVBS
CVBS
CVBS
CVBS
B
B
U
U
CVBS
CVBS
CVBS
CVBS
B
B
U
U
DAC C
C
C
C
C
R
R
V
V
C
C
C
C
R
R
V
V
CVBS: Composite video baseband signal
Y:
Luminance component signal (for YUV or Y/C mode)
C:
Chrominance signal (for Y/C mode)
U:
Chrominance component signal (for YUV mode)
V:
Chrominance component signal (for YUV mode)
R:
RED Component video (for RGB mode)
G:
GREEN Component video (for RGB mode)
B:
BLUE Component video (for RGB mode)
Each DAC can be powered on or off individually with the following control bits (0 = ON; 1 = OFF):
MR13-DAC C
MR14-DAC D
MR15-DAC B
MR16-DAC A
Rev. C | Page 32 of 64
DAC D
Y
CVBS
Y
CVBS
G
CVBS
Y
CVBS
Y
C
Y
C
G
C
Y
C
Simultaneous Output
2 composite and Y/C
2 composite and Y/C
2 composite and Y/C
2 composite and Y/C
RGB and composite
RGB and composite
YUV and composite
YUV and composite
1 composite, Y and 2C
1 composite, Y and 2C
1 composite, Y and 2C
1 composite, Y and 2C
RGB and C
RGB and C
YUV and C
YUV and C
ADV7170/ADV7171
MR46
MR45
SLEEP MODE
CONTROL
MR47
(0)
ZERO SHOULD
BE WRITTEN TO
THIS BIT
MR43
DISABLE
ENABLE
0
1
MR41
0
1
MR40
DISABLE
ENABLE
VSYNC_3H
0
1
DISABLE
ENABLE
DISABLE
ENABLE
0
1
YC OUTPUT
RGB/YUV OUTPUT
RGB/YUV
CONTROL
MR43
MR45
MR40
OUTPUT SELECT
MR42
PEDESTAL OFF
PEDESTAL ON
ACTIVE VIDEO
FILTER CONTROL
0
1
MR42
RGB SYNC
PEDESTAL
CONTROL
MR44
MR46
0
1
MR44
MR41
0
1
RGB OUTPUT
YUV OUTPUT
00221-042
MR47
Figure 42. Mode Register 4
MODE REGISTER 4 MR4 (MR47 TO MR40)
Active Video Filter Control (MR45)
(Address (SR4 to SR0) = 04H)
This bit controls the filter mode applied outside the active video
portion of the line. This filter ensures that the sync rise and fall
times are always on spec regardless of which luma filter is
selected. This mode is enabled by a Logic Level 1.
Mode Register 4 is an 8-bit-wide register. Figure 42 shows the
various operations under the control of Mode Register 4.
MR4 BIT DESCRIPTION
Output Select (MR40)
Sleep Mode Control (MR46)
This bit specifies if the part is in composite video mode or
RGB/YUV mode. Note that in RGB/YUV mode the composite
signal is still available.
When this bit is set to 1, sleep mode is enabled. With this mode
enabled, power consumption of the ADV7170/ADV7171 is
reduced to typically 200 nA. The I2C registers can be written to
and read from when the ADV7170/ADV7171 are in sleep
mode. If MR46 is set to a 0 when the device is in sleep mode,
the ADV7170/ADV7171 come out of sleep mode and resume
normal operation. Also, if the RESET signal is applied during
sleep mode, the ADV7170/ADV7171 come out of sleep mode
and resume normal operation.
RGB/YUV Control (MR41)
This bit enables the output from the RGB DACs to be set to
YUV output video standard.
RGB Sync (MR42)
This bit is used to set up the RGB outputs with the sync
information encoded on all RGB outputs.
Reserved (MR47)
A Logic Level 0 should be written to this bit.
VSYNC_3H (MR43)
When this bit is enabled (1) in slave mode, it is possible to
drive the VSYNC active low input for 2.5 lines in PAL mode and
3 lines in NTSC mode. When this bit is enabled in master
mode, the ADV7170/ADV7171 output an active low VSYNC
signal for 3 lines in NTSC mode and 2.5 lines in PAL mode.
TIMING MODE REGISTER 0 (TR07 TO TR00)
(Address [SR4 to SR0] = 07H)
Figure 43 shows the various operations under the control of
Timing Register 0. This register can be read from as well as
written to.
Pedestal Control (MR44)
This bit specifies whether a pedestal is to be generated on the
NTSC composite video signal. This bit is invalid if the
ADV7170/ADV7171 are configured in PAL mode.
Rev. C | Page 33 of 64
ADV7170/ADV7171
TR06
TR05
TR04
TR03
TIMING
REGISTER RESET
TR01
TR00
MASTER/SLAVE
CONTROL
BLANK INPUT
CONTROL
TR03
0
1
TR07
PIXEL PORT
CONTROL
TR06
0
1
TR02
8 BIT
16 BIT
TR00
ENABLE
DISABLE
0
1
0
1
0ns DELAY
74ns DELAY
148ns DELAY
222ns DELAY
SLAVE TIMING
MASTER TIMING
TIMING MODE
SELECTION
LUMA DELAY
TR05 TR04
0
0
1
1
0
1
TR02 TR01
0
0
1
1
0
1
0
1
MODE 0
MODE 1
MODE 2
MODE 3
00221-043
TR07
Figure 43. Timing Register 0
TR0 BIT DESCRIPTION
TIMING MODE REGISTER 1 (TR17 TO TR10)
Master/Slave Control (TR00)
(Address (SR4 to SR0) = 08H)
This bit controls whether the ADV7170/ADV7171 is in
Master or Slave Mode.
Timing Register 1 is an 8-bit-wide register.
Timing Mode Selection (TR02 to TR01)
These bits control the timing mode of the ADV7170/ ADV7171.
These modes are described in more detail in
the Timing and Control section.
Figure 44 shows the various operations under the control of
Timing Register 1. This register can be read from as well written
to. This register can be used to adjust the width and position of
the master mode timing signals.
TR1 BIT DESCRIPTION
BLANK Control (TR03)
HSYNC Width (TR11 to TR10)
This bit controls whether the BLANK input is used when the
part is in slave mode.
These bits adjust the HSYNC pulse width.
Luma Delay (TR05 to TR04)
These bits adjust the position of the HSYNC output relative to
the FIELD/VSYNC output.
These bits control the addition of a luminance delay. Each bit
represents a delay of 74 ns.
Pixel Port Control (TR06)
This bit is used to set the pixel port to accept 8-bit or 16-bit
data. If an 8-bit input is selected, the data will be set up on
Pin P7 to Pin P0.
HSYNC to FIELD/VSYNC Delay (TR13 to TR12)
HSYNC to FIELD Rising Edge Delay (TR15 to TR14)
When the ADV7170/ADV7171 are in Timing Mode 1, these
bits adjust the position of the HSYNC output relative to the
FIELD output rising edge.
VSYNC Width (TR15 to TR14)
Timing Register Reset (TR07)
Toggling TR07 from low to high and low again resets the
internal timing counters. This bit should be toggled after
power-up, reset or changing to a new timing mode.
When the ADV7170/ADV7171 are configured in Timing
Mode 2, these bits adjust the VSYNC pulse width.
HSYNC to Pixel Data Adjust (TR17 to TR16)
This enables the HSYNC to be adjusted with respect to the pixel
data. This allows the Cr and Cb components to be swapped.
This adjustment is available in both master timing mode and
slave timing mode.
Rev. C | Page 34 of 64
ADV7170/ADV7171
TR17
TR16
TR15
HSYNC TO PIXEL
DATA ADJUST
TR14
HSYNC TO FIELD
RISING EDGE DELAY
(MODE 1 ONLY)
TR17 TR16
0
0
1
1
0
1
0
1
TR13
TR12
TC
TR15 TR14
x
x
0
1
TB
TB + 32μs
0
0
1
1
0
1
0
1
TR10
HSYNC WIDTH
HSYNC TO
FIELD/VSYNC DELAY
TA
TR11 TR10
TB
TR13 TR12
0 × TPCLK
1 × TPCLK
2 × TPCLK
3 × TPCLK
TR11
0
0
1
1
0 × TPCLK
4 × TPCLK
8 × TPCLK
16 × TPCLK
0
1
0
1
1 × TPCLK
4 × TPCLK
16 × TPCLK
128 × TPCLK
VSYNC WIDTH
(MODE 2 ONLY)
TR15 TR14
0
0
1
1
0
1
0
1
1 × TPCLK
4 × TPCLK
16 × TPCLK
128 × TPCLK
TIMING MODE 1 (MASTER/PAL)
LINE 1
LINE 313
LINE 314
TA
HSYNC
TC
00221-044
TB
FIELD/VSYNC
Figure 44. Timing Register 1
SUBCARRIER FREQUENCY REGISTERS 0 TO 3
(FSC3 TO FSC0)
SUBCARRIER PHASE REGISTERS (FP7 TO FP0)
(Address [SR4 to SR00] = 09H to 0CH)
This 8-bit-wide register is used to set up the subcarrier phase.
Each bit represents 1.41°. For normal operation this register is
set to 00Hex.
(Address [SR4 to SR0] = 0DH)
No. of Subcarrier Frequency Values in One Line of Video Line
× 232
No. of 27 MHz Clock Cycles in One Video Line
For example, in NTSC mode,
Subcarrier Frequency Value =
227.5
× 232 = 569408542d = 21F 07C1Fh
1716
Note that on power-up, FSC Register 0 is set to 16h. A value of 1F
as derived above is recommended.
CLOSED CAPTIONING EVEN FIELD DATA
REGISTER 1 TO 0 (CED15 TO CED0)
(Address [SR4–SR0] = 0E to 0FH)
These 8-bit-wide registers are used to set up the closed
captioning extended data bytes on even fields. Figure 46
shows how the high and low bytes are set up in the registers.
BYTE 1
BYTE 0
CED15 CED14 CED13 CED12 CED11 CED10
CED7
CED6
CED5
CED4
CED3
CED2
CED1
CED8
CED0
Figure 46. Closed Captioning Extended Data Register
Program as follows:
FSC Register 2: 7CH
CLOSED CAPTIONING ODD FIELD DATA
REGISTERS 1 TO 0 (CCD15 TO CCD0)
FSC Register 3: F0H
(Subaddress [SR4 to SR0] = 10H to 11H)
FSC Register 4: 21H
Figure 45 shows how the frequency is set up by the four registers.
SUBCARRIER
FREQUENCY
REG 0
FSC7
FSC2
FSC1
FSC0
SUBCARRIER
FREQUENCY
REG 1
FSC15 FSC14 FSC13 FSC12 FSC11 FSC10
FSC9
FSC8
SUBCARRIER
FREQUENCY
REG 2
FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16
SUBCARRIER
FREQUENCY
REG 3
FSC31 FSC30 FSC29 FSC28 FSC27 FSC26 FSC25 FSC24
FSC5
FSC4
FSC3
These 8-bit-wide registers are used to set up the closed
captioning data bytes on odd fields. Figure 47 shows how the
high and low bytes are set up in the registers.
BYTE 1
BYTE 0
CCD15 CCD14 CCD13 CCD12 CCD11 CCD10
CCD7
CCD6
CCD5
CCD4
CCD3
CCD2
CCD1
00221-045
Figure 47. Closed Captioning Data Register
Figure 45. Subcarrier Frequency Register
Rev. C | Page 35 of 64
CCD9
CCD8
CCD0
00221-047
FSC Register 0: 1FH
FSC6
CED9
00221-046
These 8-bit-wide registers are used to set up the subcarrier
frequency. The value of these registers is calculated by using
the following equation, rounded to the nearest integer:
ADV7170/ADV7171
TTXREQ Rising Edge Control (TC07 to TC04)
NTSC PEDESTAL/PAL TELETEXT CONTROL
REGISTERS 3 TO 0 (PCE15 TO PCE0, PCO15
TO PCO0)/(TXE15 TO TXE0, TXO15 TO TXO0)
These bits control the position of the rising edge of TTXREQ.
It can be programmed from zero CLOCK cycles to a maximum
of 15 CLOCK cycles. See Figure 59.
(Subaddress [SR4–SR0] = 12H to 15H)
These 8-bit-wide registers are used to enable the NTSC
pedestal/PAL teletext on a line-by-line basis in the vertical
blanking interval for both odd and even fields. Figure 48 and
Figure 49 show the four control registers. A Logic Level 1 in any
of the bits of these registers has the effect of turning the pedestal
off on the equivalent line when used in NTSC. A Logic Level 1
in any of the bits of these registers has the effect of turning on
teletext on the equivalent line when used in PAL.
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
FIELD 1/3
PCO7
PCO6
PCO5
PCO4
PCO3
PCO2
PCO1
PCO0
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
FIELD 1/3
PCO15 PCO14 PCO13 PCO12
PCO11 PCO10
PCO9
TTXREQ Falling Edge Control (TC03 to TC00)
These bits control the position of the falling edge of TTXREQ.
It can be programmed from zero CLOCK cycles to a max of
15 CLOCK cycles. This controls the active window for teletext
data. Increasing this value reduces the amount of teletext bits
below the default of 360. If Bit TC03 to Bit TC00 are 00Hex
when bits TC07 to TC04 are changed, the falling edge of
TTXREQ tracks that of the rising edge (that is, the time
between the falling and rising edge remains constant).
See Figure 59.
CGMS_WSS REGISTER 0 C/W0 (C/W07 TO C/W00)
PCO8
(Address [SR4 to SR0] = 16H)
CGMS_WSS Register 0 is an 8-bit-wide register. Figure 51
shows the operations under the control of this register.
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
PCE7
PCE6
PCE5
PCE4
PCE3
PCE2
PCE1
PCE0
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
FIELD 2/4
PCE15
PCE14
PCE13
PCE12
PCE11
PCE10
PCE9
PCE8
00221-048
FIELD 2/4
Figure 48. Pedestal Control Registers
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9
FIELD 1/3
TXO7
TXO6
TXO5
TXO4
TXO3
TXO2
TXO0
CGMS CRC Check Control (C/W04)
LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15
FIELD 2/4
TXO15
TXO10
TXO9
TXO8
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9
LINE 8
LINE 7
TXE1
TXE0
TXE7
TXO14
TXE6
TXO13
TXE5
TXO12
TXE4
TXO11
TXE3
TXE2
LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15
FIELD 2/4
TXE15
TXE14
TXE13
TXE12
TXE11
TXE10
TXE9
TXE8
When this bit is enabled (1), the last six bits of the CGMS data
(that is, the CRC check sequence) are calculated internally by
the ADV7170/ADV7171. If this bit is disabled (0), the CRC
values in the register are output to the CGMS data stream.
00221-049
FIELD 1/3
CGMS Data Bits (C/W03 to C/W00)
These four data bits are the final four bits of the CGMS data
output stream. Note it is CGMS data ONLY in these bit
positions; that is, WSS data does not share this location.
LINE 8 LINE 7
TXO1
C/W0 BIT DESCRIPTION
Figure 49. Teletext Control Registers
CGMS Odd Field Control (C/W05)
When this bit is set (1), CGMS is enabled for odd fields. Note
this is valid only in NTSC mode.
TELETEXT REQUEST CONTROL REGISTER TC07
(TC07 TO TC00)
CGMS Even Field Control (C/W06)
(Address [SR4 to SR0] = 19H)
Teletext control register is an 8-bit-wide register. See Figure 50.
When this bit is set (1), CGMS is enabled for even fields. Note
this is valid only in NTSC mode.
WSS Control (C/W07)
When this bit is set (1), wide screen signaling is enabled. Note
this is valid only in PAL mode.
Rev. C | Page 36 of 64
ADV7170/ADV7171
TC06
TC05
TC04
TC03
TTXREQ RISING EDGE CONTROL
TC07 TC06
0
0
"
1
1
0
0
"
1
1
TC03 TC02
0
1
"
0
1
TC01
TC00
TTXREQ FALLING EDGE CONTROL
TC05 TC04
0
0
"
1
1
TC02
0 PCLK
1 PCLK
" PCLK
14 PCLK
15 PCLK
0
0
"
1
1
TC01 TC00
0
0
"
1
1
0
0
"
1
1
0
1
"
0
1
0 PCLK
1 PCLK
" PCLK
14 PCLK
15 PCLK
00221-050
TC07
Figure 50. Teletext Control Register
C/W06
WIDE SCREEN
SIGNAL CONTROL
C/W07
0
DISABLE
1
ENABLE
C/W05
C/W04
C/W03
C/W02
CGMS ODD FIELD
CONTROL
C/W05
0
DISABLE
1
ENABLE
CGMS EVEN FIELD
CONTROL
C/W06
0
DISABLE
1
ENABLE
C/W01
C/W00
C/W03 – C/W00
CGMS DATA BITS
CGMS CRC CHECK
CONTROL
C/W04
0
DISABLE
1
ENABLE
00221-051
C/W07
Figure 51. CGMS_WSS Register 0
CGMS_WSS REGISTER 1 C/W1 (C/W17 TO C/W10)
CGMS_WSS REGISTER 2 C/W1 (C/W27 TO C/W20)
(Address [SR4 to SR0] = 17H)
(Address [SR4 to SR0] = 18H)
CGMS_WSS Register 1 is an 8-bit-wide register. Figure 52
shows the operations under the control of this register.
CGMS_WSS Register 2 is an 8-bit-wide register. Figure 53
shows the operations under the control of this register.
C/W1 BIT DESCRIPTION
C/W2 BIT DESCRIPTION
CGMS/WSS Data Bits (C/W15 to C/W10)
CGMS/WSS Data Bits (C/W27 to C/W20)
These bit locations are shared by CGMS data and WSS data. In
NTSC mode, these bits are CGMS data. In PAL mode, these bits
are WSS data.
These bit locations are shared by CGMS data and WSS data. In
NTSC mode, these bits are CGMS data. In PAL mode, these bits
are WSS data.
CGMS DATA BITS (C/W17 TO C/W16)
These bits are CGMS data bits only.
C/W16
C/W15
C/W14
C/W13
C/W12
C/W17 – C/W16
C/W15 – C/W10
CGMS DATA BITS
CGMS/WSS DATA BITS
C/W11
C/W10
C/W21
C/W20
00221-052
C/W17
C/W27
C/W26
C/W25
C/W24
C/W23
C/W22
C/W27 – C/W20
CGMS/WSS DATA BITS
Figure 53. CGMS_ WSS Register 2
Rev. C | Page 37 of 64
00221-053
Figure 52. CGMS_WSS Register 1
ADV7170/ADV7171
APPENDICES
Supply Decoupling
APPENDIX 1—BOARD DESIGN
AND LAYOUT CONSIDERATIONS
The ADV7170/ADV7171 are highly integrated circuits
containing both precision analog and high speed digital
circuitry. They have been designed to minimize interference
effects of the high speed digital circuitry on the integrity of the
analog circuitry. It is imperative that these same design and
layout techniques be applied to the system level design so that
high speed, accurate performance is achieved. Figure 54 shows
the analog interface between the device and monitor.
The layout should be optimized for lowest noise on the
ADV7170/ADV7171 power and ground lines by shielding the
digital inputs and providing good decoupling. The lead length
between groups of VAA and GND pins should be minimized to
minimize inductive ringing.
Ground Planes
The ground plane should encompass all ADV7170/ADV7171
ground pins, voltage reference circuitry, power supply bypass
circuitry for the ADV7170/ADV7171, the analog output traces,
and all the digital signal traces leading up to the ADV7170/
ADV7171. The ground plane is the board’s common ground
plane.
Power Planes
The ADV7170, the ADV7171, and any associated analog
circuitry should each have its own power plane, referred to
as the analog power plane (VAA). This power plane should be
connected to the regular PCB power plane (VCC) at a single
point through a ferrite bead. This bead should be located within
three inches of the ADV7170/ADV7171.
The metallization gap separating device power plane and board
power plane should be as narrow as possible to minimize the
obstruction to the flow of heat from the device into the general
board.
For optimum performance, bypass capacitors should be
installed using the shortest leads possible, consistent with
reliable operation, to reduce the lead inductance. Best
performance is obtained with 0.1 μF ceramic capacitor
decoupling. Each group of VAA pins on the ADV7170/
ADV7171 must have at least one 0.1 μF decoupling capacitor
to GND. These capacitors should be placed as close as possible
to the device.
It is important to note that while the ADV7170/ADV7171
contain circuitry to reject power supply noise, this rejection
decreases with frequency. If a high frequency switching power
supply is used, the designer should pay close attention to
reducing power supply noise and consider using a threeterminal voltage regulator for supplying power to the analog
power plane.
Digital Signal Interconnect
The digital inputs to the ADV7170/ADV7171 should be isolated
as much as possible from the analog outputs and other analog
circuitry. Also, these input signals should not overlay the analog
power plane.
Due to the high clock rates involved, long clock lines to the
ADV7170/ADV7171 should be avoided to reduce noise pickup.
Any active termination resistors for the digital inputs should be
connected to the regular PCB power plane (VCC) and not to the
analog power plane.
Analog Signal Interconnect
The ADV7170/ADV7171 should be located as close as possible
to the output connectors to minimize noise pickup and
reflections due to impedance mismatch.
The video output signals should overlay the ground plane, not
the analog power plane, to maximize the high frequency power
supply rejection.
The PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV7170/ADV7171 power pins and voltage
reference circuitry.
Digital inputs, especially pixel data inputs and clocking signals,
should never overlay any of the analog signal circuitry and
should be kept as far away as possible.
Plane-to-plane noise coupling can be reduced by ensuring that
portions of the regular PCB power and ground planes do not
overlay portions of the analog power plane unless they can be
arranged so that the plane-to-plane noise is common-mode.
For best performance, the outputs should each have a 75 Ω load
resistor connected to GND. These resistors should be placed as
close as possible to the ADV7170/ADV7171 to minimize
reflections.
The ADV7170/ADV7171 should have no inputs left floating.
Any inputs that are not required should be tied to ground.
Rev. C | Page 38 of 64
ADV7170/ADV7171
POWER SUPPLY DECOUPLING
FOR EACH POWER SUPPLY GROUP
0.1μF
0.01μF
L1
(FERRITE BEAD)
5V (VAA)
5V (VAA)
5V (VAA)
0.1μF
0.1μF
25
COMP
33
VREF
5V
VCC
GND
VAA
DAC D 27
75Ω
ADV7170/
ADV7171
38–42,
2–9, 12–14
5V (VAA)
33μF
10μF
1, 11, 20, 28, 30
DAC C 26
P15–P0
S-VIDEO
75Ω
4kΩ
RESET
100nF
UNUSED
INPUTS
SHOULD BE
GROUNDED
5V (VCC)
TTX
100kΩ
35
SCRESET/RTC
15
HSYNC
16
FIELD/VSYNC
17
BLANK
22
RESET
37
TTX
36
TTXREQ
44
CLOCK
DAC A 32
5V (VCC)
75Ω
5kΩ
100Ω
5V (VCC)
5kΩ
MPU BUS
100Ω
SDATA 24
RSET 34
5V (VAA)
ALSB
GND
18
10kΩ
150Ω
10, 19, 21,
29, 43
00221-054
TELETEXT PULL-UP AND
PULL-DOWN RESISTORS
SHOULD ONLY BE USED
IF THESE PINS ARE NOT
CONNECTED
75Ω
SCLOCK 23
TTXREQ
100kΩ
DAC B 31
27MHz CLOCK
(SAME CLOCK AS USED BY
MPEG2 DECODER)
Figure 54. Recommended Analog Circuit Layout
The circuit in Figure 55 can be used to generate a 13.5 MHz waveform using the 27 MHz clock and the HSYNC pulse. This waveform is
guaranteed to produce the 13.5 MHz clock in synchronization with the 27 MHz clock. This 13.5 MHz clock can be used if a 13.5 MHz
clock is required by the MPEG decoder. This guarantees that the Cr and Cb pixel information is input to the ADV7170/ADV7171 in the
correct sequence.
D
CLOCK
Q
D
CK
Q
13.5MHz
00221-055
CK
HSYNC
Figure 55. Circuit to Generate 13.5 MHz
Rev. C | Page 39 of 64
ADV7170/ADV7171
FCC Code of Federal Regulations (CFR) 47 Section 15.119 and
EIA608 describe the closed captioning information for Line 21
and Line 284.
APPENDIX 2—CLOSED CAPTIONING
The ADV7170/ADV7171 support closed captioning, conforming to the standard television synchronizing waveform for color
transmission. Closed captioning is transmitted during the
blanked active line time of the odd fields Line 21 and the even
fields Line 284.
The ADV7170/ADV7171 use a single buffering method. This
means that the closed captioning buffer is only one byte deep;
therefore, there is no frame delay in outputting the closed
captioning data, unlike other 2-byte deep buffering systems.
The data must be loaded at least one line before (Line 20 or
Line 283) it is outputted on Line 21 and Line 284. A typical
implementation of this method is to use VSYNC to interrupt a
microprocessor, which in turn loads the new data (two bytes) in
every field. If no new data is required for transmission, you
must insert zeros in both the data registers; this is called
nulling. It is also important to load control codes, all of which
are double bytes, on Line 21, or a TV does not recognize them.
If you have a message like “Hello World,” which has an odd
number of characters, it is important to pad it out to an even
number to get end-of-caption, 2-byte control code to land in
the same field.
Closed captioning consists of a 7-cycle sinusoidal burst that is
frequency- and phase-locked to the caption data. After the clock
run-in signal, the blanking level is held for two data bits and is
followed by a Logic Level 1 start bit. 16 bits of data follow the
start bit. These consist of two 8-bit bytes, seven data bits and
one odd parity bit. The data for these bytes is stored in Closed
Captioning Data Register 0 and Closed Captioning Data
Register 1.
The ADV7170/ADV7171 also support the extended closed
captioning operation, which is active during even fields and is
encoded on scan Line 284. The data for this operation is stored
in Closed Captioning Extended Data Register 0 and Closed
Captioning Extended Data Register 1.
All clock run-in signals and timing to support closed captioning
on Line 21 and Line 284 are automatically generated by the
ADV7170/ADV7171. All pixel inputs are ignored during
Line 21 and Line 284.
10.5 ± 0.25μs
12.91μs
7 CYCLES
OF 0.5035MHz
(CLOCK RUN-IN)
TWO 7-BIT + PARITY
ASCII CHARACTERS
(DATA)
S
T
A
R
T
50 IRE
D0–D6
P
A
R
I
T
Y
D0–D6
P
A
R
I
T
Y
BYTE 1
BYTE 0
40 IRE
10.003μs
33.764μs
27.382μs
Figure 56. Closed Captioning Waveform (NTSC)
Rev. C | Page 40 of 64
00221-056
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = FSC = 3.579545MHz
AMPLITUDE = 40 IRE
ADV7170/ADV7171
APPENDIX 3—COPY GENERATION MANAGEMENT SYSTEM (CGMS)
The ADV7170/ADV7171 support copy generation management systems (CGMS) conforming to the standard. CGMS data is transmitted
on Line 20 of the odd fields and Line 283 of even fields. Bit C/W05 and Bit C/W06 control whether or not CGMS data is output on odd
and even fields. CGMS data can only be transmitted when the ADV7170/ADV7171 are configured in NTSC mode.
The CGMS data is 20 bits long; the function of each of these bits is shown below. The CGMS data is preceded by a reference pulse of the
same amplitude and duration as a CGMS bit (see Figure 57). The bits are output from the configuration registers in the following order:
C/W00 = C16, C/W01 = C17, C/W02 = C18, C/W03 = C19, C/W10 = C8, C/W11 = C9, C/W12 = C10, C/W13 = C11, C/W14 = C12,
C/W15 = C13, C/W16 = C14, C/W17 = C15, C/W20 = C0, C/W21 = C1, C/W22 = C2, C/W23 = C3, C/W24 = C4, C/W25 = C5,
C/W26 = C6, C/W27 = C7.
If the Bit C/W04 is set to a Logic Level 1, the last six bits, C19 to C14, which comprise the 6-bit CRC check sequence, are calculated
automatically on the ADV7170/ADV7171 based on the lower 14 bits (C0 to C13) of the data in the data registers and output with the
remaining 14 bits to form the complete 20 bits of the CGMS data. The calculation of the CRC sequence is based on the polynomial
X6 + X + 1 with a preset value of 111111. If C/W04 is set to a Logic Level 0, all 20 bits (C0 to C19) are directly output from the CGMS
registers (no CRC is calculated; it must be calculated by the user).
Function of CGMS Bits
Word 0
– 6 Bits
Word 1
– 4 Bits
Word 2
– 6 Bits
CRC
– 6 Bits
CRC Polynomial = X6 + X + 1 (Preset to 111111)
Word 0
1
0
B1
Aspect Ratio
16:94:3
B2
Display Format
Letterbox
B3
Undefined
Normal
Word 0
B4, B5, B6
Identification information about video and other signals (for example, audio)
Word 1
B7, B8, B9, B10
Identification signal incidental to Word 0
Word 2
B11, B12, B13, B14
Identification signal and information incidental to Word 0
+100 IRE
CRC SEQUENCE
REF
+70 IRE
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0 IRE
49.1μs ± 0.5μs
–40 IRE
00221-057
11.2μs
2.235μs ± 20ns
Figure 57. CGMS Waveform Diagram
Rev. C | Page 41 of 64
ADV7170/ADV7171
APPENDIX 4—WIDE SCREEN SIGNALING
The ADV7170/ADV7171 support wide screen signaling (WSS) conforming to the standard. WSS data is transmitted on Line 23.
WSS data can only be transmitted when the ADV7170/ADV7171 are configured in PAL mode. The WSS data is 14 bits long; the function
of each of these bits is as shown below.
The WSS data is preceded by a run-in sequence and a start code (see Figure 58). The bits are output from the configuration registers in
the following order:
C/W20 = W0, C/W21 = W1, C/W22 = W2, C/W23 = W3, C/W24 = W4, C/W25 = W5, C/W26 = W6, C/W27 = W7, C/W10 = W8,
C/W11 = W9, C/W12 = W10, C/W13 = W11, C/W14 = W12, C/W15 = W13.
If Bit C/W07 is set to a Logic Level 1, it enables the WSS data to be transmitted on Line 23. The latter portion of Line 23 (42.5 μs from the
falling edge of HSYNC) is available for the insertion of video.
Function of CGMS Bits
Bit 0 to Bit 2
Aspect Ratio/Format/Position
Bit 3 is odd parity check of Bit 0 to Bit 2
B0
B1
B2
B3
Aspect Ratio
Format
Position
0
0
0
1
4:3
Full format
Nonapplicable
1
0
0
0
14:9
Letterbox
Center
0
1
0
0
14:9
Letterbox
Top
1
1
0
1
16:9
Letterbox
Center
0
0
1
0
16:9
Letterbox
Top
1
0
1
1
>16:9
Letterbox
Center
0
1
1
1
14:9
Full format
Center
1
1
1
0
16:9
Nonapplicable
Nonapplicable
B9
0
1
0
1
B11
0
1
B12
B13
Camera Mode
Film Mode
Standard Coding
Motion Adaptive Color Plus
No Helper
Modulated Helper
RESERVED
B10
0
0
1
1
No open subtitles
Subtitles in active image area
Subtitles out of active image area
Reserved
No surround sound information
Surround sound mode
RESERVED
RESERVED
500mV
W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13
RUN-IN
SEQUENCE
START
CODE
ACTIVE
VIDEO
11.0μs
00221-058
B4
0
1
B5
0
1
B6
0
1
B7
38.4μs
42.5μs
Figure 58. WSS Waveform Diagram
Rev. C | Page 42 of 64
ADV7170/ADV7171
APPENDIX 5—TELETEXT INSERTION
Teletext Protocol
The tPD is the time needed by the ADV7170/ADV7171 to
interpolate input data on TTX and insert it onto the CVBS
or Y outputs, such that it appears tSYNTTXOUT = 10.2 μs after the
leading edge of the horizontal signal. Time TTXDEL is the
pipeline delay time by the source that is gated by the TTXREQ
signal in order to deliver TTX data.
The relationship between the TTX bit clock (6.9375 MHz) and
the system CLOCK (27 MHz) for 50 Hz is as follows:
(27 MHz/4) = 6.75 MHz
(6.9375 × 106/6.75 × 106) = 1.027777
Thus, 37 TTX bits correspond to 144 clocks (27 MHz), and
each bit has a width of nearly four clock cycles. The ADV7170/
ADV7171 use an internal sequencer and variable phase
interpolation filter to minimize the phase jitter and thus
generate a bandlimited signal that can be output on the CVBS
and Y outputs.
With the programmability offered with the TTXREQ signal on
the rising/falling edges, the TTX data is always inserted at the
correct position of 10.2 μs after the leading edge of horizontal
sync pulse, thus enabling a source interface with variable
pipeline delays.
At the TTX input, the bit duration scheme repeats after every 37
TTX bits or 144 clock cycles. The protocol requires that TTX
Bit 10, Bit 19, Bit 28, and Bit 37 are carried by three clock cycles;
all other bits are carried by four clock cycles. After 37 TTX bits,
the next bits with three clock cycles are Bit 47, Bit 56, Bit 65,
and Bit 74. This scheme holds for all following cycles of 37 TTX
bits, until all 360 TTX bits are completed. All teletext lines are
implemented in the same way. Individual control of teletext
lines is controlled by teletext setup registers.
The width of the TTXREQ signal must always be maintained to
allow the insertion of 360 (to comply with the Teletext Standard
of PAL-WST) teletext bits at a text data rate of 6.9375 Mbits/sec;
this is achieved by setting TC03 to TC00 to 0. The insertion
window is not open if the teletext enable bit (MR35) is set to 0.
45 BYTES (360 BITS) – PAL
RUN-IN CLOCK
00221-059
ADDRESS AND DATA
TELETEXT VBI LINE
Figure 59. Teletext VBI Line
tSYNTTXOUT
CVBS/Y
tPD
tPD
HSYNC
10.2μs
TTXDATA
TTXDEL
TTXREQ
PROGRAMMABLE PULSE EDGES
tSYNTTXOUT = 10.2μs
tPD = PIPELINE DELAY THROUGH ADV7170/ADV7171
TTXDEL = TTXREQ TO TTX (PROGRAMMABLE RANGE = 4 BITS [0–15 CLOCK CYCLES])
Figure 60. Teletext Functionality Diagram
Rev. C | Page 43 of 64
00221-060
TTXST
ADV7170/ADV7171
APPENDIX 6—WAVEFORMS
NTSC Waveforms (with Pedestal)
+130.8 IRE
PEAK COMPOSITE
1268.1mV
+100 IRE
REF WHITE
1048.4mV
BLACK LEVEL
BLANK LEVEL
–40 IRE
SYNC LEVEL
48.3mV
REF WHITE
1048.4mV
387.6mV
334.2mV
00221-061
714.2mV
+7.5 IRE
0 IRE
Figure 61. NTSC Composite Video Levels
+100 IRE
+7.5 IRE
0 IRE
BLACK LEVEL
BLANK LEVEL
387.6mV
334.2mV
–40 IRE
SYNC LEVEL
48.3mV
00221-062
714.2mV
Figure 62. NTSC Luma Video Levels
PEAK CHROMA
963.8mV
629.7mV p-p
286mV p-p
BLANK/BLACK LEVEL
650mV
PEAK CHROMA
00221-063
335.2mV
0mV
Figure 63. NTSC Chroma Video Levels
+100 IRE
REF WHITE
1052.2mV
+7.5 IRE
0 IRE
BLACK LEVEL
BLANK LEVEL
387.5mV
331.4mV
–40 IRE
SYNC LEVEL
45.9mV
Figure 64. NTSC RGB Video Levels
Rev. C | Page 44 of 64
00221-064
720.8mV
ADV7170/ADV7171
NTSC Waveforms (without Pedestal)
+130.8 IRE
PEAK COMPOSITE
1289.8mV
+100 IRE
REF WHITE
1052.2mV
0 IRE
BLANK/BLACK LEVEL
338mV
SYNC LEVEL
52.1mV
–40 IRE
00221-065
714.2mV
Figure 65. NTSC Composite Video Levels
REF WHITE
+100 IRE
1052.2mV
0 IRE
BLANK/BLACK LEVEL
–40 IRE
SYNC LEVEL
338mV
52.1mV
00221-066
714.2mV
Figure 66. NTSC Luma Video Levels
978mV
PEAK CHROMA
694.9mV p-p
286mV p-p
650mV
BLANK/BLACK LEVEL
PEAK CHROMA
00221-067
299.3mV
0mV
Figure 67. NTSC Chroma Video Levels
+100 IRE
REF WHITE
1052.2mV
BLANK/BLACK LEVEL
0 IRE
SYNC LEVEL
–40 IRE
Figure 68. NTSC RGB Video Levels
Rev. C | Page 45 of 64
336.5mV
51mV
00221-068
715.7mV
ADV7170/ADV7171
PAL Waveforms
1284.2mV
PEAK COMPOSITE
1047.1mV
REF WHITE
BLANK/BLACK LEVEL
350.7mV
SYNC LEVEL
50.8mV
00221-069
696.4mV
Figure 69. PAL Composite Video Levels
1047mV
REF WHITE
BLANK/BLACK LEVEL
350.7mV
SYNC LEVEL
50.8mV
00221-070
696.4mV
Figure 70. PAL Luma Video Levels
989.7mV
PEAK CHROMA
672mV p-p
300mV p-p
650mV
BLANK/BLACK LEVEL
PEAK CHROMA
00221-071
317.7mV
0mV
Figure 71. PAL Chroma Video Levels
1050.2mV
REF WHITE
BLANK/BLACK LEVEL
351.8mV
SYNC LEVEL
51mV
Figure 72. PAL RGB Video Levels
Rev. C | Page 46 of 64
00221-072
698.4mV
ADV7170/ADV7171
+505mV
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
WHITE
YELLOW
UV Waveforms
+505mV
+423mV
+334mV
BETACAM LEVEL
+171mV
+82mV
BETACAM LEVEL
0mV
0mV
0mV
–82mV
0mV
–334mV
–423mV
–505mV
00221-073
+467mV
BLACK
BLUE
RED
MAGENTA
CYAN
WHITE
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
GREEN
Figure 76. NTSC 100% Color Bars, No Pedestal V Levels
Figure 73. NTST 100% Color Bars, No Pedestal U Levels
YELLOW
–505mV
WHITE
00221-076
–171mV
+467mV
+391mV
+309mV
BETACAM LEVEL
+158mV
+76mV
BETACAM LEVEL
0mV
0mV
–76mV
0mV
0mV
00221-077
–158mV
–391mV
–309mV
00221-074
–467mV
BLACK
BLUE
RED
MAGENTA
CYAN
WHITE
+350mV
GREEN
Figure 77. NTSC 100% Color Bars with Pedestal V Levels
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
Figure 74. NTSC 100% Color Bars with Pedestal U Levels
YELLOW
–467mV
+350mV
+293mV
+232mV
SMPTE LEVEL
+57mV
+118mV
0mV
0mV
SMPTE LEVEL
–57mV
0mV
0mV
–293mV
–232mV
00221-075
–350mV
–350mV
Figure 75. PAL 100% Color Bars, U Levels
Figure 78. PAL 100% Color Bars, V Levels
Rev. C | Page 47 of 64
00221-078
–118mV
ADV7170/ADV7171
APPENDIX 7—OPTIONAL OUTPUT FILTER
APPENDIX 8—OPTIONAL DAC BUFFERING
If an output filter is required for the CVBS, Y, UV, Chroma, and
RGB outputs of the ADV7170/ADV7171, the filter shown in
Figure 79 can be used. Plots of the filter characteristics are
shown in Figure 80. An output filter is not required if the
outputs of the ADV7170/ADV7171 are connected to most
analog monitors or analog TVs. However, if the output signals
are applied to a system where sampling is used (for example,
digital TVs), then a filter is required to prevent aliasing.
When external buffering of the ADV7170/ADV7171 DAC
outputs is needed, the configuration in Figure 81 is recommended. This configuration shows the DAC outputs running
at half (18 mA) their full current (36 mA) capability. This allows
the ADV7170/ADV7171 to dissipate less power; the analog
current is reduced by 50% with a RSET of 300 Ω and a RLOAD of
75 Ω. This mode is recommended for 3.3 V operation, because
optimum performance is obtained from the DAC outputs at
18 mA with a VAA of 3.3 V. This buffer also adds extra isolation
on the video outputs (see the buffer circuit in Figure 82).
22pF
When calculating absolute output full-scale current and voltage,
use the following equations:
1.8μH
FILTER I/P
FILTER O/P
VOUT = I OUT × RLOAD
330pF
00221-079
75R
270pF
(VREF × K )
I OUT =
Figure 79. Output Filter
RSET
K = 4.2146 constant, VREF = 1.235 V
0
10
VAA
ADV7170/ADV7171
30
VREF
DAC A
OUTPUT
BUFFER
CVBS
DAC B
OUTPUT
BUFFER
CVBS
DAC C
OUTPUT
BUFFER
LUMA
DAC D
OUTPUT
BUFFER
CHROMA
40
50
PIXEL
PORT
DIGITAL
CORE
60
1M
10M
300Ω
100M
FREQUENCY (Hz)
Figure 80. Output Filter Plot
Figure 81. Output DAC Buffering Configuration
VCC+
4
5
AD8061
INPUT/
OPTIONAL
FILTER O/P
3
1
OUTPUT TO
TV MONITOR
2
VCC–
Figure 82. Recommended Output DAC Buffer
Rev. C | Page 48 of 64
00221-082
80
100k
RSET
00221-081
70
00221-080
MAGNITUDE (dB)
20
ADV7170/ADV7171
APPENDIX 9—RECOMMENDED REGISTER VALUES
The ADV7170/ADV7171 registers can be set depending on the
user standard required.
The following examples give the various register formats for
several video standards.
In each case, the output is set to composite o/p with all DACs
powered up and with the BLANK input control disabled.
Additionally, the burst and color information are enabled on the
Table 13. PAL B/D/G/H/I (FSC = 4.43361875 MHz)
Address
00Hex
01Hex
02Hex
03Hex
04Hex
07Hex
08Hex
09Hex
0AHex
0BHex
0CHex
0DHex
0EHex
0FHex
10Hex
11Hex
12Hex
13Hex
14Hex
15Hex
16Hex
17Hex
18Hex
19Hex
Mode Register 0
Mode Register 1
Mode Register 2
Mode Register 3
Mode Register 4
Timing Register 0
Timing Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
CGMS_WSS Register 0
CGMS_WSS Register 1
CGMS_WSS Register 2
Teletext Request Control Register
output and the internal color bar generator is switched off. In
the examples shown, the timing mode is set to Mode 0 in slave
format. TR02 to TR00 of the Timing Register 0 control the
timing modes. For a detailed explanation of each bit in the
command registers, please see the Register Programming
section. TR07 should be toggled after setting up a new timing
mode. Timing Register 1 provides additional control over the
position and duration of the timing signals. In the examples,
this register is programmed in default mode.
Table 14. PAL M (FSC = 3.57561149 MHz)
Data
05Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
CBHex
8AHex
09Hex
2AHex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
Address
00Hex
01Hex
02Hex
03Hex
04Hex
07Hex
08Hex
09Hex
0AHex
0BHex
0CHex
0DHex
0EHex
0FHex
10Hex
11Hex
12Hex
13Hex
14Hex
15Hex
16Hex
17Hex
18Hex
19Hex
Rev. C | Page 49 of 64
Mode Register 0
Mode Register 1
Mode Register 2
Mode Register 3
Mode Register 4
Timing Register 0
Timing Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
CGMS_WSS Register 0
CGMS_WSS Register 1
CGMS_WSS Register 2
Teletext Request Control Register
Data
02Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
A3Hex
EFHex
E6Hex
21Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
ADV7170/ADV7171
Table 15. PAL N (FSC = 4.43361875 MHz)
Address
00Hex
01Hex
02Hex
03Hex
04Hex
07Hex
08Hex
09Hex
0AHex
0BHex
0CHex
0DHex
0EHex
0FHex
10Hex
11Hex
12Hex
13Hex
14Hex
15Hex
16Hex
17Hex
18Hex
19Hex
Mode Register 0
Mode Register 1
Mode Register 2
Mode Register 3
Mode Register 4
Timing Register 0
Timing Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
CGMS_WSS Register 0
CGMS_WSS Register 1
CGMS_WSS Register 2
Teletext Request Control Register
Table 17. Power-Up Reset Values NTSC (FSC = 3.5795454 MHz)
Data
05Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
CBHex
8AHex
09Hex
2AHex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
Address
00Hex
01Hex
02Hex
03Hex
04Hex
07Hex
08Hex
09Hex
0AHex
0BHex
0CHex
0DHex
0EHex
0FHex
10Hex
11Hex
12Hex
13Hex
14Hex
15Hex
16Hex
17Hex
18Hex
19Hex
Table 16. PAL60 (FSC = 4.43361875 MHz)
Address
00Hex
01Hex
02Hex
03Hex
04Hex
07Hex
08Hex
09Hex
0AHex
0BHex
0CHex
0DHex
0EHex
0FHex
10Hex
11Hex
12Hex
13Hex
14Hex
15Hex
16Hex
17Hex
18Hex
19Hex
Mode Register 0
Mode Register 1
Mode Register 2
Mode Register 3
Mode Register 4
Timing Register 0
Timing Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
CGMS_WSS Register 0
CGMS_WSS Register 1
CGMS_WSS Register 2
Teletext Request Control Register
Data
04Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
CBHex
8AHex
09Hex
2AHex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
Rev. C | Page 50 of 64
Mode Register 0
Mode Register 1
Mode Register 2
Mode Register 3
Mode Register 4
Timing Register 0
Timing Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
CGMS_WSS Register 0
CGMS_WSS Register 1
CGMS_WSS Register 2
Teletext Request Control Register
Data
00Hex
58Hex
00Hex
00Hex
10Hex
00Hex
00Hex
16Hex
7CHex
F0Hex
21Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
ADV7170/ADV7171
APPENDIX 10—OUTPUT WAVEFORMS
0.6
VOLTS
0.4
0.2
0.0
–0.2
L608
0.0
10.0
20.0
30.0
40.0
50.0
60.0
MICROSECONDS
NOISE REDUCTION: 0.00dB
PRECISION MODE OFF
NO FILTERING
SOUND-IN-SYNC OFF
SYNCHRONOUS
SLOW CLAMP TO 0.00V AT 6.72μs
00221-083
APL = 39.1%
625 LINE PAL
SYNC = SOURCE
FRAMES SELECTED: 1 2 3 4
Figure 83. 100/0/75/0 PAL Color Bars
VOLTS
0.5
0.0
L575
10.0
20.0
APL NEEDS SYNC = SOURCE!
625 LINE PAL
NO FILTERING
30.0
40.0
50.0
MICROSECONDS
PRECISION MODE OFF
SYNCHRONOUS
SLOW CLAMP TO 0.00V AT 6.72μs
60.0
SOUND-IN-SYNC OFF
SYNC = A
FRAMES SELECTED: 1
Figure 84. 100/0/75/0 PAL Color Bars Luminance
Rev. C | Page 51 of 64
70.0
00221-084
0.0
ADV7170/ADV7171
VOLTS
0.5
0.0
–0.5
L575
20.0
30.0
40.0
50.0
MICROSECONDS
APL NEEDS SYNC = SOURCE!
625 LINE PAL
NO FILTERING
60.0
NO BRUCH SIGNAL
PRECISION MODE OFF
SYNCHRONOUS
SLOW CLAMP TO 0.00V AT 6.72μs
SOUND-IN-SYNC OFF
SYNC = A
FRAMES SELECTED: 1
Figure 85. 100/0/75/0 Pal Color Bars Chrominance
100.0
VOLTS
IRE:FLT
0.5
50.0
0.0
0.0
F1
L76
0.0
10.0
20.0
APL = 44.6%
525 LINE NTSC
30.0
40.0
MICROSECONDS
50.0
60.0
PRECISION MODE OFF
NO FILTERING
SYNCHRONOUS
SLOW CLAMP TO 0.00V AT 6.72μs
SYNC = A
FRAMES SELECTED: 1 2
Figure 86. 100/7.5/75/7.5 NTSC Color Bars
Rev. C | Page 52 of 64
00221-086
–50.0
00221-085
10.0
ADV7170/ADV7171
0.6
0.4
IRE:FLT
VOLTS
50.0
0.2
0.0
0.0
–0.2
F2
L238
10.0
20.0
30.0
40.0
MICROSECONDS
50.0
60.0
APL = 44.7%
525 LINE NTSC
PRECISION MODE OFF
NO FILTERING
SYNCHRONOUS
SLOW CLAMP TO 0.00V AT 6.72μs
SYNC = SOURCE
FRAMES SELECTED: 1 2
00221-087
NOISE REDUCTION: 15.05dB
Figure 87. 100/7.5/75/7.5 NTSC Color Bars Luminance
0.4
50.0
0.0
IRE:FLT
VOLTS
0.2
–0.2
–50.0
–0.4
F1
L76
10.0
20.0
NOISE REDUCTION: 15.05dB
APL NEEDS SYNC = SOURCE!
525 LINE NTSC
30.0
40.0
MICROSECONDS
50.0
60.0
PRECISION MODE OFF
NO FILTERING
SYNCHRONOUS
SLOW CLAMP TO 0.00V AT 6.72μs
SYNC = B
FRAMES SELECTED: 1 2
Figure 88. 100/7.5/75/7.5 NTSC Color Bars Chrominance
Rev. C | Page 53 of 64
00221-088
0.0
ADV7170/ADV7171
V
APL = 39.6%
SYSTEM LINE L608
ANGLE (DEG) 0.0
GAIN × 1.000 0.000dB
625 LINE PAL
BURST FROM SOURCE
DISPLAY +V AND –V
cy
R
g
M
g
75%
100%
YI
b
U
yl
B
G
Cy
m
g
00221-089
r
SOUND IN SYNC OFF
Figure 89. PAL Vector Plot
R–Y
APL = 45.1%
SYSTEM LINE L76F1
ANGLE (DEG) 0.0
GAIN × 1.000 0.000dB
525 LINE NTSC
BURST FROM SOURCE
cy
I
R
M
g
YI
Q
b
100%
B–Y
75%
B
G
Cy
–Q
00221-090
–I
SETUP 7.5%
Figure 90. NTSC Vector Plot
Rev. C | Page 54 of 64
ADV7170/ADV7171
WFM →
COLOR BAR (NTSC)
FIELD = 2 LINE = 28
LUMINANCE LEVEL (IRE)
0.4
0.2
FCC COLOR BAR
0.2
0.0
0.2
0.1
0.2
0.1
–0.2
–0.3
–0.2
–0.3
0.0
0.0
–0.2
–0.2
–0.1
–0.3
–0.2
30.0
20.0
10.0
0.0
–10.0
CHROMINANCE LEVEL (IRE)
0.0
–0.2
1.0
0.0
–1.0
CHROMINANCE PHASE (DEG)
.....
–0.1
-----
0.0
–1.0
GRAY
AVERAGE:
YELLOW
32 → 32
CYAN
GREEN
MAGENTA
RED
BLUE
BLACK
REFERENCE 75/7.5/75/7.5 COLOR BAR STANDARD
00221-091
–2.0
Figure 91. NTSC Color Bar Measurement
WFM →
DGDP (NTSC)
MOD 5 STEP
BLOCK MODE START F2 L64, STEP = 32, END = 192
DIFFERENTIAL GAIN (%)
MIN = –0.00 MAX = 0.11 p-p/MAX = 0.11
0.00
0.08
0.07
0.11
0.07
0.05
0.3
0.2
0.1
0.0
–0.1
DIFFERENTIAL PHASE (DEG)
0.00
0.03
–0.02
MIN = 0.02 MAX = 0.14 p-p = 0.16
0.14
0.10
0.10
0.20
0.15
0.10
0.05
–0.00
–0.10
1ST
2ND
3RD
4TH
5TH
Figure 92. NTSC Differential Gain and Phase Measurement
Rev. C | Page 55 of 64
6TH
00221-092
–0.05
ADV7170/ADV7171
WFM →
LUMINANCE NONLINEARITY (NTSC)
FIELD = 2 LINE = 21
LUMINANCE NONLINEARITY (%)
99.9
100.0
99.9
5 STEP
p-p = 0.2
99.9
99.8
100.4
100.3
100.2
100.1
100.0
99.9
99.8
99.7
99.6
99.5
99.4
99.3
99.2
99.1
99.0
98.9
98.8
00221-093
98.7
98.6
1ST
2ND
3RD
4TH
5TH
Figure 93. NTSC Luminance Nonlinearity Measurement
WFM →
CHROMINANCE AM PM (NTSC)
FULL FIELD (BOTH FIELDS)
BANDWIDTH 100Hz TO 500kHz
APPROPRIATE
AM NOISE
–68.4dB RMS
–75.0
–70.0
–65.0
–60.0
–55.0
–45.0
–40.0
dB RMS
–45.0
–40.0
dB RMS
–64.4dB RMS
–75.0
–70.0
–65.0
–60.0
–55.0
–50.0
(0dB = 714mV p-p WITH AGC FOR 100% CHROMINANCE LEVEL)
Figure 94. NTSC AMPM Noise Measurement
Rev. C | Page 56 of 64
00221-094
PM NOISE
–50.0
ADV7170/ADV7171
WFM →
NOISE SPECTRUM (NTSC)
FIELD = 2 LINE = 64
AMPLITUDE (0dB = 714mV p-p)
BANDWIDTH 100kHz TO FULL
PEDESTAL
NOISE LEVEL = –80.1dB RMS
–5.0
–10.0
–15.0
–20.0
–25.0
–30.0
–35.0
–40.0
–45.0
–50.0
–55.0
–60.0
–65.0
–70.0
–75.0
–80.0
–85.0
–90.0
–95.0
1.0
2.0
3.0
4.0
5.0
6.0
(MHz)
00221-095
–100.0
Figure 95. NTSC SNR Pedestal Measurement
WFM →
NOISE SPECTRUM (NTSC)
FIELD = 2 LINE = 64
AMPLITUDE (0dB = 714mV p-p)
BANDWIDTH 10kHz TO FULL (TILT NULL)
RAMP SIGNAL
NOISE LEVEL = –61.7dB RMS
–5.0
–10.0
–15.0
–20.0
–25.0
–30.0
–35.0
–40.0
–45.0
–50.0
–55.0
–60.0
–65.0
–70.0
–75.0
–80.0
–85.0
–90.0
–95.0
1.0
2.0
3.0
4.0
(MHz)
Figure 96. NTSC SNR Ramp Measurement
Rev. C | Page 57 of 64
5.0
00221-096
–100.0
ADV7170/ADV7171
PARADE SMPTE/EBU PAL
Y(A)
mV
Pb(B)
mV
Pr(C)
250
250
600
200
200
500
150
150
400
100
100
300
50
50
200
0
0
–50
–50
0
–100
–100
–100
–150
–150
–200
–200
–200
–250
–250
100
–300
00221-097
mV
700
Figure 97. PAL YUV Parade Plot
LIGHTNING
L183
YI
–274.82
0.93%
COLORBARS: 75% SMPTE/EBU (50Hz)
Pk-WHITE (100%) 700.0mV SETUP 0.0% COLOR p-p 525.0mV
G
–173.24
0.19%
R
–88.36
0.19%
CY
88.31
0.28%
AVERAGE 32 → 32
M
174.35
–0.65%
B
260.51
–0.14%
B–Y
W
YI
462.80
–0.50%
CY
864.78
–0.88%
YI
G
307.54
–0.21%
G
CY
R
M
216.12
–0.33%
M
R
156.63
–0.22%
B
B
61.00
1.92%
B
R
G
M
CY
YI
W
R–Y
G
–218.70
–0.51%
B
–42.54
0.69%
COLOR Pk-Pk: B–Y 532.33mV
1.40%
Pk-WHITE: 700.4mV (100%) SETUP –0.01%
YI
41.32
–0.76%
R–Y 514.90mV
–1.92%
DELAY: B–Y –6ns R–Y –6ns
Figure 98. PAL YUV Lighting Plot
Rev. C | Page 58 of 64
M
212.28
–3.43%
R
252.74
–3.72%
00221-098
CY
–262.17
–0.13%
ADV7170/ADV7171
COMPONENT NOISE
LINE = 202
AMPLITUDE (0dB = 700mV p-p)
BANDWIDTH 10kHz TO 5.0MHz
NOISE dB RMS
0.0
–5.0
–10.0
→Y 82.1
Pb 82.3
Pr 83.3
–15.0
–20.0
–25.0
–30.0
–35.0
–40.0
–45.0
–50.0
–55.0
–60.0
–65.0
–70.0
–75.0
–80.0
–85.0
–90.0
–95.0
1.0
2.0
3.0
4.0
5.0
00221-099
–100.0
6.0
(MHz)
Figure 99. PAL YUV SNR Plot
COMPONENT MULTIBURST
LINE = 202
AMPLITUDE (0dB = 100% OF
688.1mV
683.4mV
668.9mV)
(dB)
0.04
–0.02
–0.05
–0.68
–2.58
–8.05
0.49
0.99
2.00
3.99
4.79
5.79
0.0
Y
–5.0
–10.0
0.21
0.23
–0.78
–2.59
–7.15
0.49
0.99
1.99
2.39
2.89
0.25
0.25
–0.77
–2.59
–7.13
0.49
0.99
1.99
2.39
2.89
0.0
Pb
–5.0
–10.0
0.0
–5.0
–10.0
(MHz)
Figure 100. PAL YUV Multiburst Response
Rev. C | Page 59 of 64
00221-100
Pr
ADV7170/ADV7171
COMPONENT VECTOR SMPTE/EBU, 75%
R
M
g
YI
BK
B
G
00221-101
CY
Figure 101. PAL YUV Vector Plot
GREEN (A)
mV
BLUE (B)
mV
RED (C)
700
700
600
600
500
500
400
400
300
300
300
200
200
200
100
100
100
0
0
0
700
600
500
400
–100
–100
–100
–200
–200
–200
–300
–300
–300
Figure 102. PAL RGB Waveforms
Rev. C | Page 60 of 64
00221-102
mV
ADV7170/ADV7171
OUTLINE DIMENSIONS
1.03
0.88
0.73
14.15
13.90 SQ
13.65
2.45
MAX
34
44
1.95 REF
1
33
PIN 1
SEATING
PLANE
10.20
10.00 SQ
9.80
TOP VIEW
(PINS DOWN)
2.20
2.00
1.80
0.23
0.11
23
11
7°
0°
0.25 MIN
0.10
COPLANARITY
22
12
VIEW A
VIEW A
0.80 BSC
LEAD PITCH
0.45
0.30
LEAD WIDTH
041807-A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MO-112-AA-1
Figure 103. 44-Lead Thin Plastic Quad Flat Package [MQFP]
(S-44-2)
Dimensions shown in millimeters
1.20
MAX
0.75
0.60
0.45
12.00 BSC SQ
34
44
1
33
PIN 1
TOP VIEW
10.00
BSC SQ
(PINS DOWN)
0° MIN
1.05
1.00
0.95
0.15
0.05
SEATING
PLANE
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
23
11
12
VIEW A
VIEW A
22
0.80
BSC
LEAD PITCH
ROTATED 90° CCW
0.45
0.37
0.30
COMPLIANT TO JEDEC STANDARDS MS-026ACB
Figure 104. 44-Lead Thin Plastic Quad Flat Package [TQFP]
(SU-44)
Dimensions shown in millimeters
Rev. C | Page 61 of 64
ADV7170/ADV7171
1.03
0.88
0.73
13.45
13.20 SQ
12.95
2.45
MAX
34
44
1.60 REF
1
33
PIN 1
SEATING
PLANE
10.20
10.00 SQ
9.80
TOP VIEW
(PINS DOWN)
2.20
2.00
1.80
0.23
0.11
23
11
0.25
0.10
7°
0°
0.10
COPLANARITY
VIEW A
VIEW A
22
12
0.80 BSC
LEAD PITCH
0.45
0.29
LEAD WIDTH
COMPLIANT TO JEDEC STANDARDS MS-022-AB-1
041807-A
ROTATED 90° CCW
Figure 105. 44-Lead Metric Quad Flat Package [MQFP]
(S-44-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADV7170KSZ 1
ADV7170KSZ-REEL1
ADV7170KSUZ1
ADV7170KSUZ-REEL1
ADV7171KSZ1
ADV7171KSZ-REEL1
ADV7171KSUZ1
ADV7171KSUZ-REEL1
ADV7171WBSZ-REEL1
EVAL-ADV7170EBM
EVAL-ADV7171EBM
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Descriptions
44-Lead Metric Quad Flat Package [MQFP]
44-Lead Metric Quad Flat Package [MQFP]
44-Lead Thin Plastic Quad Flat Package [TQFP]
44-Lead Thin Plastic Quad Flat Package [TQFP]
44-Lead Metric Quad Flat Package [MQFP]
44-Lead Metric Quad Flat Package [MQFP]
44-Lead Thin Plastic Quad Flat Package [TQFP]
44-Lead Thin Plastic Quad Flat Package [TQFP]
44-Lead Metric Quad Flat Package [MQFP]
Evaluation Board
Evaluation Board
Z = RoHS Compliant Part.
Rev. C | Page 62 of 64
Package Options
S-44-2
S-44-2
SU-44
SU-44
S-44-2
S-44-2
SU-44
SU-44
S-44-1
ADV7170/ADV7171
NOTES
Rev. C | Page 63 of 64
ADV7170/ADV7171
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2002–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
Printed in the U.S.A.
D00221-0-3/09(C)
Rev. C | Page 64 of 64