Fujitsu MB90884SPMC 16-bit proprietary microcontroller Datasheet

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13743-2E
16-Bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90880 Series
MB90F882(S)/F883(S)/F883A(S)/F884(S)/F884A(S)
MB90882(S)/883(S)/884(S)/V880(A)-101/-102
■ DESCRIPTION
The MB90880 series is a general-purpose 16-bit microcontroller, designed by Fujitsu, for process control of
devices such as consumer appliances, which require high-speed real-time processing capabilities.
The instruction set of the F2MC-16LX CPU core retains the same AT architecture as the F2MC*1 family, with further
refinements including high-level language instructions, an expanded addressing mode, enhanced multiplierdivider instructions and bit processing. In addition, a 32-bit accumulator is built in to enable long word processing.
As its peripheral resources, the MB90880 series has a 16-bit PPG, multi-function serial interface (software switch
over enabled for SIO, UART and I2C*2) , 10-bit A/D converter, 16-bit I/O timer, 8/16-bit up-down counter, base
timer (software switch over enabled for 16-bit reload timer, PWC timer, PPG timer and PWM timer) ,
DTP / external interrupt and chip select pins.
*1 : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
*2 : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these
components in an I2C system provided that the system conforms to the I2C Standard Specification as defined
by Philips.
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2006-2007 FUJITSU LIMITED All rights reserved
MB90880 Series
■ FEATURES
• Clock
Minimum instruction execution time : 30.3 ns / 4.125 MHz source oscillation × eight times
(in internal operation : 33 MHz/3.3 V ± 0.3 V)
PLL clock multiplication system
• Maximum memory space
16 Mbytes
• Instruction set optimized for control applications
Supported data types : bit, byte, word and long word
Standard addressing modes : 23 types
Enhanced high-precision calculation realized by 32-bit accumulator
Signed multiplication/division instructions and extended RETI instruction functions
• Instruction set supporting high-level language (C language) and multi-task operations
Introduction of system stack pointer
Symmetrical instruction set and barrel shift instructions
• Improved execution speed
4-byte queue
• Powerful interrupt functions
Eight priority levels programmable; External interrupts : 24
• Data transfer functions (µDMAC)
Up to 16 channels
• Built-in ROM
Flash ROM : 256, 384 and 512 Kbytes; MASK ROM : 256, 384 and 512 Kbytes
• Built-in RAM
Flash RAM : 16, 24 and 30 Kbytes; MASK RAM : 16, 24 and 30 Kbytes
• General-purpose ports
Dual clock product : up to 81 channels; Single clock product : up to 83 channels
• A/D converter
RC successive approximation conversion type : 20 channels (Resolution : 8 or 10 bits)
• Multi-function serial interface
7 channels (software switchable between for SIO, UART and I2C)
• 16-bit PPG
8 channels
• 8/16-bit up-down counter/timer
Event input pins : 6
8-bit up-down counters : 2
8-bit reload/compare registers : 2
• Base timer
4 channels (software switchable between 16-bit reload timer, PWC timer, PPG timer, and PWM timer)
• 16-bit I/O timer
Input capture × 2 channels, output compare × 6 channels, free run timer × 1 channel
• Built-in dual clock generator
• Low power consumption modes
Stop mode, sleep mode, CPU intermittent operation mode, watch timer, time base timer mode
• Package
QFP-100/LQFP-100
• Process
CMOS technology
• Power supply voltage
3V : Single power supply operation
2
MB90880 Series
■ PRODUCT LINEUP
Item
Name
Class
MB90882 (S) MB90883 (S) MB90884 (S) MB90F882 (S)
MASK ROM product
MB90F883 (S) / MB90F884 (S) /
MB90F883A (S) MB90F884A (S)
Flash memory product
ROM size
256 Kbytes
384 Kbytes
512 Kbytes
256 Kbytes
384 Kbytes
512 Kbytes
RAM size
16 Kbytes
24 Kbytes
30 Kbytes
16 Kbytes
24 Kbytes
30 Kbytes
CPU functions
Number of instructions
Instruction bit length
Instruction length
Data bit length
Minimum execution time
: 351
: 8 bits, 16 bits
: 1 to 7 bytes
: 1 bit, 8 bits, 16 bits
: 30.3 ns (machine clock : 33 MHz)
The maximum operating frequency of MB90F883(S) and MB90F884(S) is 25 MHz.
Ports
General-purpose I/O ports : up to 81 for dual clock model, up to 83 for single clock model
General-purpose I/O ports (CMOS output)
Multi-function
serial interface
7 channels (software switchable between SIO, UART & I2C)
16-bit PPG timer
8 channels
8/16-bit up-down
counter/timer
Event input pins : 6, 8-bit up-down counters : 2
8-bit reload/compare registers : 2
16-bit
free run
timer
16-bit
I/O
timer
Number of channels : 1
Overflow interrupt
Output
Number of channels : 6
compare
Pin input source : Match signal of compare register
(OCU)
Input
capture
(ICU)
Number of channels : 2
Rewriting register by pin input (rising, falling or both edges)
DTP/external
interrupt circuit
External interrupt pins : 24 channels (edge/level support)
Base timer
4 channels
(software switchable between 16-bit reload timer, PWC timer, PPG timer, and PWM timer)
In MB90F883(S) and MB90F884(S), P24/TIO0, P25/TIO1, P26/TIO2, and P27/TIO3
cannot be used as input function.
Time base timer
18-bit counter
Interrupt interval : 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (source oscillation : 4 MHz)
A/D converter
Conversion accuracy : 8 or 10 bits can be switched
Single conversion mode (Selected channel converted only once)
Scan conversion mode (Multiple successive channels converted)
Successive conversion mode (Selected channel converted repeatedly)
Stop conversion mode (Selected channel converted and stopped repeatedly)
Watchdog timer
Reset generation interval : 3.58 ms, 14.33 ms, 57.23ms, 458.75 ms
(source oscillation : 4 MHz, minimum value)
(Continued)
3
MB90880 Series
(Continued)
Item
Name
Low power
consumption
(standby)
modes
Flash memory
Process
4
MB90882 (S) MB90883 (S) MB90884 (S) MB90F882 (S)
MB90F883 (S) / MB90F884 (S) /
MB90F883A (S) MB90F884A (S)
Sleep, stop, CPU intermittent operation, watch timer, time base timer
⎯
Flash security/ write-protect feature
(not available in MB90F883(S), MB90F884(S),
MB90F883A(S), and MB90F884A(S))
CMOS technology
MB90880 Series
■ PIN ASSIGNMENTS
X1
VSS
VCC
P14/AD12/D12/OUT4
P13/AD11/D11/OUT3
P12/AD10/D10/OUT2
P11/AD09/D09/OUT1
P10/AD08/D08/OUT0
P07/AD07/D07/IRQ7
P06/AD06/D06/IRQ6
P05/AD05/D05/IRQ5
P04/AD04/D04/IRQ4
92
91
90
89
88
87
86
85
84
83
82
81
P16/AD14/D14/IN0
95
P15/AD13/D13/OUT5
P17/AD15/D15/IN1
96
X0
P20/A16/PPG0
97
93
P21/A17/PPG1
98
94
P22/A18/PPG2
99
100 P23/A19/PPG3
(TOP VIEW)
P24/A20/TIO0
1
80
P03/AD03/D03/IRQ3
P25/A21/TIO1
2
79
P02/AD02/D02/IRQ2
P26/A22/TIO2
3
78
P01/AD01/D01/IRQ1
P27/A23/TIO3
4
77
P00/AD00/D00/IRQ0
P30/A00/ZIN0/UI1
5
76
P57/CLK/PPG7
P31/A01/AIN0/UO1
6
75
P56/RDY/PPG6
P32/A02/BIN0/UCK1
7
74
P55/HAK/PPG5
P33/A03/UI2
8
73
P54/HRQ/PPG4
P34/A04/UO2
9
72
P53/WRH/IRQ23
P35/A05/ZIN1/UCK2
10
71
P52/WRL
P36/A06/AIN1/IRQ8
11
70
P51/RD
P37/A07/BIN1/IRQ9
12
69
P50/ALE
P40/A08/X0A*
13
68
PA3/(PPG7)/IRQ22
P41/A09/X1A*
14
67
PA2/(PPG6)/IRQ21
VCC
15
66
DVSS
VSS
16
65
DVCC
C
17
64
PA1/(PPG5)/IRQ20
P42/A10/UI3
18
63
PA0/(PPG4)/IRQ19
P43/A11/UO3
19
62
P87/IRQ18/ADTG
P44/A12/UCK3
20
61
P86/UCK0
P45/A13/UI4
21
60
P85/UO0
P46/A14/UO4
22
59
P84/UI0
P47/A15/UCK4
23
58
P83/IRQ17
P90/CS0/AN8
24
57
P82/IRQ16/UCK6
P91/CS1/AN9
25
56
P81/UO6
P92/CS2/AN10
26
55
P80/IRQ15/UI6
P93/CS3/AN11
27
54
RST
P94/AN12
28
53
MD0
P95/(UI3)/AN13
29
52
MD1
P96/(UO3)/AN14
30
51
MD2
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P97/(UCK3)/AN15
AVCC
AVRH
P70/AN16
AVSS
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
VSS
P71/(UI4)/IRQ10/AN17
P72/(UO4)/IRQ11/AN18
P73/(UCK4)/IRQ12/AN19
P74/IRQ13/UI5
P75/UO5
P76/IRQ14/UCK5
QFP-100
(FPT-100P-M06)
* : dual clock product is sub clock oscillation pin.
5
MB90880 Series
P25/A21/TIO1
P24/A20/TIO0
P23/A19/PPG3
P22/A18/PPG2
P21/A17/PPG1
P20/A16/PPG0
P17/AD15/D15/IN1
P16/AD14/D14/IN0
P15/AD13/D13/OUT5
X0
X1
VSS
VCC
P14/AD12/D12/OUT4
P13/AD11/D11/OUT3
P12/AD10/D10/OUT2
P11/AD09/D09/OUT1
P10/AD08/D08/OUT0
P07/AD07/D07/IRQ7
P06/AD06/D06/IRQ6
P05/AD05/D05/IRQ5
P04/AD04/D04/IRQ4
P03/AD03/D03/IRQ3
P02/AD02/D02/IRQ2
P01/AD01/D01/IRQ1
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
(TOP VIEW)
P26/A22/TIO2
1
75
P00/AD00/D00/IRQ0
P27/A23/TIO3
2
74
P57/CLK/PPG7
P30/A00/ZIN0/UI1
3
73
P56/RDY/PPG6
P31/A01/AIN0/UO1
4
72
P55/HAK/PPG5
P32/A02/BIN0/UCK1
5
71
P54/HRQ/PPG4
P33/A03/UI2
6
70
P53/WRH/IRQ23
P34/A04/UO2
7
69
P52/WRL
P35/A05/ZIN1/UCK2
8
68
P51/RD
P36/A06/AIN1/IRQ8
9
67
P50/ALE
P37/A07/BIN1/IRQ9
10
66
PA3/(PPG7)/IRQ22
P40/A08/X0A*
11
65
PA2/(PPG6)/IRQ21
P41/A09/X1A*
12
64
DVSS
VCC
13
63
DVCC
VSS
14
62
PA1/(PPG5)/IRQ20
C
15
61
PA0/(PPG4)/IRQ19
P42/A10/UI3
16
60
P87/IRQ18/ADTG
P43/A11/UO3
17
59
P86/UCK0
P44/A12/UCK3
18
58
P85/UO0
P45/A13/UI4
19
57
P84/UI0
P46/A14/UO4
20
56
P83/IRQ17
P47/A15/UCK4
21
55
P82/IRQ16/UCK6
P90/CS0/AN8
22
54
P81/UO6
P91/CS1/AN9
23
53
P80/IRQ15/UI6
P92/CS2/AN10
24
52
RST
P93/CS3/AN11
25
51
MD0
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P94/AN12
P95/(UI3)/AN13
P96/(UO3)/AN14
P97/(UCK3)/AN15
AVCC
AVRH
P70/AN16
AVSS
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
VSS
P71/(UI4)/IRQ10/AN17
P72/(UO4)/IRQ11/AN18
P73/(UCK4)/IRQ12/AN19
P74/IRQ13/UI5
P75/UO5
P76/IRQ14/UCK5
MD2
MD1
LQFP-100
(FPT-100P-M20)
* : dual clock product is sub clock oscillation pin.
6
MB90880 Series
■ PIN DESCRIPTIONS
Pin no.
LQFP *1
QFP *2
Pin
name
I/O
circuit
type*3
P26
1
2
3
4
3
4
5
6
A22
General-purpose I/O port
D
P27
General-purpose I/O port
A23
D
P30
General-purpose I/O port
A00
ZIN0
E
9
Serves as an external address pin in non-multiplex mode.
8/16-bit up-down counter/timer input pin (ch.0)
UI1
Multi-function serial input pin
P31
General-purpose I/O port
A01
Serves as an external address pin in non-multiplex mode.
AIN0
E
BIN0
A03
8/16-bit up-down counter/timer input pin (ch.0)
Multi-function serial output pin
General-purpose I/O port
Serves as an external address pin in non-multiplex mode.
E
8/16-bit up-down counter/timer input pin (ch.0)
Multi-function serial clock I/O pin
P33
7
In non-multiplex mode, it serves as higher address output pin (A23)
when corresponding bit in external address output control register
(HACR) is set to "0".
Base timer I/O pin (ch.3)
UCK1/
(SCL1)
8
In multiplex mode, it serves as higher address output pin (A23) when
corresponding bit in external address output control register (HACR)
is set to "0".
TIO3
A02
6
In non-multiplex mode, it serves as higher address output pin (A22)
when corresponding bit in external address output control register
(HACR) is set to "0".
Base timer I/O pin (ch.2)
P32
7
In multiplex mode, it serves as higher address output pin (A22) when
corresponding bit in external address output control register (HACR)
is set to "0".
TIO2
UO1/
(SDA1)
5
Function
General-purpose I/O port
E
Serves as an external address pin in non-multiplex mode.
UI2
Multi-function serial input pin
P34
General-purpose I/O port
A04
UO2/
(SDA2)
E
Serves as an external address pin in non-multiplex mode.
Multi-function serial output pin
(Continued)
7
MB90880 Series
Pin no.
LQFP *1
QFP *2
Pin
name
I/O
circuit
type*3
P35
General-purpose I/O port
A05
8
10
ZIN1
Serves as an external address pin in non-multiplex mode.
E
UCK2/
(SCL2)
10
11
12
11
12
13
14
A06
AIN1
8/16-bit up-down counter/timer input pin (ch.1)
Multi-function serial clock I/O pin
P36
9
Function
General-purpose I/O port
D
Serves as an external address pin in non-multiplex mode.
8/16-bit up-down counter/timer input pin (ch.1)
IRQ8
External interrupt input pin
P37
General-purpose I/O port
A07
BIN1
D
Serves as an external address pin in non-multiplex mode.
8/16-bit up-down counter/timer input pin (ch.1)
IRQ9
External interrupt input pin
P40
General-purpose I/O port
A08
A/D
Serves as an external address pin in non-multiplex mode.
X0A
32 kHz oscillator connecting pin
P41
General-purpose I/O port
A09
A/D
X1A
Serves as an external address pin in non-multiplex mode.
32 kHz oscillator connecting pin
13
15
VCC
-
Power supply pin
14
16
VSS
-
Power supply pin (GND)
15
17
C
-
Regulator stabilization capacity connecting pin
P42
16
17
18
19
A10
General-purpose I/O port
E
UI3
Multi-function serial input pin
P43
General-purpose I/O port
A11
E
UO3/
(SDA3)
20
A12
General-purpose I/O port
E
UCK3/
(SCL3)
21
A13
UI4
Serves as an external address pin in non-multiplex mode.
Multi-function serial clock I/O pin
P45
19
Serves as an external address pin in non-multiplex mode.
Multi-function serial output pin
P44
18
Serves as an external address pin in non-multiplex mode.
General-purpose I/O port
E
Serves as an external address pin in non-multiplex mode.
Multi-function serial input pin
(Continued)
8
MB90880 Series
Pin no.
LQFP *1
QFP *2
Pin
name
I/O
circuit
type*3
P46
20
22
A14
General-purpose I/O port
E
UO4/
(SDA4)
23
A15
General-purpose I/O port
E
UCK4/
(SCL4)
23
24
24
25
26
CS0
General-purpose I/O port
H
Analog input pin
P91
General-purpose I/O port
CS1
H
Analog input pin
P92
General-purpose I/O port
CS2
H
CS3
28
P94
AN12
General-purpose I/O port
H
28
29
30
AN13
H
K
Analog input pin
Analog input pin
(UI3)
Multi-function serial input pin (when set by P9FSR register)
P96
General-purpose I/O port
AN14
K
AN15
Analog input pin
Multi-function serial output pin (when set by P9FSR register)
P97
31
General-purpose I/O port
General-purpose I/O port
(UO3)/
(SDA3)
29
Chip select 3
Analog input pin
P95
27
Chip select 2
Analog input pin
AN11
26
Chip select 1
AN9
P93
27
Chip select 0
AN8
AN10
25
Serves as an external address pin in non-multiplex mode.
Multi-function serial clock I/O pin
P90
22
Serves as an external address pin in non-multiplex mode.
Multi-function serial output pin
P47
21
Function
General-purpose I/O port
K
(UCK3)/
(SCL3)
Analog input pin
Multi-function serial clock I/O pin (when set by P9FSR register)
30
32
AVCC
-
A/D converter power supply pin
31
33
AVRH
-
A/D converter external reference power supply pin
32
34
P70
AN16
H
General-purpose I/O port
Analog input pin
(Continued)
9
MB90880 Series
Pin no.
LQFP *1
QFP *2
Pin
name
33
35
AVSS
34
36
35
37
36
38
37
39
38
40
39
41
40
42
41
43
42
44
P60
AN0
P61
AN1
P62
AN2
P63
AN3
P64
AN4
P65
AN5
P66
AN6
P67
AN7
VSS
I/O
circuit
type*3
H
H
H
H
H
H
H
H
-
P71
43
44
45
46
IRQ10
AN17
K
General-purpose I/O port
Analog input pin
General-purpose I/O port
Analog input pin
General-purpose I/O port
Analog input pin
General-purpose I/O port
Analog input pin
General-purpose I/O port
Analog input pin
General-purpose I/O port
Analog input pin
General-purpose I/O port
Analog input pin
Power supply pin (GND)
External interrupt input pin
Analog input pin
P72
General-purpose I/O port
IRQ11
External interrupt input pin
AN18
K
AN19
General-purpose I/O port
External interrupt input pin
K
UI5
Analog input pin
Multi-function serial clock I/O pin (when set by F7FSR register)
P74
IRQ13
Analog input pin
Multi-function serial output pin (when set by P7FSR register)
(UCK4)/
(SCL4)
48
Analog input pin
Multi-function serial input pin (when set by P7FSR register)
IRQ12
46
General-purpose I/O port
(UI4)
P73
47
A/D converter power supply pin
General-purpose I/O port
(UO4)/
(SDA4)
45
Function
General-purpose I/O port
G
External interrupt input pin
Multi-function serial input pin
(Continued)
10
MB90880 Series
Pin no.
LQFP *1
QFP *2
47
49
Pin
name
I/O
circuit
type*3
P75
UO5/
(SDA5)
General-purpose I/O port
G
P76
48
50
IRQ14
Function
Multi-function serial output pin
General-purpose I/O port
G
UCK5/
(SCL5)
External interrupt input pin
Multi-function serial clock I/O pin
49
51
MD2
L
Operation mode specification input pin
50
52
MD1
L
Operation mode specification input pin
51
53
MD0
L
Operation mode specification input pin
52
54
RST
B
Reset input pin
P80
53
55
IRQ15
General-purpose I/O port
G
UI6
Multi-function serial input pin
P81
54
56
UO6/
(SDA6)
General-purpose I/O port
G
P82
55
57
IRQ16
58
57
59
58
60
59
61
P83
IRQ17
P84
UI0
G
I
G
62
IRQ18
I
IRQ19
(PPG4)
Multi-function serial input pin
Multi-function serial output pin
Multi-function serial clock I/O pin
External interrupt input pin
External trigger input pin, when A/D converter is used.
PA0
63
General-purpose I/O port
General-purpose I/O port
ADTG
61
External interrupt input pin
General-purpose I/O port
G
P87
60
General-purpose I/O port
General-purpose I/O port
G
P86
UCK0/
(SCL0)
External interrupt input pin
Multi-function serial clock I/O pin
P85
UO0/
(SDA0)
Multi-function serial output pin
General-purpose I/O port
UCK6/
(SCL6)
56
External interrupt input pin
General-purpose I/O port
J
External interrupt input pin
PPG timer output pin (when set by PAFSR register)
(Continued)
11
MB90880 Series
Pin no.
LQFP *1
QFP *2
Pin
name
I/O
circuit
type*3
PA1
62
64
IRQ20
Function
General-purpose I/O port
J
(PPG5)
External interrupt input pin
PPG timer output pin (when set by PAFSR register)
63
65
DVCC
-
PA port power supply pin
64
66
DVSS
-
PA port power supply pin (GND)
PA2
65
67
IRQ21
General-purpose I/O port
J
(PPG6)
PPG timer output pin (when set by PAFSR register)
PA3
66
68
IRQ22
General-purpose I/O port
J
(PPG7)
69
68
70
ALE
P51
RD
General-purpose I/O port
F
F
P52
69
71
WRL
71
72
73
WRH
F
F
Serves as read strobe output (RD) pin in external bus mode.
Serves as lower data write strobe output (WRL) pin in external bus
mode, and serves as a general-purpose I/O port when WRE bit in
EPCR register is "0".
Serves as higher data write strobe output (WRH) pin in external bus
mode with 16-bit bus width, and serves as a general-purpose I/O
port when WRE bit in EPCR register is "0".
IRQ23
External interrupt input pin
P54
General-purpose I/O port
HRQ
F
HAK
PPG5
Serves as hold request input (HRQ) pin in external bus mode, and
serves as a general-purpose I/O port when HDE bit in EPCR register
is "0".
PPG timer output pin
P55
74
General-purpose I/O port
General-purpose I/O port
PPG4
72
Serves as address latch enable signal (ALE) pin in external bus
mode.
General-purpose I/O port
P53
70
External interrupt input pin
PPG timer output pin (when set by PAFSR register)
P50
67
External interrupt input pin
General-purpose I/O port
F
Serves as hold acknowledge output (HAK) pin in external bus mode,
and serves as a general-purpose I/O port when HDE bit in EPCR
register is "0".
PPG timer output pin
(Continued)
12
MB90880 Series
Pin no.
LQFP *1
QFP *2
Pin
name
I/O
circuit
type*3
P56
73
75
RDY
General-purpose I/O port
F
PPG6
76
CLK
General-purpose I/O port
F
PPG7
76
77
78
79
77
78
79
80
81
AD00/
D00
Serves as machine cycle clock output (CLK) pin in external bus
mode, and serves as a general-purpose I/O port when CKE bit in
EPCR register is "0".
PPG timer output pin
P00
75
Serves as external ready input (RDY) pin in external bus mode, and
serves as a general-purpose I/O port when RYE bit in EPCR register
is "0".
PPG timer output pin
P57
74
Function
General-purpose I/O port
C
In multiplex mode, it serves as lower external address/data bus I/O
pin.
Serves as lower external data bus output pin in non-multiplex mode.
IRQ0
External interrupt input pin
P01
General-purpose I/O port
AD01/
D01
C
Serves as an external address/lower data bus I/O pin in multiplex
mode.
Serves as a lower external data bus output pin in non-multiplex
mode.
IRQ1
External interrupt input pin
P02
General-purpose I/O port
AD02/
D02
C
Serves as an external address/lower data bus I/O pin in multiplex
mode.
Serves as a lower external data bus output pin in non-multiplex
mode.
IRQ2
External interrupt input pin
P03
General-purpose I/O port
AD03/
D03
C
Serves as an external address/lower data bus I/O pin in multiplex
mode.
Serves as a lower external data bus output pin in non-multiplex
mode.
IRQ3
External interrupt input pin
P04
General-purpose I/O port
AD04/
D04
IRQ4
C
In multiplex mode, it serves as lower external address/data bus I/O
pin.
Serves as a lower external data bus output pin in non-multiplex
mode.
External interrupt input pin
(Continued)
13
MB90880 Series
Pin no.
LQFP *1
QFP *2
Pin
name
I/O
circuit
type*3
P05
80
81
82
83
82
83
84
85
AD05/
D05
General-purpose I/O port
C
P06
General-purpose I/O port
AD06/
D06
C
Serves as a lower external data bus output pin in non-multiplex
mode.
External interrupt input pin
P07
General-purpose I/O port
AD07/
D07
C
In multiplex mode, it serves as lower external address/data bus I/O
pin.
Serves as a lower external data bus output pin in non-multiplex
mode.
IRQ7
External interrupt input pin
P10
General-purpose I/O port
AD08/
D08
C
AD09/
D09
AD10/
D10
In multiplex mode, it serves as higher external address/data bus I/O
pin.
In non-multiplex mode, it serves as higher external data output pin.
Output compare event output pin
General-purpose I/O port
C
In multiplex mode, it serves as higher external address/data bus I/O
pin.
In non-multiplex mode, it serves as higher external data output pin.
Output compare event output pin
P12
87
In multiplex mode, it serves as lower external address/data bus I/O
pin.
IRQ6
OUT1
85
Serves as a lower external data bus output pin in non-multiplex
mode.
External interrupt input pin
P11
86
In multiplex mode, it serves as lower external address/data bus I/O
pin.
IRQ5
OUT0
84
Function
General-purpose I/O port
C
In multiplex mode, it serves as higher external address/data bus I/O
pin.
In non-multiplex mode, it serves as higher external data output pin.
OUT2
Output compare event output pin
P13
86
88
AD11/
D11
General-purpose I/O port
C
In multiplex mode, it serves as higher external address/data bus I/O
pin.
In non-multiplex mode, it serves as higher external data output pin.
OUT3
Output compare event output pin
(Continued)
14
MB90880 Series
Pin no.
LQFP *1
QFP *2
Pin
name
I/O
circuit
type*3
P14
87
89
AD12/
D12
Function
General-purpose I/O port
C
OUT4
In non-multiplex mode, it serves as higher external data output pin.
Output compare event output pin
88
90
VCC
-
Power supply pin
89
91
VSS
-
Power supply pin (GND)
90
92
X1
A
Main oscillator connecting pin
91
93
X0
A
Main oscillator connecting pin
P15
92
94
AD13/
D13
General-purpose I/O port
C
In non-multiplex mode, it serves as higher external data output pin.
OUT5
Output compare event output pin
P16
93
94
95
95
96
97
AD14/
D14
General-purpose I/O port
C
IN0
Trigger input pin for input capture ch.0
P17
General-purpose I/O port
AD15/
D15
C
In multiplex mode, it serves as higher external address/data bus I/O
pin.
In non-multiplex mode, it serves as higher external data output pin.
IN1
Trigger input pin for input capture ch.1
P20
General-purpose I/O port
A16
D
A17
PPG1
In multiplex mode, it serves as higher address output pin (A16) when
corresponding bit in external address output control register (HACR)
is set to "0".
In non-multiplex mode, it serves as higher address output pin (A16)
when corresponding bit in external address output control register
(HACR) is set to "0".
PPG timer output pin
P21
98
In multiplex mode, it serves as higher external address/data bus I/O
pin.
In non-multiplex mode, it serves as higher external data output pin.
PPG0
96
In multiplex mode, it serves as higher external address/data bus I/O
pin.
General-purpose I/O port
D
In multiplex mode, it serves as higher address output pin (A17) when
corresponding bit in external address output control register (HACR)
is set to "0".
In non-multiplex mode, it serves as higher address output pin (A17)
when corresponding bit in external address output control register
(HACR) is set to "0".
PPG timer output pin
(Continued)
15
MB90880 Series
(Continued)
Pin no.
LQFP *1
QFP *2
Pin
name
I/O
circuit
type*3
P22
97
99
A18
General-purpose I/O port
D
PPG2
100
A19
D
100
2
A20
In multiplex mode, it serves as higher address output pin (A19) when
corresponding bit in external address output control register (HACR)
is set to "0".
In non-multiplex mode, it serves as higher address output pin (A19)
when corresponding bit in external address output control register
(HACR) is set to "0".
PPG timer output pin
P24
1
In non-multiplex mode, it serves as higher address output pin (A18)
when corresponding bit in external address output control register
(HACR) is set to "0".
General-purpose I/O port
PPG3
99
In multiplex mode, it serves as higher address output pin (A18) when
corresponding bit in external address output control register (HACR)
is set to "0".
PPG timer output pin
P23
98
Function
General-purpose I/O port
D
In multiplex mode, it serves as higher address output pin (A20) when
corresponding bit in external address output control register (HACR)
is set to "0".
In non-multiplex mode, it serves as higher address output pin (A20)
when corresponding bit in external address output control register
(HACR) is set to "0".
TIO0
Base timer I/O pin (ch.0)
P25
General-purpose I/O port
A21
TIO1
D
In multiplex mode, it serves as higher address output pin (A21) when
corresponding bit in external address output control register (HACR)
is set to "0".
In non-multiplex mode, it serves as higher address output pin (A21)
when corresponding bit in external address output control register
(HACR) is set to "0".
Base timer I/O pin (ch.1)
*1 : LQFP : FPT-100P-M20
*2 : QFP : FPT-100P-M06
*3 : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”.
16
MB90880 Series
■ I/O CIRCUIT TYPE
Type
Circuit
X1, X1A
A
P-ch
N-ch
Remarks
• Oscillation feedback resistance
X1, X0 : approx. 1 MΩ
X1A, X0A : approx. 10 MΩ
• Standby control provided
Xout
X0, X0A
Standby control
signal
Hysteresis input with pull-up resistor
B
R
R
Hysteresis input
Pull-up control signal
P-ch
P-ch
N-ch
•
•
•
•
Input pull-up resistor control provided
CMOS level output
Hysteresis input
CMOS input (in external bus mode)
C
R
CMOS input
Hysteresis input
Standby control for
input shutdown
• CMOS level output
• Hysteresis input
P-ch
N-ch
D
R
Hysteresis input
Standby control for
input shutdown
• CMOS level output
• Hysteresis input
• I2C level hysteresis input
P-ch
N-ch
E
R
Hysteresis input
I2C level
hysteresis input
Standby control for
input shutdown
(Continued)
17
MB90880 Series
Type
Circuit
Remarks
• CMOS level output
• Hysteresis input
• CMOS input (in external bus mode)
P-ch
N-ch
F
R
CMOS input
Hysteresis input
Standby control for
input shutdown
P-ch
Open-drain control
signal
N-ch
G
• CMOS level output
(Open-drain control provided)
• 5V tolerant
• Hysteresis input
• I2C level hysteresis input
R
Hysteresis input
I2C level
hysteresis input
Standby control for
input shutdown
• CMOS level output
• Hysteresis input
• Analog input
P-ch
N-ch
H
R
Hysteresis input
Standby control for
input shutdown
Analog input
P-ch
Open-drain control
signal
N-ch
• CMOS level output
(Open-drain control provided)
• 5V tolerant
• Hysteresis input
I
R
Hysteresis input
Standby control for
input shutdown
(Continued)
18
MB90880 Series
(Continued)
Type
Circuit
Remarks
• CMOS/level output
(high-current type)
• Hysteresis input
P-ch
N-ch
J
R
Hysteresis input
Standby control for
input shutdown
•
•
•
•
P-ch
N-ch
K
CMOS level output
Hysteresis input
Analog input
I2C level hysteresis input
R
Hysteresis input
I2C level
Hysteresis input
Standby control for
input shutdown
Analog input
Flash memory product
• CMOS level input
• High-voltage control for flash test
provided
Flash memory product
N-ch
N-ch
Control signal
L
N-ch
R
Mode input
Diffused resistor
N-ch
MASK ROM product
Hysteresis input
MASK ROM product
R
Hysteresis input
19
MB90880 Series
■ HANDLING DEVICES
1. Maximum rated voltages for the prevention of latch-up
Be cautious not to exceed the absolute maximum rating.
CMOS ICs may cause latch-up, when a voltage higher than VCC or lower than VSS is applied to input or output
pins other than medium-to-high resistant pins, or when a voltage exceeding the rating is applied between VCC
and VSS pins.
If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the
device. Take the utmost care not to let it occur.
Likewise, care must be taken not to allow the analog power supply (AVCC, AVRH) and analog input to exceed
the digital power supply (VCC) when turning on or off any analog system.
2. Handling unused pins
Leaving unused input pins open may cause a malfunction or latch-up which leads to fatal damage to the device.
Therefore, they must be pulled up or down through at least 2 kΩ resistance. Also, any unused I/O pin should be
left open in the output state, or set to the input state and handled in the same way as an unused input pin.
3. Notes on using external clock
Even when an external clock is being used, oscillation stabilization wait time is required for a power-on reset or
release from sub clock mode or stop mode. Note that 25 MHz is the upper limit on the external clock that can
be used. The following diagram shows an example of using an external clock.
X0
Open
X1
4. Handling power supply pins (VCC/VSS)
When multiple VCC and VSS pins supply pins are used, all the power supply pins must be connected to external
power and ground lines due to the device design, to reduce latch-up and unwanted radiation, prevent abnormal
operation of strobe signals caused by the rise in the ground level and to conform to the total output current rating.
Make sure to connect the VCC and VSS pins of this device via lowest impedance to power lines. It is recommended
that a bypass capacitor of around 0.1 µF be placed between the VCC and VSS pins near the device.
5. Crystal oscillator circuit
Noises around X0/X1 or X0A/X1A pins may cause abnormal operations. It is strongly recommended to provide
bypass capacitors via shortest distance from X0/X1, X0A/X1A pins, crystal oscillator (or ceramic oscillator) and
ground lines and also not to allow the lines of the oscillation circuit to cross the lines of other circuits. This will
ensure stable operations of the printed circuit boards. Please ask each crystal maker to evaluate the oscillational
characteristics of the crystal and this device.
6. Notes on PLL clock mode operation
If an oscillator comes off or clock input stops during PLL clock mode operation, this microcontroller may continue
its operation using a free-running frequency from a self-excited oscillation circuit within PLL. This is not a
guaranteed operation.
20
MB90880 Series
7. Power-on and power-off sequence of A/D converter and analog input
Turn on the A/D converters (AVCC, AVRH) and analog inputs (AN0 to AN19) after turning on the digital power
supply (VCC) .
During power-off, turn off the digital power supply (VCC) after turning off the A/D converters and analog inputs
(AN0 to AN19) .
In this case, make sure that AVRH does not exceed AVCC during the power-on/power-off procedure.
Also make sure that the input voltage does not exceed AVCC when a pin which is also used as an analog input
is used as an input port.
8. Handling power supply pins on A/D converter-mounted models
Make sure to achieve "AVCC = AVRH = VCC" and "AVSS = VSS" in connecting the circuits, even when not using the
A/D converter function.
9. Note on power-up
To prevent the internal regulator from malfunctioning, maintain the voltage rise time at 50 µs (between 0.2V and
2.7V) or more during power-up.
10. Stabilization of power supply
Even when the VCC power supply voltage is within the specified operating range, it may still cause the device to
malfunction, if the power supply changes rapidly. For stabilization reference, it is recommended to control the
supply voltage so that VCC ripple variations (P-P values) at commercial frequencies (50/60 Hz) fall below 10%
of the standard VCC supply voltage and the coefficient of fluctuation does not exceed 0.1 V/ms at instantaneous
power switching.
11. Writing to Flash memory
For serial writing to Flash memory, always make sure that the operating voltage VCC is between 3.13V and 3.6V.
For normal writing to Flash memory, always make sure that the operating voltage VCC is between 3.0V and 3.6V.
12. P90/CS0 pins
P90/CS0 pins output “L” during writing Flash serial. Do not input from external.
13. Note of MB90F883 (S) , MB90F884 (S)
• Maximum operating frequency is 25 MHz.
• The base timer cannot use P24/TIO0, P25/TIO1, P26/TIO2, and P27/TIO3 as input function.
• MB90F883(S) and MB90F884(S) do not contain the flash security feature and write-protect feature.
21
MB90880 Series
■ BLOCK DIAGRAM
X0, X1, RST
X0A, X1A
MD0 to MD2
CPU
F2MC-16LX
series core
Clock control
circuit
RAM
Interrupt controller
ROM
µDMAC
16-bit PPG
UI0 to UI6
UO0 to UO6
UCK0 to UCK6
F2MC-16LX bus
Multifunction serial
SIO/UART/I2C
mode switching
enabled
8/16-bit
up-down
counter/timer
PPG0 to PPG7
AIN0, AIN1
BIN0, BIN1
ZIN0, ZIN1
I/O timer
AVCC
AVRH
AVSS
ADTG
AN0 to AN19
16-bit input capture ×
2 channels
10-bit
A/D converter
24
IRQ0 to IRQ23
16-bit output compare ×
6 channels
16-bit free-run timer
External interrupt
16-bit base timer
IN0, IN1
OUT0 to OUT5
TIO0 to TIO3
Reload timer/PWM/PWC
mode switching enabled
I/O port
8
8
8
8
8
8
8
7
8
8
4
P00
to
P07
P10
to
P17
P20
to
P27
P30
to
P37
P40
to
P47
P50
to
P57
P60
to
P67
P70
to
P76
P80
to
P87
P90
to
P97
PA0
to
PA3
Note : The I/O ports shown in the diagram above are shared by other built-in function blocks. They cannot be used
as I/O ports when used as pins for a built-in module.
22
MB90880 Series
■ MEMORY MAP
Single chip mode
Internal ROM
external bus
ROM area
ROM area
External ROM
external bus
FFFFFFH
Address #1
010000H
Address #2
007900H
ROM area
ROM area
Image of FF bank
Image of FF bank
Peripheral area
Peripheral area
Peripheral area
Address #3
RAM
Register
RAM
Register
RAM
Register
000100H
0000F0H
000000H
Peripheral area
: Internal
Parts No.
Address #1
Peripheral area
: External
Address #2
Peripheral area
: Access prohibited
Address #3
MB90882 (S)
FC0000H
004100H
MB90F882 (S)
FC0000H
004100H
MB90883 (S)
FA0000H
006100H
MB90F883 (S) /
MB90F883A (S)
FA0000H
MB90884 (S)
F80000H
007900H
MB90F884 (S) /
MB90F884A (S)
F80000H
007900H
MB90V880 (S)
(F80000H)
007900H
008000H, fixed
006100H
Note : The image of the ROM data in the FF band appears at the top of the 00 bank in order to enable efficient use
of the C compiler small memory model. The lower 16-bit address for the FF bank will be assigned to the
same address, so that tables in ROM can be referenced without declaring a "far" indication with the pointer.
For example, when accessing the address 00C000H, the actual access is to address FFC000H in ROM.
Here the FF bank ROM area exceeds 32 Kbytes, it is not possible to see the entire area in the 00 bank
image. Therefore, the ROM data in FF8000H to FFFFFFH can be seen in the 00 bank image, while the data
in FF0000H to FF7FFFH can only be seen in the FF bank.
23
MB90880 Series
■ F2MC-16L CPU PROGRAMMING MODEL
• Dedicated register
AH
Accumulator
AL
USP
User stack pointer
SSP
System stack pointer
PS
Processor status
PC
Program counter
DPR
Direct page register
PCB
Program bank register
DTB
Data bank register
USB
User stack bank register
SSB
System stack bank register
ADB
Additional data bank register
8 bits
16 bits
32 bits
• General-purpose register
MSB
LSB
16 bits
000180H + RP × 10H
RW0
RL0
RW1
RW2
RL1
RW3
R1
R0
RW4
R3
R2
RW5
R5
R4
RW6
R7
R6
RW7
RL2
RL3
• Processor status
bit 15
PS
24
bit 13 bit 12
ILM
bit 8 bit 7
RP
bit 0
CCR
MB90880 Series
■ I/O MAP
Address
Register
abbreviation
000000H
PDR0
000001H
Register name
R/W
Resource
Initial value
Port 0 data register
R/W
Port 0
XXXXXXXXB
PDR1
Port 1 data register
R/W
Port 1
XXXXXXXXB
000002H
PDR2
Port 2 data register
R/W
Port 2
XXXXXXXXB
000003H
PDR3
Port 3 data register
R/W
Port 3
XXXXXXXXB
000004H
PDR4
Port 4 data register
R/W
Port 4
XXXXXXXXB
000005H
PDR5
Port 5 data register
R/W
Port 5
XXXXXXXXB
000006H
PDR6
Port 6 data register
R/W
Port 6
XXXXXXXXB
000007H
PDR7
Port 7 data register
R/W
Port 7
XXXXXXXXB
000008H
PDR8
Port 8 data register
R/W
Port 8
XXXXXXXXB
000009H
PDR9
Port 9 data register
R/W
Port 9
XXXXXXXXB
00000AH
PDRA
Port A data register
R/W
Port A
XXXXXXXXB
00000BH
UDER
Up-down timer input enable register
R/W
Up-down timer input
control
XX000000B
00000CH
ILSR0
Serial input level selection register 0
R/W
00000DH
ILSR1
Serial input level selection register 1
R/W
00000EH
ILSR2
Serial input level selection register 2
R/W
00000FH
00000000B
Multi-function serial
control
00000000B
---00000B
Disabled
000010H
DDR0
Port 0 direction register
R/W
Port 0
00000000B
000011H
DDR1
Port 1 direction register
R/W
Port 1
00000000B
000012H
DDR2
Port 2 direction register
R/W
Port 2
00000000B
000013H
DDR3
Port 3 direction register
R/W
Port 3
00000000B
000014H
DDR4
Port 4 direction register
R/W
Port 4
00000000B
000015H
DDR5
Port 5 direction register
R/W
Port 5
00000000B
000016H
DDR6
Port 6 direction register
R/W
Port 6
00000000B
000017H
DDR7
Port 7 direction register
R/W
Port 7
-0000000B
000018H
DDR8
Port 8 direction register
R/W
Port 8
00000000B
000019H
DDR9
Port 9 direction register
R/W
Port 9
00000000B
00001AH
DDRA
Port A direction register
R/W
Port A
----0000B
00001BH
ADER0
Analog input enable register 0
R/W
Port 6, A/D
11111111B
00001CH
ADER1
Analog input enable register 1
R/W
Port 9, A/D
11111111B
00001DH
ADER2
Analog input enable register 2
R/W
Port 7, A/D
----1111B
00001EH
RDR0
Port 0 input resistance register
R/W
Port 0 (pull-up
resistance control)
00000000B
00001FH
RDR1
Port 1 input resistance register
R/W
Port 1 (pull-up
resistance control)
00000000B
(Continued)
25
MB90880 Series
Address
Register
abbreviation
000020H
SMR0
000021H SCR0/IBCR0
Register name
R/W
Resource
Initial value
Serial bus mode register ch.0
R/W
$$$$$$$$B
SCR0/IBCR0 serial bus control
register/I2C bus control register ch.0
R/W
$$$$$$$$B
Extended communication control
register/I2C bus status register ch.0
R/W
$$$$$$$$B
Serial status register ch.0
R/W
$$$$$$$$B
000022H
ESCR0/
IBSR0
000023H
SSR0
000024H
RDR00/
TDR00
Transmission/reception data register 0
ch.0
R,W
000025H
RDR10/
TDR10
Transmission/reception data register 1
ch.0
R,W
$$$$$$$$B
000026H
BGR00
Baud rate generator register 0 ch.0
R/W
$$$$$$$$B
000027H
BGR10
Baud rate generator register 1 ch.0
R/W
$$$$$$$$B
000028H
ISBA0
7-bit slave address register ch.0
R/W
00000000B
000029H
ISMK0
7-bit slave address mask register ch.0
R/W
01111111B
00002AH
SMR1
Serial bus mode register ch.1
R/W
$$$$$$$$B
Serial bus control register / I2C bus
control register ch.1
R/W
$$$$$$$$B
Extended communication control
register / I2C bus status register ch.1
R/W
$$$$$$$$B
Serial status register ch.1
R/W
$$$$$$$$B
00002BH SCR1/IBCR1
Multi-function serial
ch.0
$$$$$$$$B
00002CH
ESCR1/
IBSR1
00002DH
SSR1
00002EH
RDR01/
TDR01
Transmission/reception data register 0
ch.1
R,W
00002FH
RDR11/
TDR11
Transmission/reception data register 1
ch.1
R,W
$$$$$$$$B
000030H
BGR01
Baud rate generator register 0 ch.1
R/W
$$$$$$$$B
000031H
BGR11
Baud rate generator register 1 ch.1
R/W
$$$$$$$$B
000032H
ISBA1
7-bit slave address register ch.1
R/W
00000000B
000033H
ISMK1
7-bit slave address mask register ch.1
R/W
01111111B
000034H
ADCSL
Lower A/D control status register
R/W
00011110B
000035H
ADCSH
Higher A/D control status register
R/W
00000000B
000036H
ADCRL
Lower A/D data register
R
XXXXXXXXB
000037H
ADCRH
Higher A/D data register
R
000038H
ADSRL
Lower A/D conversion channel setting
register
R/W
00000000B
000039H
ADSRH
Higher A/D conversion channel setting
register
R/W
00000000B
00003AH
Multi-function serial
ch.1
A/D Converter
$$$$$$$$B
111111XXB
Reserved
(Continued)
26
MB90880 Series
Address
Register
abbreviation
00003BH
PACSR1
00003CH
Register name
R/W
Resource
Initial value
Address detection control status
register 1
R/W
Address match
detection function
00000000B
OLSR0
Output level selection register 0
R/W
Port 7 (N-ch
open-drain control)
-000----B
00003DH
OLSR1
Output level selection register 1
R/W
Port 8 (N-ch
open-drain control)
00000000B
00003EH
SMR2
Serial bus mode register ch.2
R/W
$$$$$$$$B
Serial bus control register / I C bus
control register ch.2
R/W
$$$$$$$$B
Extended communication control
register / I2C bus status register ch.2
R/W
$$$$$$$$B
Serial status register ch.2
R/W
$$$$$$$$B
2
00003FH SCR2/IBCR2
000040H
ESCR2/
IBSR2
000041H
SSR2
000042H
RDR02/
TDR02
Transmission/reception data register 0
ch.2
R,W
000043H
RDR12/
TDR12
Transmission/reception data register 1
ch.2
R,W
$$$$$$$$B
000044H
BGR02
Baud rate generator register 0 ch.2
R/W
$$$$$$$$B
000045H
BGR12
Baud rate generator register 1 ch.2
R/W
$$$$$$$$B
000046H
ISBA2
7-bit slave address register ch.2
R/W
00000000B
000047H
ISMK2
7-bit slave address mask register ch.2
R/W
01111111B
000048H
SMR3
Serial bus mode register ch.3
R/W
$$$$$$$$B
Serial bus control register / I2C bus
control register ch.3
R/W
$$$$$$$$B
Extended communication control
register / I2C bus status register ch.3
R/W
$$$$$$$$B
Serial status register ch.3
R/W
$$$$$$$$B
000049H SCR3/IBCR3
Multi-function serial
ch.2
$$$$$$$$B
00004AH
ESCR3/
IBSR3
00004BH
SSR3
00004CH
RDR03/
TDR03
Transmission/reception data register 0
ch.3
R,W
00004DH
RDR13/
TDR13
Transmission/reception data register 1
ch.3
R,W
$$$$$$$$B
00004EH
BGR03
Baud rate generator register 0 ch.3
R/W
$$$$$$$$B
00004FH
BGR13
Baud rate generator register 1 ch.3
R/W
$$$$$$$$B
000050H
ISBA3
7-bit slave address register ch.3
R/W
00000000B
000051H
ISMK3
7-bit slave address mask register ch.3
R/W
01111111B
000052H
SMR4
Serial bus mode register ch.4
R/W
2
000053H SCR4/IBCR4
Serial bus control register / I C bus
control register ch.4
R/W
Multi-function serial
ch.3
$$$$$$$$B
$$$$$$$$B
Multi-function serial
ch.4
$$$$$$$$B
(Continued)
27
MB90880 Series
Address
Register
abbreviation
000054H
ESCR4/
IBSR4
000055H
SSR4
000056H
Register name
R/W
Resource
Initial value
Extended communication control
register / I2C bus status register ch.4
R/W
$$$$$$$$B
Serial status register ch.4
R/W
$$$$$$$$B
RDR04/
TDR04
Transmission/reception data register 0
ch.4
R,W
$$$$$$$$B
000057H
RDR14/
TDR14
Transmission/reception data register 1
ch.4
R,W
000058H
BGR04
Baud rate generator register 0 ch.4
R/W
$$$$$$$$B
000059H
BGR14
Baud rate generator register 1 ch.4
R/W
$$$$$$$$B
00005AH
ISBA4
7-bit slave address register ch.4
R/W
00000000B
00005BH
ISMK4
7-bit slave address mask register ch.4
R/W
01111111B
00005CH
SMR5
Serial bus mode register ch.5
R/W
$$$$$$$$B
Serial bus control register / I C bus
control register ch.5
R/W
$$$$$$$$B
Extended communication control
register / I2C bus status register ch.5
R/W
$$$$$$$$B
Serial status register ch.5
R/W
$$$$$$$$B
Multi-function serial
ch.4
$$$$$$$$B
2
00005DH SCR5/IBCR5
00005EH
ESCR5/
IBSR5
00005FH
SSR5
000060H
RDR05/
TDR05
Transmission/reception data register 0
ch.5
R,W
000061H
RDR15/
TDR15
Transmission/reception data register 1
ch.5
R,W
$$$$$$$$B
000062H
BGR05
Baud rate generator register 0 ch.5
R/W
$$$$$$$$B
000063H
BGR15
Baud rate generator register 1 ch.5
R/W
$$$$$$$$B
000064H
ISBA5
7-bit slave address register ch.5
R/W
00000000B
000065H
ISMK5
7-bit slave address mask register ch.5
R/W
01111111B
000066H
000067H
000068H
000069H
00006AH
00006BH
00006CH
00006DH
OCCP0
OCCP1
OCCP2
OCCP3
00006EH
00006FH
Lower output compare register (ch.0)
Higher output compare register (ch.0)
Lower output compare register (ch.1)
Higher output compare register (ch.1)
Lower output compare register (ch.2)
Higher output compare register (ch.2)
Lower output compare register (ch.3)
Higher output compare register (ch.3)
Multi-function serial
ch.5
00000000B
R/W
R/W
R/W
$$$$$$$$B
00000000B
00000000B
16-bit I/O timer output
compare
(ch.0 to ch.5)
00000000B
00000000B
00000000B
00000000B
R/W
00000000B
Reserved
ROMM
ROM mirror function selection register
R/W
ROM mirror function
-------1B
(Continued)
28
MB90880 Series
Address
000070H
000071H
000072H
000073H
Register
abbreviation
OCCP4
OCCP5
Register name
R/W
Lower output compare register (ch.4)
Higher output compare register (ch.4)
Lower output compare register (ch.5)
Higher output compare register (ch.5)
Resource
Initial value
00000000B
R/W
00000000B
00000000B
R/W
00000000B
Lower output compare control register
(ch.0, ch.1)
R/W
000075H
Higher output compare control register
(ch.0, ch.1)
R/W
000076H
Lower output compare control register
(ch.2, ch.3)
R/W
0000--00B
000077H
Higher output compare control register
(ch.2, ch.3)
R/W
---00000B
000078H
Lower output compare control register
(ch.4, ch.5)
R/W
0000--00B
000079H
Higher output compare control register
(ch.4, ch.5)
R/W
---00000B
00007AH
Lower input capture data register (ch.0)
R
XXXXXXXXB
Higher input capture data register
(ch.0)
R
XXXXXXXXB
Lower input capture data register (ch.1)
R
IPCP1
Higher input capture data register
(ch.1)
R
00007EH
ICS01
Input capture control status register
00007FH
ICE01
Input capture edge register
000080H
TCDT
000081H
000074H
OCS01
OCS23
OCS45
00007BH
IPCP0
00007CH
00007DH
0000--00B
16-bit I/O timer output
compare
(ch.0 to ch.5)
6-bit I/O timer
input capture
(ch.0, ch.1)
---00000B
XXXXXXXXB
XXXXXXXXB
R/W
00000000B
R
------XXB
Lower timer counter data register
R/W
00000000B
TCDT
Higher timer counter data register
R/W
00000000B
000082H
TCCS
Timer control status register
R/W
000083H
TCCS
Timer control status register
R/W
000084H
000085H
CPCLR
Lower compare clear register
00000000B
XX-00000B
XXXXXXXXB
R/W
Higher compare clear register
000086H
to
00009AH
16-bit I/O timer
free-run timer
XXXXXXXXB
Reserved
00009BH
DCSR
DMAC descriptor channel specification
register
R/W
DMAC
00000000B
00009CH
DSRL
DMAC lower status register
R/W
DMAC
00000000B
00009DH
DSRH
DMAC higher status register
R/W
DMAC
00000000B
(Continued)
29
MB90880 Series
Address
Register
abbreviation
00009EH
PACSR0
00009FH
DIRR
0000A0H
LPMCR
Low power consumption mode control
register
W, R/W
0000A1H
CKSCR
Clock selection register
R, R/W
Register name
R/W
Resource
Initial value
Address detection control status
register 0
R/W
Address match
detection function
00000000B
Delayed interrupt source generation/
release register
R/W
Delayed interrupt
generation module
-------0B
0000A2H,
0000A3H
Low power
consumption
00011000B
11111100B
Reserved
0000A4H
DSSR
DMAC stop status register
0000A5H
ARSR
Auto ready function selection register
W
0000A6H
HACR
External address output control register
W
0000A7H
EPCR
Bus control signal selection register
W
0000A8H
WDTC
Watchdog timer control register
R, W
Watchdog timer
XXXXX111B
0000A9H
TBTC
Time base timer control register
W, R/W
Time base timer
1XX00100B
0000AAH
WTC
Watch timer control register
R, R/W
Watch timer
10001000B
0000ABH
R/W
DMAC
00000000B
0011--00B
External pin
********B
1000*10-B
Reserved
0000ACH
DERL
DMAC lower enable register
R/W
0000ADH
DERH
DMAC higher enable register
R/W
0000AEH
FMCS
Flash memory control status register
0000AFH
W, R/W
DMAC
Flash memory I/F
00000000B
00000000B
000X0000B
Prohibited
0000B0H
ICR00
Interrupt control register 00
W, R/W
00000111B
0000B1H
ICR01
Interrupt control register 01
W, R/W
00000111B
0000B2H
ICR02
Interrupt control register 02
W, R/W
00000111B
0000B3H
ICR03
Interrupt control register 03
W, R/W
00000111B
0000B4H
ICR04
Interrupt control register 04
W, R/W
00000111B
0000B5H
ICR05
Interrupt control register 05
W, R/W
00000111B
0000B6H
ICR06
Interrupt control register 06
W, R/W
0000B7H
ICR07
Interrupt control register 07
W, R/W
0000B8H
ICR08
Interrupt control register 08
W, R/W
00000111B
0000B9H
ICR09
Interrupt control register 09
W, R/W
00000111B
0000BAH
ICR10
Interrupt control register 10
W, R/W
00000111B
0000BBH
ICR11
Interrupt control register 11
W, R/W
00000111B
0000BCH
ICR12
Interrupt control register 12
W, R/W
00000111B
0000BDH
ICR13
Interrupt control register 13
W, R/W
00000111B
Interrupt control
00000111B
00000111B
(Continued)
30
MB90880 Series
Address
Register
abbreviation
0000BEH
ICR14
Interrupt control register 14
W, R/W
0000BFH
ICR15
Interrupt control register 15
W, R/W
0000C0H
CMR0
Chip select area MASK register 0
R/W
0000C1H
CAR0
Chip select area register 0
R/W
11111111B
0000C2H
CMR1
Chip select area MASK register 1
R/W
00001111B
0000C3H
CAR1
Chip select area register 1
R/W
11111111B
0000C4H
CMR2
Chip select area MASK register 2
R/W
00001111B
0000C5H
CAR2
Chip select area register 2
R/W
0000C6H
CMR3
Chip select area MASK register 3
R/W
00001111B
0000C7H
CAR3
Chip select area register 3
R/W
11111111B
0000C8H
CSCR
Chip select control register
R/W
----000*B
0000C9H
CALR
Chip select active level register
R/W
----0000B
Register name
0000CAH
to
0000CEH
R/W
Resource
Interrupt control
Chip select function
Interrupt control
Initial value
00000111B
00000111B
00001111B
11111111B
Reserved
0000CFH
PLLOS
0000D0H
BAPL
DMA buffer address pointer (low)
R/W
XXXXXXXXB
0000D1H
BAPM
DMA buffer address pointer (middle)
R/W
XXXXXXXXB
0000D2H
BAPH
DMA buffer address pointer (high)
R/W
XXXXXXXXB
0000D3H
MACS
DMA control register
R/W
0000D4H
IOAL
DMAI/O register address pointer (low)
R/W
0000D5H
IOAH
DMAI/O register address pointer (high)
R/W
XXXXXXXXB
0000D6H
DCTL
DMA data counter (low)
R/W
XXXXXXXXB
0000D7H
DCTH
DMA data counter (high)
R/W
XXXXXXXXB
00000000B
0000D8H
to
0000DFH
PLL output selection register
W
PLL
DMAC
------X0B
XXXXXXXXB
XXXXXXXXB
Reserved
0000E0H
ENIR0
Interrupt/DTP enable register 0
R/W
0000E1H
EIRR0
Interrupt/DTP source register 0
R/W
Request level setting register 0
R/W
Request level setting register 0
R/W
00000000B
00000000B
0000E2H
0000E3H
ELVR0
0000E4H
ENIR1
Interrupt/DTP enable register 1
R/W
0000E5H
EIRR1
Interrupt/DTP source register 1
R/W
Request level setting register 1
R/W
Request level setting register 1
R/W
0000E6H
0000E7H
ELVR1
DTP / external
interrupt
DTP / external
interrupt
XXXXXXXXB
00000000B
XXXXXXXXB
00000000B
00000000B
(Continued)
31
MB90880 Series
Address
Register
abbreviation
0000E8H
ENIR2
Interrupt/DTP enable register 2
R/W
0000E9H
EIRR2
Interrupt/DTP source register 2
R/W
Request level setting register 2
R/W
Request level setting register 2
R/W
0000EAH
0000EBH
ELVR2
Register name
R/W
0000ECH
to
0000EFH
Reserved
0000F0H
to
0000FFH
External area
000100H
to
#H*
RAM area
007900H
PCNTL0
PPG0 lower control status register
R/W
007901H
PCNTH0
PPG0 higher control status register
R/W
007902H
PCNTL1
PPG1 lower control status register
R/W
007903H
PCNTH1
PPG1 higher control status register
R/W
007904H
PCNTL2
PPG2 lower control status register
R/W
007905H
PCNTH2
PPG2 higher control status register
R/W
007906H
PCNTL3
PPG3 lower control status register
R/W
007907H
PCNTH3
PPG3 higher control status register
R/W
007908H
PCNTL4
PPG4 lower control status register
R/W
007909H
PCNTH4
PPG4 higher control status register
R/W
00790AH
PCNTL5
PPG5 lower control status register
R/W
00790BH
PCNTH5
PPG5 higher control status register
R/W
00790CH
PCNTL6
PPG6 lower control status register
R/W
00790DH
PCNTH6
PPG6 higher control status register
R/W
00790EH
PCNTL7
PPG7 lower control status register
R/W
00790FH
PCNTH7
PPG7 higher control status register
R/W
007910H
PPGDIV
PPG0 output division setting register
R/W
007911H
Resource
Initial value
XXXX0000B
DTP / external
interrupt
XXXXXXXXB
00000000B
00000000B
16-bit PPG0
16-bit PPG1
16-bit PPG2
16-bit PPG3
16-bit PPG4
16-bit PPG5
16-bit PPG6
16-bit PPG7
16-bit PPG0
00000000B
00000001B
00000000B
00000001B
00000000B
00000001B
00000000B
00000001B
00000000B
00000001B
00000000B
00000001B
00000000B
00000001B
00000000B
00000001B
11111100B
Reserved
007912H
PDCRL0
007913H
PDCRH0
007914H
PCSRL0
007915H
PCSRH0
PPG0 down counter register
11111111B
R
16-bit PPG0
PPG0 period setting register
W
11111111B
11111111B
11111111B
(Continued)
32
MB90880 Series
Address
Register
abbreviation
007916H
PUDUTL0
007917H
PUDUTH0
Register name
PPG0 duty setting register
007918H
Disabled
007919H
Disabled
00791AH
PDCRL1
00791BH
PDCRH1
00791CH
PCSRL1
00791DH
PCSRH1
00791EH
PUDUTL1
00791FH
PUDUTH1
W
PPG1 duty setting register
W
Disabled
PDCRH2
007924H
PCSRL2
007925H
PCSRH2
007926H
PUDUTL2
007927H
PUDUTH2
PPG2 down counter register
R
PPG2 period setting register
W
PPG2 duty setting register
W
007928H
Disabled
007929H
Disabled
00792AH
PDCRL3
00792BH
PDCRH3
00792CH
PCSRL3
00792DH
PCSRH3
00792EH
PUDUTL3
00792FH
PUDUTH3
PPG3 down counter register
R
PPG3 period setting register
W
PPG3 duty setting register
W
007930H
Disabled
007931H
Disabled
007932H
PDCRL4
007933H
PDCRH4
007934H
PCSRL4
007935H
PCSRH4
007936H
PUDUTL4
007937H
PUDUTH4
16-bit PPG0
PPG1 period setting register
007921H
007923H
W
R
Disabled
PDCRL2
Resource
PPG1 down counter register
007920H
007922H
R/W
PPG4 down counter register
R
PPG4 period setting register
W
PPG4 duty setting register
W
Initial value
00000000B
00000000B
11111111B
11111111B
16-bit PPG1
11111111B
11111111B
00000000B
00000000B
11111111B
11111111B
16-bit PPG2
11111111B
11111111B
00000000B
00000000B
11111111B
11111111B
16-bit PPG3
11111111B
11111111B
00000000B
00000000B
11111111B
11111111B
16-bit PPG4
11111111B
11111111B
00000000B
00000000B
(Continued)
33
MB90880 Series
Address
Register
abbreviation
Register name
R/W
007938H
Disabled
007939H
Disabled
00793AH
PDCRL5
00793BH
PDCRH5
00793CH
PCSRL5
00793DH
PCSRH5
00793EH
PUDUTL5
00793FH
PUDUTH5
PPG5 down counter register
R
PPG5 period setting register
W
PPG5 duty setting register
W
007940H
Disabled
007941H
Disabled
007942H
PDCRL6
007943H
PDCRH6
007944H
PCSRL6
007945H
PCSRH6
007946H
PUDUTL6
007947H
PUDUTH6
PPG6 down counter register
R
PPG6 period setting register
W
PPG6 duty setting register
W
007948H
Disabled
007949H
Disabled
00794AH
PDCRL7
00794BH
PDCRH7
00794CH
PCSRL7
00794DH
PCSRH7
00794EH
PUDUTL7
00794FH
PUDUTH7
PPG7 down counter register
R
PPG7 period setting register
W
PPG7 duty setting register
W
007950H
Disabled
007951H
Disabled
007952H
007953H
007954H
TMCR0
Timer control register ch.0
R/W
STC0
Status control register ch.0
R/W
007955H
Resource
11111111B
11111111B
16-bit PPG5
11111111B
11111111B
00000000B
00000000B
11111111B
11111111B
16-bit PPG6
11111111B
11111111B
00000000B
00000000B
11111111B
11111111B
16-bit PPG7
11111111B
11111111B
00000000B
00000000B
00000000B
Base timer ch.0
00000000B
00000000B
Disabled
007956H
TMR0
007957H
Initial value
Timer register ch.0
R/W
Base timer ch.0
00000000B/
XXXXXXXXB
00000000B/
XXXXXXXXB
(Continued)
34
MB90880 Series
Address
007958H
007959H
00795AH
00795BH
00795CH
00795DH
00795EH
Register
abbreviation
PCSR0/
PRLL0
Register name
R/W
Period/L-width setting register ch.0
Resource
XXXXXXXXB
R/W
XXXXXXXXB
Base timer ch.0
PDUT0/
PRLH0/
DTBF0
Duty/H-width/data buffer register ch.0
R/W
TMCR1
Timer control register ch.1
R/W
STC1
Status control register ch.1
R/W
00795FH
00000000B
Base timer ch.1
Disabled
TMR1
007964H
007965H
007966H
007967H
007968H
Timer register ch.1
R/W
PCSR1/
PRLL1
Period/L-width setting register ch.1
R/W
PDUT1/
PRLH1/
DTBF1
Duty/H-width/data buffer register ch.1
R/W
TMCR2
Timer control register ch.2
R/W
STC2
Status control register ch.2
R/W
007969H
00000000B/
XXXXXXXXB
00000000B/
XXXXXXXXB
Base timer ch.1
00000000B
Base timer ch.2
00796FH
007970H
007971H
007972H
00000000B
00000000B
Disabled
TMR2
00796EH
XXXXXXXXB
XXXXXXXXB/
00000000B
00000000B/
XXXXXXXXB
Timer register ch.2
R/W
Period/L-width setting register ch.2
R/W
00000000B/
XXXXXXXXB
00796BH
00796DH
XXXXXXXXB
XXXXXXXXB/
00000000B
00796AH
00796CH
00000000B
00000000B
007961H
007963H
XXXXXXXXB/
00000000B
XXXXXXXXB/
00000000B
007960H
007962H
Initial value
PCSR2/
PRLL2
PDUT2/
PRLH2/
DTBF2
Duty/H-width/data buffer register ch.2
R/W
TMCR3
Timer control register ch.3
R/W
STC3
Status control register ch.3
R/W
Base timer ch.2
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB/
00000000B
XXXXXXXXB/
00000000B
00000000B
Base timer ch.3
00000000B
00000000B
(Continued)
35
MB90880 Series
Address
Register
abbreviation
Register name
R/W
007973H
Resource
Disabled
00000000B/
XXXXXXXXB
007974H
TMR3
Timer register ch.3
R/W
Period/L-width setting register ch.3
R/W
00000000B/
XXXXXXXXB
007975H
007976H
007977H
007978H
Initial value
PCSR3/
PRLL3
Base timer ch.3
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB/
00000000B
Duty/H-width/data buffer register ch.3
007979H
PDUT3/
PRLH3/
DTBF3
00797AH
UDCR0
Up-down count register (ch.0)
R
00000000B
00797BH
UDCR1
Up-down count register (ch.1)
R
00000000B
00797CH
RCR0
Reload/compare register (ch.0)
W
00000000B
00797DH
RCR1
Reload/compare register (ch.1)
W
R/W
XXXXXXXXB/
00000000B
00000000B
8/16-bit up-down
counter/timer
00797EH
CCRL0
Lower counter control register (ch.0)
W, R/W
00797FH
CCRH0
Higher counter control register (ch.0)
R/W
00000000B
007980H
CCRL1
Lower counter control register (ch.1)
W, R/W
XX00X000B
007981H
CCRH1
Higher counter control register (ch.1)
R/W
-0000000B
007982H
CSR0
R, R/W
00000000B
Counter status register (ch.0)
007983H
007984H
Reserved
CSR1
Counter status register (ch.1)
007985H
to
00798FH
007990H
XX00X000B
R, R/W
8/16-bit up-down
counter/timer
00000000B
Reserved
SMR6
007991H SCR6/IBCR6
Serial bus mode register ch.6
R/W
$$$$$$$$B
Serial bus control register / I2C bus
control register ch.6
R/W
$$$$$$$$B
Extended communication control
register / I2C bus status register ch.6
R/W
$$$$$$$$B
Serial status register ch.6
R/W
007992H
ESCR6/
IBSR6
007993H
SSR6
007994H
RDR06/
TDR06
Transmission/reception data register 0
ch.6
R,W
$$$$$$$$B
007995H
RDR16/
TDR16
Transmission/reception data register 1
ch.6
R,W
$$$$$$$$B
007996H
BGR06
Baud rate generator register 0 ch.6
R/W
$$$$$$$$B
007997H
BGR16
Baud rate generator register 1 ch.6
R/W
$$$$$$$$B
Multi-function serial
ch.6
$$$$$$$$B
(Continued)
36
MB90880 Series
Address
Register
abbreviation
007998H
ISBA6
007999H
Register name
R/W
Resource
Initial value
7-bit slave address register ch.6
R/W
00000000B
ISMK6
7-bit slave address mask register ch.6
R/W
Multi-function serial
ch.6
00799AH
PAFSR
PPG pin assignment switching register
R/W
PPG pin switching
control
----0000B
00799BH
PMSSR
PPG multi-channel start register
R/W
PPG multi-start
control
00000000B
R/W
Multi-function serial
pin control
-----000B
00799CH
00799DH
01111111B
Reserved
P9FSR
Serial pin switching register 1
00799CH
to
0079A1H
Reserved
0079A2H
P7FSR
Serial pin switching register 0
R/W
Multi-function serial
pin control
----000XB
0079A3H
LSYNS
LIN SYNCH FIELD switching register
R/W
Input capture input
control
10001000B
0079A4H,
0079A5H
Reserved
0079A6H
FWR0
Flash memory write control register 0
R/W
0079A7H
FWR1
Flash memory write control register 1
R/W
0079A8H
to
0079DFH
Detection address register 0 (low)
PADR0
Detection address register 0 (middle)
0079E2H
Detection address register 0 (high)
0079E3H
Detection address register 1 (low)
0079E4H
PADR1
Detection address register 1 (middle)
0079E5H
Detection address register 1 (high)
0079E6H
Detection address register 2 (low)
0079E7H
PADR2
0079E8H
Detection address register 2 (middle)
R/W
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
R/W
Address match
detection function
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
R/W
Address match
detection function
XXXXXXXXB
XXXXXXXXB
Reserved
0079F0H
0079F2H
00000000B
XXXXXXXXB
Address match
detection function
Detection address register 2 (high)
0079E9H
to
0079EFH
0079F1H
00000000B
Reserved
0079E0H
0079E1H
Flash memory I/F
Detection address register 3 (low)
PADR3
Detection address register 3 (middle)
Detection address register 3 (high)
XXXXXXXXB
R/W
Address match
detection function
XXXXXXXXB
XXXXXXXXB
(Continued)
37
MB90880 Series
(Continued)
Address
Register
abbreviation
PADR4
Detection address register 4 (middle)
0079F5H
Detection address register 4 (high)
0079F6H
Detection address register 5 (low)
0079F7H
R/W
Resource
R/W
Address match
detection function
Detection address register 4 (low)
0079F3H
0079F4H
Register name
PADR5
0079F8H
0079F9H
to
007FFFH
Detection address register 5 (middle)
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
R/W
Address match
detection function
Detection address register 5 (high)
Reserved
Explanation on R/W
R/W : Readable/Writable
R
: Read only
W : Write only
Explanation on initial value
0
: The initial value of this bit is “0”.
1
: The initial value of this bit is “1”.
X
: The initial value of this bit is undefined.
: This bit is not used.
*
: The initial value of this bit is “1” or “0”.
It varies depending on the mode pin (MD2, MD1 or MD0 pin) .
+ : The initial value of this bit is “1” or “0”.
$
: The initial value of this bit varies depending on the operation mode of the resource.
#H* : Varies depending on the RAM area of the device.
38
Initial value
XXXXXXXXB
XXXXXXXXB
MB90880 Series
■ INTERRUPT SOURCES, INTERRUPT VECTORS AND INTERRUPT CONTROL
REGISTERS
Interrupt source
µDMAC
Clearing
channel
of EI2OS
no.
Interrupt vector
Interrupt control
register
No.
Address
No.
Address
Reset
×
⎯
#08
FFFFDCH
⎯
⎯
INT9 instruction
×
⎯
#09
FFFFD8H
⎯
⎯
Exception
×
⎯
#10
FFFFD4H
⎯
⎯
INT0 (IRQ0/1)
0
#11
FFFFD0H
INT0 (IRQ2 to IRQ7)
×
#12
FFFFCCH
ICR00
0000B0H
INT0 (IRQ8 to IRQ15)
×
#13
FFFFC8H
INT0 (IRQ16 to IRQ23)
×
#14
FFFFC4H
ICR01
0000B1H
Base timer ch.0 (source 0,1)
1
#15
FFFFC0H
Base timer ch.1 (source 0,1)
2
#16
FFFFBCH
ICR02
0000B2H
Base timer ch.2 (source 0,1)
3
#17
FFFFB8H
Base timer ch.3 (source 0,1)
4
#18
FFFFB4H
ICR03
0000B3H
PPG0/PPG4 counter borrow
5
#19
FFFFB0H
PPG1/PPG5 counter borrow
6
#20
FFFFACH
ICR04
0000B4H
PPG2/PPG6 counter borrow
7
#21
FFFFA8H
ICR05
0000B5H
ICR06
0000B6H
ICR07
0000B7H
ICR08
0000B8H
ICR09
0000B9H
ICR10
0000BAH
ICR11
0000BBH
ICR12
0000BCH
ICR13
0000BDH
PPG3/PPG7 counter borrow
×
8
#22
FFFFA4H
8/16-bit up-down counter/timer (ch.0/1)
compare / underflow / overflow / up-down
inversion
×
×
#23
FFFFA0H
Input capture retrieval (ch.0/1)
×
#24
FFFF9CH
Output compare (ch.0/1/2) match
×
#25
FFFF98H
Output compare (ch.3/4/5) match
×
#26
FFFF94H
A/D converter
×
#27
FFFF90H
Overflow in 16-bit free-run timer / compare
clear / multi-function serial ch.4/5/6 status
9
#28
FFFF8CH
Multi-function serial ch.4 reception
10
#29
FFFF88H
Multi-function serial ch.4 transition
11
#30
FFFF84H
Multi-function serial ch.5 reception
12
#31
FFFF80H
Multi-function serial ch.5 transition
13
#32
FFFF7CH
Multi-function serial ch.6 reception
14
#33
FFFF78H
Multi-function serial ch.6 transition
15
#34
FFFF74H
Multi-function serial ch.0/1 reception / status
×
#35
FFFF70H
Multi-function serial ch.0/1 transmission
×
#36
FFFF6CH
Multi-function serial ch.2 reception / status
×
#37
FFFF68H
Multi-function serial ch.2 transmission
×
#38
FFFF64H
(Continued)
39
MB90880 Series
(Continued)
Interrupt source
µDMAC
Clearing
channel
2
of EI OS
no.
Interrupt vector
No.
Address
Multi-function serial ch.3 reception / status
×
#39
FFFF60H
Multi-function serial ch.3 transmission
×
#40
FFFF5CH
Flash writing/deletion, time base timer, watch
timer*
×
×
#41
FFFF58H
Delayed interrupt generation module
×
×
#42
FFFF54H
×
Interrupt control
register
No.
Address
ICR14
0000BEH
ICR15
0000BFH
: The interrupt request flag is not cleared by the interrupt clear signal.
: The interrupt request flag is cleared by the interrupt clear signal.
: The interrupt request flag is cleared by the interrupt clear signal. Stop request function provided at receiving
only.
* : Flash writing/deletion, the time base timer and watch timer cannot be used simultaneously.
Note : If a resource has two interrupt sources for the same interrupt number, both of the interrupt request flags are
cleared by the EI2OS/µDMAC interrupt clear signal. Therefore, when either of the two sources for the EI2OS/
µDMAC function is used, the other interrupt function can not be used. In this case, set the interrupt request
enable bit to “0” in the appropriate resource and take measures by software polling.
40
MB90880 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute maximum ratings
Parameter
Symbol
Rating
Unit
Remarks
Min
Max
VCC
VSS − 0.3
VSS + 4.0
V
DVCC
VSS − 0.3
VSS + 4.0
V
DVcc = Vcc*2
AVCC
VSS − 0.3
VSS + 4.0
V
*2
AVRH
VSS − 0.3
VSS + 4.0
V
*2
VSS − 0.3
VSS + 4.0
V
*3
VSS − 0.3
VSS + 7.0
V
*3, *8
VSS − 0.3
VSS + 4.0
V
*3
VSS − 0.3
VSS + 7.0
V
*3, *8
ICLAMP
− 2.0
+2.0
mA
*7
Total maximum clamp current
Σ⏐ICLAMP⏐
⎯
20
mA
*7
“L” level maximum output current
IOL1
⎯
10
mA
*4
IOL2
⎯
20
mA
PA0 to PA3*4
IOLAV1
⎯
3
mA
*5
IOLAV2
⎯
10
mA
PA0 to PA3*5
ΣIOL1
⎯
60
mA
ΣIOL2
⎯
80
mA
PA0 to PA3
ΣIOLAV1
⎯
30
mA
*6
ΣIOLAV2
⎯
40
mA
PA0 to PA3*6
IOH1
⎯
−10
mA
*4
IOH2
⎯
−20
mA
PA0 to PA3*4
IOHAV1
⎯
−3
mA
*5
IOHAV2
⎯
−10
mA
PA0 to PA3*5
ΣIOH1
⎯
−60
mA
ΣIOH2
⎯
−80
mA
PA0 to PA3
ΣIOHAV1
⎯
−30
mA
*6
ΣIOHAV2
⎯
−40
mA
PA0 to PA3*6
Power consumption
PD
⎯
320
mW
Operating temperature
TA
−40
+85
°C
Tstg
−55
+150
°C
Power supply voltage*1
Input voltage*1
VI
Output voltage*1
VO
Maximum clamp current
“L” level average output current
“L” level maximum total output
current
“L” level average total output
current
“H” level maximum output
current
“H” level average output current
“H” level maximum total output
current
“H” level average total output
current
Storage temperature
*1 : The parameter is based on VSS = AVSS = DVSS = 0.0 V.
*2 : Set AVCC, DVCC and AVRH to the same voltage. AVCC and DVCC must not exceed VCC. Also, AVRH must not
exceed AVCC.
*3 : VI and VO must not exceed 0.3V. When the maximum current to/from an input is limited by using an external
component, the ICLAMP rating supersedes the VI rating.
*4 : The maximum output current is defined as the peak value of the current of any one of the corresponding pins.
(Continued)
41
MB90880 Series
(Continued)
*5 : The average output current is defined as the value of the average current flowing over 100 ms at any one of
the corresponding pins.
*6 : The average total output current is defined as the value of the average current flowing over 100 ms at all of the
corresponding pins.
*7 : • Relevant pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67,
P70 to P76, P80 to P87, P90 to P97, PA0 to PA3
• Use within recommended operating conditions.
• Use with DC voltage (current) .
• The + B signal should always be applied with a limiting resistance placed between the + B signal and the
microcontroller.
• Set the limiting resistor value, whether instantaneous or stationary, so that the current to be input to the
microcontroller pin does not exceed the rating during the input of the + B signal.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the + B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may
affect other devices.
• Note that if a + B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply
is provided from the pins, so that incomplete operation may result.
• Note that if the + B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the + B input pin open.
• Note that analog system input/output pins (LCD drive pins, comparator input pins, etc.) cannot accept + B
signal input.
• Sample recommended circuit :
• Input/Output equivalent circuit
Protective diode
VCC
Limiting
resistance
P-ch
+ B input (0V to 16V)
N-ch
R
*8 : P74 to P76 and P80 to P87 can be used as 5V I/F pins.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed any of these ratings.
42
MB90880 Series
2. Recommended operating conditions
(VSS = AVSS = 0.0 V)
Parameter
Power supply voltage
“H” level input voltage
“L” level input voltage
Symbol
Value
Unit
Remarks
Min
Max
VCC
DVcc
2.7
3.6
V
In normal operation
1.8
3.6
V
Hold stop status
VIH
0.7 VCC
VCC + 0.3
V
All pins other than VIH2, VIHS,
VIHM and VIHX
VIH2
0.7 VCC
VSS + 5.8
V
P74 to P76, P80 to P87
VIHS
0.8 VCC
VCC + 0.3
V
Hysteresis input pins
VIHS2
0.7 VCC
VCC + 0.3
V
Hysteresis input pins
(multi-function serial pins)
VIHS3
0.7 VCC
VCC + 0.3
V
CMOS input pins (external
bus mode input pins)
VIHM
VCC − 0.3
VCC + 0.3
V
MD pin input
VIHX
0.8 VCC
VCC + 0.3
V
X0A and X1A pins
VIL
VSS − 0.3
0.3 VCC
V
All pins other than VILS, VILM
and VIHX
VILS
VSS − 0.3
0.2 VCC
V
Hysteresis input pins
VILS2
VSS − 0.3
0.3 VCC
V
Hysteresis input pins
(multi-function serial pins)
VILS3
VSS − 0.3
0.3 VCC
V
CMOS input pins (external
bus mode pins)
VILM
VSS − 0.3
VSS + 0.3
V
MD pin input
VILX
VSS − 0.3
0.1
V
X0A and X1A pins
Use a ceramic capacitor or
comparable capacitor of the
AC characteristics. Bypass
capacitor at the VCC pin
should be greater than this
capacitor.
Smoothing capacitor
CS
0.1
1.0
µF
Operating temperature
TA
−40
+85
°C
• C Pin Connection Diagram
C
CS
43
MB90880 Series
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges. Always use semiconductor devices within their recommended operating
condition ranges. Operation outside these ranges may adversely affect reliability and could result in
device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
44
MB90880 Series
3. DC characteristics
(VCC = 2.7V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter Symbol
“H” level
output
voltage
“L” level
output
voltage
Input leak
current
Pull-up
resistance
Open-drain
output
current
VOH
VOL
IIL
RPULL
Ileak
Pin name
Conditions
Value
Min
Typ
Max
Unit
Remarks
All pins
except
P74 to P76,
P80 to P87
and
PA0 to PA3
VCC = 3.0 V,
IOH = −4.0 mA
VCC − 0.5
⎯
⎯
V
P74 to P76,
P80 to P87
VCC = 3.0 V,
IOH = −2.0 mA
VCC − 0.5
⎯
⎯
V
PA0 to PA3
DVCC = 3.0 V,
IOH = −10.0 mA
DVCC − 0.6
⎯
⎯
V
All pins
except
P74 to P76,
P80 to P87
and
PA0 to PA3
VCC = 3.0 V,
IOL = 4.0 mA
⎯
⎯
0.4
V
P74 to P76,
P80 to P87
VCC = 3.0 V,
IOH = −2.0 mA
⎯
⎯
0.4
V
PA0 to PA3
DVCC = 3.0 V,
IOL = 10.0 mA
⎯
⎯
0.5
V
All input pins
VCC = 3.3 V,
VSS < VI < VCC
−10
⎯
+10
µA
25
50
100
kΩ
Evaluation
version
Flash
memory
version /
MASK ROM
version
⎯
P31, P32,
P34, P35,
P43, P44,
P46, P47,
P72 to P76,
P80 to P87,
P96, P97
⎯
⎯
15
33
66
kΩ
⎯
0.1
10
µA
(Continued)
45
MB90880 Series
(Continued)
(VCC = 2.7V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Pin name
Value
Unit
Min
Typ
Max
VCC = 3.3V;
Normal internal 25 MHz
operation
⎯
20
28
mA
VCC = 3.3V;
Normal internal 33 MHz
operation
⎯
28
38
mA
VCC = 3.3V;
Internal 25 MHz
operation; flash write
⎯
30
40
mA
VCC = 3.3V;
Internal 33 MHz
operation; flash write
⎯
40
52
mA
VCC = 3.3V;
Internal 25 MHz
operation; sleep mode
⎯
6
12
mA
VCC = 3.3V;
Internal 33 MHz
operation; sleep mode
⎯
10
20
mA
⎯
VCC = 3.3 V;
Internal 2 MHz,
operation; Time-base timer
⎯
0.25
0.9
mA
⎯
VCC = 3.3V;
External 32 kHz & internal
8 kHz operation;
sub-operation
(TA = + 25 °C)
⎯
80
200
µA
⎯
VCC = 3.3 V;
External 32 MHz,
Internal 8 MHz operation;
sub sleep mode (TA = +25 °C)
⎯
50
160
µA
ICCT
⎯
VCC = 3.3V;
External 32 kHz & internal
8 kHz operation; watch
operation
(TA = + 25 °C)
⎯
20
110
µA
ICCH
⎯
TA = + 25 °C;
Stop mode; VCC = 3.3V
⎯
15
100
µA
AVCC, AVSS, VCC, DVCC, VSS, DVSS
⎯
5
15
pF
ICC
ICCS
⎯
⎯
Supply current
ICTS
ICCL
ICCLS
Input
capacitance
Conditions
CIN
All pins except
AVCC, AVSS,
VCC, DVCC,
VSS, DVSS
Note : P74 to P76 and P80 to P87 are N-ch open-drain pins with controls and normally used at the CMOS level.
46
MB90880 Series
4. AC characteristics
(1) Clock timing ratings
(VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol Pin name
FCH
Clock frequency
Clock cycle time
Input clock pulse width
Input clock rise/fall time
Internal operating clock
frequency
Internal operating clock
cycle time
X0, X1
Value
Conditions
Min
Typ
Max
⎯
3
⎯
25
External crystal
oscillation
⎯
3
⎯
50
External clock input
⎯
4
⎯
25
PLL1 multiplication
⎯
3
⎯
12.5
⎯
3
⎯
6.66
MHz PLL2 multiplication
PLL3 multiplication
⎯
3
⎯
6.25
PLL4 multiplication
⎯
3
⎯
5.5
PLL6 multiplication
⎯
3
⎯
4.125
PLL8 multiplication
Unit
Remarks
FCL
X0A, X1A
⎯
⎯
32.768
⎯
kHz
tC
X0, X1
⎯
15.15
⎯
333
ns
tCL
X0A, X1A
⎯
⎯
30.5
⎯
µs
PWH
PWL
X0
⎯
5
⎯
⎯
ns
PWLH
PWLL
X0A
⎯
⎯
15.2
⎯
µs
*2
tcr
tcf
X0
⎯
⎯
⎯
5
ns
External clock in
use
fCP
⎯
⎯
1.5
⎯
33
MHz *1
fCPL
⎯
⎯
⎯
8.192
⎯
kHz
tCP
⎯
⎯
30.3
⎯
666
ns
tCPL
⎯
⎯
⎯
122.1
⎯
µs
*1
*1
*1 : Observe the operating voltage with care.
The maximum operating frequency is 25 MHz in MB90F883(S) and MB90F884(S).
*2 : Input it at a duty ratio of 50% ±3%.
• X0, X1 clock timing
tC
0.8 VCC
X0
0.2 VCC
PWH
PWL
tcf
tcr
47
MB90880 Series
• X0A, X1A clock timing
tCL
0.8 VCC
X0A
0.1 VCC
PWLH
PWLL
tcf
48
tcr
MB90880 Series
• PLL warranted operating range
Internal operating clock frequency vs. Supply voltage
Supply voltage VCC (V)
3.6
PLL warranted operating range
3.0
2.7
Normal operating range
1.5
16
4
33
Internal clock fCP (MHz) *4
Notes: • Use the fCP at 4 MHz or higher only for PLL1 multiplication.
• For A/D operating frequencies, refer to “5. A/D Converter electrical characteristics”.
Source oscillator frequency vs. Internal operating clock frequency
33
8 Multiplication*3
Internal clock fCP (MHz) *4
25
24
20
18
16
12
3 Multiplication*1
No multiplication
6 Multiplication*3
2 Multiplication*1, *2
1 Multiplication*1
4 Multiplication
*1, *2
9
8
6
4
1.5
3 4 5 6 8 10 12.5
16
20
25
32
40
50
Source oscillator clock FCH (MHz)
*1 :
*2 :
*3 :
*4 :
When using the internal clock at “20 MHz < fCP ≤ 25 MHz” in PLL1, 2, 3 or 4 multiplication setting, set both of
the DIV2 and PLL2 bits to “1” in the PLLOS register.
Example : When the source oscillator frequency is 24 MHz in PLL1 multiplication :
CKSCR register : CS1 = “0”, CS0 = “0”
PLLOS register : DIV2 = “1”, PLL2 = “1”
Example : When the source oscillator frequency is 6 MHz in PLL3 multiplication :
CKSCR register : CS1 = “1”, CS0 = “0”
PLLOS register : DIV2 = “1”, PLL2 = “1”
When using the internal clock at “20 MHz < fCP ≤ 25 MHz” in PLL 2 or 4 multiplication setting, the following
settings can also be used.
PLL2 multiplication : CKSCR register : CS1 = “0”, CS0 = “0”
PLLOS register : DIV2 = “0”, PLL2 = “1”
PLL4 multiplication CKSCR register : CS1 = “0”, CS0 = “1”
PLLOS register : DIV2 = “0”, PLL2 = “1”
When using the PLL6 or 8 multiplication setting, set DIV2 to “0” and PLL2 to “1” in the PLLOS register.
Example : When the source oscillator frequency is 4 MHz in PLL6 multiplication :
CKSCR register : CS1 = “1”, CS0 = “0”
PLLOS register : DIV2 = “0”, PLL2 = “1”
Example : When the source oscillator frequency is 3 MHz in PLL8 multiplication :
CKSCR register : CS1 = “1”, CS0 = “1”
PLLOS register : DIV2 = “0”, PLL2 = “1”
The maximum operating frequency of MB90F883(S) and MB90F884(S) is 25 MHz.
49
MB90880 Series
AC characteristics are determined using the following measurement reference voltage values.
• Input signal waveform
Hysteresis input pins
Output pins
0.8 VCC
2.4 V
0.2 VCC
0.8 V
Pins other than hysteresis input/MD input pins
0.7 VCC
0.3 VCC
50
• Output signal waveform
MB90880 Series
(2) Clock output timing
(VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Cycle time
CLK↑ → CLK↓
Symbol
Pin name
Conditions
tCYC
CLK
⎯
tCHCL
CLK
Value
Min
Max
tCP*
⎯
Unit
Remarks
ns
VCC = 3.0 V to 3.6 V tCP* / 2 − 15 tCP* / 2 + 15
ns
fCP = 25 MHz
VCC = 2.7 V to 3.3 V tCP* / 2 − 20 tCP* / 2 + 20
ns
fCP = 16 MHz
VCC = 2.7 V to 3.3 V tCP* / 2 − 64 tCP* / 2 + 64
ns
fCP = 5 MHz
* : tCP is the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”.
tCYC
tCHCL
2.4 V
CLK
2.4 V
0.8 V
51
MB90880 Series
(3) Reset input ratings
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Reset input time
Symbol
tRSTL
Pin
name
Value
Conditions
⎯
RST
Min
Max
16 tCP*1
⎯
Unit
Remarks
ns
In normal
operation
Oscillator oscillation time *2
+ 100 µs + 16 tCP*1
⎯
ms
In sub clock,
sub-sleep,
watch and stop
modes
100
⎯
µs
In time base
timer mode
*1 : tCP is the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”.
*2 : Oscillator oscillation time is the time to reach 90% amplitude. For a crystal oscillator, this is a few to several
tens of ms; for a ceramic oscillator, this is several hundred ms to a few ms, and for an external clock this is 0 ms.
• In sub clock, sub-sleep, watch and stop modes
tRSTL
RST
0.2 VCC
0.2 VCC
90% of amplitude
X0
Internal operation
clock
100 µs +
16 tCP
Oscillator
oscillation
time
Internal reset
Oscillation stabilization
wait time
Execution of instruction
• Measurement conditions for AC ratings
CL : Load capacitance applied to pin during testing
Pin
CL
52
CLK, ALE : CL = 30 pF
AD15 to AD00 (Address, data bus) , RD, WR,
A23 to A00/D15 to D00 : CL = 30 pF
MB90880 Series
(4) Power-on ratings (Power-on reset)
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol Pin name
Power rise time
Power cutoff time
tR
VCC
tOFF
VCC
Conditions
⎯
Value
Unit
Remarks
Min
Max
0.05
30
ms
*
1
⎯
ms
For continuous
operation
* : During the power rise time, VCC must be less than 0.2V.
Notes : • The above ratings are values used for power-on reset.
• A power-on reset should be applied by restarting the power supply inside the device.
tR
2.7 V
VCC
0.2 V
0.2 V
0.2 V
tOFF
A sudden change in the supply voltage may activate a power-on reset.
As shown in the following figure, it is recommended to apply a smooth voltage rise with
suppressed fluctuation when changing the supply voltage during operation.
Main power
voltage
VCC
Sub supply voltage
VSS
RAM data held
A rise slope of 50mV/ms or less
is recommended.
53
MB90880 Series
(5) Bus read timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 °C to +70 °C)
Parameter
ALE pulse width
Symbol Pin name
tLHLL
ALE
Conditions
⎯
Value
Unit
Remarks
⎯
ns
16 MHz < fCP ≤
25 MHz
tCP* / 2 − 20
⎯
ns
8 MHz < fCP ≤
16 MHz
tCP* / 2 − 35
⎯
ns
fCP ≤ 8 MHz
tCP* / 2 − 17
⎯
ns
tCP* / 2 − 40
⎯
ns
Min
Max
tCP* / 2 − 15
Valid address →
ALE↓ time
tAVLL
Address,
ALE
⎯
ALE ↓ →
valid address time
tLLAX
ALE,
address
⎯
tCP* / 2 − 15
⎯
ns
valid address →
RD↓ Time
tAVRL
RD,
address
⎯
tCP* − 25
⎯
ns
Valid address →
valid data input
tAVDV
Address /
data
⎯
⎯
5 tCP* / 2 − 55
ns
⎯
5 tCP* / 2 − 80
ns
fCP ≤ 8 MHz
3 tCP* / 2 − 25
⎯
ns
16 MHz < fCP ≤
25 MHz
3 tCP* / 2 − 20
⎯
ns
8 MHz < fCP ≤
16 MHz
⎯
3 tCP* / 2 − 55
ns
⎯
3 tCP* / 2 − 80
ns
RD pulse width
tRLRH
RD
⎯
RD↓ →
valid data input
tRLDV
RD, data
⎯
RD↑→
data hold time
tRHDX
RD, data
⎯
0
⎯
ns
RD↑ → ALE↑ time
tRHLH
RD, ALE
⎯
tCP* / 2 − 15
⎯
ns
RD↑ →
valid address time
tRHAX
Address,
RD
⎯
tCP* / 2 − 10
⎯
ns
Valid address →
CLK↑ time
tAVCH
Address,
CLK
⎯
tCP* / 2 − 17
⎯
ns
RD↓ → CLK↑ time
tRLCH
RD, CLK
⎯
tCP* / 2 − 17
⎯
ns
ALE↓ → RD↓ time
tLLRL
RD, ALE
⎯
tCP* / 2 − 15
⎯
ns
* : tCP is the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”.
54
fCP ≤ 8 MHz
fCP ≤ 8 MHz
MB90880 Series
tAVCH
tRLCH
2.4 V
2.4 V
CLK
tRHLH
ALE
2.4 V
2.4 V
tLHLL
2.4 V
0.8 V
tRLRH
2.4 V
RD
tAVLL
tLLAX
0.8 V
tLLRL
Multiplex mode
tAVRL
A23 to A16
tRLDV
tRHAX
2.4 V
2.4 V
0.8 V
0.8 V
tAVDV
2.4 V
2.4 V
tRHDX
0.7 VCC
0.8 V
0.7 VCC
Read data
Address
AD15 to AD00
0.8 V
0.3 VCC
0.3 VCC
tRHAX
Non-multiplex mode
A23 to A00
2.4 V
2.4 V
0.8 V
0.8 V
tRLDV
tRHDX
tAVDV
0.7 VCC
0.7 VCC
Read data
D15 to D00
0.3 VCC
0.3 VCC
55
MB90880 Series
(6) Bus write timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 °C to +70 °C)
Parameter
Valid address → WR ↓
time
WR pulse width
Valid data output → WR↑
time
WR↑ → data hold time
Value
Symbol
Pin name
Conditions
Min
Max
tAVWL
Address,
WR
⎯
tCP* − 15
⎯
ns
⎯
3 tCP* / 2 − 25
⎯
ns
16 MHz < fCP ≤
25 MHz
⎯
3 tCP* / 2 − 20
⎯
ns
8 MHz < fCP ≤ 16
MHz
⎯
3 tCP* / 2 − 15
⎯
ns
⎯
10
⎯
ns
16 MHz < fCP ≤
25 MHz
⎯
20
⎯
ns
8 MHz < fCP ≤ 16
MHz
⎯
30
⎯
ns
fCP ≤ 8 MHz
tWLWH
tDVWH
tWHDX
WRL, WRH
Data,
WR
WR, data
WR↑ → valid address time
tWHAX
WR,
address
⎯
tCP* / 2 − 10
⎯
ns
WR↑ → ALE↑ time
tWHLH
WR, ALE
⎯
tCP* / 2 − 15
⎯
ns
WR↓ → CLK↑ time
tWLCH
WR, CLK
⎯
tCP* / 2 − 17
⎯
ns
* : tCP is the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”.
56
Unit
Remarks
MB90880 Series
tWLCH
2.4 V
CLK
tWHLH
2.4 V
ALE
tWLWH
2.4 V
WR
(WRL, WRH)
0.8 V
Multiplex mode
tAVWL
A23 to A16
tWHAX
2.4 V
2.4 V
0.8 V
0.8 V
tDVWH
2.4 V
Address
AD15 to AD00
2.4 V
2.4 V
Write data
0.8 V
0.8 V
0.8 V
tWHAX
Non-multiplex mode
A23 to A00
2.4 V
2.4 V
0.8 V
0.8 V
tDVWH
D15 to D00
tWHDX
2.4 V
0.8 V
tWHDX
2.4 V
Write data
0.8 V
57
MB90880 Series
(7) Ready input timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 °C to +70 °C)
Parameter
Symbol
RDY setup time
tRYHS
RDY hold time
tRYHH
Pin name
RDY
Conditions
Value
Max
⎯
35
⎯
ns
⎯
70
⎯
ns
⎯
0
⎯
ns
2.4 V
2.4 V
CLK
ALE
RD/WR
tRYHS
tRYHH
When
RDY wait is
not applied
When
RDY wait is
applied
(1 cycle)
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tRYHS
58
Unit
Min
Remarks
fCP = 8 MHz
MB90880 Series
(8) Hold timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 °C to +70 °C)
Parameter
Symbol
Pin name
Pin floating → HAK↓
time
tXHAL
HAK
HAK↓ → valid pin time
tHAHV
HAK
Conditions
⎯
Value
Unit
Min
Max
30
tCP*
ns
tCP*
2 tCP*
ns
* : tCP is the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”.
Note : It takes one or more cycles from when the HRQ pin is read to when HAK changes.
HAK
2.4 V
0.8 V
tXHAL
Pins
2.4 V
0.8 V
tHAHV
High-Z
2.4 V
0.8 V
59
MB90880 Series
(9) Multi-function serial timing (UART, SIO)
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Pin name
Serial clock cycle time
tSCYC
⎯
UCK↓ → UO delay time
tSLOV
⎯
Valid UI → UCK↑
tIVSH
⎯
UCK↑ → valid UI hold time
tSHIX
Serial clock “H” pulse width
Value
Conditions
Max
8 tCP*2
⎯
ns
−50
+50
ns
50
⎯
ns
⎯
0
⎯
ns
tSHSL
⎯
4 tCP*2
⎯
ns
Serial clock “L” pulse width
tSLSH
⎯
4 tCP*2
⎯
ns
UCK↓ → UO delay time
tSLOV
⎯
⎯
50
ns
Valid UI → UCK↑
tIVSH
⎯
50
⎯
ns
UCK↑ → valid UI hold time
tSHIX
⎯
50
⎯
ns
Internal shift clock mode
output pin :
CL*1 = 80 pF + 1 TTL
External shift clock mode
output pin :
CL*1 = 80 pF + 1 TTL
*1 : CL is the load capacitance applied to pins during testing.
*2 : tCP is the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”.
Note : The above AC characteristics are for CLK synchronous mode operation.
• Internal shift clock mode
tSCYC
UCK
2.4 V
0.8 V
0.8 V
tSLOV
2.4 V
UO
0.8 V
tIVSH
UI
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
• External shift clock mode
tSLSH
tSHSL
UCK
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tSLOV
2.4 V
UO
0.8 V
tIVSH
UI
60
Unit
Min
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
MB90880 Series
(10) Multi-function serial timing (I2C)
a. Master mode operation
Parameter
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Symbol
Conditions
Standard mode
High-speed
mode*3
Min
Max
Min
Max
Unit
SCL clock frequency
fSCL
0
100
0
400
kHz
SCL clock “L” width
tLOW
4.7
⎯
4.7
⎯
µs
SCL clock “H” width
tHIGH
4.0
⎯
4.0
⎯
µs
Bus-free time between “stop”
condition and “start” condition
tBUS
4.7
⎯
1.3
⎯
µs
4.7
⎯
0.6
⎯
µs
4.0
⎯
0.6
⎯
µs
Repeat “start” condition setup time
SCL↑ → SDA↓
tSUSTA
(Repeat) “start” condition hold time
SDA↓ → SCL↓
tHDSTA
“Stop” condition setup time
SCL↑ → SDA↑
tSUSTO
4.0
⎯
0.6
⎯
µs
Data hold time
SCL↓ → SDA↓↑
tHDDAT
2tcp*1
⎯
2tcp*1
⎯
µs
Data setup time
SDA↓↑ → SCL↑
tSUDAT
250
⎯
100*2
⎯
ns
R=1kΩ
C=50pF*4
61
MB90880 Series
b. Slave mode operation
Parameter
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Symbol
Conditions
Standard mode
High-speed mode
*3
Min
Max
Min
Max
Unit
SCL clock frequency
fSCL
0
100
0
400
kHz
SCL clock “L” width
tLOW
4.7
⎯
1.3
⎯
µs
SCL clock “H” width
tHIGH
4.0
⎯
0.6
⎯
µs
Bus-free time between “stop”
condition and “start” condition
tBUS
4.7
⎯
1.3
⎯
µs
4.7
⎯
0.6
⎯
µs
4.0
⎯
0.6
⎯
µs
Repeat “start” condition setup time
SCL↑ → SDA↓
tSUSTA
(Repeat) “start” condition hold time
SDA↓ → SCL↓
tHDSTA
“Stop” condition setup time
SCL↑ → SDA↑
tSUSTO
4.0
⎯
0.6
⎯
µs
Data hold time
SCL↓ → SDA↓↑
tHDDAT
2tcp*1
⎯
2tcp*1
⎯
µs
Data setup time
SDA↓↑ → SCL↑
tSUDAT
250
⎯
100*2
⎯
ns
R=1kΩ
C=50pF*4
*1 : tCP is the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”.
*2 : The high-speed mode I2C bus device can be used in a standard mode I2C bus system. However, the device
must satisfy the required condition “tSUDAT ≥ 250 ns”. If the device does not extend the “L” period of the SCL
signal, the succeeding data must be output to the SDA line before a period of 1250 ns (the maximum time of
SDA/SCL rise + tSUDAT) in which the SCL line is open.
*3 : Set the internal operation clock to 6MHz or higher when using this over 100kHz.
*4 : “R” and “C” are the pull-up resistance and load capacitance of the SCL/SDA lines.
62
MB90880 Series
• Note on SDA/SCL setup time
SDA
Input data setup time
SCL
6 tcp
Note: The specification for the input data setup time of the device which is connected to the bus may not be satisfied,
depending on the load capacitance and pull-up resistance.
If the specification of the input data setup time can not be satisfied, adjust the pull-up resistance of SDA and
SCL.
• Timing definition
SDA
tBUS
tLOW
tHDSTA
tSUDAT
SCL
tHDSTA
tHIGH
tHDDAT
fSCL
tSUSTA
tSUSTO
63
MB90880 Series
(11) Timer input timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Pin name
Conditions
Input pulse width
tTIWH
tTIWL
IN0, IN1,
TIO0 to TIO3
⎯
Value
Min
Max
4 tCP*
⎯
Unit
ns
*: tCP is the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”.
IN0, IN1
TIO0 to TIO3
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tTIWL
tTIWH
(12) Timer output timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
CLK↑ → change time
PPG0 to PPG5 change
time
OUT0 to OUT5 change
time
CLK
PPG0 to PPG7
OUT0 to OUT5
TIO0 to TIO3
Symbol
Pin name
Conditions
tTO
PPG0 to PPG7,
OUT0 to OUT5,
TIO0 to TIO3
Load
condition :
80 pF
0.7 VCC
0.7 VCC
0.3 VCC
tTO
64
Value
Min
Max
30
⎯
Unit
ns
MB90880 Series
(13) Trigger input timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Pin name
Conditions
Input pulse width
tTRGH
tTRGL
ADTG,
IRQ0 to IRQ7
⎯
Value
Unit
Remarks
⎯
ns
In normal operation
⎯
µs
In stop mode
Min
Max
5 tCP*
1
*: tCP is the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”.
IRQ0 to IRQ7
ADTG
0.8 VCC
0.8 VCC
0.2 VCC
tTRGH
0.2 VCC
tTRGL
65
MB90880 Series
(14) Chip select output timing
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Pin name
Conditions
Chip select output valid time
→ RD↓
tSVRL
CS0 to CS3,
RD
Chip select output valid time
→ WR↓
tSVWL
RD↑ →
Chip select output valid time
WR↑ →
Chip select output valid time
Value
Unit
Min
Max
⎯
tCP* / 2 − 7
⎯
ns
CS0 to CS3,
WRH, WRL
⎯
tCP* / 2 − 7
⎯
ns
tRHSV
RD,
CS0 to CS3
⎯
tCP* / 2 − 17
⎯
ns
tWHSV
WRH, WRL,
CS0 to CS3
⎯
tCP* / 2 − 17
⎯
ns
*: tCP is the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”.
tSVRL
2.4 V
RD
0.8 V
tRHSV
A23 to A16
CS0 to CS3
2.4 V
0.8 V
2.4 V
D15 to D00
Read data
0.8 V
tSVWL
tWHSV
2.4 V
WRH, WRL
0.8 V
D15 to D00
Undefined
Write data
Note : The chip select output signal changes simultaneously due to the internal bus configuration; therefore, this
may generate a bus wait. AC cannot be warranted between the ALE output signal and the chip select output
signal.
66
MB90880 Series
5. A/D converter electrical characteristics
(VCC = AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, 2.7 V ≤ AVRH, TA = −40 °C to +85 °C)
Value
Symbol
Pin
name
Min
Standard
Max
Resolution
⎯
⎯
⎯
⎯
10
bit
Total error
⎯
⎯
⎯
⎯
±3.0
LSB
Linear error
⎯
⎯
⎯
⎯
±2.5
LSB
Differential linear
error
⎯
⎯
⎯
⎯
±1.9
LSB
Zero transition
voltage
VOT
AN0 to
AN7
AVSS − 1.5 LSB
AVSS + 0.5 LSB
AVSS + 2.5 LSB
V
Full-scale transition
voltage
VFST
AN0 to
AN7 AVRH − 3.5 LSB AVRH − 1.5 LSB AVRH + 0.5 LSB
V
Sampling time
tSMP
⎯
1.2
⎯
⎯
µs
*1
Compare time
tCMP
⎯
1.8
⎯
⎯
µs
*1
Conversion time
tCNV
⎯
3.0
⎯
⎯
µs
*1
Analog port input
current
IAIN
AN0 to
AN7
− 3.0
⎯
+ 3.0
µA
Analog input voltage
VAIN
AN0 to
AN7
AVSS
⎯
AVRH
V
⎯
AVRH
AVSS + 2.2
⎯
AVCC
V
IA
AVCC
⎯
1.9
3.7
mA
IAH
AVCC
⎯
⎯
5*2
µA
IR
AVRH
⎯
520
720
µA
Parameter
Reference voltage
Supply current
Unit Remarks
Reference voltage
supply current
IRH
AVRH
⎯
⎯
5
µA
Inter-channel
variation
⎯
AN0 to
AN7
⎯
⎯
4
LSB
*2
*1 : Time per channel
*2 : Current when the A/D converter is not in operation and the CPU is stopped (VCC = AVCC = AVRH = 3.0 V )
67
MB90880 Series
• External impedance and sampling time for analog input
This is an A/D converter with a sample hold function. If high external impedance is preventing it from securing
sufficient sampling time, a sufficient analog voltage will not be charged in the internal sample hold capacitor,
affecting the accuracy of the A/D conversion. In order to satisfy the A/D conversion accuracy specifications,
adjust the register values and operating frequency or decrease the external impedance so that the sampling
time becomes longer than the minimum value, based on the relationship between the external impedance and
the minimum sampling time. If a sufficient sampling time cannot be secured, connect a capacitor with a capacitance of approximately 0.1 µF to the analog input pin.
Model diagram of analog input circuit
R
Analog input
Comparator
C
Turned on during sampling ON
R
C
12.2kΩ (Max)
8.5pF (Max)
Note : These are reference values.
• Relation between external impedance and minimum sampling time
[External impedance = 0 kΩ to 20 kΩ]
[External impedance = 0 kΩ to 100 kΩ]
Flash memory device
MASK ROM device
100
20
90
18
External impedance [kΩ]
External impedance [kΩ]
Flash memory device
MASK ROM device
80
70
60
50
40
30
20
16
14
12
10
10
6
4
2
0
0
0
5
10
15
20
25
30
35
Minimum sampling time [µs]
• Errors :
As | AVRH⎯AVSS | decreases, the absolute error increases.
68
8
0
1
2
3
4
5
6
Minimum sampling time [µs]
7
8
MB90880 Series
6. Definition of A/D Converter Terms
Differential
linearity error
Total error
: Analog variation that is recognized by an A/D converter.
: Deviation between a line across zero-transition line ( “00 0000 0000” ← → “00 0000 0001” )
and full-scale transition line ( “11 1111 1110” ← → “11 1111 1111” ) and actual conversion
characteristics.
: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal
value.
: Difference between an actual value and a theoretical value. A total error includes zero transition error, full-scale transition error, and linear error.
Total error
3FFH
3FEH
1.5 LSB
Actual conversion
characteristics
3FDH
Digital output
Resolution
Non linearity
error
{1 LSB × (N − 1) + 0.5 LSB}
004H
VNT
(Actual measurement value)
003H
Actual conversion
characteristics
002H
Ideal characteristics
001H
0.5 LSB
AVSS
AVRH
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}
1 LSB
AVRH − AVSS
1 LSB (Ideal value) =
[V]
1024
Total error of digital output “N” =
[LSB]
VOT (Ideal value) = AVSS + 0.5 LSB [V]
VFST (Ideal value) = AVRH − 1.5 LSB [V]
VNT : A voltage at which digital output transits from (N − 1) H, NH.
(Continued)
69
MB90880 Series
(Continued)
Linearity error
Differential linearity error
Ideal
characteristics
3FFH
Actual conversion
characteristics
Digital output
3FDH
(N + 1)H
{1 LSB × (N − 1)
+ VOT }
VFST (actual
measurement
value)
VNT (actual
measurement value)
004H
Actual conversion
characteristics
003H
Digital output
3FEH
Actual conversion
characteristics
NH
V (N + 1) T
(actual measurement
value)
(N − 1)H
VNT
(actual measurement value)
Actual conversion
characteristics
002H
Ideal characteristics
001H
(N − 2)H
VOT (actual measurement value)
AVSS
AVRH
AVSS
AVRH
Analog input
Analog input
Non linearity error of digital output N =
Differential linearity error of digital output N =
VNT − {1 LSB × (N − 1) + VOT}
1 LSB
V (N+1) T − VNT
1 LSB
1 LSB =
[LSB]
−1 LSB [LSB]
VFST − VOT
1022
[V]
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
• Flash memory write/erase characteristics
Parameter
Conditions
Unit
Remarks
3.6
s
Excludes internal write time before
erase operation.
6.2
⎯
s
Excludes internal write time before
erase operation.
⎯
23
⎯
µs
Excludes overhead time at system
level.
⎯
10000
⎯
⎯
cycle
Average
TA = +85 °C
100000
⎯
⎯
h
Sector erase time
Chip erase time
TA = +25 °C,
VCC = 3.0 V
Byte (16-bit width)
write time
Number of write/erase
cycles
Flash memory data
hold time
Value
Min
Standard
Max
⎯
0.9
⎯
*
* : Value converted from the evaluation result of technology reliability (The Arrhenius equation is used to convert
the high-temperature high-speed test result into the average temperature + 85 °C.)
70
MB90880 Series
■ ORDERING INFORMATION
Part number
Package
MB90F882PF
MB90F883PF
MB90F883APF
MB90F884PF
MB90F884APF
MB90882PF
MB90883PF
MB90884PF
MB90F882SPF
MB90F883SPF
MB90F883ASPF
MB90F884SPF
MB90F884ASPF
MB90882SPF
MB90883SPF
MB90884SPF
100-pin plastic QFP
(FPT-100P-M06)
MB90F882PMC
MB90F883PMC
MB90F883APMC
MB90F884PMC
MB90F884APMC
MB90882PMC
MB90883PMC
MB90884PMC
MB90F882SPMC
MB90F883SPMC
MB90F883ASPMC
MB90F884SPMC
MB90F884ASPMC
MB90882SPMC
MB90883SPMC
MB90884SPMC
100-pin plastic LQFP
(FPT-100P-M20)
MB90V880-101CR-ES
MB90V880-102CR-ES
MB90V880A-101CR-ES
MB90V880A-102CR-ES
Remarks
With S :
Single clock product (without sub clock)
Without S :
Dual clock product (with sub clock)
299-pin ceramic PGA
(PGA-299C-A01)
Evaluation product
101 :
Single clock product (without sub clock)
102 :
Dual clock product (with sub clock)
71
MB90880 Series
■ PACKAGE DIMENSIONS
100-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
14.0 mm × 14.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm Max
Weight
0.65 g
Code
(Reference)
P-LFQFP100-14×14-0.50
(FPT-100P-M20)
100-pin plastic LQFP
(FPT-100P-M20)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
* 14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
+0.20
26
100
1
C
0.08(.003)
(0.50(.020))
0.25(.010)
0.60±0.15
(.024±.006)
25
0.20±0.05
(.008±.002)
0.10±0.10
(.004±.004)
(Stand off)
0˚~8˚
"A"
0.50(.020)
+.008
1.50 –0.10 .059 –.004
(Mounting height)
INDEX
M
0.145±0.055
(.0057±.0022)
2005 FUJITSU LIMITED F100031S-c-2-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
(Continued)
72
MB90880 Series
(Continued)
100-pin plastic QFP
Lead pitch
0.65 mm
Package width ×
package length
14.00 × 20.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
3.35 mm MAX
Code
(Reference)
P-QFP100-14×20-0.65
(FPT-100P-M06)
100-pin plastic QFP
(FPT-100P-M06)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
23.90±0.40(.941±.016)
* 20.00±0.20(.787±.008)
80
51
81
50
0.10(.004)
17.90±0.40
(.705±.016)
*14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
1
30
0.65(.026)
0.32±0.05
(.013±.002)
0.13(.005)
M
"A"
C
0.25(.010)
+0.35
3.00 –0.20
+.014
.118 –.008
(Mounting height)
0~8˚
31
2002 FUJITSU LIMITED F100008S-c-5-5
0.17±0.06
(.007±.002)
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
0.25±0.20
(.010±.008)
(Stand off)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
73
MB90880 Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
⎯
⎯
3
■ PRODUCT LINEUP
Change Results
Added the following part numbers:
MB90F883A (S), MB90F884A (S)
Added the following details to the CPU functions:
“Maximum operating frequency is 25 MHz in MB90F883 (S) ,
MB90F884 (S)”
Added the following details to the base timer:
“In MB90F883(S) and MB90F884(S), P24/TIO0, P25/TIO1,
P26/TIO2, and P27/TIO3 cannot be used as input function.”
4
Added the "Flash memory" item
21
■ HANDLING DEVICES
43
■ ELECTRICAL CHARACTERISTICS Added the "Smoothing capacitor" item
2. Recommended operating conditions
Added the "• C Pin Connection Diagram"
46
■ ELECTRICAL CHARACTERISTICS
3. DC characteristics
Added "13. Note of MB90F883 (S), MB90F884 (S)"
Added the "ICTS" and "ICCLS" items to the supply current
Changed supply current ratings:
ICCS Internal 25 MHz operation;
Typ 9 → 6, Max 16 → 12
ICCS Internal 33 MHz operation;
Typ 12 → 10, Max 22 → 20
ICCL Typ 70 → 80
ICCT Typ 15 → 20
ICCH Typ 10 → 15
47
■ELECTRICAL CHARACTERISTICS
4. AC characteristics
(1) Clock timing ratings
Added the following details to footnote 1 of the table:
“The maximum operating frequency is 25 MHz in
MB90F883(S) and MB90F884(S).”
71
■ ORDERING INFORMATION
Added the following part numbers:
MB90F883APF, MB90F884APF, MB90F883ASPF,
MB90F884ASPF, MB90F883APMC, MB90F884APMC,
MB90F883ASPMC, MB90F884ASPMC
Added the following details to the remarks:
With S :
Single clock product (without sub clock)
Without S :
Dual clock product (with sub clock)
Added the MB90V880 item
The vertical lines marked in the left side of the page show the changes.
74
MB90880 Series
The information for microcontroller supports is shown in the following homepage.
http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
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circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
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operation of the device with respect to use based on such
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Please note that Fujitsu will not be liable against you and/or any
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Any semiconductor devices have an inherent chance of failure. You
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If any products described in this document represent goods or
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Edited
Business Promotion Dept.
F0702