Burr-Brown OPA3681 Triple wideband, current-feedback operational amplifier with disable Datasheet

OPA3
OPA36
OPA3691
691
91
SBOS227A – DECEMBER 2001 – REVISED OCTOBER 2002
Triple Wideband, Current-Feedback
OPERATIONAL AMPLIFIER With Disable
FEATURES
DESCRIPTION
● FLEXIBLE SUPPLY RANGE:
+5V to +12V Single-Supply
±2.5V to ±6V Dual Supply
● UNITY-GAIN STABLE: 280MHz (G = 1)
● HIGH OUTPUT CURRENT: 190mA
● OUTPUT VOLTAGE SWING: ±4.0V
● HIGH SLEW RATE: 2100V/µs
● LOW SUPPLY CURRENT: 5.1mA/ch
● LOW DISABLED CURRENT: 150µA/ch
● IMPROVED HIGH-FREQUENCY PINOUT
● WIDEBAND +5V OPERATION: 190MHz (G = +2)
The OPA3691 sets a new level of performance for broadband, triple current-feedback op amps. Operating on a very
low 5.1mA/ch supply current, the OPA3691 offers a slew
rate and output power normally associated with a much
higher supply current. A new output stage architecture
delivers a high output current with minimal voltage headroom and crossover distortion. This gives exceptional singlesupply operation. Using a single +5V supply, the OPA3691
can deliver a 1V to 4V output swing with over 120mA drive
current and 150MHz bandwidth. This combination of features makes the OPA3691 an ideal RGB line driver or
single-supply Analog-to-Digital Converter (ADC) input driver.
The OPA3691’s low 5.1mA/ch supply current is precisely
trimmed at 25°C. This trim, along with low drift over temperature, ensures lower maximum supply current than competing products. System power may be further reduced by
using the optional disable control pin. Leaving this disable
pin open, or holding it HIGH, gives normal operation. If
pulled LOW, the OPA3691 supply current drops to less than
150µA/ch while the output goes into a high impedance
state. This feature may be used for power savings.
APPLICATIONS
●
●
●
●
●
●
●
●
RGB AMPLIFIERS
WIDEBAND INA
BROADBAND VIDEO BUFFERS
HIGH-SPEED IMAGING CHANNELS
PORTABLE INSTRUMENTS
ADC BUFFERS
ACTIVE FILTERS
CABLE DRIVERS
OPA3691 RELATED PRODUCTS
Voltage-Feedback
Current-Feedback
Fixed Gain
+5V
V1
SINGLES
DUALS
TRIPLES
OPA690
OPA691
OPA692
OPA2690
OPA2691
—
OPA3690
OPA3681
OPA3692
1/3
OPA3691
HIGH-SPEED INA FREQUENCY RESPONSE
301Ω
250Ω
66.5Ω
301Ω
+5V
25
+5V
1/3
OPA3691
10 (V1 – V2)
20
Gain (dB)
–5V
250Ω
–5V
499Ω
15
10
499Ω
5
1/3
OPA3691
V2
0
–5V
High-Speed INA (120MHz)
0.1
1
10
100
400
Frequency (MHz)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
Power Supply ............................................................................... ±6.5VDC
Internal Power Dissipation(2) ............................ See Thermal Information
Differential Input Voltage .................................................................. ±1.2V
Input Voltage Range ............................................................................ ±VS
Storage Temperature Range: ID, IDBQ ......................... –40°C to +125°C
Lead Temperature (soldering, 10s) .............................................. +300°C
Junction Temperature (TJ ) ........................................................... +175°C
ESD Resistance: HBM .................................................................... 2000V
CDM ................................................................... 1500V
MM ........................................................................ 200V
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTES:: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability. (2) Packages must be derated based on specified θJA.
Maximum TJ must be observed.
PACKAGE/ORDERING INFORMATION
PRODUCT
OPA3691
"
OPA3691
"
PACKAGE-LEAD
PACKAGE
DESIGNATOR(1)
TEMPERATURE
RANGE
SPECIFIED
PACKAGE
MARKING
SSOP-16 Surface-Mount
DBQ
–40°C to +85°C
OPA3691
OPA3691IDBQT
Tape and Reel, 250
"
"
"
"
OPA3691IDBQR
Tape and Reel, 2500
SO-16 Surface-Mount
D
–40°C to +85°C
OPA3691
OPA3691ID
Rails, 48
"
"
"
"
OPA3691IDR
Tape and Reel, 2500
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
PIN CONFIGURATION
Top View
SSOP, SO
OPA3691
–IN A
1
16 DIS A
+IN A
2
15 +VS
DIS B
3
14 OUT A
–IN B
4
13 –VS
+IN B
5
12 OUT B
DIS C
6
11 +VS
–IN C
7
10 OUT C
+IN C
8
9
–VS
ELECTRICAL CHARACTERISTICS: VS = ±5V
Boldface limits are tested at +25°C.
RF = 402Ω, RL = 100Ω, and G = +2, (see Figure 1 for AC performance only), unless otherwise noted.
OPA3691ID, IDBQ
TYP
PARAMETER
AC PERFORMANCE (see Figure 1)
Small-Signal Bandwidth (VO = 0.5Vp-p)
Bandwidth for 0.1dB Gain Flatness
Peaking at a Gain of +1
Large-Signal Bandwidth
Slew Rate
2
CONDITIONS
+25°C
G = +1, RF = 453Ω
G = +2, RF = 402Ω
G = +5, RF = 261Ω
G = +10, RF = 180Ω
G = +2, VO = 0.5Vp-p
RF = 453, VO = 0.5Vp-p
G = +2, VO = 5Vp-p
G = +2, 4V Step
280
225
210
200
90
0.2
200
2100
MIN/MAX OVER TEMPERATURE
+25°C(1)
0°C to
70°C(2)
–40°C to
+85°C(2)
200
190
180
40
1
35
1.5
20
2
1400
1375
1350
UNITS
MHz
MHz
MHz
MHz
MHz
dB
MHz
V/µs
MIN/ TEST
MAX LEVEL(3)
typ
min
typ
typ
min
max
typ
min
C
B
C
C
B
B
C
B
OPA3691
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SBOS227A
ELECTRICAL CHARACTERISTICS: VS = ±5V (Cont.)
Boldface limits are tested at +25°C.
RF = 402Ω, RL = 100Ω, and G = +2, (see Figure 1 for AC performance only), unless otherwise noted.
OPA3691ID, IDBQ
TYP
CONDITIONS
+25°C
G = +2, VO = 0.5V Step
G = +2, 5V Step
G = +2, VO = 2V Step
G = +2, VO = 2V Step
G = +2, f = 5MHz, VO = 2Vp-p
RL = 100Ω
RL ≥ 500Ω
RL = 100Ω
RL ≥ 500Ω
f > 1MHz
f > 1MHz
f > 1MHz
G = +2, NTSC, VO = 1.4Vp, RL = 150Ω
RL = 37.5Ω
G = +2, NTSC, VO = 1.4Vp, RL = 150Ω
RL = 37.5Ω
Input Referred, f = 5MHz, All Hostile
1.6
1.9
12
8
PARAMETER
AC PERFORMANCE (Cont.)
Rise-and-Fall Time
Settling Time to 0.02%
0.1%
Harmonic Distortion
2nd-Harmonic
3rd-Harmonic
Input Voltage Noise
Noninverting Input Current Noise
Inverting Input Current Noise
Differential Gain
Differential Phase
Crosstalk
DC PERFORMANCE(4)
Open-Loop Transimpedance Gain (ZOL)
Input Offset Voltage
Average Offset Voltage Drift
Noninverting Input Bias Current
Average Noninverting Input Bias Current Drift
Inverting Input Bias Current
Average Inverting Input Bias Current Drift
INPUT
Common-Mode Input Range(5)
Common-Mode Rejection (CMRR)
Noninverting Input Impedance
Inverting Input Resistance (RI )
OUTPUT
Voltage Output Swing
Current Output, Sourcing
Current Output, Sinking
Short-Circuit Current
Closed-Loop Output Impedance
DISABLE (Disabled LOW)
Power-Down Supply Current (+VS)
Disable Time
Enable Time
Off Isolation
Output Capacitance in Disable
Turn-On Glitch
Turn-Off Glitch
Enable Voltage
Disable Voltage
Control Pin Input Bias Current (DIS )
POWER SUPPLY
Specified Operating Voltage
Maximum Operating Voltage Range
Max Quiescent Current (3 Channels)
Min Quiescent Current (3 Channels)
Power-Supply Rejection Ratio (–PSRR)
MIN/MAX OVER TEMPERATURE
+25°C(1)
0°C to
70°C(2)
–40°C to
+85°C(2)
UNITS
MIN/ TEST
MAX LEVEL(3)
ns
ns
ns
ns
typ
typ
typ
typ
C
C
C
C
–70
–79
–74
–93
1.7
12
15
0.07
0.17
0.02
0.07
–80
–63
–70
–72
–87
2.5
14
17
–60
–67
–70
–82
2.9
15
18
–58
–65
–68
–78
3.1
15
19
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
pA/√Hz
%
%
deg
deg
dBc
max
max
max
max
max
max
max
typ
typ
typ
typ
typ
B
B
B
B
B
B
B
C
C
C
C
C
225
±0.8
125
±3
+15
+35
±5
±25
110
±3.7
±12
+43
–300
±30
±90
100
±4.3
±20
+45
–300
±40
±200
kΩ
mV
µV/°C
µA
nA/°C
µA
nA°/C
min
max
max
max
max
max
max
A
A
B
A
B
A
B
±3.4
±3.3
51
±3.2
50
Open Loop
±3.5
56
100 || 2
37
V
dB
kΩ || pF
Ω
min
min
typ
typ
A
A
C
C
No Load
RL = 100Ω
VO = 0
VO = 0
VO = 0
G = +2, f = 100kHz
±4.0
±3.9
+190
–190
±250
0.03
±3.8
±3.7
+160
–160
±3.7
±3.6
+140
–140
±3.6
±3.3
+100
–100
V
V
mA
mA
mA
Ω
min
min
min
min
typ
typ
A
A
A
A
C
C
VDIS = 0, All Channels
VIN = 1VDC
VIN = 1VDC
G = +2, 5MHz
–450
400
25
70
4
±50
±20
3.3
1.8
75
–900
–1050
–1200
3.5
1.7
130
3.6
1.6
150
3.7
1.5
160
µA
ns
ns
dB
pF
mV
mV
V
V
µA
max
typ
typ
typ
typ
typ
typ
min
max
max
A
C
C
C
C
C
C
A
A
A
±6
±6
16.5
14.1
50
±6
17.1
13.5
49
V
V
mA
mA
dB
typ
max
max
min
min
C
A
A
A
A
–40 to +85
°C
typ
C
100
100
°C/W
°C/W
typ
typ
C
C
VO = 0V, RL = 100Ω
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
G = +2, RL = 150Ω, VIN = 0
G = +2, RL = 150Ω, VIN = 0
VDIS = 0, Each Channel
±5
VS = ±5V
VS = ±5V
Input Referred
15.3
15.3
58
TEMPERATURE RANGE
Specification: D, DBQ
Thermal Resistance, θJA
DBQ SSOP-16
D
SO-16
52
15.9
14.7
52
NOTES: (1) Junction temperature = ambient for +25°C specifications. (2) Junction temperature = ambient at low temperature limit: Junction temperature = ambient +15°C
at high temperature limit for over temperature specifications. (3) Test Levels: (A) 100% tested at +25°C. Over-temperature limits by characterization and simulation.
(B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. VCM is the input common-mode
voltage. (5) Tested < 3dB below minimum specified CMRR at ± CMIR limits.
OPA3691
SBOS227A
www.ti.com
3
ELECTRICAL CHARACTERISTICS: VS = +5V
Boldface limits are tested at +25°C.
RF = 453Ω, RL = 100Ω to VS/2, and G = +2, (see Figure 2 for AC performance only), unless otherwise noted.
OPA3691ID, IDBQ
TYP
PARAMETER
AC PERFORMANCE (see Figure 2)
Small-Signal Bandwidth (VO = 0.5Vp-p)
Bandwidth for 0.1dB Gain Flatness
Peaking at a Gain of +1
Large-Signal Bandwidth
Slew Rate
Rise-and-Fall Time
Settling Time to 0.02%
0.1%
Harmonic Distortion
2nd-Harmonic
3rd-Harmonic
Input Voltage Noise
Noninverting Input Current Noise
Inverting Input Current Noise
DC PERFORMANCE(4)
Open-Loop Transimpedance Gain (ZOL)
Input Offset Voltage
Average Offset Voltage Drift
Noninverting Input Bias Current
Average Noninverting Input Bias Current Drift
Inverting Input Bias Current
Average Inverting Input Bias Current Drift
INPUT
Least Positive Input Voltage(5)
Most Positive Input Voltage(5)
Common-Mode Rejection (CMRR)
Noninverting Input Impedance
Inverting Input Resistance (RI)
OUTPUT
Most Positive Output Voltage
Least Positive Output Voltage
Current Output, Sourcing
Current Output, Sinking
Short-Circuit Current
Closed-Loop Output Impedance
DISABLE (Disabled LOW)
Power-Down Supply Current (+VS)
Off Isolation
Output Capacitance in Disable
Turn-On Glitch
Turn-Off Glitch
Enable Voltage
Disable Voltage
Control Pin Input Bias Current (DIS )
POWER SUPPLY
Specified Single-Supply Operating Voltage
Maximum Single-Supply Operating Voltage
Max Quiescent Current (3 Channels)
Min Quiescent Current (3 Channels)
Power-Supply Rejection Ratio (+PSRR)
TEMPERATURE RANGE
Specification: D, DBQ
Thermal Resistance, θJA
DBQ SSOP-16
D
SO-16
MIN/MAX OVER TEMPERATURE
+25°C(1)
0°C to
70°C(2)
–40°C to
+85°C(2)
168
160
140
40
1
30
2.5
25
3.0
600
575
530
–66
–73
–71
–77
1.7
12
15
–58
–65
–68
–72
2.5
14
17
–57
–63
–67
–70
2.9
15
18
200
±0.8
±3.5
100
+20
+40
±5
±20
Open Loop
1.5
3.5
54
100 || 2
40
No Load
RL = 100Ω, 2.5V
No Load
RL = 100Ω, 2.5V
VO = VS /2
VO = VS /2
VO = VS/2
G = +2, f = 100kHz
VDIS = 0, All Channels
G = +2, 5MHz
CONDITIONS
+25°C
G = +1, RF = 499Ω
G = +2, RF = 453Ω
G = +5, RF = 340Ω
G = +10, RF = 180Ω
G = +2, VO < 0.5Vp-p
RF = 649Ω, VO < 0.5Vp-p
G = +2, VO = 2Vp-p
G = +2, 2V Step
G = +2, VO = 0.5V Step
G = +2, VO = 2V Step
G = +2, VO = 2V Step
G = +2, VO = 2V Step
210
190
180
155
90
0.2
210
850
2.0
2.3
14
10
G = +2, f = 5MHz, VO = 2Vp-p
RL = 100Ω to VS /2
RL ≥ 500Ω to VS /2
RL = 100Ω to VS /2
RL ≥ 500Ω to VS /2
f > 1MHz
f > 1MHz
f > 1MHz
VO = VS/2, RL = 100Ω to VS/2
VCM = 2.5V
VCM = 2.5V
VCM = 2.5V
VCM = 2.5V
VCM = 2.5V
VCM = 2.5V
VCM = VS/2
G = +2, RL = 150Ω, VIN = VS /2
G = +2, RL = 150Ω, VIN = VS /2
VDIS = 0, Each Channel
MIN/ TEST
MAX LEVEL(3)
MHz
MHz
MHz
MHz
MHz
dB
MHz
V/µs
ns
ns
ns
ns
typ
min
typ
typ
min
max
typ
min
typ
typ
typ
typ
C
B
C
C
B
B
C
B
C
C
C
C
–56
–62
–65
–69
3.1
15
19
dBc
dBc
dBc
dBc
nV/ √Hz
pA/ √Hz
pA/ √Hz
max
max
max
max
max
max
max
B
B
B
B
B
B
B
90
±4.1
±12
+46
–250
±25
±112
80
±4.8
±20
+56
–250
±35
±250
kΩ
mV
µV/°C
µA
nA/°C
µA
nA /°C
min
max
max
max
max
max
max
A
A
B
A
B
A
B
1.6
3.4
50
1.7
3.3
49
1.8
3.2
48
V
V
dB
kΩ || pF
Ω
max
min
min
typ
typ
A
A
A
C
C
4
3.9
1
1.1
+160
–160
250
0.03
3.8
3.7
1.2
1.3
+120
–120
3.7
3.6
1.3
1.4
+100
–100
3.5
3.4
1.5
1.6
+80
–80
V
V
V
V
mA
mA
mA
Ω
min
min
max
max
min
min
typ
typ
A
A
A
A
A
A
C
C
–450
65
4
±50
±20
3.3
1.8
75
–900
–1050
–1200
3.5
1.7
130
3.6
1.6
150
3.7
1.5
160
µA
dB
pF
mV
mV
V
V
µA
max
typ
typ
typ
typ
min
max
typ
A
C
C
C
C
A
A
C
12
14.4
12.3
12
15.0
12
12
15.6
11.4
V
V
mA
mA
dB
typ
max
max
min
typ
C
A
A
A
C
–40 to +85
°C
typ
C
100
100
°C/W
°C/W
typ
typ
C
C
5
VS = +5V
VS = +5V
Input Referred
UNITS
13.5
13.5
55
NOTES: (1) Junction temperature = ambient for +25°C specifications. (2) Junction temperature = ambient at low temperature limit: Junction temperature = ambient +15°C
at high temperature limit for over temperature specifications. (3) Test Levels: (A) 100% tested at +25°C. Over-temperature limits by characterization and simulation.
(B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. VCM is the input common-mode
voltage. (5) Tested < 3dB below minimum specified CMRR at ± CMIR limits.
4
OPA3691
www.ti.com
SBOS227A
TYPICAL CHARACTERISTICS: VS = ±5V
TA = +25°C, G = +2, and RL = 100Ω, (see Figure 1 for AC performance only), unless otherwise noted.
SMALL-SIGNAL FREQUENCY RESPONSE
1
0
–1
–3
G = +5, RF = 261Ω
–5
G = +10, RF = 180Ω
–6
2Vp-p
5.5
5.0
4.5
4.0
3.5
4Vp-p
3.0
–7
7Vp-p
2.5
VO = 0.5Vp-p
–8
2.0
0
125MHz
250MHz
0
125MHz
Frequency (25MHz/div)
SMALL-SIGNAL PULSE RESPONSE
LARGE-SIGNAL PULSE RESPONSE
+4
G = +2
VO = 0.5Vp-p
+300
G = +2
VO = 5Vp-p
+3
Output Voltage (1V/div)
Output Voltage (100mV/div)
250MHz
Frequency (25MHz/div)
+400
+200
+100
0
–100
–200
+2
+1
0
–1
–2
–3
–300
–4
–400
Time (5ns/div)
Time (5ns/div)
DISABLED FEEDTHROUGH vs FREQUENCY
COMPOSITE VIDEO dG/dP
0.2
–45
+5
Video
In
0.18
No Pull-Down
With 1.3kΩ Pull-Down
Video
Loads
1/3
OPA3691
0.16
–55
Feedthrough (5dB/div)
dG
402Ω
–5
Optional 1.3kΩ
Pull-Down
0.12
dG
0.1
0.08
0.06
VDIS = 0
–50
402Ω
0.14
dG/dP (%/°)
1Vp-p
6.0
–2
–4
G = +2, RL = 100Ω
6.5
G = +2,
RF = 402Ω
Gain (0.5dB/div)
Normalized Gain (1dB/div)
LARGE-SIGNAL FREQUENCY RESPONSE
7.0
G = +1, RF = 453Ω
dP
0.04
–60
–65
–70
–75
–80
Reverse
–85
–90
dP
0.02
Forward
–95
–100
0
1
2
3
0.3
4
10
100
Frequency (MHz)
Number of 150Ω Loads
OPA3691
SBOS227A
1
www.ti.com
5
TYPICAL CHARACTERISTICS: VS = ±5V
(Cont.)
TA = +25°C, G = +2, and RL = 100Ω, (see Figure 1 for AC performance only), unless otherwise noted.
HARMONIC DISTORTION vs LOAD RESISTANCE
HARMONIC DISTORTION vs SUPPLY VOLTAGE
–60
–60
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
VO = 2Vp-p
RL = 100Ω
f = 5MHz
VO = 2Vp-p
f = 5MHz
–65
–70
2nd-Harmonic
–75
–80
–85
3rd-Harmonic
–90
–65
2nd-Harmonic
–70
–75
3rd-Harmonic
–80
–95
–100
–85
100
1000
2.5
3
Load Resistance (Ω)
HARMONIC DISTORTION vs FREQUENCY
5
5.5
6
HARMONIC DISTORTION vs OUTPUT VOLTAGE
–60
RL = 100Ω
f = 5MHz
VO = 2Vp-p
RL = 100Ω
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
4.5
–65
dBc = dB Below Carrier
2nd-Harmonic
–70
3rd-Harmonic
–80
–90
–100
2nd-Harmonic
–70
–75
3rd-Harmonic
–80
–85
0.1
1
10
20
0.1
1
Frequency (MHz)
5
Output Voltage Swing (Vp-p)
HARMONIC DISTORTION vs INVERTING GAIN
HARMONIC DISTORTION vs NONINVERTING GAIN
–50
–50
VO = 2Vp-p
RL = 100Ω
f = 5MHz
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
4
Supply Voltage (V)
–50
–60
2nd-Harmonic
–70
3rd-Harmonic
–80
VO = 2Vp-p
RL = 100Ω
f = 5MHz
RF = 402Ω
–60
2nd-Harmonic
–70
3rd-Harmonic
–80
–90
–90
1
1
10
10
Inverting Gain (V/V)
Gain (V/V)
6
3.5
OPA3691
www.ti.com
SBOS227A
TYPICAL CHARACTERISTICS: VS = ±5V
(Cont.)
TA = +25°C, G = +2, and RL = 100Ω, (see Figure 1 for AC performance only), unless otherwise noted.
2-TONE, 3RD-ORDER
INTERMODULATION SPURIOUS
INPUT VOLTAGE AND CURRENT NOISE DENSITY
–30
3rd-Order Spurious Level (dBc)
Inverting Input Current Noise (15pA/√Hz)
10
Noninverting Input Current Noise (12pA/√Hz)
Voltage Noise (1.7nV/√Hz)
dBc = dB below carriers
20MHz
–50
10MHz
–60
–70
–80
Load Power at Matched 50Ω Load
–90
1
100
1k
10k
100k
1M
–8
10M
–6
RECOMMENDED RS vs CAPACITIVE LOAD
Normalized Gain to Capacitive Load (dB)
60
RS (Ω)
50
40
30
20
10
0
0
2
4
6
8
10
100
9
6
CL = 10pF
3
CL = 22pF
0
CL = 47pF
VIN
–3
1/3
OPA3691
402Ω
RS
VO
CL
1kΩ
–6
402Ω
CL = 100pF
1kΩ is optional.
–9
1k
0
125MHz
Capacitive Load (pF)
250MHz
Frequency (25MHz/div)
OPEN-LOOP TRANSIMPEDANCE GAIN/PHASE
CMRR AND PSRR vs FREQUENCY
65
120
+PSRR
Transimpedance Gain (20dBΩ/div)
Common-Mode Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
–2
FREQUENCY RESPONSE vs CAPACITIVE LOAD
70
10
–4
Single-Tone Load Power (dBm)
Frequency (Hz)
1
50MHz
–40
60
55
CMRR
50
45
–PSRR
40
35
30
25
0
100
–40
| ZOL|
80
–80
∠ ZOL
60
–120
40
–160
20
–200
0
20
1k
10k
100k
1M
10M
100M
Frequency (Hz)
100k
1M
10M
100M
1G
Frequency (Hz)
OPA3691
SBOS227A
–240
10k
www.ti.com
7
Transimpedance Phase (40°/div)
Current Noise (pA/√Hz)
Voltage Noise (nV/√Hz)
100
TYPICAL CHARACTERISTICS: VS = ±5V
(Cont.)
TA = +25°C, G = +2, and RL = 100Ω, (see Figure 1 for AC performance only), unless otherwise noted.
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
250
18
5
Sourcing Output Current
Sinking Output Current
150
14
100
Quiescent Supply Current
(all channels)
12
50
3
1
0
25Ω
Load Line
–1
–2
50Ω Load Line
–3
100Ω Load Line
1W Internal
Power Limit
Single Channel
–4
0
10
–50
–25
0
25
50
75
100
Output Current Limit
1W Internal
Power Limit
Single Channel
2
VO (V)
Supply Current (2mA/div)
200
16
Output Current (50mA/div)
4
Output Current Limit
–5
125
–300 –250 –200 –150 –100 –50
0
+50 +100 +150 +200 +250 +300
Ambient Temperature (°C)
IO (mA)
TYPICAL DC DRIFT OVER TEMPERATURE
CLOSED-LOOP OUTPUT IMPEDANCE
vs FREQUENCY
2
40
1.5
30
10
20
0.5
10
0
0
Inverting Input
Bias Current (IB–)
–0.5
–10
–1
–20
Input Offset
Voltage (VOS)
–1.5
–2
Output Impedance (Ω)
Noninverting Input Bias Current (IB+)
1
Input Bias Currents (µA)
Input Offset Voltage (mV)
+5
–25
0
25
50
75
100
1/3
OPA3691
ZO
1
–5
402Ω
402Ω
0.1
–30
0.01
–40
–50
50Ω
125
10k
100k
1M
Ambient Temperature (°C)
4.0
0
1.6
Output Voltage
1.2
–60
–65
Crosstalk (dB)
2.0
–55
VDIS (2V/div)
Output Voltage (400mV/div)
6.0
2.0
0.8
0.4
0
100M
ALL HOSTILE CROSSTALK
LARGE-SIGNAL DISABLE/ENABLE RESPONSE
VDIS
10M
Frequency (Hz)
–70
–75
–80
–85
–90
VIN = +1V
–95
–100
0.1
Time (200ns/div)
1
10
100
Frequency (MHz)
8
OPA3691
www.ti.com
SBOS227A
TYPICAL CHARACTERISTICS: VS = +5V
TA = +25°C, G = +2, and RL = 100Ω to +2.5V, (see Figure 2 for AC performance only), unless otherwise noted.
LARGE-SIGNAL FREQUENCY RESPONSE
SMALL-SIGNAL FREQUENCY RESPONSE
1
7.0
G = +1,
RF = 499Ω
6.0
–1
G = +2,
RF = 453Ω
–2
G = +5,
RF = 340Ω
–3
–4
–5
–6
–7
–8
0
5.5
5.0
VO = 2Vp-p
4.5
4.0
3.5
3.0
G = +10,
RF = 180Ω
VO = 0.5Vp-p
VO = 0.5Vp-p
6.5
Gain (0.5dB/div)
Normalized Gain (1dB/div)
0
2.0
125MHz
0
250MHz
125MHz
SMALL-SIGNAL PULSE RESPONSE
LARGE-SIGNAL PULSE RESPONSE
4.1
2.9
2.7
2.6
2.5
2.4
2.3
G = +2
VO = 2Vp-p
3.7
Output Voltage (400mV/div)
G = +2
VO = 0.5Vp-p
2.8
2.2
3.3
2.9
2.5
2.1
1.7
1.3
2.1
0.9
Time (5ns/div)
Time (5ns/div)
RECOMMENDED RS vs CAPACITIVE LOAD
FREQUENCY RESPONSE vs CAPACITIVE LOAD
Normalized Gain to Capacitive Load (dB)
60
50
40
RS (Ω)
250MHz
Frequency (25MHz/div)
Frequency (25MHz/div)
Output Voltage (100mV/div)
VO = 1Vp-p
G = +2
RL = 100Ω to 2.5V
2.5
30
20
10
0
1
10
100
6
CL = 10pF
3
CL = 47pF
0
CL = 22pF
+5V
–3
VI
0.1µF
57.6Ω
806Ω
806Ω
VO
1/3
OPA3691
CL = 100pF
RS
–6
453Ω
CL
1kΩ
453Ω
0.1µF
1kΩ is optional.
–9
0
Capacitive Load (pF)
125MHz
250MHz
Frequency (25MHz/div)
OPA3691
SBOS227A
9
www.ti.com
9
TYPICAL CHARACTERISTICS: VS = +5V
(Cont.)
TA = +25°C, G = +2, and RL = 100Ω to +2.5V, (see Figure 2 for AC performance only), unless otherwise noted.
HARMONIC DISTORTION vs FREQUENCY
HARMONIC DISTORTION vs LOAD RESISTANCE
–50
–60
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
VO = 2Vp-p
f = 5MHz
–65
2nd-Harmonic
–70
3rd-Harmonic
–75
100
2nd-Harmonic
–70
3rd-Harmonic
–80
0.1
1000
1
Frequency (MHz)
HARMONIC DISTORTION vs OUTPUT VOLTAGE
2-TONE, 3RD-ORDER
INTERMODULATION SPURIOUS
–30
3rd-Order Spurious Level (dBc)
RL = 100Ω to 2.5V
f = 5MHz
2nd-Harmonic
–65
–70
3rd-Harmonic
–75
–80
1
dBc = dB below carriers
50MHz
–50
–60
20MHz
–70
10MHz
–80
–90
Load Power at Matched 50Ω Load
–14
3
20
–40
–100
0.1
10
Resistance (Ω)
–60
Harmonic Distortion (dBc)
–60
–90
–80
–12
–10
–8
–6
–4
–2
0
2
Single-Tone Load Power (dBm)
Output Voltage Swing (Vp-p)
10
VO = 2Vp-p
RL = 100Ω to 2.5V
OPA3691
www.ti.com
SBOS227A
APPLICATIONS INFORMATION
WIDEBAND CURRENT-FEEDBACK OPERATION
The OPA3691 gives the exceptional AC performance of a
wideband current-feedback op amp with a highly linear, highpower output stage. Requiring only 5.1mA/ch quiescent
current, the OPA3691 will swing to within 1V of either supply
rail and deliver in excess of 160mA at room temperature.
This low output headroom requirement, along with supply
voltage independent biasing, gives remarkable single (+5V)
supply operation. The OPA3691 will deliver greater than
200MHz bandwidth driving a 2Vp-p output into 100Ω on a
single +5V supply. Previous boosted output stage amplifiers
have typically suffered from very poor crossover distortion as
the output current goes through zero. The OPA3691 achieves
a comparable power gain with much better linearity. The
primary advantage of a current-feedback op amp over a
voltage-feedback op amp is that AC performance (bandwidth
and distortion) is relatively independent of signal gain.
Figure 1 shows the DC-coupled, gain of +2, dual powersupply circuit configuration used as the basis of the ±5V
Electrical Characteristics and Typical Characteristics. For
test purposes, the input impedance is set to 50Ω with a
resistor to ground and the output impedance is set to 50Ω
with a series output resistor. Voltage swings reported in the
electrical characteristics are taken directly at the input and
output pins while load powers (dBm) are defined at a matched
50Ω load. For the circuit of Figure 1, the total effective load
will be 100Ω || 998Ω. The disable control line (DIS) is
typically left open to ensure normal amplifier operation. One
optional component is included in Figure 1. In addition to the
usual power-supply decoupling capacitors to ground, a 0.01µF
0.1µF
+5V
+VS
capacitor is included between the two power-supply pins. In
practical PC board layouts, this optionally added capacitor
will typically improve the 2nd-harmonic distortion performance by 3dB to 6dB.
Figure 2 shows the AC-coupled, gain of +2, single-supply
circuit configuration used as the basis of the +5V Specifications and Typical Characteristics. Though not a “rail-to-rail”
design, the OPA3691 requires minimal input and output
voltage headroom compared to other very wideband currentfeedback op amps. It will deliver a 3Vp-p output swing on a
single +5V supply with greater than 150MHz bandwidth. The
key requirement of broadband single-supply operation is to
maintain input and output signal swings within the usable
voltage ranges at both the input and the output. The circuit of
Figure 2 establishes an input midpoint bias using a simple
resistive divider from the +5V supply (two 806Ω resistors).
The input signal is then AC-coupled into this midpoint voltage
bias. The input voltage can swing to within 1.5V of either
supply pin, giving a 2Vp-p input signal range centered between the supply pins. The input impedance matching resistor (57.6Ω) used for testing is adjusted to give a 50Ω input
match when the parallel combination of the biasing divider
network is included. The gain resistor (RG) is AC-coupled,
giving the circuit a DC gain of +1, which puts the input DC bias
voltage (2.5V) on the output as well. Again, on a single +5V
supply, the output voltage can swing to within 1V of either
supply pin while delivering more than 120mA output current.
A demanding 100Ω load to a midpoint bias is used in this
characterization circuit. The new output stage used in the
OPA3691 can deliver large bipolar output currents into this
midpoint load with minimal crossover distortion, as shown by
the +5V supply, 3rd-harmonic distortion plots.
+5V
+VS
6.8µF
+
50Ω
VO
1/3
OPA3691
0.01µF
6.8µF
806Ω
DIS
VI
+
0.1µF
50Ω Source
50Ω
50Ω Load
0.1µF
VI
57.6Ω
DIS
806Ω
1/3
OPA3691
VO
100Ω
VS/2
RF
499Ω
RF
499Ω
RG
499Ω
RG
499Ω
+
6.8µF
0.1µF
0.1µF
–VS
–5V
FIGURE 1. DC-Coupled, G = +2, Bipolar Supply, Specification and Test Circuit.
FIGURE 2. AC-Coupled, G = +2, Single-Supply, Specification and Test Circuit.
OPA3691
SBOS227A
www.ti.com
11
TRIPLE ADC BUFFER CHANNEL
WIDEBAND RGB MULTIPLEXER
The OPAx691 family is ideally suited to single-supply,
wideband ADC driving. A current-feedback op amp is ideal
where high gains with high bandwidths are required. The
wide 3Vp-p output swing with over 150MHz full-power bandwidth on a single +5V supply is well suited to the
2Vp-p input range commonly required from modern CMOS
pipelined ADCs. Three channels of very high-speed digitizer
channels are shown in Figure 3 using the OPA3691 driving
three ADS831s (8-bit, 80MSPS CMOS converters). Each
input is AC-coupled into a 50Ω gain resistor that also will act
as a 50Ω impedance match at high frequencies. The amplifier’s
inputs and outputs are centered on the ADC common-mode
input voltage by tying each converter’s VCM to the noninverting
inputs of the amplifier. This VCM acts as the swing midpoint
for the input to the converter. Since the ADS831 can operate
with differential inputs, driving into the IN input will give a net
noninverting signal channel even with the amplifiers operating at an inverting gain of –6. The other input to the ADS831
is tied to this VCM as well to give an input signal midpoint
equal to VCM. The 300Ω feedback resistor will be the output
load in this configuration. Harmonic distortion for the OPA3691
will not degrade the converter’s SFDR performance in this
application.
The OPA3691 is ideally suited to implementing a simple,
very wideband, 2x1 RGB multiplexer. This simple “wired-OR
video multiplexer” can be easily implemented using the
circuit shown in Figure 4.
This circuit uses two OPA3691s where each package accepts
the three RGB component video signals from one of two
possible sources. Each noninverting input is terminated in 75Ω
+5V
VDIS
+5V
Power-supply
decoupling not shown.
U1
R1
75Ω
82.5Ω
1/3
OPA3691
VOUT Red
75Ω Line
340Ω
402Ω
G1
75Ω
82.5Ω
1/3
OPA3691
VOUT Green
75Ω Line
340Ω
Power-supply
decoupling not shown.
0.1µF
402Ω
+5V
300Ω
1/3
OPA3691
IN
VCM
22Ω
IN
47pF
B1
75Ω
82.5Ω
1/3
OPA3691
VOUT Blue
75Ω Line
ADS831
8-Bit
80MSPS
340Ω
402Ω
–5V
0.1µF 50Ω
+5V
300Ω
V1
U2
300Ω
0.1µF
1/3
OPA3691
R2
IN
VCM
22Ω
IN
47pF
75Ω
ADS831
8-Bit
80MSPS
1/3
OPA3691
340Ω
402Ω
G2
0.1µF 50Ω
300Ω
75Ω
V1
300Ω
0.1µF
1/3
OPA3691
22Ω
IN
47pF
0.1µF 50Ω
IN
VCM
ADS831
8-Bit
80MSPS
1/3
OPA3691
340Ω
300Ω
82.5Ω
402Ω
B2
75Ω
82.5Ω
1/3
OPA3691
340Ω
82.5Ω
402Ω
V1
–5V
FIGURE 3. Triple-Channel ADC Driver.
12
FIGURE 4. Wideband 2x1 RGB Multiplexer.
OPA3691
www.ti.com
SBOS227A
sampling rate, and a 5.5MHz cutoff frequency.
The first op amp buffers the video DAC output and the first
filter section from each other. This first filter section provides
group delay equalization. The second and third filter sections
provide a 6th-order low-pass filter response that also compensates for the DAC’s sin(x)/x response. The filter response
can be seen in Figure 6.
20
f–3dB
0
–20
Gain (dB)
to match the typical video source impedance. The disable
control is used to switch between channels by feeding a logic
control line directly to all three VDIS inputs on one package,
and its complement to the three VDIS inputs on the other.
Since the disable feature is intentionally make-before-break
(to ensure that the output does not float in transition), each of
the two possible outputs for the three RGB lines are combined
through a limiting resistor. This 82.5Ω resistor limits the current
between the two outputs during switching. The feedback and
output network connected on the output slightly attenuates the
signal going out onto the 75Ω cable. The gain and output
matching resistors (82.5Ω) have been slightly increased to get
a signal gain of +1 to the matched load and provide a 75Ω
output impedance to the cable. The section on Disable Operation shows the turn-on and turn-off switching glitches, using a
grounded input for the single channel, is typically less than
±50mV. Where two outputs are switched (see Figure 4), the
output line is always under the control of one amplifier or the
other due to the “make-before-break” disable timing. In this
case, the switching glitches for 0V inputs drops to < 20mV.
Large output swing can cause the inactive inverting inputs to
turn on degrading distortion. Keep the voltages across the
inactive channel inputs < ±1.2Vp-p.
–40
–60
–80
–100
0
1
10
100
Frequency (MHz)
FIGURE 6. DAC Reconstruction Filter Response.
VIDEO DAC RECONSTRUCTION FILTER
Wideband current-feedback op amps make ideal elements
for implementing high-speed active filters where the amplifier
is used as fixed gain block inside a passive RC circuit
network. Their relatively constant bandwidth versus gain
provides low interaction between the actual filter poles and
the required gain for the amplifier. Figure 5 shows an example of a video Digital-to-Analog Converter (DAC) reconstruction filter.
The delay-equalized filter in Figure 5 compensates for the
DAC’s sin(x)/x response, and minimizes aliasing artifacts. It
is designed for single +5V operation, with a 13.5MSPS DAC
HIGH-POWER XDSL LINE DRIVER
Emerging broadband access technologies are making significant demands on the output stage drivers. Some of the
higher frequency versions, particularly in VDSL, require passive bandpass filters to spectrally isolate the upstream from
downstream frequency bands. See Figure 7 for one possible
implementation of this using single-ended filters and giving
differential push/pull drive into a transformer. The DAC output from the Analog Front End (AFE) typically requires
isolation from the complex filter impedance. The first stage
provides a tunable gain (using RG) with a fixed termination for
100pF
Video
100µF 402Ω
In
100pF
+5V
402Ω
97.6Ω
237Ω
220pF
+5V
402Ω
+5V
56pF
1/3
OPA3691
82.5Ω
243Ω
220pF
120pF
1/3
OPA3691
412Ω
56pF
1/3
OPA3691
75.5Ω
VO
402Ω
402Ω
402Ω
953Ω
+5V
100µF
953Ω
FIGURE 5. Filter Schematic.
OPA3691
SBOS227A
www.ti.com
13
the DAC, RT. It is very useful from a distortion standpoint to
scale the characteristic impedance up for the filter. This
reduces the loading at the 1st-stage amplifier output, typically improving 3rd-order terms directly, as well as some
improvement in 2nd-order terms. Figure 7 assumes a 100Ω
characteristic impedance for the filter. The filter is driven from
a 100Ω source resistor into a 100Ω load that is formed by the
input gain resistor of the inverting amplifier channel. The
other noninverting input is isolated by a series 50Ω resistor—
principally to isolate that input from the out-of-band source
impedance of the filter. In this example, the output stage is
set up for a differential gain of 8. The total gain from the
output of the bandpass filter to the line will be 4 • n, where n
is the turns ratio used in the transformer. Very broad bandwidths at high power levels are possible using the OPA3691
in the circuit of Figure 7. Recognize also, that the output is in
fact bandlimited by the filter. Very high dynamic range is
possible inside the filter bandwidth due to the significant
performance margin provided by the OPA3691.
WIDEBAND DIFFERENTIAL/SINGLE-ENDED AMPLIFIER
The differential amplifier (three amplifier instrumentation topology) on the front page of this data sheet shows a common
application applied to this triple current-feedback op amp.
The two input stage amplifiers are configured for a relatively
high differential gain of 10. Lowering the feedback resistor
values in this input stage provides 120MHz bandwidth, even
at this high gain setting. The signal is applied to the high
impedance, noninverting inputs at the input stage. The differential gain is set by (1 + 2RF/RG) = 10 using the values shown
on the front page. The third amplifier performs the differential-to-single-ended conversion in a standard single op amp
differential stage. This differential stage, built using the 3rd
wideband current-feedback op amp, in the OPA3691 will give
lower CMRR at DC than using a voltage-feedback part, but
higher CMRR at higher frequencies. Measured performance,
with no resistor value tuning, gave approximately 75dB at DC
and > 55dB CMRR (input referred) through 10MHz. To
maintain good distortion performance for the input stage
amplifiers, the loading at each output has been matched
while achieving the gain of 1 and differential characteristic of
the output stage. To improve DC CMRR, tune the resistor to
ground at the noninverting input of the output stage amplifier.
WIDEBAND PROGRAMMABLE GAIN
By tying all three inputs together from a single source, and all
three outputs together to drive a common load, a very
wideband, programmable gain function may be implemented.
See Figure 8 for an example of this application where the
three channels have been set up for gains of 1, 2, and 4 to
the load. The feedback resistor value has been optimized for
maximum flat bandwidth in each channel. This will give an
almost constant > 200MHz bandwidth at any of the three gain
settings. The desired gain is selected by using the disable
control lines to choose one of the three possible amplifiers as
the active channel. Isolation resistors have been optimized to
match the 50Ω load, and will limit the output current if more
than one output is on during gain-select transition. The
isolation resistors have been adjusted for each amplifier such
that the load impedance sees a matching 50Ω independant
from the operating amplifier. This, in turn, requires gain
matching so that the gains are 1, 2, and 4 to the load.
The 20Ω series resistors on each noninverting input serves
to isolate the input parasitic capacitance from the source.
Also, limit the voltage swing across the inputs of the inactive
channels to < ±1.2Vp-p.
50Ω
1/3
OPA3691
+5V
Supply decoupling
not shown.
DSL
AFE
RT
1/3
OPA3691
400Ω
400Ω
RS
1:n
100Ω
133Ω
Bandpass
Filter
100Ω
RS
400Ω
1/3
OPA3691
–5V
RG
FIGURE 7. Single-to-Differential xDSL Line Driver.
14
OPA3691
www.ti.com
SBOS227A
+5V
74HC238
Power-supply
decoupling not shown.
+5V
Y0
D1
Y1
D2
20Ω
Y2
1/3
OPA3691
191Ω
73.2Ω
365Ω
20Ω
VIN
1/3
OPA3691
50Ω
61.2Ω
68.1Ω
50Ω Load
274Ω
20Ω
1/3
OPA3691
20Ω
63.4Ω
182Ω
–5V
FIGURE 8. Wideband Programmable Gain.
DESIGN-IN TOOLS
SPICE MODELS
APPLICATIONS SUPPORT
The Texas Instruments Applications Department is available
for design assistance at phone number 1-800-548-6132
(U.S.A./Canada only). The TI web site (www.ti.com) has the
latest data sheets and other design aids.
DEMONSTRATION BOARDS
A PC board will be available to assist in the initial evaluation
of circuit performance of the OPA3691. This is available as
an unpopulated PCB with descriptive documentation. See
the demonstration board literature for more information. The
summary information for this board is shown below:
PRODUCT
OPA3691IDBQ
OPA3691ID
PACKAGE
DEMONSTRATION
BOARD
LITERATURE
REQUEST
NUMBER
SSOP-16
SO-16
DEM-OPA368xE
DEM-OPA368xU
SBOU006
SBOU007
Computer simulation of circuit performance using SPICE is
often useful when analyzing the performance of analog
circuits and systems. This is particularly true for high-speed
active devices, like the OPA3691, where parasitic capacitance and inductance can have a major effect on frequency
response.
SPICE models will be available through the TI web page or
on a disk (call our Applications Department). These models
do a good job of predicting small-signal AC and transient
performance under a wide variety of operating conditions.
They do not do as well in predicting the harmonic distortion
or differential gain and phase characteristics. These models
do not distinguish between the AC performance of different
package types.
OPERATING SUGGESTIONS
SETTING RESISTOR VALUES TO
OPTIMIZE BANDWIDTH
Check the TI web site (www.ti.com) for availability of these
boards.
A current-feedback op amp like the OPA3691 can hold an
almost constant bandwidth over signal gain settings with the
proper adjustment of the external resistor values. This is
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15
shown in the Typical Characteristics; the small-signal bandwidth decreases only slightly with increasing gain. These
curves also show that the feedback resistor has been changed
for each gain setting. The resistor “values” on the inverting
side of the circuit for a current-feedback op amp can be
treated as frequency response compensation elements while
their “ratios” set the signal gain. Figure 9 shows the smallsignal frequency response analysis circuit for the OPA3691.
This is written in a loop-gain analysis format where the errors
arising from a non-infinite open-loop gain are shown in the
denominator. If Z(S) were infinite over all frequencies, the
denominator of Equation 1 would reduce to 1 and the ideal
desired signal gain shown in the numerator would be achieved.
The fraction in the denominator of Equation 1 determines the
frequency response. Equation 2 shows this as the loop-gain
equation:
Z(S)
RF + RI NG
VO
Z(S) iERR
RF
RG
FIGURE 9. Current-Feedback Transfer Function Analysis Circuit.
The key elements of this current-feedback op amp model are:
α → Buffer gain from the noninverting input to the inverting input
RI → Buffer output impedance
iERR → Feedback error current signal
Z(s) → Frequency dependent open-loop transimpedance
gain from iERR to VO
The buffer gain is typically very close to 1.00 and is normally
neglected from signal gain considerations. It will, however, set
the CMRR for a single op amp differential amplifier configuration. For a buffer gain α < 1.0, the CMRR = –20 • log(1 – α)dB.
RI, the buffer output impedance, is a critical portion of the
bandwidth control equation. The OPA3691 is typically 37Ω.
A current-feedback op amp senses an error current in the
inverting node (as opposed to a differential input error voltage for a voltage-feedback op amp) and passes this on to the
output through an internal frequency dependent transimpedance gain. The Typical Characteristics show this open-loop
transimpedance response. This is analogous to the openloop voltage gain curve for a voltage-feedback op amp.
Developing the transfer function for the circuit of Figure 9
gives Equation 1:

R 
α1 + F 
R

VO
αNG
G
=
=
VI

RF  1 + RF + RI NG
RF + RI 1 +
Z(S)
RG 

Z(S)


R 
NG ≡ 1 + F  
R


G  
16
The OPA3691 is internally compensated to give a maximally
flat frequency response for RF = 402Ω at NG = 2 on ±5V
supplies. Evaluating the denominator of Equation 2 (which is
the feedback transimpedance) gives an optimal target of 476Ω.
As the signal gain changes, the contribution of the NG • RI term
in the feedback transimpedance will change, but the total can
be held constant by adjusting RF. Equation 3 gives an approximate equation for optimum RF over signal gain:
RF = 476Ω − NG RI
(3)
As the desired signal gain increases, this equation will
eventually predict a negative RF. A somewhat subjective limit
to this adjustment can also be set by holding RG to a
minimum value of 20Ω. Lower values will load both the buffer
stage at the input and the output stage if RF gets too low—
actually decreasing the bandwidth. Figure 10 shows the
recommended RF versus NG for both ±5V and a single +5V
operation. The values shown in Figure 10 give a good
starting point for design where bandwidth optimization is
desired.
600
500
Feedback Resistor (Ω)
α
iERR
(2)
If 20 • log(RF + NG • RI) were drawn on top of the open-loop
transimpedance plot, the difference between the two would
be the loop gain at a given frequency. Eventually, Z(S) rolls off
to equal the denominator of Equation 2 at which point the
loop gain has reduced to 1 (and the curves have intersected).
This point of equality is where the amplifier’s closed-loop
frequency response, given by Equation 1, will start to roll off
and is exactly analogous to the frequency at which the noise
gain equals the open-loop voltage gain for a voltage-feedback op amp. The difference here is that the total impedance
in the denominator of Equation 2 may be controlled somewhat separately from the desired signal gain (or NG).
VI
RI
= Loop Gain
400
+5V
300
±5V
200
100
0
(1)
0
5
10
15
20
Noise Gain
FIGURE 10. Recommended Feedback Resistor vs Noise Gain.
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The total impedance going into the inverting input may be
used to adjust the closed-loop signal bandwidth. Inserting a
series resistor between the inverting input and the summing
junction will increase the feedback impedance (denominator
of Equation 2), decreasing the bandwidth. The internal buffer
output impedance for the OPA3691 is slightly influenced by
the source impedance looking out of the noninverting input
terminal. High source resistors will have the effect of increasing RI, decreasing the bandwidth. For those single-supply
applications which develop a midpoint bias at the noninverting
input through high valued resistors, the decoupling capacitor
is essential for power-supply ripple rejection, noninverting
input noise current shunting, and to minimize the highfrequency value for RI in Figure 9.
INVERTING AMPLIFIER OPERATION
Since the OPA3691 is a general-purpose, wideband currentfeedback op amp, most of the familiar op amp application
circuits are available to the designer. Those triple op amp
applications that require considerable flexibility in the feedback
element (e.g., integrators, transimpedance, and some filters)
should consider the unity-gain stable voltage-feedback
OPA3690, since the feedback resistor is the compensation
element for a current-feedback op amp. Wideband inverting
operation (especially summing) is particularly suited to the
OPA3691. Figure 11 shows a typical inverting configuration
where the I/O impedances and signal gain from Figure 1 are
retained in an inverting circuit configuration.
+5V
Note that the noninverting input in this bipolar supply inverting application is connected directly to ground. It is often
suggested that an additional resistor be connected to ground
on the noninverting input to achieve bias current error cancellation at the output. The input bias currents for a current
feedback op amp are not generally matched in either magnitude or polarity. Connecting a resistor to ground on the
noninverting input of the OPA3691 in the circuit of Figure 11
will actually provide additional gain for that input’s bias and
noise currents, but will not decrease the output DC error
since the input bias currents are not matched.
1/3
OPA3691
VO
The OPA3691 provides output voltage and current capabilities that are unsurpassed in a low-cost dual monolithic op
amp. Under no-load conditions at 25°C, the output voltage
typically swings closer than 1V to either supply rail; the tested
swing limit is within 1.2V of either rail. Into a 15Ω load (the
minimum tested load), it is tested to deliver more than
±160mA.
50Ω Load
DIS
50Ω
RF
374Ω
RG
187Ω
The second major consideration, touched on in the previous
paragraph, is that the signal source impedance becomes
part of the noise gain equation and will have slight effect on
the bandwidth through Equation 1. The values shown in
Figure 11 have accounted for this by slightly decreasing RF
(from Figure 1) to re-optimize the bandwidth for the noise
gain of Figure 11 (NG = 2.73) In the example of Figure 11,
the RM value combines in parallel with the external 50Ω
source impedance, yielding an effective driving impedance of
50Ω || 68.1Ω = 28.8Ω. This impedance is added in series with
RG for calculating the noise gain—which gives NG = 2.73.
This value, along with the RF of Figure 10 and the inverting
input impedance of 37Ω, are inserted into Equation 3 to get
a feedback transimpedance nearly equal to the 476Ω optimum value.
OUTPUT CURRENT AND VOLTAGE
Power-supply
decoupling not shown.
50Ω
Source
impedance since its value, along with the desired gain, will
determine a RF which may be non-optimal from a frequency
response standpoint. The total input impedance for the
source becomes the parallel combination of RG and RM.
VI
RM
68.1Ω
–5V
FIGURE 11. Inverting Gain of –2 with Impedance Matching.
In the inverting configuration, two key design considerations
must be noted. The first is that the gain resistor (RG)
becomes part of the signal channel input impedance. If input
impedance matching is desired (which is beneficial whenever the signal is coupled through a cable, twisted-pair, long
PC board trace or other transmission line conductor), it is
normally necessary to add an additional matching resistor to
ground. RG by itself is normally not set to the required input
The specifications described above, though familiar in the
industry, consider voltage and current limits separately. In
many applications, it is the voltage • current, or V-I product,
which is more relevant to circuit operation. Refer to the
“Output Voltage and Current Limitations” plot in the Typical
Characteristics. The X- and Y-axes of this graph show the
zero-voltage output current limit and the zero-current output
voltage limit, respectively. The four quadrants give a more
detailed view of the OPA3691’s output drive capabilities,
noting that the graph is bounded by a “Safe Operating Area”
of 1W maximum internal power dissipation. Superimposing
resistor load lines onto the plot shows that the OPA3691 can
drive ±2.5V into 25Ω or ±3.5V into 50Ω without exceeding the
output capabilities or the 1W dissipation limit. A 100Ω load
line (the standard test circuit load) shows the full ±3.9V
output swing capability, as shown in the Electrical Characteristics Table.
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17
The minimum specified output voltage and current over
temperature are set by worst-case simulations at the cold
temperature extreme. Only at cold start-up will the output
current and voltage decrease to the numbers shown in the
electrical characteristic tables. As the output transistors deliver power, their junction temperatures will increase, decreasing their VBE’s (increasing the available output voltage
swing), and increasing their current gains (increasing the
available output current). In steady-state operation, the available output voltage and current will always be greater than
that shown in the over-temperature specifications since the
output stage junction temperatures will be higher than the
minimum specified operating ambient.
To protect the output stage from accidental shorts to ground
and the power supplies, output short-circuit protection is
included in the OPA3691. This circuit acts to limit the maximum source or sink current to approximately 250mA.
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an ADC—including additional
external capacitance which may be recommended to improve the ADC linearity. A high-speed, high open-loop gain
amplifier like the OPA3691 can be very susceptible to decreased stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin. When the
amplifier’s open-loop output resistance is considered, this
capacitive load introduces an additional pole in the signal
path that can decrease the phase margin. Several external
solutions to this problem have been suggested. When the
primary considerations are frequency response flatness, pulse
response fidelity, and/or distortion, the simplest and most
effective solution is to isolate the capacitive load from the
feedback loop by inserting a series isolation resistor between
the amplifier output and the capacitive load. This does not
eliminate the pole from the loop response, but rather shifts it
and adds a zero at a higher frequency. The additional zero
acts to cancel the phase lag from the capacitive load pole,
thus increasing the phase margin and improving stability.
The Typical Characteristics show the recommended “RS vs
Capacitive Load” and the resulting frequency response at the
load. Parasitic capacitive loads greater than 2pF can begin to
degrade the performance of the OPA3691. Long PC board
traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always
consider this effect carefully, and add the recommended
series resistor as close as possible to the OPA3691 output
pin (see Board Layout Guidelines).
DISTORTION PERFORMANCE
The OPA3691 provides good distortion performance into a
100Ω load on ±5V supplies. Relative to alternative solutions,
it provides exceptional performance into lighter loads and/or
18
operating on a single +5V supply. Generally, until the fundamental signal reaches very high frequency or power levels, the
2nd-harmonic will dominate the distortion with a negligible 3rdharmonic component. Focusing then on the 2nd-harmonic,
increasing the load impedance improves distortion directly.
Remember that the total load includes the feedback network;
in the noninverting configuration (see Figure 1), this is the sum
of RF + RG, while in the inverting configuration it is just RF.
Also, providing an additional supply decoupling capacitor
(0.01µF) between the supply pins (for bipolar operation) improves the 2nd-order distortion slightly (3dB to 6dB).
In most op amps, increasing the output voltage swing increases harmonic distortion directly. The Typical Characteristics show the 2nd-harmonic increasing at a little less than
the expected 2x rate while the 3rd-harmonic increases at a
little less than the expected 3x rate. Where the test power
doubles, the difference between it and the 2nd-harmonic
decreases less than the expected 6dB while the difference
between it and the 3rd-harmonic decreases by less than the
expected 12dB. This also shows up in the 2-tone, 3rd-order
intermodulation spurious (IM3) response curves. The 3rdorder spurious levels are extremely low at low output power
levels. The output stage continues to hold them low even as
the fundamental power reaches very high levels. As the
Typical Characteristics show, the spurious intermodulation
powers do not increase as predicted by a traditional intercept
model. As the fundamental power level increases, the dynamic range does not decrease significantly. For two tones
centered at 20MHz, with 10dBm/tone into a matched 50Ω
load (i.e., 2Vp-p for each tone at the load, which requires
8Vp-p for the overall 2-tone envelope at the output pin), the
Typical Characteristics show 48dBc difference between the
test-tone power and the 3rd-order intermodulation spurious
levels. This exceptional performance improves further when
operating at lower frequencies.
NOISE PERFORMANCE
Wideband current-feedback op amps generally have a higher
output noise than comparable voltage-feedback op amps. The
OPA3691 offers an excellent balance between voltage and
current noise terms to achieve low output noise. The inverting
current noise (15pA/√Hz) is significantly lower than earlier
solutions while the input voltage noise (1.7nV/√Hz) is lower
than most unity-gain stable, wideband, voltage-feedback op
amps. This low input voltage noise was achieved at the price
of higher noninverting input current noise (12pA/√Hz). As long
as the AC source impedance looking out of the noninverting
node is less than 100Ω, this current noise will not contribute
significantly to the total output noise. The op amp input voltage
noise and the two input current noise terms combine to give
low output noise under a wide variety of operating conditions.
See Figure 12 for the op amp noise analysis model with all the
noise terms included. In this model, all noise terms are taken
to be noise voltage or current density terms in either nV/√Hz
or pA/√Hz.
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ENI
1/3
OPA3691
RS
EO
IBN
contribution to the output is ineffective. Evaluating the configuration of Figure 1, using worst-case +25°C input offset
voltage and the two input bias currents, gives a worst-case
output offset range equal to:
± (NG • VOS(MAX)) + (IBN • RS/2 • NG) ± (IBI • RF)
where NG = noninverting signal gain
= ± (2 • 3.0mV) + (35µA • 25Ω • 2) ± (402Ω • 25µA)
ERS
RF
√ 4kTRS
4kT
RG
IBI
RG
= ±6mV + 1.75mV ± 10.05mV
√ 4kTRF
= –14.3mV → +17.8mV
4kT = 1.6E – 20J
at 290°K
DISABLE OPERATION
FIGURE 12. Op Amp Noise Analysis Model.
The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 4 shows the general form for the
output noise voltage using the terms shown in Figure 12.
The OPA3691 provides an optional disable feature that may
be used either to reduce system power or to implement a
simple channel multiplexing operation. If the DIS control pin
is left unconnected, the OPA3691 will operate normally.
To disable, the control pin must be asserted low. Figure 13
shows a simplified internal circuit for the disable control
feature.
(4)
EO =
(
+VS
)
ENI 2 + (IBN RS )2 + 4kTRS NG2 + (IBI RF )2 + 4kTRF NG
Dividing this expression by the noise gain (NG = (1 + RF/RG))
will give the equivalent input referred spot noise voltage at
the noninverting input, as shown in Equation 5.
 I R  2 4kTRF
EN = ENI 2 + (IBN RS )2 + 4kTRS +  BI F  +
 NG 
NG
15kΩ
(5)
Evaluating these two equations for the OPA3691 circuit and
component values (see Figure 1) will give a total output spot
noise voltage of 8.08nV/√Hz and a total equivalent input spot
noise voltage of 4.04nV/√Hz. This total input-referred spot
noise voltage is higher than the 1.7nV/√Hz specification for
the op amp voltage noise alone. This reflects the noise
added to the output by the inverting current noise times the
feedback resistor. If the feedback resistor is reduced in high
gain configurations (as suggested previously), the total inputreferred voltage noise given by Equation 5 will approach just
the 1.7nV/√Hz of the op amp itself. For example, going to a
gain of +10 using RF = 182Ω will give a total input referred
noise of 2.1nV/√Hz.
DC ACCURACY AND OFFSET CONTROL
A current-feedback op amp like the OPA3691 provides
exceptional bandwidth in high gains, giving fast pulse settling
but only moderate DC accuracy. The Electrical Characteristics Table shows an input offset voltage comparable to highspeed, voltage-feedback amplifiers. However, the two input
bias currents are somewhat higher and are unmatched.
Whereas bias current cancellation techniques are very effective with most voltage-feedback op amps, they do not generally reduce the output DC offset for wideband current-feedback op amps. Since the two input bias currents are unrelated in both magnitude and polarity, matching the source
impedance looking out of each input to reduce their error
Q1
25kΩ
VDIS
IS
Control
–VS
FIGURE 13. Simplified Disable Control Circuit.
In normal operation, base current to Q1 is provided through
the 110kΩ resistor while the emitter current through the 15kΩ
resistor sets up a voltage drop that is inadequate to turn on
the two diodes in Q1’s emitter. As VDIS is pulled low,
additional current is pulled through the 15kΩ resistor eventually turning on these two diodes (≈ 75µA). At this point, any
further current pulled out of V DIS goes through those diodes
holding the emitter-base voltage of Q1 at approximately 0V.
This shuts off the collector current out of Q1, turning the
amplifier off. The supply current in the disable mode is that
only required to operate the circuit of Figure 13. Additional
circuitry ensures that turn-on time occurs faster than turn-off
time (make-before-break).
When disabled, the output and input nodes go to a high
impedance state. If the OPA3691 is operating in a gain of +1,
this will show a very high impedance (4pF || 1MΩ) at the
output and exceptional signal isolation. If operating at a
gain greater than +1, the total feedback network resistance
(RF + RG) will appear as the impedance looking back into the
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19
As a worst-case example, compute the maximum TJ using an
OPA3691 SO-16 (see the circuit of Figure 1), operating at the
maximum specified ambient temperature of +85°C with all
three outputs driving a grounded 20Ω load to +2.5V:
One key parameter in disable operation is the output glitch
when switching in and out of the disable mode. Figure 14
shows these glitches for the circuit of Figure 1 with the input
signal set to 0V. The glitch waveform at the output pin is
plotted along with the DIS pin voltage.
Maximum TJ = +85°C + (1.13 • 100°C/W) = 198°C
6.0
4.0
2.0
Output Voltage (10mV/div)
0.0
VDIS (2V/div)
output, but the circuit will still show very high forward and
reverse isolation. If configured as an inverting amplifier, the
input and output will be connected through the feedback
network resistance (RF + RG) giving relatively poor input to
output isolation.
30
20
10
0
–10
–20
–30
Time (20ns/div)
FIGURE 14. Disable/Enable Glitch.
The transition edge rate (dv/dt) of the DIS control line will
influence this glitch. For the plot of Figure 14, the edge rate
was reduced until no further reduction in glitch amplitude was
observed. This approximately 1V/ns maximum slew rate may
be achieved by adding a simple RC filter into the V DIS pin
from a higher speed logic line. If extremely fast transition
logic is used, a 2kΩ series resistor between the logic gate
and the V DIS input pin will provide adequate bandlimiting
using just the parasitic input capacitance on the V DIS pin
while still ensuring adequate logic level swing.
THERMAL ANALYSIS
Due to the high output power capability of the OPA3691,
heatsinking or forced airflow may be required under extreme
operating conditions. Maximum desired junction temperature
will set the maximum allowed internal power dissipation as
described below. In no case should the maximum junction
temperature be allowed to exceed 175°C. Operating junction
temperature (TJ) is given by TA + PD • θJA. The total internal
power dissipation (PD) is the sum of quiescent power (PDQ)
and additional power dissipation in the output stage (PDL) to
deliver load power. Quiescent power is simply the specified
no-load supply current times the total supply voltage across
the part. PDL will depend on the required output signal and
load but would, for a grounded resistive load, be at a
maximum when the output is fixed at a voltage equal to 1/2
of either supply voltage (for equal bipolar supplies). Under
this condition, PDL = VS2/(4 • RL) where RL includes feedback
network loading.
Note that it is the power in the output stage and not into the
load that determines internal power dissipation.
20
PD = 10V • 17.1mA + 3 • [52/(4 • (20Ω || 804Ω))] = 1.13W
This absolute worst-case condition exceeds specified maximum junction temperature. Normally this extreme case will
not be encountered. Careful attention to internal power
dissipation is required and perhaps airflow considered under
extreme conditions.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high-frequency amplifier like the OPA3691 requires careful attention to board
layout parasitics and external component types. Recommendations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for all
of the signal I/O pins. Parasitic capacitance on the output and
inverting input pins can cause instability: on the noninverting
input, it can react with the source impedance to cause
unintentional bandlimiting. To reduce unwanted capacitance,
a window around the signal I/O pins should be opened in all
of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board.
b) Minimize the distance (< 0.25") from the power-supply
pins to high-frequency 0.1µF decoupling capacitors. At the
device pins, the ground and power plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. The power-supply
connections (on pins 4 and 7) should always be decoupled
with these capacitors. An optional supply decoupling capacitor across the two power supplies (for bipolar operation) will
improve 2nd-harmonic distortion performance. Larger (2.2µF
to 6.8µF) decoupling capacitors, effective at lower frequency,
should also be used on the main supply pins. These may be
placed somewhat farther from the device and may be shared
among several devices in the same area of the PC board.
c) Careful selection and placement of external components will preserve the high-frequency performance of
the OPA3691. Resistors should be a very low reactance
type. Surface-mount resistors work best and allow a tighter
overall layout. Metal-film and carbon composition, axially
leaded resistors can also provide good high-frequency performance. Again, keep their leads and PC board trace length
as short as possible. Never use wirewound type resistors in
a high-frequency application. Since the output pin and inverting input pin are the most sensitive to parasitic capacitance,
always position the feedback and series output resistor, if
any, as close as possible to the output pin. Other network
components, such as noninverting input termination resistors, should also be placed close to the package. Where
double-side component mounting is allowed, place the feedback resistor directly under the package on the other side of
the board between the output and inverting input pins. The
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frequency response is primarily determined by the feedback
resistor value as described previously. Increasing its value
will reduce the bandwidth, while decreasing it will give a more
peaked frequency response. The 402Ω feedback resistor
used in the typical performance specifications at a gain of +2
on ±5V supplies is a good starting point for design. Note that
a 453Ω feedback resistor, rather than a direct short, is
recommended for the unity-gain follower application. A current-feedback op amp requires a feedback resistor even in
the unity-gain follower configuration to control stability.
d) Connections to other wideband devices on the board
may be made with short direct traces or through onboard
transmission lines. For short connections, consider the trace
and the input to the next device as a lumped capacitive load.
Relatively wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up around
them. Estimate the total capacitive load and set RS from the
plot of “Recommended RS vs Capacitive Load”. Low parasitic
capacitive loads (< 5pF) may not need an RS since the
OPA3691 is nominally compensated to operate with a 2pF
parasitic load. If a long trace is required, and the 6dB signal
loss intrinsic to a doubly-terminated transmission line is
acceptable, implement a matched impedance transmission
line using microstrip or stripline techniques (consult an ECL
design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary on
board, and in fact, a higher impedance environment will
improve distortion as shown in the “Distortion vs Load” plots.
With a characteristic board trace impedance defined based
on board material and trace dimensions, a matching series
resistor into the trace from the output of the OPA3691 is used
as well as a terminating shunt resistor at the input of the
destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor
and the input impedance of the destination device: this total
effective impedance should be set to match the trace impedance. The high output voltage and current capability of the
OPA3691 allows multiple destination devices to be handled
as separate transmission lines, each with their own series
and shunt terminations. If the 6dB attenuation of a doublyterminated transmission line is unacceptable, a long trace
can be series-terminated at the source end only. Treat the
trace as a capacitive load in this case and set the series
resistor value as shown in the plot of “RS vs Capacitive
Load”. This will not preserve signal integrity as well as a
doubly-terminated line. If the input impedance of the destination device is low, there will be some signal attenuation due
to the voltage divider formed by the series output into the
terminating impedance.
e) Socketing a high-speed part like the OPA3691 is not
recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it
almost impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering the OPA3691
onto the board.
INPUT AND ESD PROTECTION
The OPA3691 is built using a very high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins have limited ESD protection using internal diodes to the power supplies as shown in
Figure 15.
+V CC
External
Pin
–V CC
FIGURE 15. Internal ESD Protection.
These diodes provide moderate protection to input overdrive
voltages above the supplies as well. The protection diodes
can typically support 30mA continuous current. Where higher
currents are possible (e.g., in systems with ±15V supply parts
driving into the OPA3691), current limiting series resistors
should be added into the two inputs. Keep these resistor
values as low as possible since high values degrade both
noise performance and frequency response.
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Internal
Circuitry
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21
PACKAGE DRAWINGS
DBQ (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0.012 (0,30)
0.008 (0,20)
0.025 (0,64)
24
0.005 (0,13) M
13
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (3,99)
0.150 (3,81)
1
Gage Plane
12
A
0.010 (0,25)
0°– 8°
0.069 (1,75) MAX
0.035 (0,89)
0.016 (0,40)
Seating Plane
0.010 (0,25)
0.004 (0,10)
0.004 (0,10)
PINS **
16
20
24
28
A MAX
0.197
(5,00)
0.344
(8,74)
0.344
(8,74)
0.394
(10,01)
A MIN
0.188
(4,78)
0.337
(8,56)
0.337
(8,56)
0.386
(9,80)
DIM
4073301/E 10/00
NOTES: A.
B.
C.
D.
22
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-137
OPA3691
www.ti.com
SBOS227A
PACKAGE DRAWINGS (Cont.)
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
0.020 (0,51)
0.014 (0,35)
0.050 (1,27)
8
0.010 (0,25)
5
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
4
0.010 (0,25)
0°– 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
0.004 (0,10)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
4040047/E 09/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
OPA3691
SBOS227A
www.ti.com
23
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
OPA3691ID
ACTIVE
SOIC
D
16
48
None
CU SNPB
Level-3-260C-168 HR
OPA3691IDBQR
ACTIVE
SSOP/
QSOP
DBQ
16
2500
None
CU NIPDAU
Level-3-235C-168 HR
OPA3691IDBQRG4
PREVIEW
SSOP/
QSOP
DBQ
16
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA3691IDBQT
ACTIVE
SSOP/
QSOP
DBQ
16
250
None
CU NIPDAU
Level-3-235C-168 HR
OPA3691IDR
ACTIVE
SOIC
D
16
2500
None
CU SNPB
Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
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information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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