Renesas HD74LS93P 4-bit binary counter Datasheet

HD74LS93
4-bit Binary Counter
REJ03D0423–0200
Rev.2.00
Feb.18.2005
The HD74LS93 contains four master-slave flip-flops and additional gating to provide a divide-by-two counter and
three-state binary counter for divide-by-eight. To use this maximum count length of this counter, the B input is
connected to the QA output. The input count pulses are applied to input A and the outputs are described in the
appropriate function table.
Features
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74LS93P
DILP-14 pin
PRDP0014AB-B
(DP-14AV)
P
—
HD74LS93FPEL
SOP-14 pin (JEITA)
PRSP0014DF-B
(FP-14DAV)
FP
EL (2,000 pcs/reel)
Note: Please consult the sales office for the above package availability.
Pin Arrangement
B
1
B
R0(1)
2
R0(1)
R0(2)
3
R0(2)
NC
4
VCC
5
NC
6
NC
7
14
A
13
NC
QA
12
QA
QD
11
QD
10
GND
9
QB
8
QC
A
QC
QB
(Top view)
Rev.2.00, Feb.18.2005, page 1 of 8
HD74LS93
Function Table
• Reset / Count Function Table
Reset inputs
R0(1)
H
L
X
Note:
Outputs
R0(2)
H
X
L
QD
L
QC
L
QB
L
QA
L
Count
Count
H; high level, L; low level, X; irrelevant
• BCD Count Sequence (Notes 1)
Count
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Outputs
QD
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
QC
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
Notes: 1. Output QA is connected to input B for BCD count.
2. H; high level, L; low level
Rev.2.00, Feb.18.2005, page 2 of 8
QB
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
QA
L
H
L
H
H
H
L
H
L
H
L
H
L
H
L
H
HD74LS93
Block Diagram
J
Input A
Q
QA
Q
QB
Q
QC
Q
QD
CK
K
J
Input B
CK
K
J
CK
K
J
CK
K
R0(1)
R0(2)
Absolute Maximum Ratings
Item
Symbol
VCC
VIN
VIN
Ratings
7
R Inputs
7
Input voltage
A, B Inputs
5.5
Power dissipation
PT
400
Storage temperature
Tstg
–65 to +150
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Supply voltage
Unit
V
V
V
mW
°C
Recommended Operating Conditions
Item
Supply voltage
Output current
Operating temperature
A input
Count frequency
B input
A input
Pulse width
B input
Symbol
VCC
IOH
IOL
Topr
tw
Min
4.75
—
—
–20
0
0
15
30
Typ
5.00
—
—
25
—
—
—
—
Max
5.25
–400
8
75
32
16
—
—
tsu
15
25
—
—
—
—
fcount
Reset input
Setup time
Rev.2.00, Feb.18.2005, page 3 of 8
Unit
V
µA
mA
°C
MHz
ns
ns
HD74LS93
Electrical Characteristics
(Ta = –20 to +75 °C)
Item
Input voltage
Symbol
VIH
VIL
min.
2.0
—
2.7
typ.*
—
—
—
max.
—
0.8
—
IIL
—
—
—
—
—
—
—
—
0.4
0.5
–0.4
–2.4
mA
VCC = 5.25 V, VI = 0.4 V
IIH
—
—
—
—
—
—
–1.6
20
40
µA
VCC = 5.25 V, VI = 2.7 V
II
—
—
—
—
—
—
40
0.1
0.2
mA
—
—
0.2
VI = 7 V
VI = 5.5 V
VI = 5.5 V
IOS
–20
—
–100
mA
VCC = 5.25 V
ICC***
VIK
—
—
9
—
15
–1.5
mA
V
VCC = 5.25 V
VCC = 4.75 V, IIN = –18 mA
VOH
Output voltage
VOL
Input
current
Any reset
A input
B input
Any reset
A input
B input
Any reset
A input
B input
Short-circuit output
current
Supply current
Input clamp voltage
Unit
V
V
Condition
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V,
IOH = –400 µA
IOL = 4 mA**
VCC = 4.75 V, VIH = 2 V,
VIL = 0.8 V
IOL = 8 mA**
V
V
VCC = 5.25 V
Notes: * VCC = 5 V, Ta = 25°C
** QA output is tested at specified IOL plus the limit value of IIL for the B input. This permits driving the B input
while maintaining full fan-out capability.
*** ICC is measured with all outputs open, both R0 inputs grounded following momentary connection to 4.5 V, and
all other inputs grounded.
Switching Characteristics
(VCC = 5 V, Ta = 25°C)
Item
Maximum count frequency
Propagation delay time
Symbol
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
Inputs
A
B
Outputs
QA
QB
A
QA
A
QD
B
QB
min.
32
16
—
—
—
—
—
—
typ.
42
—
10
12
46
46
10
14
max.
—
—
16
18
70
70
16
21
21
23
32
35
B
QC
—
—
B
QD
—
—
34
34
51
51
Set-to-0
QA to QD
—
26
40
Unit
Condition
MHz
ns
CL = 15 pF,
RL = 2 kΩ
Note: Refer to Test Circuit and Waveform of the Common Item "TTL Common Matter (Document No.: REJ27D00050100)".
Rev.2.00, Feb.18.2005, page 4 of 8
HD74LS93
Timing Definition
tw
3V
R0
1.3 V
1.3 V
0V
tsu
3V
A or B
Input
1.3 V
1.3 V
0V
tw
Testing Method
Test Circuit
VCC
QA
4.5V
RL
Load circuit 1
QA
A
CL
P.G.
Zout = 50Ω
See Testing Table
B
QB
QB
R0
R0
QC
1. CL includes probe and jig capacitance.
2. All diodes are 1S2074(H).
Rev.2.00, Feb.18.2005, page 5 of 8
Same as Load Circuit 1.
QD
QD
Notes:
Same as Load Circuit 1.
QC
Same as Load Circuit 1.
HD74LS93
Testing Table
Inputs
From input
to output
Item
A
IN
4.5 V
IN
IN
4.5 V
4.5 V
4.5 V
IN*
A→Q
B→Q
A → QA
A → QD
B → QB
B → QC
B → QD
R0** → Q
fmax
tPLH
tPHL
Outputs
B
to QA
IN
to QA
to QA
IN
IN
IN
to QA
R0
GND
GND
GND
GND
GND
GND
GND
IN
QA
Out
—
Out
—
—
—
—
Out
QB
Out
Out
—
—
Out
—
—
Out
QC
Out
Out
—
—
—
Out
—
Out
QD
Out
Out
—
Out
—
—
Out
Out
* For initialized.
** Measured with each input and unused inputs at 4.5 V.
Waveform
1. fmax, tPLH, tPHL (Clock → Q)
tTHL
tTLH
3V
Clock
10%
90% 90%
1.3 V
10%
tPHL(Measure at tn+2)
1.3 V
0V
tPLH (Measure at tn+1)
VOH
QA
1.3 V
1.3 V
VOL
tPHL (Measure at tn+4)
QB
tPLH (Measure at tn+2)
VOH
1.3 V
tPHL (Measure at tn+8)
1.3 V
tPLH (Measure at tn+4)
VOL
VOH
QC
1.3 V
1.3 V
tPHL (Measure at tn+16) tPLH (Measure at tn+8)
VOL
VOH
QD
1.3 V
1.3 V
VOL
Notes:
1. Input pulse; tTLH ≤ 15 ns, tTHL ≤ 5 ns, PRR = 1 MHz, duty cycle = 50% and for fmax.,
tTLH = tTHL ≤ 2.5 ns
2. tn is reference bit time when all outputs are low.
Rev.2.00, Feb.18.2005, page 6 of 8
HD74LS93
2. tPHL (R0 → Q)
tTLH
tTHL
3V
90% 90%
1.3 V 1.3 V
R0
10%
10%
tw ≥ 15ns
0V
tPHL
VOH
QA to QD
Notes:
tTLH ≤ 15 ns, tTHL ≤ 5 ns
Rev.2.00, Feb.18.2005, page 7 of 8
1.3 V
VOL
HD74LS93
Package Dimensions
JEITA Package Code
P-DIP14-6.3x19.2-2.54
RENESAS Code
PRDP0014AB-B
MASS[Typ.]
0.97g
Previous Code
DP-14AV
D
8
E
14
1
7
b3
Z
A1
A
Reference
Symbol
Nom
e1
7.62
D
19.2
E
6.3
L
A
θ
bp
e
Dimension in Millimeters
Min
e1
A1
0.51
bp
0.40
0.48
JEITA Package Code
P-SOP14-5.5x10.06-1.27
RENESAS Code
PRSP0014DF-B
*1
Previous Code
FP-14DAV
D
0.56
c
0.19
θ
0°
e
2.29
0.25
0.31
2.54
2.79
15°
2.39
L
2.54
MASS[Typ.]
0.23g
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
F
14
7.4
1.30
Z
( Ni/Pd/Au plating )
20.32
5.06
b3
c
Max
8
c
HE
*2
E
bp
Index mark
Reference
Symbol
Terminal cross section
( Ni/Pd/Au plating )
1
Z
*3
Nom
Max
D
10.06
10.5
E
5.50
A2
7
e
A1
bp
Dimension in Millimeters
Min
x
M
0.00
0.10
0.34
0.40
0.46
0.15
0.20
0.25
7.80
8.00
A
L1
0.20
2.20
bp
b1
c
A
c
A1
θ
y
L
Detail F
1
θ
0°
HE
7.50
e
1.27
x
0.12
y
0.15
1.42
Z
L
L
Rev.2.00, Feb.18.2005, page 8 of 8
8°
0.50
1
0.70
1.15
0.90
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