ON NTHD4502NT1 Power mosfet 30 v, 3.9 a, dual n−channel chipfet Datasheet

NTHD4502N
Power MOSFET
30 V, 3.9 A, Dual N−Channel ChipFET
Features
• Planar Technology Device Offers Low RDS(on) and Fast Switching Speed
• Leadless ChipFET Package has 40% Smaller Footprint than TSOP−6.
Ideal Device for Applications Where Board Space is at a Premium.
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• ChipFET Package Exhibits Excellent Thermal Capabilities. Ideal for
•
Applications Where Heat Transfer is Required.
Pb−Free Package is Available
V(BR)DSS
RDS(on) TYP
ID MAX
80 m @ 10 V
Applications
• DC−DC Buck or Boost Converters
• Low Side Switching
• Optimized for Battery and Low Side Switching Applications in
30 V
3.9 A
110 m @ 4.5 V
D1, D2
Computing and Portable Equipment
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Parameter
Value
Unit
Drain−to−Source Voltage
VDSS
30
V
Gate−to−Source Voltage
VGS
±20
V
ID
2.9
A
Continuous Drain
Current (Note 1)
Power Dissipation
(Note 1)
Steady
State
TA = 25°C
TA = 85°C
2.1
t≤5s
TA = 25°C
3.9
Steady
State
t≤5s
Continuous Drain
Current (Note 2)
Power Dissipation
(Note 2)
PD
TA = 85°C
TA = 25°C
A
2.2
1.6
PD
0.64
W
12
A
125
V
TJ,
TSTG
−55 to
150
°C
Source Current (Body Diode)
IS
2.5
A
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
TL
260
°C
Operating Junction and Storage Temperature
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq
[1 oz] including traces).
2. Surface Mounted on FR4 Board using the minimum recommended pad size
(Cu area = 0.214 in sq).
3. ESD Rating Information: HBM Class 0.
 Semiconductor Components Industries, LLC, 2004
1
PIN
CONNECTIONS
MARKING
DIAGRAM
D1 8
1 S1
1
8
D1 7
2 G1
2
7
D2 6
3 S2
3
D2 5
4 G2
4
C5 M
IDM
ESD−
HBM
October, 2004 − Rev. 4
ChipFET
CASE 1206A
STYLE 2
2.1
ID
tp = 10 s
ESD Capability
(Note 3)
N−Channel MOSFET
W
C = 100 pF,
RS = 1500 Pulsed Drain Current
S1, S2
TA = 25°C
25 C
TA = 25°C
Steady
y
State
1.13
G 1 , G2
6
5
C5 = Specific Device Code
M = Month Code
ORDERING INFORMATION
Package
Shipping†
NTHD4502NT1
ChipFET
3000/Tape & Reel
NTHD4502NT1G
ChipFET
(Pb−Free)
3000/Tape & Reel
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
NTHD4502N/D
NTHD4502N
THERMAL RESISTANCE RATINGS
Symbol
Max
Unit
Junction−to−Ambient – Steady State (Note 4)
Parameter
RJA
110
°C/W
Junction−to−Ambient – t ≤ 5 s (Note 4)
RJA
60
Junction−to−Ambient – Steady State (Note 5)
RJA
195
4. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces).
5. Surface Mounted on FR4 Board using the minimum recommended pad size (Cu area = 0.214 in sq).
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Symbol
Test Conditions
Min
Typ
V(BR)DSS
VGS = 0 V, ID = 250 A
30
36
IDSS
VGS = 0 V, VDS = 24 V
1.0
VGS = 0 V, VDS = 24 V, TJ = 125°C
10
IGSS
VDS = 0 V, VGS = 20 V
100
nA
Gate Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250 A
1.65
3.0
V
Drain−to−Source On−Resistance
RDS(on)
( )
VGS = 10 V, ID = 2.9 A
78
85
m
VGS = 4.5 V, ID = 2.2 A
105
140
VDS = 15 V, ID = 2.9 A
3.8
S
140
pF
Parameter
Max
Units
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
V
A
ON CHARACTERISTICS (Note 6)
Forward Transconductance
gFS
1.0
CHARGES AND CAPACITANCES
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
Input Capacitance
CISS
VGS = 0 V, f = 1.0 MHz,
VDS = 15 V
53
16
VGS = 0 V, f = 1.0 MHz,
VDS = 24 V
135
250
42
75
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
13
25
Total Gate Charge
QG(TOT)
3.6
7.0
Threshold Gate Charge
QG(TH)
0.3
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
0.7
Total Gate Charge
QG(TOT)
1.9
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
VGS = 10 V, VDS = 15 V,
ID = 2.9 A
VGS = 4.5 V, VDS = 24 V,
ID = 2.9 A
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2
nC
0.6
0.3
0.6
0.9
6. Pulse Test: Pulse Width 300 s, Duty Cycle 2%.
pF
nC
NTHD4502N
ELECTRICAL CHARACTERISTICS (continued) (TJ = 25°C unless otherwise noted)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
1.2
V
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
VSD
VGS = 0 V, IS = 2.5 A
0.85
Reverse Recovery Time
tRR
8.6
ns
Reverse Recovery Charge
QRR
VGS = 0 V, IS = 2.9 A,
dIS/dt = 100 A/s
4.0
nC
Reverse Recovery Time
tRR
8.4
ns
Reverse Recovery Charge
QRR
VGS = 0 V, IS = 1.0 A,
dIS/dt = 100 A/s
4.0
nC
SWITCHING CHARACTERISTICS (Note 7)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
6.5
12
5.4
10
14.9
25
tf
1.8
5.0
td(ON)
7.8
tr
td(OFF)
tr
td(OFF)
VGS = 10 V, VDD = 24 V,
ID = 1 A, RG = 6 VGS = 4.5 V, VDD = 24 V,
ID = 2.9 A, RG = 2.5 tf
12.6
9.6
2.8
7. Switching characteristics are independent of operating junction temperatures.
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3
ns
ns
NTHD4502N
TYPICAL PERFORMANCE CURVES
10
6
3.6 V
6
3.4 V
4
3.2 V
TJ = 25°C
3V
2
2.8 V
2.6 V
0
1
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
ID, DRAIN CURRENT (AMPS)
3.8 V
2
4
3
5
5
4
3
2
TJ = −55°C
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
3
2
4
5
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
1
ID = 2.9 A
TJ = 25°C
0.25
0.2
0.15
0.1
0.05
0
3
8
9
4
5
6
7
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
2
10
6
0.12
TJ = 25°C
0.11
VGS = 4.5 V
0.10
0.09
VGS = 10 V
0.08
0.07
2
4
3
6
5
ID, DRAIN CURRENT (AMPS)
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
1.8
1000
VGS = 0 V
ID = 2.9 A
VGS = 10 V
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
25°C
1
6
0.3
1.6
100°C
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
ID, DRAIN CURRENT (AMPS)
8
VDS ≥ 10 V
4V
VGS = 10, 6, 5, 4.5 & 4.2 V resp.
1.4
1.2
1.0
TJ = 150°C
100
10
TJ = 100°C
1
0.8
0.6
−50
0.1
−25
0
25
50
75
100
125
150
5
10
15
20
25
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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4
30
NTHD4502N
VGS = 0 V
VDS = 0 V
TJ = 25°C
C, CAPACITANCE (pF)
QG
10
CISS
200
CRSS
100
COSS
0
10
24
12
5
VGS
0
VDS
5
10
15
20
25
30
VDS
8
16
VGS
12
6
4
QGS
8
QGD
ID = 2.9 A
TJ = 25°C
2
4
0
0
0
1
2
3
QG, TOTAL GATE CHARGE (nC)
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
4
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
Figure 7. Capacitance Variation
100
3
IS, SOURCE CURRENT (AMPS)
t, TIME (ns)
20
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
300
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
TYPICAL PERFORMANCE CURVES
td(off)
td(on)
tr
10
1
tf
VDD = 24 V
ID = 1.0 A
VGS = 10 V
0.1
1
10
VGS = 0 V
TJ = 25°C
2
1
0
0.3
100
0.4
0.5
0.6
0.7
0.8
0.9
RG, GATE RESISTANCE (OHMS)
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
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5
1
NTHD4502N
PACKAGE DIMENSIONS
ChipFET
CASE 1206A−03
ISSUE E
A
8
7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM
PER SIDE.
4. LEADFRAME TO MOLDED BODY OFFSET IN
HORIZONTAL AND VERTICAL SHALL NOT EXCEED
0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE
BURRS.
6. NO MOLD FLASH ALLOWED ON THE TOP AND
BOTTOM LEAD SURFACE.
7. 1206A−01 AND 1206A−02 OBSOLETE. NEW
STANDARD IS 1206A−03.
M
6
K
5
S
5
6
7
8
4
3
2
1
B
1
2
3
L
4
D
J
G
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
C
0.05 (0.002)
DIM
A
B
C
D
G
J
K
L
M
S
SOURCE 1
GATE 1
SOURCE 2
GATE 2
DRAIN 2
DRAIN 2
DRAIN 1
DRAIN 1
MILLIMETERS
MIN
MAX
2.95
3.10
1.55
1.70
1.00
1.10
0.25
0.35
0.65 BSC
0.10
0.20
0.28
0.42
0.55 BSC
5 ° NOM
1.80
2.00
INCHES
MIN
MAX
0.116
0.122
0.061
0.067
0.039
0.043
0.010
0.014
0.025 BSC
0.004
0.008
0.011
0.017
0.022 BSC
5 ° NOM
0.072
0.080
SOLDERING FOOTPRINT*
2.032
0.08
2.032
0.08
0.457
0.018
0.635
0.025
1.092
0.043
0.635
0.025
0.178
0.007
0.457
0.018
0.711
0.028
0.66
0.026
SCALE 20:1
mm inches
0.254
0.010
0.66
0.026
SCALE 20:1
Basic
mm inches
Style 2
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ChipFET is a trademark of Vishay Siliconix.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NTHD4502N/D