AD AD5384BBC-5 32-channel, 14-bit, parallel and serial input, bipolar voltage output dac Datasheet

32-Channel, 14-Bit, Parallel and
Serial Input, Bipolar Voltage Output DAC
AD5378
Preliminary Technical Data
Interface options
Parallel interface
DSP/microcontroller-compatible 3-wire serial interface
2.5 V to 5.5 V JEDEC-compliant digital levels
SDO daisy-chaining option
Power-on reset
Digital reset (RESET pin and soft reset function)
FEATURES
32-channel DAC in 13 mm × 13 mm 108-lead CSPBGA
Guaranteed monotonic to 14 bits
Buffered voltage outputs
Output voltage span of 3.5 V × VREF(+)
Maximum output voltage span of 17.5 V
System calibration function allowing user-programmable
offset and gain
Pseudo differential outputs relative to REFGND
Clear function to user-defined REFGND (CLR pin)
Simultaneous update of DAC outputs (LDAC pin)
DAC increment/decrement mode
Channel grouping and addressing features
APPLICATIONS
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOAs)
Optical switches
Industrial control systems
FUNCTIONAL BLOCK DIAGRAM
VCC
VDD
VSS
AGND
DGND
LDAC
VBIAS VREF1(+) VREF1(–) REFGND A1
AD5378
POWER-ON
RESET
VBIAS
CLR
RESET
DCEN/WR
14
/
SYNC/CS
REG0
REG1
STATE MACHINE
INTERFACE
A7
/
INPUT 14
REG
2
DAC
14
REG
0–1
/
DAC 14
REG
2
/
DAC 0–1
VOUT 0
VOUT 1
/
DAC 2
m REG2
c REG2
/
/
14
/
14
14
/
m REG0–1
c REG0–1
/
14
14
/
14
DB13
SCLK/DB12
DIN/DB11
DB0
INPUT
14
REG
0–1
VOUT 2
VOUT 3
A0
14
SER/PAR
DIN
SCLK
SDO
FIFOEN
/
INPUT
14
REG
5
14
/
VOUT 4
/
DAC
14
REG
5
/
DAC 5
/
DAC 14
REG
6–7
/
DAC 6–7
VOUT 5
m REG7
c REG7
14
/
REFGND B1
14
/
REFGND C1
INPUT 14
REG
6–7
/
REFGND C2
14
/
REFGND D1
14
m REG8–9
c REG8–9
REFGND D2
VOUT 6
VOUT 7
VOUT 8
×4
BUSY
VOUT 31
VREF2(+) VREF2(–) REFGND A2
05292-001
REFGND B2
Figure 1.
Protected by U.S. Patent No. 5,969,657 and 6,823,416; other patents pending.
Rev. PrA
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However, no responsibility is assumed by Analog Devices for its use, nor for any
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Fax: 781.326.8703
© 2005 Analog Devices, Inc. All rights reserved.
AD5378
Preliminary Technical Data
TABLE OF CONTENTS
General Description ..........................................................................3
Clear Function ............................................................................ 20
Specifications......................................................................................4
BUSY and LDAC Functions...................................................... 20
AC Characteristics........................................................................ 5
FIFO vs. Non-FIFO Operation................................................. 21
Timing Characteristics......................................................................6
BUSY Input Function ................................................................ 21
Serial Interface .............................................................................. 6
Power-On Reset Function......................................................... 21
Parallel Interface ........................................................................... 9
RESET Input Function .............................................................. 21
Absolute Maximum Ratings...........................................................11
Increment/Decrement Function .............................................. 21
ESD Caution................................................................................ 11
Interfaces...........................................................................................22
Pin Configuration and Function Descriptions............................12
Parallel Interface......................................................................... 22
Typical Performance Characteristics ............................................15
Serial Interface ............................................................................ 22
Terminology .....................................................................................17
Data Decoding .................................................................................24
Functional Description ...................................................................18
Address Decoding ...........................................................................25
DAC Architecture—General..................................................... 18
Power Supply Decoupling ..............................................................26
Channel Groups.......................................................................... 18
Power-On .................................................................................... 26
Transfer Function ....................................................................... 18
Typical Application Circuit ............................................................27
VBIAS Function ............................................................................. 19
Outline Dimensions ........................................................................28
Reference Selection .................................................................... 19
Ordering Guide .......................................................................... 28
Calibration................................................................................... 20
REVISION HISTORY
1/05—Revision PrA: Preliminary Version
Rev. PrA | Page 2 of 28
Preliminary Technical Data
AD5378
GENERAL DESCRIPTION
The AD5378 contains 32 14-bit DACs in one CSPBGA package.
The AD5378 provides a bipolar output range determined by the
voltages applied to the VREF(+) and VREF(−) inputs. The maximum
output voltage span is 17.5 V, corresponding to a bipolar output
range of −8.75 V to +8.75 V, and is achieved with reference voltages of VREF(−) = −3.5 V and VREF(+) = +5 V.
The AD5378 guarantees operation over a wide VSS/VDD supply
range from ±11.4 V to ±16.5 V. The output amplifier headroom
requirement is 2.5 V operating with a load current of 1.5 mA,
and 2 V operating with a load current of 0.5 mA.
The DAC outputs are updated when the DAC registers receive
new data. All the outputs can be updated simultaneously by
taking the LDAC input low. Each channel has a programmable
gain and an offset adjust register.
Each DAC output is gained and buffered on-chip with respect
to an external REFGND input. The DAC outputs can also be
switched to REFGND via the CLR pin. Table 1 and Table 2
show the product portfolio for high channel count bipolar and
unipolar voltage output DACs.
The AD5378 contains a double-buffered parallel interface in
which 14 data bits are loaded into one of the input registers
under the control of the WR, CS, and DAC channel address
pins, A0 to A7. It also has a 3-wire serial interface, which is
compatible with SPI®, QSPI™, MICROWIRE™, and DSP interface standards and can handle clock speeds of up to 50 MHz.
Table 1. 40-Channel, Bipolar, Voltage Output DAC
Model
AD5379ABC
Resolution
14 Bits
Analog Supplies
±11.4 V to ±16.5 V
Output
Channels
40
Linearity Error (LSB)
±3
Package
Description
108-Lead CSPBGA
Package Option
BC-108
Linearity Error (LSB)
±4
±4
±1
±1
±4
±4
±4
±4
±1
±1
±3
±3
±4
±4
±1
±1
±1
±1
±3
±3
±4
±4
Package
Description
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
100-Lead CSPBGA
100-Lead CSPBGA
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
52-Lead LQFP
64-Lead LFCSP
52-Lead LQFP
64-Lead LFCSP
52-Lead LQFP
64-Lead LFCSP
52-Lead LQFP
64-Lead LFCSP
52-Lead LQFP
64-Lead LFCSP
52-Lead LQFP
64-Lead LFCSP
Package Option
ST-100
ST-100
ST-100
ST-100
BC-100
BC-100
ST-100
ST-100
ST-100
ST-100
ST-52
CP-64
ST-52
CP-64
ST-52
CP-64
ST-52
CP-64
ST-52
CP-64
ST-52
CP-64
Table 2. High Channel Count, Low Voltage, Single-Supply DACs
Model
AD5380BST-5
AD5380BST-3
AD5381BST-5
AD5381BST-3
AD5384BBC-5
AD5384BBC-3
AD5382BST-5
AD5382BST-3
AD5383BST-5
AD5383BST-3
AD5390BST-5
AD5390BCP-5
AD5390BST-3
AD5390BCP-3
AD5391BST-5
AD5391BCP-5
AD5391BST-3
AD5391BCP-3
AD5392BST-5
AD5392BCP-5
AD5392BST-3
AD5392BCP-3
Resolution
14 Bits
14 Bits
12 Bits
12 Bits
14 Bits
14 Bits
14 Bits
14 Bits
12 Bits
12 Bits
14 Bits
14 Bits
14 Bits
14 Bits
12 Bits
12 Bits
12 Bits
12 Bits
14 Bits
14 Bits
14 Bits
14 Bits
AVDD Range
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
2.7 V to 3.6 V
4.5 V to 5.5 V
4.5 V to 5.5 V
2.7 V to 3.6 V
2.7 V to 3.6 V
4.5 V to 5.5 V
4.5 V to 5.5 V
2.7 V to 3.6 V
2.7 V to 3.6 V
4.5 V to 5.5 V
4.5 V to 5.5 V
2.7 V to 3.6 V
2.7 V to 3.6 V
Output
Channels
40
40
40
40
40
40
32
32
32
32
16
16
16
16
16
16
16
16
8
8
8
8
Rev. PrA | Page 3 of 28
AD5378
SPECIFICATIONS
VCC = 2.7 V to 5.5 V; VDD = 11.4 V to 16.5 V; VSS = −11.4 V to −16.5 V; VREF(+) = +5 V; VREF(−) = −3.5 V; AGND = DGND = REFGND =
0 V; VBIAS = 5 V; CL = 200 pF to GND; RL = 11 kΩ to 3 V; gain = 1; offset = 0 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error
Full-Scale Error
Gain Error
VOUT Temperature Coefficient
DC Crosstalk2
REFERENCE INPUTS2
VREF(+) DC Input Impedance
VREF(−) DC Input Impedance
VREF(+) Input Current
VREF(+) Range
VREF(−) Range
REFGND INPUTS2
DC Input Impedance
Input Range
OUTPUT CHARACTERISTICS2
Output Voltage Range
Short-Circuit Current
Load Current
Capacitive Load
DC Output Impedance
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Current (with pull-up/pull-down)
Input Current (no pull-up/pull-down)
Input Capacitance2
DIGITAL OUTPUTS (BUSY, SDO)
Output Low Voltage
Output High Voltage (SDO)
High Impedance Leakage Current
High Impedance Output Capacitance2
A Version1
Unit
Test Conditions/Comments
14
±3
±2.5
−1/+1.5
±12
±5
±12
±8
±8
±1/±5
5
0.5
Bits
LSB max
LSB max
LSB max
mV max
mV max
mV max
mV max
mV max
mV typ/max
ppm FSR/°C typ
mV max
−40°C to +85°C
0°C to 70°C
Guaranteed monotonic by design over temperature
−40°C to +85°C
0°C to 70°C
−40°C to +85°C
0°C to 70°C
−40°C to +85°C
0°C to 70°C
Includes linearity, offset, and gain drift; see Figure 11
Typically 100 µV
1
8
±10
1.5/5
−3.5/0
MΩ min
kΩ min
µA max
V min/max
V min/max
Typically 100 MΩ
Typically 12 kΩ
Per input; typically ±30 nA
±2% for specified operation
±2% for specified operation
80
±0.5
kΩ min
V min/max
Typically 120 kΩ
VSS + 2/VSS + 2.5
VDD − 2/VDD − 2.5
15
±1.5
2200
1
V min
V max
mA max
mA max
pF max
Ω max
ILOAD = ±0.5 mA/±1.5 mA
ILOAD = ±0.5 mA/±1.5 mA
1.7
2.0
0.8
±8
±1
10
V min
V min
V max
µA max
µA max
pF max
0.5
VCC − 0.5
−70
10
V max
V min
µA max
pF typ
Rev. PrA | Page 4 of 28
JEDEC-compliant
VCC = 2.7 V to 3.6 V
VCC = 3.6 V to 5.5 V
VCC = 2.7 V to 5.5 V
SER/PAR, FIFOEN, and RESET pins only
All other digital input pins
Sinking 200 µA
Sourcing 200 µA
SDO only
Preliminary Technical Data
Parameter
POWER REQUIREMENTS
VCC
VDD
VSS
Power Supply Sensitivity2
∆ Full Scale/∆ VDD
∆ Full Scale/∆ VSS
∆ Full Scale/∆ VCC
ICC
IDD
ISS
Power Dissipation
Power Dissipation Unloaded (P)
Power Dissipation Loaded (PTOTAL)
Junction Temperature
AD5378
A Version1
Unit
2.7/5.5
8.5/16.5
−3/−16.5
V min/max
V min/max
V min/max
−75
−75
−90
5
28
23
dB typ
dB typ
dB typ
mA max
mA max
mA max
VCC = 5.5 V, VIH = VCC, VIL = GND
Outputs unloaded; typically 20 mA
Outputs unloaded; typically 15 mA
850
2000
130
mW max
mW max
°C max
VDD = 16.5 V, VSS = −16.5 V
PTOTAL = P + Σ(VDD − VO) × ISOURCE + Σ(VO − VSS) × ISINK
TJ = TA + PTOTAL × θJ3
Test Conditions/Comments
1
Temperature range for the A version: −40°C to +85°C. Typical specifications are at 25°C.
Guaranteed by design and characterization; not production tested.
3
Where θJ represents the package thermal impedance.
2
AC CHARACTERISTICS
VCC = 2.7 V to 5.5 V; VDD = 11.4 V to 16.5 V; VSS = −11.4 V to −16.5 V; VREF(+) = +5 V; VREF(−) = −3.5 V;
AGND = DGND = REFGND = 0 V; VBIAS = 5 V; CL = 220 pF; RL = 11 kΩ to 3 V; gain = 1; offset = 0 V.
Table 4.
A Version1
Unit
Test Conditions/Comments
20
30
µs typ
µs max
Full-scale change to ±1/2 LSB
DAC latch contents alternately loaded with all 0s and
all 1s
Slew Rate
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Channel-to-Channel Isolation
DAC-to-DAC Crosstalk
1
20
15
100
40
V/µs typ
nV-s typ
mV max
dB typ
nV-s typ
Digital Crosstalk
Digital Feedthrough
Output Noise Spectral Density @ 1 kHz
10
0.1
1
350
nV-s typ
nV-s typ
nV-s typ
nV/(Hz)1/2 typ
Parameter
DYNAMIC PERFORMANCE
Output Voltage Settling Time
1
Guaranteed by design and characterization; not production tested.
Rev. PrA | Page 5 of 28
VREF(+) = 2 V p-p, (1 VBIAS) 1 kHz, VREF(−) = −1 V
See the Terminology section; between DACs inside a
group
Between DACs from different groups
Effect of input bus activity on DAC output under test
VREF(+) = VREF(−) = 0 V
AD5378
TIMING CHARACTERISTICS
SERIAL INTERFACE
VCC = 2.7 V to 5.5 V; VDD = 11.4 V to 16.5 V; VSS = −11.4 V to −16.5 V; VREF(+) = +5 V; VREF(−) = −3.5 V;
AGND = DGND = REFGND = 0 V; VBIAS = 5 V, FIFOEN = 0 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 5.
Parameter1, 2, 3
t1
t2
t3
t4
t54
t64
t7
t8
t9
t104, 5
t11
t124
t13
t14
t15
t16
t17
t18
t19
t206, 7
t217
t227
t237
t245
t25
t26
Limit at TMIN, TMAX
20
8
8
10
15
25
10
5
4.5
30
330
20
20
150
0
100
20/30
10
350
25
5
5
20
30
10
120
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns typ
ns min
ns min
µs typ/max
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
µs max
Description
SCLK Cycle Time.
SCLK High Time.
SCLK Low Time.
SYNC Falling Edge to SCLK Falling Edge Setup Time.
24th SCLK Falling Edge to SYNC Falling Edge.
Minimum SYNC Low Time.
Minimum SYNC High Time.
Data Setup Time.
Data Hold Time.
24th SCLK Falling Edge to BUSY Falling Edge.
BUSY Pulse Width Low (Single-Channel Update). See Table 11.
24th SCLK Falling Edge to LDAC Falling Edge.
LDAC Pulse Width Low.
BUSY Rising Edge to DAC Output Response Time.
BUSY Rising Edge to LDAC Falling Edge.
LDAC Falling Edge to DAC Output Response Time.
DAC Output Settling Time.
CLR Pulse Width Low.
CLR/RESET Pulse Activation Time.
SCLK Rising Edge to SDO Valid.
SCLK Falling Edge to SYNC Rising Edge.
SYNC Rising Edge to SCLK Rising Edge.
SYNC Rising Edge to LDAC Falling Edge.
SYNC Rising Edge to BUSY Falling Edge.
RESET Pulse Width Low.
RESET Time Indicated by BUSY Low.
1
Guaranteed by design and characterization; not production tested.
All input signals are specified with tr = tf = 2 ns (10% to 90% of VCC) and timed from a voltage level of 1.2 V.
See Figure 4 and Figure 5.
4
Standalone mode only.
5
This is measured with the load circuit of Figure 2.
6
This is measured with the load circuit of Figure 3.
7
Daisy-chain mode only.
2
3
VCC
200µA
TO
OUTPUT
PIN
VOL
CL
50pF
VOH(min) + VOL(max)
CL
2
50pF
200µA
IOH
Figure 3. Load Circuit for SDO Timing Diagram
(Serial Interface, Daisy-Chain Mode)
Figure 2. Load Circuit for BUSY Timing Diagram
Rev. PrA | Page 6 of 28
05292-003
TO
OUTPUT
PIN
2.2kΩ
05292-002
RL
IOL
Preliminary Technical Data
AD5378
t1
SCLK
1
2
24
t3
t4
SYNC
t7
24
t2
t5
t6
t8 t9
DB23
DIN
DB0
t10
t11
BUSY
t12
t13
t17
LDAC1
t14
VOUT1
t15
t13
LDAC2
t16
VOUT2
t17
t18
CLR
t19
VOUT
1LDAC
2LDAC
ACTIVE DURING BUSY.
ACTIVE AFTER BUSY.
t25
RESET
BUSY
t19
05292-004
VOUT
t26
Figure 4. Serial Interface Timing Diagram (Standalone Mode)
Rev. PrA | Page 7 of 28
AD5378
t1
SCLK
24
t3
t7
48
t22
t2
t21
t4
SYNC
t8
DIN
t9
D23
D0
D23'
INPUT WORD FOR DAC N
D0'
INPUT WORD FOR DAC N+1
t20
SDO
D23
UNDEFINED
D0
INPUT WORD FOR DAC N
t23
t13
LDAC
t11
BUSY
Figure 5. Serial Interface Timing Diagram (Daisy-Chain Mode)
Rev. PrA | Page 8 of 28
05292-005
t24
Preliminary Technical Data
AD5378
PARALLEL INTERFACE
VCC = 2.7 V to 5.5 V; VDD = 11.4 V to 16.5 V; VSS = −11.4 V to −16.5 V; AGND = DGND = DUTGND = 0 V; VREF(+) = +5 V;
VREF(−) = −3.5 V, FIFOEN = 0 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 6.
Parameter1, 2, 3
t0
t1
t2
t3
t4
t5
t6
t7
t8
t9
t104
t114
t12
t13
t14
t154
t16
t17
t18
t19
t20
t21
t22
t23
Limit at TMIN to TMAX
4.5
4.5
10
10
0
0
4.5
4.5
20
240
0/30
330
0
30
20
150
20
0
100
20/30
10
350
10
120
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min/max
ns max
ns min
ns min
ns min
ns typ
ns min
ns min
ns typ
µs typ/ max
ns min
ns max
ns min
µs max
Description
REG0, REG1, Address to WR Rising Edge Setup Time.
REG0, REG1, Address to WR Rising Edge Hold Time.
CS Pulse Width Low.
WR Pulse Width Low.
CS to WR Falling Edge Setup Time.
WR to CS Rising Edge Hold Time.
Data to WR Rising Edge Setup Time.
Data to WR Rising Edge Hold Time.
WR Pulse Width High.
Minimum WR Cycle Time (Single-Channel Write).
WR Rising Edge to BUSY Falling Edge.
BUSY Pulse Width Low (Single-Channel Update). See Table 11.
BUSY Rising Edge to WR Rising Edge.
WR Rising Edge to LDAC Falling Edge.
LDAC Pulse Width Low.
BUSY Rising Edge to DAC Output Response Time.
LDAC Rising Edge to WR Rising Edge.
BUSY Rising Edge to LDAC Falling Edge.
LDAC Falling Edge to DAC Output Response Time.
DAC Output Settling Time.
CLR Pulse Width Low.
CLR/RESET Pulse Activation Time.
RESET Pulse Width Low.
RESET Time Indicated by BUSY Low.
1
Guaranteed by design and characterization; not production tested.
All input signals are specified with tr = tf = 2 ns (10% to 90% of VCC) and timed from a voltage level of 1.2 V.
3
See Figure 6.
4
Measured with load circuit in Figure 2.
2
Rev. PrA | Page 9 of 28
AD5378
t0
t1
REG0,
REG1,
A7–A02
t4
t5
t2
CS
t9
t3
WR
t8
t6
t16
t7
DB12–DB0
t12
t10
t11
BUSY
t13
t14
t19
LDAC1
t15
VOUT1
t17
t14
LDAC2
t18
VOUT2
t19
t20
CLR
t21
VOUT
1LDAC
2LDAC
ACTIVE DURING BUSY.
ACTIVE AFTER BUSY.
t22
RESET
t21
t23
BUSY
Figure 6. Parallel Interface Timing Diagram
Rev. PrA | Page 10 of 28
05292-006
VOUT
Preliminary Technical Data
AD5378
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Transient currents of up to 100 mA do not cause SCR latch-up.
Table 7.
Parameter
VDD to AGND
VSS to AGND
VCC to DGND
Digital Inputs to DGND
Digital Outputs to DGND
VREF1(+), VREF2(+) to AGND
VREF1(−), VREF2(−) to AGND
VBIAS to AGND
VOUT0–VOUT31 to AGND
REFGND to AGND
AGND to DGND
Operating Temperature Range (TA)
Industrial (A Version)
Storage Temperature Range
Junction Temperature (TJ max)
108-Lead CSPBGA Package
θJA Thermal Impedance
θJC Thermal Impedance
Reflow Soldering
Peak Temperature
Time at Peak Temperature
Rating
−0.3 V to +17 V
−17 V to +0.3 V
−0.3 V to +7 V
−0.3 V to VCC + 0.3 V
−0.3 V to VCC + 0.3 V
−0.3 V to +7 V
VSS − 0.3 V to VDD + 0.3 V
−0.3 V to +7 V
VSS − 0.3 V to VDD + 0.3 V
VSS − 0.3 V to VDD + 0.3 V
−0.3 V to +0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Only one absolute maximum rating may be
applied at any one time.
−40°C to +85°C
−65°C to +150°C
150°C
37.5°C/W
8.5°C/W
230°C
10 sec to 40 sec
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrA | Page 11 of 28
AD5378
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9 10 11 12
A
A
B
B
C
C
D
D
F
AD5378
F
G
TOP VIEW
G
H
H
J
J
K
K
L
L
M
M
1
2
3
4
5
6
7
8
9 10 11 12
05292-007
E
E
Figure 7. Pin Configuration
Table 8. 108-Lead CSPBGA Ball Configuration
CSPBGA No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
B1
B2
B3
B4
Ball Name
REG0
VCC3
DB10
AGND4
VBIAS
VOUT5
AGND3
REFGNDA1
VDD5
VSS5
VSS4
VDD4
REG1
DGND4
DB9
CLR
B5
B6
B7
B8
B9
B10
B11
B12
C1
C2
C3
AGND
AGND
VOUT0
VOUT1
VOUT2
VOUT25
REFGNDD1
VOUT24
DB13
DB12/SCLK
DB11/DIN
CSPBGA No.
C4
SER/PAR1
Ball Name
C5
LDAC
C6
C7
C8
C9
C10
C11
C12
D1
D2
D3
D10
D11
D12
E1
E2
E3
E10
E11
E12
F1
F2
F3
F10
F11
F12
VOUT6
VOUT3
VOUT4
VOUT7
VOUT28
VOUT26
VOUT27
DB7
DB8
DGND1
VREF1(−)
VOUT29
AGND
DB5
DB6
VCC1
REFGNDB2
AGND
VOUT30
DB4
DB3
DB2
VDD3
REFGNDD2
VOUT31
CSPBGA No.
G1
G2
G3
Ball Name
DB1
DB0
BUSY
G10
G11
G12
H1
VSS3
VOUT23
REFGNDC2
WR/DCEN
H2
H3
SDO3
CS/SYNC
H10
H11
H12
J1
J2
J3
J10
J11
J12
K1
K2
K3
K4
K5
K6
K7
K8
K9
VOUT22
AGND
AGND
A0
A1
A2
VOUT15
VOUT20
VOUT21
A4
A5
A3
DGND2
REFGNDA2
VREF2(−)
VOUT10
VOUT11
AGND
_________________________
1
Internal 1 MΩ pull-down device on this logic input. Therefore, it can be left floating, and it defaults to a logic low condition.
2
N/C—Do not connect to this pin. Internal active pull-up device on these logic inputs. They default to a logic high condition.
3
Internal 1 MΩ pull-up device on this logic input. Therefore, it can be left floating, and it defaults to a logic high condition.
Rev. PrA | Page 12 of 28
CSPBGA No.
K10
K11
K12
L1
L2
L3
L4
Ball Name
VOUT14
VOUT18
VOUT19
A7
A6
N/C2
RESET3
L5
L6
L7
L8
L9
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
AGND
AGND2
VOUT12
VOUT8
VDD1
VREF2(+)
VOUT16
VOUT17
DGND3
VCC2
FIFOEN1
AGND1
VOUT13
VOUT9
REFGNDB1
VREF1(+)
VSS1
VSS2
VDD2
REFGNDC1
Preliminary Technical Data
AD5378
Table 9. Pin Function Descriptions
Pin
VCC(1–3)
VSS(1–5)
VDD(1–5)
AGND(1–4)
DGND(1–4)
VREF1(+), VREF1(−)
VREF2(+), VREF2(−)
VBIAS
VOUT0 to VOUT31
SER/PAR
SYNC1
SCLK1
DIN1
SDO1
DCEN1
CS
WR
DB13 to DB0
A0 to A7
REG0
REG1
CLR
BUSY
LDAC
Description
Logic Power Supply. 2.7 V to 5.5 V. These pins should be decoupled with 0.1 µF ceramic capacitors and 10 µF tantalum
capacitors.
Negative Analog Power Supply. −11.4 V to −16.5 V for specified performance. These pins should be decoupled with
0.1 µF ceramic capacitors and 10 µF tantalum capacitors.
Positive Analog Power Supply. +11.4 V to +16.5 V for specified performance. These pins should be decoupled with
0.1 µF ceramic capacitors and 10 µF tantalum capacitors.
Ground for All Analog Circuitry. All AGND pins should be connected to the AGND plane.
Ground for All Digital Circuitry. All DGND pins should be connected to the DGND plane.
Reference Inputs for DACs 0 to 5, 8 to 13, 16 to 21, and 24 to 30. These voltages are referred to AGND.
Reference Inputs for DACs 6, 7, 14, 15, 22, 23, 30, and 31. These reference voltages are referred to AGND.
DAC Bias Voltage Input/Output. This pin provides an access to the on-chip voltage generator voltage. It is provided
for bypassing and overdriving purposes only.
If VREF(+) > 4.25 V, VBIAS must be pulled high externally to an equal or higher potential, for example, 5 V.
If VREF(+) < 4.25 V, the on-chip bias generator can be used. In this case, the VBIAS pin should be decoupled with a 10 nF
capacitor to AGND.
DAC Outputs. Buffered analog outputs for each of the 32 DAC channels. Each analog output can drive an output load
of 5 kΩ to ground. Typical output impedance of these amplifiers is 1 Ω.
Interface Select Input. This pin allows the user to select whether the serial or parallel interface is used. This pin has an
internal 1 MΩ pull-down resistor, meaning that the default state at power-on is parallel mode. If this pin is tied high,
the serial interface is used.
Active Low Input. This is the frame synchronization signal for the serial interface.
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This pin operates at clock speeds
up to 50 MHz.
Serial Data Input. Data must be valid on the falling edge of SCLK.
Serial Data Output. CMOS output. SDO can be used for daisy-chaining several devices together. Data is clocked out on
SDO on the rising edge of SCLK and is valid on the falling edge of SCLK.
Daisy-Chain Select Input. Level sensitive, active high. When high, this signal is used in conjunction with SER/PAR high
to enable serial interface daisy-chain mode.
Parallel Interface Chip Select Input. Level sensitive, active low. When this pin is low, the device is selected.
Parallel Interface Write Input. Edge sensitive. The rising edge of WR is used in conjunction with CS low and the
address bus inputs to write to the selected AD5378 registers.
Parallel Data Inputs. The AD5378 can accept a straight 14-bit parallel word on DB0 to DB13, where DB13 is the MSB
and DB0 is the LSB.
Parallel Address Inputs. A7 to A4 are decoded to select one group or multiple groups of registers (input registers, gain
registers (m), or offset registers (c)) for a data transfer. This pin is used in conjunction with the REG1 and REG0 pins to
determine the destination register for the input data. See the Parallel Interface section for details of the address
decoding.
Parallel Interface Register Select Input. This pin is used together with REG1 to select data registers, gain registers,
offset registers, increment/decrement mode, or the soft reset function. See Table 12.
Parallel Interface Register Select Input. This pin is used together with REG0 to select data registers, gain registers,
offset registers, increment/decrement mode, or the soft reset function. See Table 12.
Asynchronous Clear Input. Level sensitive, active low. When CLR is low, the input to each of the DAC output buffer
stages, VOUT0 to VOUT31, is switched to the externally set potential on the relevant REFGND pin. While CLR is low, all
LDAC pulses are ignored. When CLR is taken high again, the DAC outputs remain cleared until LDAC is taken low. The
contents of input registers and DAC Registers 0 to 31 are not affected by taking CLR low.
Digital Input/Open-Drain Output. This pin must be pulled high with a pull-up resistor for correct operation. BUSY goes
low during internal calculations of x2. During this time, the user can continue writing new data to additional ×1, c,
and m registers (these are stored in a FIFO), but no further updates to the DAC registers and DAC outputs can take
place. If LDAC is taken low while BUSY is low, this event is stored. Because BUSY is bidirectional, it can be pulled low
externally to delay LDAC action. BUSY also goes low during power-on reset or when the RESET pin is low. During a
RESET operation, the parallel interface is disabled and any events on LDAC are ignored.
Load DAC Logic Input. Active low. If LDAC is taken low while BUSY is inactive (high), the contents of the input
registers are transferred to the DAC registers, and the DAC outputs are updated. If LDAC is taken low while BUSY is
active and internal calculations are taking place, the LDAC event is stored and the DAC registers are updated when
BUSY goes inactive. However, any events on LDAC during power-on reset or RESET are ignored.
Rev. PrA | Page 13 of 28
AD5378
Pin
FIFOEN
RESET
REFGNDA1
REFGNDA2
REFGNDB1
REFGNDB2
REFGNDC1
REFGNDC2
REFGNDD1
REFGNDD2
1
Description
FIFO Enable. Level sensitive, active high. When connected to DVDD, the internal FIFO is enabled, allowing the user to
write to the device at full speed. FIFO is available in both serial and parallel modes. The FIFOEN pin has an internal
1 MΩ pull-down resistor connected to ground, meaning that the FIFO is disabled by default.
Asynchronous Digital Reset Input. Falling edge sensitive. If unused, RESET can be left unconnected; an internal pullup resistor (1 MΩ) ensures that the RESET input is held high. The function of this pin is equivalent to that of the
power-on reset generator. When this pin is taken low, the AD5378 state machine initiates a reset sequence to digitally
reset the x1, m, c, and x2 registers to their default power-on values. This sequence takes 100 µs (typ). Furthermore, the
input to each of the DAC output buffer stages, VOUT0 to VOUT31, is switched to the externally set potential on the
relevant REFGND pin. During RESET, BUSY goes low and the parallel interface is disabled. All LDAC pulses are ignored
until BUSY goes high. When RESET goes high again, the DAC ouputs remain at REFGND until LDAC is taken low.
Reference Ground for DACs 0 to 5. VOUT0 to VOUT5 are referenced to this voltage.
Reference Ground for DACs 6 and 7. VOUT6 and VOUT7 are referenced to this voltage.
Reference Ground for DACs 8 to 13. VOUT8 to VOUT13 are referenced to this voltage.
Reference Ground for DACs 14 and 15. VOUT14 and VOUT15 are referenced to this voltage.
Reference Ground for DACs 16 to 21. VOUT16 to VOUT21 are referenced to this voltage.
Reference Ground for DACs 22 and 23. VOUT22 and VOUT23 are referenced to this voltage.
Reference Ground for DACs 24 to 29. VOUT24 to VOUT29 are referenced to this voltage.
Reference Ground for DACs 30 and 31. VOUT30 and VOUT31 are referenced to this voltage.
These serial interface signals do not require separate pins, but share parallel interface pins.
Rev. PrA | Page 14 of 28
Preliminary Technical Data
AD5378
TYPICAL PERFORMANCE CHARACTERISTICS
1.5
3
VDD = +12V
VSS = –12V
VREF(+) = +5V
VREF(–) = –3.5V
TMAX = 85°C
2
1.0
1
FS
ERROR (mV)
0
0
–1
ZC
–0.5
–2
VDD = +12V
VSS = –12V
VREF(+) = +5V
VREF(–) = –3.5V
TA = 25°C
–3
–1.5
0
2
4
6
8
10
12
14
16
AD5378 CODE (103)
–4
–40
05292-008
–1.0
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 8. Typical INL Plot
05292-011
INL (LSBs)
0.5
Figure 11. Typical Full-Scale and Zero-Scale Errors vs. Temperature
1400
19.0
VDD = +12V
VSS = –12V
VREF(+) = +5V
VREF(–) = –3.5V
1200
18.9
VDD = +12V VREF(+) = +5V
VSS = –12V VREF(–) = –3.5V
18.8
+85°C
1000
800
IDD (mA)
FREQUENCY
18.7
600
18.6
+25°C
18.5
18.4
400
–40°C
18.3
200
–3
–2
–1
0
1
2
3
INL ERROR (LSB)
18.1
10.0
05292-009
0
10.5
12.0
12.5
13.0
13.5
14.0
14.5
15.0
Figure 12. IDD vs. VDD over Temperature
–14.6
3
VDD = +12V
VSS = –12V
VREF(+) = +5V
VREF(–) = –3.5V
TMAX = 85°C
VDD = +12V VREF(+) = +5V
VSS = –12V VREF(–) = –3.5V
–14.8
–40°C
–15.0
ISS (mA)
1
0
–15.2
+25°C
–1
–15.4
–2
–15.6
–3
–40
–15.8
10.0
–20
0
20
40
60
TEMPERATURE (°C)
80
Figure 10. Typical INL Error vs. Temperature
10.5
11.0
11.5
12.0
12.5
13.0
13.5
14.0
VDD (V)
Figure 13. ISS vs. VDD over Temperature
Rev. PrA | Page 15 of 28
14.5
15.0
05292-013
+85°C
05292-010
INL ERROR (LSB)
11.5
VDD (V)
Figure 9. INL Error Distribution
(−40°C, +25°C, +85°C Superimposed)
2
11.0
05292-012
18.2
AD5378
3.5
VDD = +12V
VSS = –12V
VREF(+) = +5V
VREF(–) = –3.5V
3.0
TA = 25°C
VDD = +12V
VSS = –12V
VREF(+) = +5V
VREF(–) = –3.5V
VOUT
ICC (mA)
2.5
2.0
1.5
+85°C
1.0
–40°C
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
10V
Figure 14. ICC vs. Supply
Figure 17. DAC-to-DAC Crosstalk
–0.208
1.75
TA = 25°C
VDD = +12V
VSS = –12V
VREF(+) = +5V
VREF(–) = –3.5V
–0.211
TA = 25°C
VDD = +12V
VSS = –12V
VREF(+) = +5V
VREF(–) = –3.5V
VCC = +3.3V
1.70
1.65
1.60
–0.214
ICC (mA)
AMPLITUDE (V)
5mV
05292-017
0
2.5
+25°C
05292-014
0.5
–0.217
1.55
1.50
1.45
1.40
–0.220
4
8
12
16
20
TIME (µs)
1.30
Figure 15. Major Code Transition Glitch Energy
–0.209
–0.210
–0.211
2.8
4.2
TIME (µs)
5.6
6.0
05292-016
AMPLITUDE (V)
TA = 25°C VSS = –12V VREF(–) = –3.5V
VDD = +12V VREF(+) = +5V
1.4
0.4
0.8
1.2
1.6
2.0
2.4
2.8
INPUT VOLTAGE (V)
Figure 18. Supply Current vs. Digital Input Voltage
–0.208
0
0
Figure 16. Digital Feedthrough
Rev. PrA | Page 16 of 28
3.2
05292-018
0
05292-015
1.35
–0.223
Preliminary Technical Data
AD5378
TERMINOLOGY
Relative Accuracy
Relative accuracy or endpoint linearity is a measurement of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero-scale error and full-scale error and is
expressed in least significant bits (LSB).
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
Zero-Scale Error
Zero-scale error is the error in the DAC output voltage when all
0s are loaded into the DAC register.
Ideally, with all 0s loaded to the DAC and m is all 1s,
c is 10 0000 0000 0000:
VOUT(zero-scale) = 2.5 × VREF(−) − AGND) + REFGND
Zero-scale error is a measurement of the difference between
VOUT (actual) and VOUT (ideal) expressed in mV. Zero-scale
error is mainly due to offsets in the output amplifier.
Full-Scale Error
Full-scale error is the error in DAC output voltage when all 1s
are loaded into the DAC register.
Ideally, with all 1s loaded to the DAC and m is all 1s,
c is 10 0000 0000 0000:
VOUT(full-scale) = 3.5 × (VREF(+) − AGND) + 2.5 ×
(VREF(−)− AGND) + REFGND
Full-scale error is a measurement of the difference between
VOUT (actual) and VOUT (ideal) expressed in mV. It does not
include zero-scale error.
Gain Error
Gain error is the difference between full-scale error and zeroscale error. It is expressed in mV.
Gain Error = Full-Scale Error − Zero-Scale Error
VOUT Temperature Coefficient
This includes output error contributions from linearity, offset,
and gain drift.
DC Output Impedance
DC output impedance is the effective output source resistance.
It is dominated by package lead resistance.
DC Crosstalk
The 32 DAC outputs are buffered by op amps that share
common VDD and VSS power supplies. If the dc load current
changes in one channel (due to an update), this can result in a
further dc change in one or more channel outputs. This effect is
more significant at high load currents and reduces as the load
currents are reduced. With high impedance loads, the effect is
virtually unmeasurable. Multiple VDD and VSS terminals are
provided to minimize dc crosstalk.
Output Voltage Settling Time
This is the amount of time it takes for the output of a DAC to
settle to a specified level for a full-scale input change.
Digital-to-Analog Glitch Energy
This is the amount of energy injected into the analog output at
the major code transition. It is specified as the area of the glitch
in nV-s. It is measured by toggling the DAC register data
between 0x1FFF and 0x2000.
Channel-to-Channel Isolation
Channel-to-channel isolation refers to the proportion of input
signal from one DAC’s reference input that appears at the
output of another DAC operating from another reference. It is
expressed in dB and measured at midscale.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse that appears at the
output of one converter due to both the digital change and
subsequent analog output change at another converter. It is
specified in nV-s.
Digital Crosstalk
The glitch impulse transferred to the output of one converter
due to a change in the DAC register code of another converter is
defined as the digital crosstalk and is specified in nV-s.
Digital Feedthrough
When the device is not selected, high frequency logic activity
on the device’s digital inputs can be capacitively coupled both
across and through the device to show up as noise on the
VOUT pins. It can also be coupled along the supply and ground
lines. This noise is digital feedthrough.
Output Noise Spectral Density
This is a measurement of internally generated random noise.
Random noise is characterized as a spectral density (voltage per
√Hz). It is measured by loading all DACs to midscale and
measuring noise at the output. It is measurement in nV/(Hz)1/2.
Rev. PrA | Page 17 of 28
AD5378
FUNCTIONAL DESCRIPTION
DAC ARCHITECTURE—GENERAL
The AD5378 contains 32 DAC channels and 32 output amplifiers
in a single package. The architecture of a single DAC channel
consists of a 14-bit resistor-string DAC followed by an output
buffer amplifier. The resistor-string section is simply a string of
resistors, each of value R, from VREF(+) to AGND. This type of
architecture guarantees DAC monotonicity. The 14-bit binary
digital code loaded to the DAC register determines at which
node on the string the voltage is tapped off before being fed into
the output amplifier. The output amplifier translates the output
of the DAC to a wider range. The DAC output is gained up by a
factor of 3.5 and offset by the voltage on the VREF(−) pin. See the
Transfer Function section.
Figure 19 shows a single DAC channel and its associated
registers. The power-on values for the m and c registers are full
scale and 0x2000, respectively. The user can individually adjust
the voltage range on each DAC channel by overwriting the
power-on values of m and c. The AD5378 has digital overflow
and underflow detection circuitry to clamp the DAC output at
full scale or at zero scale when the values chosen for x1, m, and
c result in x2 being out of range.
DAC
x1 INPUT
REG
INPUT
DATA
The 32 DAC channels on the AD5378 are arranged into four
groups (A, B, C, D) of eight channels. In each group, six
channels are connected to VREF1(+) and VREF1(−); the remaining
two channels are connected to VREF2(+) and VREF2(−). Each
group has two individual REFGND pins. For example, in
Group A, six channels are connected to REFGNDA1, and the
remaining two channels are connected to REFGNDA2. In
addition to an input register (x1) and a DAC register (x2), each
channel has a gain register (m) and an offset register (c). See
Table 18. Including these registers allows the user to calibrate
out errors in the complete signal chain, including the DAC
errors.
Table 10 shows the reference and REFGND inputs, and the
m and c registers for Group A. Groups B, C, and D are similar.
Table 10. Inputs and Registers for Group A
Reference
VREF1(+), VREF1(−)
REFGND
REFGNDA1
6…7
VREF2(+), VREF2(−)
REFGNDA2
m, c Registers
m REG0…5
c REG0…5
m REG6…7
c REG6…7
x2
REG
DAC
REG
DAC
VDAC
c REG
AGND
Figure 19. Single DAC Channel
The complete transfer function for the AD5378 can be
represented as
VOUT = 3.5 × ((VREF(+)− AGND) × x2/214) +
2.5 × (VREF(−)− AGND) + REFGND
where:
x2 is the data-word loaded to the resistor string DAC.
VREF(+) is the voltage at the positive reference pin.
VREF(−) is the voltage at the negative reference pin.
Figure 20 shows the output amplifier stage of a single channel.
VDAC is the voltage output from the resistor string DAC. The
nominal range of VDAC is 1 LSB to full scale.
VDAC
TRANSFER FUNCTION
VOUT
The digital input transfer function for each DAC can be
represented as
VREF(–)
R
2.5R
R
x2 = [(m + 1)/213 × x1] + (c − 2n−1)
R
where:
x2 is the data-word loaded to the resistor string DAC.
The default is 10 0000 0000 0000.
x1 is the 14-bit data-word written to the DAC input register.
The default is 10 0000 0000 0000.
m is the 13-bit gain coefficient. The default is 1 1111 1111 1111.
c is the 14-bit offset coefficient. The default is 10 0000 0000 0000.
n is the DAC resolution. n = 14.
REFGND
Rev. PrA | Page 18 of 28
2.5R
AGND
Figure 20. Output Amplifier Stage
05292-020
Channel
0…5
x2
m REG
05292-019
CHANNEL GROUPS
VREF(+)
LDAC
Preliminary Technical Data
AD5378
VBIAS FUNCTION
The AD5378 on-chip voltage generator provides a bias voltage
of 4.25 V (min). The VBIAS pin is provided for bypassing and
overdriving purposes only. It is not intended to be used as a
supply or a reference. If VREF(+) > 4.25 V, VBIAS must be pulled
high externally to an equal or higher potential such as 5 V. The
external voltage source should be capable of driving a 50 µA
(typical) current sink load.
REFERENCE SELECTION
The voltages applied to VREF(+) and VREF(−) determine the
output voltage range and span on VOUT0 to VOUT31. If the
offset and gain features are not used (m and c are left at their
power-on values), the reference levels required can be
calculated as follows:
VREF(+)min = (VOUTmax − VOUTmin)/3.5
VREF(−)max = (AGND + VOUTmin)/2.5
If the offset and gain features of the AD5378 are used, the
output range required is slightly different. The output range
chosen should take into account the offset and gain errors that
need to be trimmed out. Therefore, the output range should be
larger than the actual required range.
If this offset error too large to calibrated out, it is possible to
adjust the negative reference value to account for this by using
the following equation:
VREF(−)NEW = VREF(−)A − VOFFSET/2.625
Reference Selection Example
Nominal Output Range = 10 V; (−2 V to +8 V)
Offset Error = ±100 mV
Gain Error = ±3%
REFGND = AGND = 0 V
1.
Gain Error = ±3%;
=> Maximum Positive Gain Error = +3%
=> Output Range including Gain Error =
10 + 0.03 (10) = 10.3 V
2.
Offset Error = ±100 mV;
=> Maximum Offset Error Span = 2(100) mV = 0.2 V
=> Output Range including Gain Error and Offset Error =
10.3 + 0.2 = 10.5 V
3.
VREF(+) and VREF(−) Calculation:
Actual Output Range = 10.5 V, that is, −2.25 V to +8.25 V
(centered);
=> VREF(+) = (8.25 + 2.25)/3.5 = 3 V and
VREF(−) = −2.25/2.5 = −0.9 V
The reference levels required can be calculated as follows:
1.
Identify the nominal output range on VOUT.
2.
Identify the maximum offset span and the maximum gain
required on the full output signal range.
3.
Calculate the new maximum output range on VOUT,
including the maximum offset and gain errors expected.
4.
Choose the new VOUTmax and VOUTmin required, keeping
the new VOUT limits centered on the nominal values and
assuming REFGND is 0 V (or equal to AGND). VDD and
VSS must provide sufficient headroom.
5.
Calculate the values of VREF(+) and VREF(−) as follows:
If the solution yields inconvenient reference levels, the user can
adopt one of these approaches:
•
Use a resistor divider to divide down a convenient, higher
reference level to the required level.
•
Select convenient reference levels above VREF(+)min or below
VREF(−)max. Modify the gain and offset registers to downsize
the references digitally. In this way, the user can use almost
any convenient reference level, but can reduce performance
by overcompaction of the transfer function.
•
Use a combination of these two approaches.
VREF(+)min = (VOUTmax − VOUTmin)/3.5
VREF(−)max = (AGND + VOUTmin)/2.5
In addition, when using reference values other than those
suggested (VREF(+) = 5 V and VREF(−) = −3.5 V), the expected
offset error component changes as follows:
VOFFSET = 0.125 × (VREF(−)A + 0.7 × VREF(+)A)
where:
VREF(−)A is the new negative reference value.
VREF(+)A is the new positive reference value.
Rev. PrA | Page 19 of 28
AD5378
CALIBRATION
Software Clear
The user can perform a system calibration by overwriting the
default values in the m and c registers for any individual DAC
channel as follows:
Loading a clear code to the x1 registers also enables the user to
set VOUT0 to VOUT31 to the REFGND level. The default clear
code corresponds to m at full scale and c at midscale (x2 = x1).
1.
Calculate the nominal offset and gain coefficients for the
new output range (see the revious example).
2.
Calculate the new m and c values for each channel based
on the specified offset and gain errors.
Default Clear Code
= 214 × (−Output Offset)/(Output Range)
= 214 × 2.5 × (AGND − VREF(−))/(3.5 × (VREF(+)− AGND))
The more general expression for the clear code is as follows:
Clear Code = (214)/(m + 1) × (Default Clear Code − c)
Calibration Example
Nominal Offset Coefficient = 0
Nominal Gain Coefficient = 10/10.5 × 8191 = 0.95238 × 8191
= 7801
Example 1: Channel 0, Gain Error = 3%,
Offset Error = 100 mV
1.
Gain Error (3%) Calibration: 7801 × 1.03 = 8035
=> Load Code 1 1111 0110 0011 to m Register 0
2.
Offset Error (100 mV) Calibration:
LSB Size = 10.5 / 16384 = 641 µV;
Offset Coefficient for 100 mV Offset = 100 / 0.64 = 156 LSBs
=> Load 10 0000 1001 1100 to c Register 0
BUSY AND LDAC FUNCTIONS
The value of x2 is calculated each time the user writes new data
to the corresponding x1, c, or m registers. During the calculation of x2, the BUSY output goes low. While BUSY is low, the
user can continue writing new data to the x1, m, or c registers,
but no DAC output updates can take place. The DAC outputs
are updated by taking the LDAC input low. If LDAC goes low
while BUSY is active, the LDAC event is stored and the DAC
outputs update immediately after BUSY goes high. A user can
also hold the LDAC input permanently low. In this case, the
DAC outputs update immediately after BUSY goes high.
Table 11. BUSY Pulse Width
Example 2: Channel 1, Gain Error = −3%,
Offset Error = −100 mV
1.
Gain Error (−3%) Calibration: 7801 × 0.97 = 7567
=> Load Code 1 1110 1000 1111 to m Register 1
2.
Offset Error (−100 mV) Calibration:
LSB Size = 10.5 / 16384 = 641 µV;
Offset Coefficient for −100 mV Offset = −100 / 0.64 =
−156 LSBs
=> Load 01 1111 0110 0100 to c Register 1
BUSY Pulse Width (ns max)
Action
Loading x1, c, or m to 1 channel
Loading x1, c, or m to 2 channels
Loading x1, c, or m to 3 channels
Loading x1, c, or m to 4 channels
Loading x1, c, or m to all 32
channels
CLEAR FUNCTION
The clear function on the AD5378 can be implemented in
hardware or software.
Hardware Clear
Bringing the CLR pin low switches the outputs, VOUT0 to
VOUT31, to the externally set potential on the REFGND pin.
This is achieved by switching in REFGND and reconfiguring
the output amplifier stages into unity gain buffer mode, thus
ensuring that VOUT is equal to REFGND. The contents of the
input registers and DAC registers are not affected by taking
CLR low. When CLR is brought high, the DAC outputs remain
cleared until LDAC is taken low. While CLR is low, the value of
LDAC is ignored.
FIFO
Enabled
530
700
900
1050
5500
FIFO
Disabled
330
500
700
850
5300
The value of x2 for a single channel or group of channels is
recalculated each time there is a write to any x1 register(s), c
register(s), or m register(s). During the calculation of x2, BUSY
goes low. The duration of this BUSY pulse depends on the
number of channels being updated. For example, if x1, c, or m
data is written to one DAC channel, BUSY goes low for 550 ns
(max). However, if data is written to two DAC channels, BUSY
goes low for 700 ns (max). There are approximately 200 ns of
overhead due to FIFO access. See Table 11.
The AD5378 contains an additional feature whereby a DAC
register is not updated unless its x2 register is written to since
the last time LDAC was brought low. Normally, when LDAC is
brought low, the DAC registers are filled with the contents of
the x2 registers. However, the AD5378 updates the DAC register
only if the x2 data changes, thereby removing unnecessary
digital crosstalk.
Rev. PrA | Page 20 of 28
Preliminary Technical Data
AD5378
FIFO VS. NON-FIFO OPERATION
Data can be loaded to the AD5378 registers with FIFO disabled
or enabled. Operation with FIFO disabled is optimum for single
writes to the device. If the system requires significant data
transfers to the AD5378, however, operation with FIFO enabled
is more efficient.
When FIFO is enabled, the AD5378 uses an internal FIFO
memory to allow high speed successive writes in both serial and
parallel modes. This optimizes the interface speed and
efficiency, minimizes the total conversion time due to internal
digital efficiencies, and minimizes the overhead on the master
controller when managing the data transfers. The BUSY signal
goes low while instructions in the state machine are being
executed.
Table 11 compares operation with FIFO enabled and FIFO
disabled for different data transfers to the AD5378. Operation
with FIFO enabled is more efficient for all operations except
single write operations. When using the FIFO, the user can
continue writing new data to the AD5378 while write instructions are being executed. Up to 128 successive instructions can
be written to the FIFO at maximum speed. When the FIFO is
full, additional writes to the AD5378 are ignored.
BUSY INPUT FUNCTION
Because the BUSY pin is bidirectional and open-drain (for
correct operation, use a pull-up resistor to digital supply), a
second AD5378 or any other device (such as a system controller), can pull BUSY low and, therefore, delay DAC update(s), if
required. This is a means of delaying any LDAC action. This
feature allows synchronous updates of multiple AD5378 devices
in a system at maximum speed. As soon as the last device
connected to the BUSY pin is ready, all DACs update automatically. Tying the BUSY pin of multiple devices together enables
synchronous updating of all DACs without extra hardware.
POWER-ON RESET FUNCTION
The AD5378 contains a power-on reset generator and state
machine. During power-on, CLR becomes active (internally),
the power-on state machine resets all internal registers to their
default values, and BUSY goes low. This sequence takes 8 ms
(typical). The outputs, VOUT0 to VOUT31, are switched to the
externally set potential on the REFGND pin. During power-on,
the parallel interface is disabled, so it is not possible to write to
the part. Any transitions on LDAC during the power-on period
are ignored in order to reject initial LDAC pin glitching. A
rising edge on BUSY indicates that power-on is complete and
that the parallel interface is enabled. All DACs remain in their
power-on state until LDAC is used to update the DAC outputs.
RESET INPUT FUNCTION
The AD5378 can be placed into the power-on reset state at any
time by activating the RESET pin. The AD5378 state machine
initiates a reset sequence to digitally reset the x1, m, c, and x2
registers to their default power-on values. This sequence takes
95 µs (typical), 120 µs (max), and 70 µs (min). During this
sequence, BUSY goes low. While RESET is low, any transitions
on LDAC are ignored. As with the CLR input, while RESET is
low, the DAC outputs are switched to REFGND. The outputs
remain at REFGND until an LDAC pulse is applied. This reset
function can also be implemented via the parallel interface by
setting the REG0 and REG1 pins low and writing all 1s to DB13
to DB0. See Table 17 for soft reset.
INCREMENT/DECREMENT FUNCTION
The AD5378 has a special function register that enables the user
to increment or decrement the internal 14-bit input register
data (x1) in steps of 0 to 127 LSBs. The increment/decrement
function is selected by setting both REG1 and REG0 pins (or
bits) low. Address Pins (or bits) A7 to A0 are used to select a
DAC channel or group of channels. The amount by which the
x1 register is incremented or decremented is determined by the
DB6 to DB0 bits/pins. For example, for a 1 LSB increment or
decrement, DB6...DB0 = 0000001, while for a 7 LSB increment
or decrement, DB6...DB0 = 0000111. DB8 determines whether
the input register data is incremented (DB8 = 1) or decremented (DB8 = 0). The maximum amount by which the user is
allowed to increment or decrement the data is 127 LSBs, that is,
DB6...DB0 = 1111111. The 0 LSB step is included to facilitate
software loops in the user’s application. See Table 16.
The AD5378 has digital overflow and underflow detection
circuitry to clamp at full scale or zero scale when the values
chosen for increment or decrement mode are out of range.
Rev. PrA | Page 21 of 28
AD5378
INTERFACES
The AD5378 contains parallel and serial interfaces. The active
interface is selected via the SER/PAR pin.
The AD5378 uses an internal FIFO memory to allow high
speed successive writes in both serial and parallel modes. The
user can continue writing new data to the AD5378 while write
instructions are being executed. The BUSY signal goes low
while instructions in the FIFO are being executed. Up to
120 successive instructions can be written to the FIFO at
maximum speed. When the FIFO is full, additional writes to the
AD5378 are ignored.
To minimize both the power consumption of the device and
on-chip digital noise, the active interface powers up fully only
when the device is being written to, that is, on the falling edge
of WR or on the falling edge of SYNC.
A7 to A0 Pins
Each of the 32 DAC channels can be addressed individually. In
addition, several channel groupings enable the user to simultaneously write the same data to multiple DAC channels. Address
Bits A7 to A4 are decoded to select one group or multiple
groups of registers. Address Bits A3 to A0 select one of ten
input data registers (x1), offset registers (c), or gain registers
(m). See Table 18.
SERIAL INTERFACE
The SER/PAR pin must be tied high to enable the serial interface and disable the parallel interface. The serial interface is
controlled by the following pins.
SYNC, DIN, SCLK
Standard 3-wire interface pins.
All digital interfaces are 2.5 V LVTTL-compatible when
operating from a 2.7 V to 3.6 V VCC supply.
DCEN
PARALLEL INTERFACE
SDO
A pull-down on the SER/PAR pin makes the parallel interface
the default. If using the parallel interface, the SER/PAR pin can
be left unconnected. Figure 6 shows the timing diagram for a
parallel write to the AD5378. The parallel interface is controlled
by the following pins.
Data out pin for daisy-chain mode.
Selects standalone mode or daisy-chain mode.
Figure 4 and Figure 5 show the timing diagrams for a serial
write to the AD5378 in standalone and daisy-chain modes,
respectively.
The 24-bit data-word format for the serial interface is shown in
Figure 21.
CS Pin
Active low device select pin.
MSB
LSB
WR Pin
REG1
REG0
GROUP/CHANNEL REGISTER SELECT
SELECT BITS
BITS
DB13–DB0
REGISTER DATA BITS
05292-021
A7–A0
On the rising edge of WR, with CS low, the address values at
Pins A7 to A0 are latched and data values at Pins DB13 to DB0
are loaded into the selected AD5378 input registers.
REG1, REG0 Pins
The REG1 and REG0 pins determine the destination register of
the data being written to the AD5378. See Table 12.
Table 12. Register Selection
REG1
1
1
0
0
REG0
1
0
1
0
Register Selected
Input Data Register (x1)
Offset Register (c)
Gain Register (m)
Special Function Register
DB13 to DB0 Pins
The AD5378 accepts a straight 14-bit parallel word on DB0 to
DB13, where DB13 is the MSB and DB0 is the LSB. See Table 13
to Table 17.
Figure 21. Serial Data Format
Standalone Mode
By connecting the DCEN (daisy-chain enable) pin low,
standalone mode is enabled. The serial interface works with
both a continuous and a burst serial clock. The first falling edge
of SYNC starts the write cycle and resets a counter that counts
the number of serial clocks to ensure that the correct number of
bits is shifted into the serial shift register. Additional edges on
SYNC are ignored until 24 bits are shifted in. Once 24 bits are
shifted in, the SCLK is ignored. For another serial transfer to
take place, the counter must be reset by the falling edge of SYNC.
Rev. PrA | Page 22 of 28
Preliminary Technical Data
AD5378
Daisy-Chain Mode
For systems that contain several DACs, the SDO pin can be
used to daisy-chain several devices together. This daisy-chain
mode can be useful in system diagnostics and in reducing the
number of serial interface lines.
Connecting the DCEN (daisy-chain enable) pin high enables
daisy-chain mode. The first falling edge of SYNC starts the
write cycle. The SCLK is continuously applied to the input shift
register when SYNC is low. If more than 24 clock pulses are
applied, the data ripples out of the shift register and appears on
the SDO line. This data is clocked out on the rising edge of
SCLK and is valid on the falling edge. By connecting this line to
the DIN input on the next device in the chain, a multidevice
interface is constructed. For each AD5378 in the system,
24 clock pulses are required. Therefore, the total number of
clock cycles must equal 24N, where N is the total number of
AD5378 devices in the chain. If fewer than 24 clocks are
applied, the write sequence is ignored.
When the serial transfer to all devices is complete, SYNC
should be taken high. This latches the input data in each device
in the daisy chain and prevents any additional data from being
clocked into the input shift register.
A continuous SCLK source can be used if SYNC is held low for
the correct number of clock cycles. Alternatively, a burst clock
containing the exact number of clock cycles can be used and
SYNC taken high after the final clock to latch the data.
When the transfer to all input registers is complete, a common
LDAC signal updates all DAC registers, and all analog outputs
are updated simultaneously.
Rev. PrA | Page 23 of 28
AD5378
DATA DECODING
The AD5378 contains a 14-bit data bus, DB13 to DB0. Depending on the value of REG1 and REG0, this data is loaded into the
addressed DAC input register(s), offset (c) register(s), gain (m)
register(s), or the special function register.
Table 13. DAC Data Format (REG1 = 1, REG0 = 1)
DB13 to DB0
11 1111 1111 1111
11 1111 1111 1110
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
00 0000 0000 0001
00 0000 0000 0000
DAC Output
(16383/16384) VREF(+) V
(16382/16384) VREF(+) V
(8193/16384) VREF(+) V
(8192/16384) VREF(+) V
(8191/16384) VREF(+) V
(1/16384) VREF(+) V
0V
Table 14. Offset Data Format (REG1 = 1, REG0 = 0)
DB13 to DB0
11 1111 1111 1111
11 1111 1111 1110
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
00 0000 0000 0001
00 0000 0000 0000
Offset (LSB)
+8191
+8190
+1
+0
−1
−8191
−8192
Table 15. Gain Data Format (REG1 = 0, REG0 = 1)
DB12 to DB1
1 1111 1111 1111
1 1111 1111 1110
1 0000 0000 0001
1 0000 0000 0000
0 1111 1111 1111
0 0000 0000 0001
0 0000 0000 0000
Gain
8192/8192
8191/8192
4098/8192
4097/8192
4096/8192
2/8192
1/8192
Table 16. Special Function Data Format (REG1 = 0, REG0 = 0)
DB13 to DB0
00000 10 1111111
00000 10 0000111
00000 10 0000001
00000 X0 0000000
00000 00 0000001
00000 00 0000111
00000 00 1111111
Increment/Decrement Step (LSB)
+127
+7
+1
0
−1
−7
−128
Table 17. Soft Reset (REG1 = 0, REG0 = 0)
DB13 to DB0
11 1111 1111 1111
Rev. PrA | Page 24 of 28
DAC Output
REFGND
Preliminary Technical Data
AD5378
ADDRESS DECODING
The AD5378 contains an 8-bit address bus, A7 to A0. This
address bus allows each DAC input register (x1), each offset (c)
register, and each gain (m) register to be individually updated.
The REG1 and REG0 bits in the special function register (SFR)
(see Table 10) show the decoding for data, offset, and gain
registers. When all 32 DAC channels are selected, Address
Bits A[3:0] are ignored.
Table 18. DAC Group Addressing
A7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Group
All 32 DACs
Group A
Group B
Groups A, B
Group C
Groups A, C
Groups B, C
Groups A, B, C
Group D
Groups A, D
Groups B, D
Groups A, B, D
Groups C, D
Groups A, C, D
Groups B, C, D
Groups A, B, C, D
A3
0
0
0
0
0
0
1
1
Rev. PrA | Page 25 of 28
A2
0
0
0
0
1
1
0
0
A1
0
0
1
1
0
0
0
0
A0
0
1
0
1
0
1
0
1
Data/Offset/Gain/INC-DEC Register
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
AD5378
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit board on
which the AD5378 is mounted should be designed so that the
analog and digital sections are separated and confined to
certain areas of the board. If the AD5378 is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.
For supplies with multiple pins (VSS, VDD, VCC), it is recommended to tie these pins together and to decouple each
supply once.
The AD5378 should have ample supply decoupling of 10 µF in
parallel with 0.1 µF on each supply located as close to the
package as possible, ideally right up against the device. The
10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor should have low effective series resistance (ESR) and
effective series inductance (ESI), such as the common ceramic
types that provide a low impedance path to ground at high
frequencies, to handle transient currents due to internal
logic switching.
Digital lines running under the device should be avoided,
because these couple noise onto the device. The analog ground
plane should be allowed to run under the AD5378 to avoid
noise coupling. The power supply lines of the AD5378 should
use as large a trace as possible to provide low impedance paths
and reduce the effects of glitches on the power supply line. Fast
switching digital signals should be shielded with digital ground
to avoid radiating noise to other parts of the board, and should
never be run near the reference inputs. It is essential to minimize noise on all VREF(+) and VREF(−) lines. The VBIAS pin should
be decoupled with a 10 nF capacitor to AGND.
Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feedthrough through the
board. A microstrip technique is by far the best, but not always
possible with a double-sided board. In this technique, the
component side of the board is dedicated to ground plane,
while signal traces are placed on the solder side.
As for all thin packages, care must be taken to avoid flexing the
CSPBGA package and to avoid a point load on the surface of
this package during the assembly process.
POWER-ON
An on-chip power supply monitor makes the AD5378 robust to
power sequencing. The supply monitor powers up the analog
section after (VDD − VSS) is greater than 7 V (typical). The
output buffers power up in CLR mode forced to the DUTGND
potential, even if VCC remains at 0 V. After VSS is applied, the
analog circuitry powers up and the buffered DAC output level
settles linearly within the supply range.
Rev. PrA | Page 26 of 28
Preliminary Technical Data
AD5378
TYPICAL APPLICATION CIRCUIT
The high channel count of the AD5378 makes it wellsuited to
applications requiring high levels of integration such as optical
and automatic test equipment (ATE) systems. Figure 22 shows
the AD5378 as it is used in an ATE system. Shown here is one
pin of a typical logic tester. It is apparent that a number of
discrete levels are required for the pin driver, active load circuit,
parametric measurement unit, comparators, and clamps.
In addition to the DAC levels required in the ATE system
shown, drivers, loads, comparators, and parametric
measurement unit functions are also required. Analog Devices
provides solutions for all these functions.
DRIVEN SHIELD
DAC
CENTRAL PMU
ADC
GUARD AMP
DAC
DAC
PPMU
VCH
DAC
TIMING DATA
MEMORY
DAC
ADC
VTERM
VH
RELAYS
TIMING
GENERATOR
DLL LOGIC
50Ω COAX
DUT
FORMATTER DE-SKEW
DRIVER
DAC
VL
DAC
VCL
DAC
GND SENSE
VTH
FORMATTER DE-SKEW
COMP
VTL
DAC
DEVICE POWER
SUPPLY
DAC
ACTIVE LOAD
DAC
DAC
DAC
ADC
IOL
VCOM
IOH
05292-022
COMPARE
MEMORY
Figure 22. Typical Application Circuit for Logic Tester
Rev. PrA | Page 27 of 28
AD5378
OUTLINE DIMENSIONS
A1 CORNER
INDEX AREA
13.00
BSC SQ
12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
BALL A1
INDICATOR
TOP VIEW
11.00
BSC SQ
BOTTOM
VIEW
1.00 BSC
*1.85
1.70
1.55
DETAIL A
DETAIL A
1.05
1.00
0.90
0.75
0.70
0.65
SEATING
PLANE
*0.64 TYP
0.12 MAX
COPLANARITY
BALL DIAMETER
*COMPLIANT WITH JEDEC STANDARDS MO-192-AAD-1
WITH THE EXCEPTION OF PACKAGE HEIGHT AND BALL DIAMETER.
Figure 23. 108-Lead Chip Scale Ball Grid Array [CSPBGA]
(BC-108-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD5378ABC
AD5378ABCZ1
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Linearity Error (LSBs)
±3
±3
Z = Pb-free part.
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR05292–0–1/05(PrA)
Rev. PrA | Page 28 of 28
Package Description
108-Lead CSPBGA
108-Lead CSPBGA
Package Option
BC-108-2
BC-108-2