MC74VHC4051, MC74VHC4052, MC74VHC4053 Analog Multiplexers / Demultiplexers High–Performance Silicon–Gate CMOS http://onsemi.com The MC74VHC4051, MC74VHC4052 and MC74VHC4053 utilize silicon–gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog multiplexers/demultiplexers control analog voltages that may vary across the complete power supply range (from VCC to VEE). The VHC4051, VHC4052 and VHC4053 are identical in pinout to the high–speed HC4051A, HC4052A and HC4053A, and the metal–gate MC14051B, MC14052B and MC14053B. The Channel–Select inputs determine which one of the Analog Inputs/Outputs is to be connected, by means of an analog switch, to the Common Output/Input. When the Enable pin is HIGH, all analog switches are turned off. The Channel–Select and Enable inputs are compatible with standard CMOS outputs; with pullup resistors they are compatible with LSTTL outputs. These devices have been designed so that the ON resistance (Ron) is more linear over input voltage than Ron of metal–gate CMOS analog switches. • Fast Switching and Propagation Speeds • Low Crosstalk Between Switches • Diode Protection on All Inputs/Outputs • Analog Power Supply Range (VCC – VEE) = 2.0 to 12.0 V • Digital (Control) Power Supply Range (VCC – GND) = 2.0 to 6.0 V • Improved Linearity and Lower ON Resistance Than Metal–Gate Counterparts • Low Noise • Chip Complexity: VHC4051 — 184 FETs or 46 Equivalent Gates VHC4052 — 168 FETs or 42 Equivalent Gates VHC4053 — 156 FETs or 39 Equivalent Gates Semiconductor Components Industries, LLC, 1999 March, 2000 – Rev. 3 1 MARKING DIAGRAMS 16 SO–16 D SUFFIX CASE 751B 16 1 VHC405x AWLYWW 1 16 VHC 405x ALYW TSSOP–16 DT SUFFIX CASE 948F 16 1 1 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet. Publication Order Number: MC74VHC4051/D MC74VHC4051, MC74VHC4052, MC74VHC4053 LOGIC DIAGRAM MC74VHC4051 Single–Pole, 8–Position Plus Common Off FUNCTION TABLE – MC74VHC4051 Control Inputs 13 X0 14 X1 15 X2 ANALOG 12 MULTIPLEXER/ INPUTS/ X3 DEMULTIPLEXER OUTPUTS X4 1 5 X5 2 X6 4 X7 11 A CHANNEL 10 B SELECT 9 INPUTS C 6 ENABLE PIN 16 = VCC PIN 7 = VEE PIN 8 = GND 3 X Enable C L L L L L L L L H L L L L H H H H X COMMON OUTPUT/ INPUT Select B A ON Channels X0 X1 X2 X3 X4 X5 X6 X7 NONE L H L H L H L H X L L H H L L H H X X = Don’t Care Pinout: MC74VHC4051 (Top View) VCC 16 X2 X1 X0 X3 A B C 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 FUNCTION TABLE – MC74VHC4052 LOGIC DIAGRAM MC74VHC4052 Double–Pole, 4–Position Plus Common Off Control Inputs Select Enable B A ON Channels L L L L H L L H H X L H L H X Y0 Y1 Y2 Y3 12 ANALOG INPUTS/OUTPUTS CHANNEL-SELECT INPUTS X0 14 X1 15 X2 11 X3 Y0 Y1 Y2 Y3 A B ENABLE X SWITCH 13 X COMMON OUTPUTS/INPUTS 1 5 2 Y SWITCH 3 X = Don’t Care 4 6 NONE Y Pinout: MC74VHC4052 (Top View) 10 9 X0 X1 X2 X3 VCC 16 PIN 16 = VCC PIN 7 = VEE PIN 8 = GND http://onsemi.com 2 X2 X1 X X0 X3 A B 15 14 13 12 11 10 9 6 7 8 GND 1 2 3 4 5 Y0 Y2 Y Y3 Y1 Enable VEE MC74VHC4051, MC74VHC4052, MC74VHC4053 FUNCTION TABLE – MC74VHC4053 LOGIC DIAGRAM MC74VHC4053 Triple Single–Pole, Double–Position Plus Common Off 12 X0 13 X1 X SWITCH 2 ANALOG INPUTS/OUTPUTS Y0 1 Y1 Y SWITCH 5 Z0 3 Z1 Z SWITCH 14 15 4 Control Inputs Enable C L L L L L L L L H L L L L H H H H X X Y COMMON OUTPUTS/INPUTS Select B A L L H H L L H H X ON Channels Z0 Z0 Z0 Z0 Z1 Z1 Z1 Z1 L H L H L H L H X Y0 Y0 Y1 Y1 Y0 Y0 Y1 Y1 NONE X0 X1 X0 X1 X0 X1 X0 X1 X = Don’t Care Z 11 A 10 B 9 C 6 ENABLE CHANNEL-SELECT INPUTS PIN 16 = VCC PIN 7 = VEE PIN 8 = GND Pinout: MC74VHC4053 (Top View) VCC 16 Y X X1 X0 A B C 15 14 13 12 11 10 9 6 7 8 GND NOTE: This device allows independent control of each switch. Channel–Select Input A controls the X–Switch, Input B controls the Y–Switch and Input C controls the Z–Switch http://onsemi.com 3 1 2 3 4 5 Y1 Y0 Z1 Z Z0 Enable VEE MC74VHC4051, MC74VHC4052, MC74VHC4053 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ MAXIMUM RATINGS* Symbol Parameter Value Unit – 0.5 to + 7.0 – 0.5 to + 14.0 V Negative DC Supply Voltage (Referenced to GND) – 7.0 to + 5.0 V VIS Analog Input Voltage VEE – 0.5 to VCC + 0.5 V Vin Digital Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V ± 25 mA 500 450 mW – 65 to + 150 _C 260 _C VCC Positive DC Supply Voltage VEE I DC Current, Into or Out of Any Pin PD Power Dissipation in Still Air, Tstg Storage Temperature Range TL (Referenced to GND) (Referenced to VEE) SOIC Package† TSSOP Package† Lead Temperature, 1 mm from Case for 10 Seconds *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. †Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: – 6.1 mW/_C from 65_ to 125_C ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎ RECOMMENDED OPERATING CONDITIONS Symbol Parameter (Referenced to GND) (Referenced to VEE) Min Max Unit 2.0 2.0 6.0 12.0 V VCC Positive DC Supply Voltage VEE Negative DC Supply Voltage, Output (Referenced to GND) – 6.0 GND V VIS Analog Input Voltage VEE VCC V Vin Digital Input Voltage (Referenced to GND) GND VCC V VIO* Static or Dynamic Voltage Across Switch 1.2 V – 55 + 125 _C 0 0 0 0 1000 800 500 400 ns TA Operating Temperature Range, All Package Types tr, tf Input Rise/Fall Time (Channel Select or Enable Inputs) VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V *For voltage drops across switch greater than 1.2V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. http://onsemi.com 4 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. v v MC74VHC4051, MC74VHC4052, MC74VHC4053 DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted Symbol Parameter Condition Guaranteed Limit VCC V –55 to 25°C ≤85°C ≤125°C Unit VIH Minimum High–Level Input Voltage, Channel–Select or Enable Inputs Ron = Per Spec 2.0 3.0 4.5 6.0 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 V VIL Maximum Low–Level Input Voltage, Channel–Select or Enable Inputs Ron = Per Spec 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 V Iin Maximum Input Leakage Current, Channel–Select or Enable Inputs Vin = VCC or GND, VEE = – 6.0 V 6.0 ± 0.1 ± 1.0 ± 1.0 µA Maximum Quiescent Supply Current (per Package) Channel Select, Enable and VIS = VCC or GND; VEE = GND VIO = 0 V VEE = – 6.0 6.0 6.0 1 4 10 40 40 80 ICC µA ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎ v ÎÎÎÎ v ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ v ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ v ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ v ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ DC ELECTRICAL CHARACTERISTICS Analog Section Guaranteed Limit Symbol Ron Parameter Maximum “ON” Resistance VCC V VEE V – 55 to 25_C 85_C 125_C Vin = VIL or VIH VIS = VCC to VEE IS 2.0 mA (Figures 1, 2) 3.0 4.5 4.5 6.0 0.0 0.0 – 4.5 – 6.0 200 160 120 100 240 200 150 125 320 280 170 140 Vin = VIL or VIH VIS = VCC or VEE (Endpoints) IS 2.0 mA (Figures 1, 2) Vin = VIL or VIH VIS = 1/2 (VCC – VEE) IS 2.0 mA 3.0 4.5 4.5 6.0 0.0 0.0 – 4.5 – 6.0 150 110 90 80 180 140 120 100 230 190 140 115 3.0 4.5 4.5 6.0 0.0 0.0 – 4.5 – 6.0 40 20 10 10 50 25 15 12 80 40 18 14 Test Conditions ∆Ron Maximum Difference in “ON” Resistance Between Any Two Channels in the Same Package Ioff Maximum Off–Channel Leakage Current, Any One Channel Vin = VIL or VIH; VIO = VCC – VEE; Switch Off (Figure 3) 6.0 – 6.0 0.1 0.5 1.0 Maximum Off–Channel VHC4051 Leakage Current, VHC4052 Common Channel VHC4053 Vin = VIL or VIH; VIO = VCC – VEE; Switch Off (Figure 4) 6.0 6.0 6.0 – 6.0 – 6.0 – 6.0 0.2 0.1 0.1 2.0 1.0 1.0 4.0 2.0 2.0 Maximum On–Channel VHC4051 Leakage Current, VHC4052 Channel–to–Channel VHC4053 Vin = VIL or VIH; Switch–to–Switch = VCC – VEE; (Figure 5) 6.0 6.0 6.0 – 6.0 – 6.0 – 6.0 0.2 0.1 0.1 2.0 1.0 1.0 4.0 2.0 2.0 Ion Unit Ω Ω µA http://onsemi.com 5 µA MC74VHC4051, MC74VHC4052, MC74VHC4053 AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Guaranteed Limit VCC V –55 to 25°C ≤85°C ≤125°C Unit Maximum Propagation Delay, Channel–Select to Analog Output (Figure 9) 2.0 3.0 4.5 6.0 270 90 59 45 320 110 79 65 350 125 85 75 ns tPLH, tPHL Maximum Propagation Delay, Analog Input to Analog Output (Figure 10) 2.0 3.0 4.5 6.0 40 25 12 10 60 30 15 13 70 32 18 15 ns tPLZ, tPHZ Maximum Propagation Delay, Enable to Analog Output (Figure 11) 2.0 3.0 4.5 6.0 160 70 48 39 200 95 63 55 220 110 76 63 ns tPZL, tPZH Maximum Propagation Delay, Enable to Analog Output (Figure 11) 2.0 3.0 4.5 6.0 245 115 49 39 315 145 69 58 345 155 83 67 ns Symbol Parameter tPLH, tPHL Cin Maximum Input Capacitance, Channel–Select or Enable Inputs 10 10 10 pF CI/O Maximum Capacitance Analog I/O 35 35 35 pF Common O/I: VHC4051 VHC4052 VHC4053 130 80 50 130 80 50 130 80 50 Feedthrough 1.0 1.0 1.0 (All Switches Off) Typical @ 25°C, VCC = 5.0 V, VEE = 0 V CPD Power Dissipation Capacitance (Figure 13)* VHC4051 VHC4052 VHC4053 * Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . http://onsemi.com 6 45 80 45 pF MC74VHC4051, MC74VHC4052, MC74VHC4053 ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V) Symbol BW — — Parameter 2.25 4.50 6.00 –2.25 –4.50 –6.00 Off–Channel Feedthrough Isolation (Figure 7) fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at VIS fin = 10kHz, RL = 600Ω, CL = 50pF 2.25 4.50 6.00 –2.25 –4.50 –6.00 –50 –50 –50 fin = 1.0MHz, RL = 50Ω, CL = 10pF 2.25 4.50 6.00 –2.25 –4.50 –6.00 –40 –40 –40 Vin ≤ 1MHz Square Wave (tr = tf = 6ns); Adjust RL at Setup so that IS = 0A; Enable = GND RL = 600Ω, CL = 50pF 2.25 4.50 6.00 –2.25 –4.50 –6.00 25 105 135 RL = 10kΩ, CL = 10pF 2.25 4.50 6.00 –2.25 –4.50 –6.00 35 145 190 fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at VIS fin = 10kHz, RL = 600Ω, CL = 50pF 2.25 4.50 6.00 –2.25 –4.50 –6.00 –50 –50 –50 fin = 1.0MHz, RL = 50Ω, CL = 10pF 2.25 4.50 6.00 –2.25 –4.50 –6.00 –60 –60 –60 Total Harmonic Distortion (Figure 14) fin = 1kHz, RL = 10kΩ, CL = 50pF THD = THDmeasured – THDsource VIS = 4.0VPP sine wave VIS = 8.0VPP sine wave VIS = 11.0VPP sine wave Unit 25°C fin = 1MHz Sine Wave; Adjust fin Voltage to Obt i 0dBm Obtain 0dB att VOS; Increase I fin Frequency Until dB Meter Reads –3dB; RL = 50Ω, CL = 10pF Crosstalk Between Any Two Switches (Figure 12) (Test does not apply to VHC4051) THD Limit* VEE V Maximum On–Channel Bandwidth or Minimum Mi i Frequency F Response R (Figure 6) Feedthrough Noise. Channel–Select Input to Common I/O (Figure 8) — VCC V Condition ‘51 ‘52 ‘53 80 80 80 95 95 95 120 120 120 MHz dB mVPP dB % 2.25 4.50 6.00 –2.25 –4.50 –6.00 0.10 0.08 0.05 *Limits not tested. Determined by design and verified by qualification. 180 160 250 Ron , ON RESISTANCE (OHMS) Ron , ON RESISTANCE (OHMS) 300 200 125°C 150 25°C – 55°C 100 50 140 120 125°C 100 80 25°C 60 – 55°C 40 20 0 0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 0 2.25 0 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25 2.5 2.75 3.0 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE Figure 1a. Typical On Resistance, VCC – VEE = 2.0 V Figure 1b. Typical On Resistance, VCC – VEE = 3.0 V http://onsemi.com 7 120 105 100 90 80 Ron , ON RESISTANCE (OHMS) Ron , ON RESISTANCE (OHMS) MC74VHC4051, MC74VHC4052, MC74VHC4053 125°C 60 25°C 40 – 55°C 20 0 75 125°C 60 25°C 45 – 55°C 30 15 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 4.5 0 0.5 Figure 1c. Typical On Resistance, VCC – VEE = 4.5 V 3.0 3.5 4.0 4.5 5.0 5.5 6.0 60 70 Ron , ON RESISTANCE (OHMS) Ron , ON RESISTANCE (OHMS) 2.0 2.5 Figure 1d. Typical On Resistance, VCC – VEE = 6.0 V 80 60 50 125°C 40 30 25°C 20 – 55°C 10 0 –4.5 1.0 1.5 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE –3.5 –2.5 –1.5 –0.5 0.5 1.5 2.5 3.5 50 125°C 40 25°C 30 – 55°C 20 10 0 –6.0 –5.0 –4.0 –3.0 –2.0 –1.0 4.5 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE 2.0 3.0 4.0 5.0 6.0 Figure 1f. Typical On Resistance, VCC – VEE = 12.0 V PLOTTER – 1.0 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE Figure 1e. Typical On Resistance, VCC – VEE = 9.0 V PROGRAMMABLE POWER SUPPLY 0 MINI COMPUTER DC ANALYZER + VCC DEVICE UNDER TEST ANALOG IN COMMON OUT VEE GND Figure 1. On Resistance Test Set–Up http://onsemi.com 8 MC74VHC4051, MC74VHC4052, MC74VHC4053 VCC VCC VCC 16 VEE ANALOG I/O OFF A VCC VIH OFF VIH 6 7 8 VEE COMMON O/I 6 7 8 VEE Figure 2. Maximum Off Channel Leakage Current, Any One Channel, Test Set–Up VCC Figure 3. Maximum Off Channel Leakage Current, Common Channel, Test Set–Up VCC 16 A VEE VCC 16 0.1µF fin ON COMMON O/I OFF VCC OFF VCC COMMON O/I OFF NC VCC 16 VEE VOS dB METER ON N/C RL CL* ANALOG I/O VIL 6 7 8 6 7 8 VEE VEE Figure 4. Maximum On Channel Leakage Current, Channel to Channel, Test Set–Up VCC 16 VIS 0.1µF fin Figure 5. Maximum On Channel Bandwidth, Test Set–Up VCC 16 VOS dB METER OFF RL *Includes all probe and jig capacitance CL* RL ON/OFF COMMON O/I ANALOG I/O RL OFF/ON RL RL 6 7 8 VEE VIL or VIH Vin ≤ 1 MHz tr = tf = 6 ns VEE VCC GND CHANNEL SELECT *Includes all probe and jig capacitance 6 7 8 TEST POINT CL* VCC 11 CHANNEL SELECT *Includes all probe and jig capacitance Figure 6. Off Channel Feedthrough Isolation, Test Set–Up Figure 7. Feedthrough Noise, Channel Select to Common Out, Test Set–Up http://onsemi.com 9 MC74VHC4051, MC74VHC4052, MC74VHC4053 VCC 16 VCC VCC CHANNEL SELECT ON/OFF 50% COMMON O/I ANALOG I/O OFF/ON GND tPLH TEST POINT CL* tPHL ANALOG OUT 6 7 8 50% CHANNEL SELECT *Includes all probe and jig capacitance Figure 9a. Propagation Delays, Channel Select to Analog Out Figure 8b. Propagation Delay, Test Set–Up Channel Select to Analog Out VCC 16 ANALOG IN COMMON O/I ANALOG I/O VCC ON 50% TEST POINT CL* GND tPHL tPLH ANALOG OUT 6 7 8 50% *Includes all probe and jig capacitance Figure 10a. Propagation Delays, Analog In to Analog Out tf tr tPZL 1 VCC 90% 50% 10% ENABLE ANALOG OUT Figure 9b. Propagation Delay, Test Set–Up Analog In to Analog Out 2 GND tPLZ HIGH IMPEDANCE 1 TEST POINT ON/OFF CL* VOL ENABLE VOH 90% 1kΩ ANALOG I/O 2 50% 10% VCC 16 VCC tPZH tPHZ ANALOG OUT POSITION 1 WHEN TESTING tPHZ AND tPZH POSITION 2 WHEN TESTING tPLZ AND tPZL 50% 6 7 8 HIGH IMPEDANCE Figure 11a. Propagation Delays, Enable to Analog Out Figure 10b. Propagation Delay, Test Set–Up Enable to Analog Out http://onsemi.com 10 MC74VHC4051, MC74VHC4052, MC74VHC4053 VCC VIS A VCC 16 RL fin 16 VOS ON COMMON O/I ON/OFF NC ANALOG I/O 0.1µF OFF/ON OFF VEE RL RL CL* RL CL* 6 7 8 VEE VCC 6 7 8 11 CHANNEL SELECT *Includes all probe and jig capacitance Figure 11. Crosstalk Between Any Two Switches, Test Set–Up Figure 12. Power Dissipation Capacitance, Test Set–Up 0 VIS VCC 16 0.1µF fin – 10 VOS ON CL* TO DISTORTION METER – 30 – 40 dB RL FUNDAMENTAL FREQUENCY – 20 – 50 DEVICE – 60 6 7 8 VEE SOURCE – 70 – 80 – 90 *Includes all probe and jig capacitance – 100 1.0 2.0 3.125 FREQUENCY (kHz) Figure 14a. Total Harmonic Distortion, Test Set–Up Figure 13b. Plot, Harmonic Distortion APPLICATIONS INFORMATION outputs to VCC or GND through a low value resistor helps minimize crosstalk and feedthrough noise that may be picked up by an unused switch. Although used here, balanced supplies are not a requirement. The only constraints on the power supplies are that: VCC – GND = 2 to 6 volts VEE – GND = 0 to –6 volts VCC – VEE = 2 to 12 volts and VEE ≤ GND When voltage transients above VCC and/or below VEE are anticipated on the analog channels, external Germanium or Schottky diodes (Dx) are recommended as shown in Figure 16. These diodes should be able to absorb the maximum anticipated current surges during clipping. The Channel Select and Enable control pins should be at VCC or GND logic levels. VCC being recognized as a logic high and GND being recognized as a logic low. In this example: VCC = +5V = logic high GND = 0V = logic low The maximum analog voltage swings are determined by the supply voltages VCC and VEE. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below VEE. In this example, the difference between VCC and VEE is ten volts. Therefore, using the configuration of Figure 15, a maximum analog signal of ten volts peak–to–peak can be controlled. Unused analog inputs/outputs may be left floating (i.e., not connected). However, tying unused analog inputs and http://onsemi.com 11 MC74VHC4051, MC74VHC4052, MC74VHC4053 VCC +5V 16 +5V ANALOG SIGNAL –5V ON 6 7 8 Dx +5V ANALOG SIGNAL VCC 16 Dx Dx VEE VEE 7 8 –5V VEE Figure 14. Application Example Figure 15. External Germanium or Schottky Clipping Diodes +5V +5V 16 +5V ANALOG SIGNAL VEE ON/OFF 6 7 8 VEE Dx ON/OFF –5V TO EXTERNAL CMOS CIRCUITRY 0 to 5V DIGITAL SIGNALS 11 10 9 VCC ANALOG SIGNAL +5V * R R 11 10 9 +5V +5V VEE VEE 16 ANALOG SIGNAL ON/OFF +5V ANALOG SIGNAL R VEE +5V 6 7 8 LSTTL/NMOS CIRCUITRY VEE * 2K ≤ R ≤ 10K a. Using Pull–Up Resistors 11 10 9 LSTTL/NMOS CIRCUITRY HCT BUFFER b. Using HCT Interface Figure 16. Interfacing LSTTL/NMOS to CMOS Inputs A 11 13 LEVEL SHIFTER 14 B 10 15 LEVEL SHIFTER 12 C 9 1 LEVEL SHIFTER 5 ENABLE 6 2 LEVEL SHIFTER 4 3 Figure 18. Function Diagram, VHC4051 http://onsemi.com 12 X0 X1 X2 X3 X4 X5 X6 X7 X MC74VHC4051, MC74VHC4052, MC74VHC4053 A 10 12 LEVEL SHIFTER 14 B 9 15 LEVEL SHIFTER 11 13 ENABLE 6 1 LEVEL SHIFTER 5 2 4 3 X0 X1 X2 X3 X Y0 Y1 Y2 Y3 Y Figure 19. Function Diagram, VHC4052 A 11 13 LEVEL SHIFTER 12 14 B 10 1 LEVEL SHIFTER 2 15 C 9 3 LEVEL SHIFTER 5 4 ENABLE 6 LEVEL SHIFTER Figure 20. Function Diagram, VHC4053 http://onsemi.com 13 X1 X0 X Y1 Y0 Y Z1 Z0 Z MC74VHC4051, MC74VHC4052, MC74VHC4053 ORDERING & SHIPPING INFORMATION Package Shipping MC74VHC4051D Device SOIC–16 48 Units / Rail MC74VHC4051DR2 SOIC–16 2500 Units / Tape & Reel MC74VHC4051DT TSSOP–16 96 Units / Rail MC74VHC4051DTR2 TSSOP–16 2500 Units / Tape & Reel SOIC–16 48 Units / Rail MC74VHC4052D MC74VHC4052DR2 SOIC–16 2500 Units / Tape & Reel MC74VHC4052DT TSSOP–16 96 Units / Rail MC74VHC4052DTR2 TSSOP–16 2500 Units / Tape & Reel MC74VHC4053D SOIC–16 48 Units / Rail MC74VHC4053DR2 SOIC–16 2500 Units / Tape & Reel MC74VHC4053DT TSSOP–16 96 Units / Rail MC74VHC4053DTR2 TSSOP–16 2500 Units / Tape & Reel http://onsemi.com 14 MC74VHC4051, MC74VHC4052, MC74VHC4053 PACKAGE DIMENSIONS SOIC–16 D SUFFIX CASE 751B–05 ISSUE J –A – 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 –B – 1 P 8 PL 0.25 (0.010) 8 M B M G K DIM A B C D F G J K M P R F R X 45° C –T SEATING – J M PLANE D 16 PL 0.25 (0.010) M T B S A S MILLIMETERS MIN MAX 9.80 10.00 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7° 0° 6.20 5.80 0.50 0.25 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0° 7° 0.229 0.244 0.010 0.019 TSSOP–16 DT SUFFIX CASE 948F–01 ISSUE O 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S ÇÇÇ ÉÉÉ ÇÇÇ ÉÉÉ ÇÇÇ K K1 2X L/2 16 9 J1 B –U– L SECTION N–N J PIN 1 IDENT. 8 1 N 0.25 (0.010) 0.15 (0.006) T U S A –V– NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–. M N F DETAIL E –W– C 0.10 (0.004) –T– SEATING PLANE DETAIL E H D G http://onsemi.com 15 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 ––– 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 ––– 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC74VHC4051, MC74VHC4052, MC74VHC4053 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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