ETC2 NANO102ZB1AN Nano102/112 sery Datasheet

NuMicro Nano102/112 Datasheet
NuMicro™ Family
Nano102/112 Series
Datasheet
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system
design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
May 08, 2013
Page 1 of 100
Revision 1.01
NUMICRO™ NANO102/112 SERIES DATASHEET
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
NuMicro Nano102/112 Datasheet
Table of Contents
1
GENERAL DESCRIPTION ........................................................................................... 8
2
FEATURES ....................................................................................... 10
2.1
Nano102 Features – Base Line ....................................................................10
2.2
Nano112 Features – LCD Line .....................................................................15
3
ABBREVIATIONS ................................................................................ 21
4
PARTS INFORMATION LIST AND PIN CONFIGURATION .............................. 23
4.1
NuMicro Nano102/112 Series Selection Code.................................................23
4.2
NuMicro Nano112 Products Selection Guide ..................................................23
4.2.1
NuMicro Nano102 Base Line Selection Guide ......................................................... 23
4.2.2
NuMicro Nano112 LCD Line Selection Guide ......................................................... 24
Pin Configuration......................................................................................25
4.3
4.3.1
NuMicro Nano102 Pin Diagrams ......................................................................... 25
4.3.2
NuMicro Nano112 Pin Diagrams ......................................................................... 28
Pin Description ........................................................................................31
4.4
4.4.1
NuMicro Nano102 Pin Description ....................................................................... 31
4.4.2
NuMicro Nano112 Pin Description ....................................................................... 38
5.1
Nano102 Block Diagram .............................................................................51
5.2
Nano112 Block Diagram .............................................................................52
FUNCTIONAL DESCRIPTION ................................................................. 53
6
6.1
ARM® Cortex™-M0 Core ...........................................................................53
6.2
Memory Organization ................................................................................55
6.2.1
6.3
Overview ....................................................................................................... 55
Nested Vectored Interrupt Controller (NVIC) .....................................................56
6.3.1
Overview ....................................................................................................... 56
6.3.2
Features ........................................................................................................ 56
6.4
System Manager ......................................................................................57
6.4.1
Overview ....................................................................................................... 57
6.4.2
Features ........................................................................................................ 57
6.5
Clock Controller .......................................................................................58
6.5.1
Overview ....................................................................................................... 58
6.5.2
Features ........................................................................................................ 58
6.6
Flash Memory Controller (FMC) ....................................................................59
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BLOCK DIAGRAM ............................................................................... 51
5
NuMicro Nano102/112 Datasheet
6.6.1
Overview ....................................................................................................... 59
6.6.2
Features ........................................................................................................ 59
6.7
General Purpose I/O Controller.....................................................................60
6.7.1
Overview ....................................................................................................... 60
6.7.2
Features ........................................................................................................ 60
6.8
DMA Controller ........................................................................................61
6.8.1
Overview ....................................................................................................... 61
6.8.2
Features ........................................................................................................ 62
6.9
Timer Controller .......................................................................................63
6.9.1
Overview ....................................................................................................... 63
6.9.2
Features ........................................................................................................ 63
6.10
Pulse Width Modulation (PWM) ....................................................................64
6.10.1
Overview ....................................................................................................... 64
6.10.2
Features ........................................................................................................ 65
6.11
Watchdog Timer Controller ..........................................................................66
6.11.1
Overview ....................................................................................................... 66
6.11.2
Features ........................................................................................................ 66
6.12
Window Watchdog Timer Controller ............................................................... 67
Overview ....................................................................................................... 67
6.12.2
Features ........................................................................................................ 67
6.13
RTC .....................................................................................................68
6.13.1
Overview ....................................................................................................... 68
6.13.2
Features ........................................................................................................ 68
6.14
UART Controller ......................................................................................69
6.14.1
Overview ....................................................................................................... 69
6.14.2
Features ........................................................................................................ 69
6.15
Smart Card Host Interface (SC) ....................................................................70
6.15.1
Overview ....................................................................................................... 70
6.15.2
Features ........................................................................................................ 70
6.16
I2C .......................................................................................................71
6.16.1
Overview ....................................................................................................... 71
6.16.2
Features ........................................................................................................ 71
6.17
SPI ......................................................................................................73
6.17.1
Overview ....................................................................................................... 73
6.17.2
Features ........................................................................................................ 73
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NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
6.12.1
NuMicro Nano102/112 Datasheet
6.18
LCD Display Driver ...................................................................................74
6.18.1
Overview ....................................................................................................... 74
6.18.2
Features ........................................................................................................ 74
6.19
Analog to Digital Converter (ADC) .................................................................75
6.19.1
Overview ....................................................................................................... 75
6.19.2
Features ........................................................................................................ 75
6.20
Analog Comparator Controller (ACMP) ...........................................................76
6.20.1
Overview ....................................................................................................... 76
6.20.2
Features ........................................................................................................ 76
7
Application Circuit ................................................................................ 77
8
POWER COMSUMPTION ...................................................................... 78
9
ELECTRICAL CHARACTERISTIC ............................................................ 79
9.1
Absolute Maximum Ratings .........................................................................79
9.2
Nano102/Nano112 DC Electrical Characteristics................................................80
9.3
AC Electrical Characteristics ........................................................................85
External Input Clock .......................................................................................... 85
9.3.2
External 4~24 MHz XTAL Oscillator ....................................................................... 85
9.3.3
External 32.768 kHz Crystal ................................................................................ 86
9.3.4
Internal 12 MHz Oscillator ................................................................................... 87
9.3.5
Internal 10 kHz Oscillator .................................................................................... 87
Analog Characteristics ...............................................................................87
9.4
10
9.4.1
12-bit ADC ..................................................................................................... 87
9.4.2
Brown-out Detector ........................................................................................... 88
9.4.3
Power-on Reset ............................................................................................... 89
9.4.4
Temperature Sensor ......................................................................................... 89
9.4.5
LCD ............................................................................................................. 89
9.4.6
Internal Voltage Reference .................................................................................. 90
9.4.7
Comparator .................................................................................................... 90
PACKAGE DIMENSIONS ...................................................................... 92
10.1
100L LQFP (14x14x1.4 mm footprint 2.0 mm) ...................................................92
10.2
64R LQFP(10x10x1.4 mm footprint 2.0 mm) .....................................................93
10.3
64S LQFP (7x7x1.4 mm footprint 2.0 mm) .......................................................94
10.4
48L LQFP (7x7x1.4 mm footprint 2.0 mm)........................................................96
10.5
33L QFN (5x5x1.4 mm footprint 2.0 mm) .........................................................97
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NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
9.3.1
NuMicro Nano102/112 Datasheet
11
REVISION HISTORY ............................................................................ 99
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
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NuMicro Nano102/112 Datasheet
LIST OF FIGURES
TM
Nano112 Series Selection Code ................................................................ 23
Figure 4‑2 NuMicro
TM
Nano102 LQFP 64-pin Diagram................................................................. 25
Figure 4‑3 NuMicro
TM
Nano102 LQFP 48-pin Diagram................................................................. 26
Figure 4‑4 NuMicro
TM
Nano102 QFN 32-pin Diagram .................................................................. 27
Figure 4‑5 NuMicro
TM
Nano112 LQFP 100-pin Diagram ............................................................... 28
Figure 4‑6 NuMicro
TM
Nano112 LQFP 64-pin Diagram ................................................................. 29
Figure 4‑7 NuMicro
TM
Nano112 LQFP 48-pin Diagram ................................................................. 30
Figure 5-1 NuMicro
TM
Nano102 Block Diagram ............................................................................. 51
Figure 5-2 NuMicro
TM
Nano112 Block Diagram ............................................................................. 52
Figure 4-1 NuMicro
Figure 6-1 Functional Block Diagram ............................................................................................. 53
Figure 9‑1 Typical Crystal Application Circuit ................................................................................ 86
Figure 9‑2 Typical Crystal Application Circuit ................................................................................ 86
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
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NuMicro Nano102/112 Datasheet
LIST OF TABLES
Table 1‑1 Connectivity Support Table ............................................................................................. 9
Table 3‑1 List of Abbreviations ...................................................................................................... 22
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
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NuMicro Nano102/112 Datasheet
1
GENERAL DESCRIPTION
®
The Nano112 series ultra-low-power 32-bit microcontroller embeded with ARM Cortex™-M0
core operates at low voltage range from 1.8V to 3.6V and runs up to 32 MHz frequency with
16/32 Kbytes embedded Flash and 4/8 Kbytes embedded SRAM and 4 Kbytes Flash loader
memory for In-System Programming (ISP). The Nano112 series integrates 4 COM x 36 SEG or 6
COM x 34 SEG LCD controller, RTC, 12-bit SAR ADC, comparators and provides high
2
performance connectivity peripheral interfaces such as UART, SPI, I C, GPIOs, and ISO-7816-3
for Smart card. The Nano112 series supports Brown-out Detector, Power-down mode with RTC
turn on, RAM retention is less than 1.5 uA, Deep power down mode with RAM retention is less
than 650 nA and fast wake-up via many peripheral interfaces.
The Nano112 series provides low voltage, low operating power consumption, low standby current,
high integration peripherals, high-efficiency operation, fast wake-up function and the lowest cost
32-bit microcontrollers. The Nano112 series is suitable for a wide range of battery device
applications such as:
Wearable Device

Smart Watch

Wireless Gaming Control

Hand-Held Medical Device

RFID Reader

Mobile Payment Smart Card Reader

Security Alarm System

Smart Home Appliance

Wireless Thermostats

Wireless Sensors Node Device (WSND)

Wireless Auto Meter Reading (AMR)

Portable Wireless Data Collector

Smart Water, Gas, Heat Meters
The Nano112 series includes two product lines: Nano102 Base line and Nano112 LCD line.
®
The Nano102 Base line, an ultra-low-power 32-bit microcontroller embedded with ARM
Cortex™-M0 core, operates at low voltage range from 1.8V to 3.6V and runs up to 32 MHz
frequency with 16/32 Kbytes embedded flash and 4/8 Kbytes embedded SRAM and 4 Kbytes
Flash loader memory for In-System Programming (ISP). It integrates RTC, 8- channels 12-bit
SAR ADC, 2xComparators and provides high performance connectivity peripheral interfaces such
2
as 2 x Low Power UARTs, 2 x SPIs, 2 x I Cs, GPIOs, and 2 x ISO-7816-3 for Smart card. The
Nano102 Base line supports Brown-out Detector, Power-down mode with RAM retention and fast
wake-up via many peripheral interfaces.
®
The Nano112 LCD line, an ultra-low-power 32-bit microcontroller embedded with ARM Cortex™M0 core, operates at low voltage range from 1.8V to 3.6V and runs up to 32 MHz frequency with
16/32 Kbytes embedded flash and 4/8 Kbytes embedded SRAM and 4 Kbytes Flash loader
memory for In-System Programming (ISP). It integrates 4 COM x 36 SEG or 6 COM x 34 SEG
LCD controller, RTC, 8-channels 12-bit SAR ADC, 2 x Comparators and provides high
2
performance connectivity peripheral interfaces such as 2 x Low Power UARTs, 2 x SPIs, 2 x I Cs,
GPIOs, and 2 x ISO-7816-3 for Smart card. The Nano112 LCD line supports Brown-out Detector,
Power-down mode with RAM retention and fast wake-up via many peripheral interfaces.
May 08, 2013
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NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET

NuMicro Nano102/112 Datasheet
Product Line
UART
SPI
I2C
ADC
ACMP
RTC
SC
Timer
Nano102
●
●
●
●
●
●
●
●
Nano112
●
●
●
●
●
●
●
●
LCD
●
Table 1‑1 Connectivity Support Table
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
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NuMicro Nano102/112 Datasheet
2
FEATURES
The equipped features are dependent on the product line and their sub products.
2.1
Nano102 Features – Base Line

Low Supply Voltage Range: 1.8 V to 3.6 V

Ultra-Low Power Consumption

Operation mode : 150 uA/MHz

Power-down mode : 1.5 uA (RTC on, RAM retention)

Deep power down mode : 650 nA (RAM retention)

Fast Wake-Up From Standby Mode : Less than 6 μs

Core


ARM Cortex™-M0 core running up to 32 MHz

One 24-bit system timer

Supports Low Power Sleep mode

Single-cycle 32-bit hardware multiplier

NVIC for the 32 interrupt inputs, each with 4-levels of priority

Serial Wire Debug supports with 2 watchpoints/4 breakpoints
Flash EPROM Memory

Runs up to 32 MHz with zero wait state for discontinuous address read access

16/32 Kbytes application program memory (APROM)

4 KB in system programming (ISP) loader program memory (LDROM)

Programmable data flash start address and memory size with 512 bytes page
erase unit

In System Program (ISP)/In Application Program (IAP) to update on-chip Flash
EPROM
SRAM Memory

4/8 Kbytes embedded SRAM

Supports DMA mode
DMA: Supports 5 channels: 4 PDMA channels and one CRC channel


May 08, 2013
PDMA

Peripheral-to-memory,
transfer

Supports word boundary address

Supports word alignment transfer length in memory-to-memory mode

Supports word/half-word/byte alignment transfer length in peripheral-tomemory and memory-to-peripheral mode

Supports word/half-word/byte transfer data width from/to peripheral

Supports address direction: increment, fixed, and wrap around
memory-to-peripheral,
and
memory-to-memory
CRC
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NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET

®

NuMicro Nano102/112 Datasheet



May 08, 2013
12
5
CRC-CCITT: X

CRC-8: X + X + X + 1

CRC-16: X

CRC-32: X + X
4
2
X +X +X+1
8
+X
+X +1
2
16
32
+X
15
+X +1
2
26
+X
23
+X
22
+X
16
+X
12
+X
11
+X
10
8
7
5
+X +X +X +

Flexible selection for different applications

Built-in 12/16 MHz OSC, can be trimmed to 1 % deviation within all temperature
range when turning on auto-trim function (system must have external 32.768
kHz crystal input) otherwise 12/16 MHz OSC has 2 % deviation within all
temperarure range.

Low power 10 kHz OSC for watchdog and low power system operation

Supports one PLL, up to 32 MHz, for high performance system operation
External 4~24 MHz crystal input for precise timing operation

External 32.768 kHz crystal input for RTC function and low power system
operation
GPIO
Three I/O modes:

Push-Pull output

Open-Drain output

Input only with high impendence

All inputs with Schmitt trigger

I/O pin configured as interrupt source with edge/level setting

Supports High Driver and High Sink I/O mode

Supports input 5V tolerance, except PA.0 ~ PA.7, PA.12, PA.13, PF.0(X32I),
PF.1(X32O).
Timer

Supports 4 sets of 32-bit timers, each with 24-bit up-counting timer and one 8-bit
pre-scale counter

Independent Clock Source for each timer

Provides one-shot,periodic, output toggle and continuous operation modes

Internal trigger event to ADC and PDMA

Supports PDMA mode

Wake system up from Power-down mode
Watchdog Timer

Clock Source from LIRC (Internal 10 kHz Low Speed Oscillator Clock)

Selectable time-out period from 1.6 ms ~ 26 sec (depending on clock source)

Interrupt or reset selectable when watchdog time-out
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
16

Clock Control


Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and
CRC-32
NuMicro Nano102/112 Datasheet





May 08, 2013
Window Watchdog Timer(WWDT)

6-bit down counter and 6-bit compare value to make the window period flexible

Selectable WWDT clock pre-scale counter to make WWDT time-out interval
variable.
RTC

Supports software compensation by setting frequency compensate register
(FCR)

Supports RTC counter (second, minute, hour) and calendar counter (day,
month, year)

Supports Alarm registers (second, minute, hour, day, month, year)

Selectable 12-hour or 24-hour mode

Automatic leap year recognition

Supports periodic time tick interrupt with 8 periodic options 1/128, 1/64, 1/32,
1/16, 1/8, 1/4, 1/2 and 1 second

Wake system up from Power-down mode

Supports 80 bytes spare registers and a snoop pin to clear the content of these
spare registers

Supports 1, 1/2, 1/4, 1/8, 1/16 Hz clock output
PWM/Capture

Supports 1 PWM module with two 16-bit PWM generators

Provides four PWM outputs or two complementary paired PWM outputs

Each PWM generator equipped with one clock divider, one 8-bit prescaler, two
clock selectors, and one Dead-zone generator for complementary paired PWM

(Shared with PWM timers) with four 16-bit digital capture timers provides four
rising/ falling/both capture inputs.

Supports One-shot and Continuous mode

Supports Capture interrupt
UART

Up to 1 Mbit/s baud rate and support 9600 baud rate @ 32kHz, low power mode

Up to two 16-byte FIFO UART controllers

UART ports with flow control (TX, RX, CTSn and RTSn)

Supports IrDA (SIR) function

Supports LIN function

Supports RS-485 9 bit mode and direction control.

Programmable baud rate generator

Supports PDMA mode

Wake system (CTSn, received data or RS-485 address matched) up from
Power-down mode
SPI
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
Wake system up from Power-down mode
NuMicro Nano102/112 Datasheet

May 08, 2013
Up to two sets of SPI controllers

Master up to 32 MHz, and Slave up to 16 MHz

Supports SPI/MICROWIRE Master/Slave mode

Full duplex synchronous serial data transfer

Variable length of transfer data from 4 to 32 bits

MSB or LSB first data transfer

RX and TX on both rising or falling edge of serial clock independently

Two slave/device select lines when SPI controller is used as the master, and 1
slave/device select line when SPI controller is used as the slave

Supports byte suspend mode in 32-bit transmission

Supports two channel PDMA requests, one for transmit and another for receive

Supports three wire mode, no slave select signal, bi-direction interface

Wake system up(SPI clock toggle) from Power-down mode
2
IC
2

Up to two sets of I C device

Master/Slave up to 1 Mbit/s

Bi-directional data transfer between masters and slaves

Multi-master bus (no central master)

Arbitration between simultaneously transmitting masters without corruption of
serial data on the bus

Serial clock synchronization allows devices with different bit rates to
communicate via one serial bus

Serial clock synchronization used as a handshake mechanism to suspend and
resume serial transfer

Built-in 14-bit time-out counter requesting the I C interrupt if the I C bus hangs
up and timer-out counter overflows

Programmable clocks allowing for versatile rate control

Supports 7-bit addressing mode

Supports multiple address recognition (four slave addresses with mask option)

Wake system up(address match) from Power-down mode
2
2
ADC

12-bit SAR ADC up to 1Msps conversion rate

Up to 8-ch single-ended input from external pin (PA.0 ~ PA.7)

Four internal channels from internal reference voltage (Int_VREF), Temperature
sensor, AVDD, and AVSS.

Supports three reference voltage sources from VREF pin, internal reference
voltage (Int_VREF), and AVDD.

Supports Single Scan, Single Cycle Scan, and Continuous Scan mode

Each channel with individual result register

Only scan on enabled channels
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NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
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
NuMicro Nano102/112 Datasheet


Threshold voltage detection (comparator function)

Conversion started by software programming or external input

Supports PDMA mode

Supports up to four timer time-out events (TMR0, TMR1, TMR2 and TMR3) to
enable ADC
SmartCard (SC)

Compliant to ISO-7816-3 T=0, T=1

Supports up to two ISO-7816-3 ports

Separates receive/transmit 4 bytes entry FIFO for data payloads

Programmable transmission clock frequency

Programmable receiver buffer trigger level

Programmable guard time selection (11 ETU ~ 267 ETU)

A 24-bit and two 8-bit time-out counters for Answer to Request (ATR) and
waiting times processing

Supports auto inverse convention function

Supports transmitter and receiver error retry and error limit function

Supports hardware activation sequence process

Supports hardware warm reset sequence process

Supports hardware deactivation sequence process

Supports hardware auto deactivation sequence when detect the card is removal

Supports UART mode (full–duplex)
ACMP

Supports up to 2 analog comparators

Analog input voltage range: 0 ~ AVDD

Supports Hysteresis function

Two analog comparators with optional internal reference voltage input at
negative end
Wake-up source

Support RTC, WDT, I²C, Timer, UART, SPI, BOD, GPIO

One built-in temperature sensor with 1℃ resolution

Brown-out

Built-in 2.5V/2.0V/1.7V BOD for wide operating voltage range operation

96-bit unique ID

128-bit unique customer ID

Operating Temperature: -40℃~85℃

Packages:
May 08, 2013

All Green package (RoHS)

LQFP 64-pin(7x7) / 48-pin(7x7)/ QFN33-pin(5x5)
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NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
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
NuMicro Nano102/112 Datasheet
2.2
Nano112 Features – LCD Line

Low Supply Voltage Range: 1.8 V to 3.6 V

Ultra-Low Power Consumption

Operation mode : 150 uA/MHz

Power-down mode : 1.5 uA (RTC on, RAM retention)

Deep power down mode : 650 nA (RAM retention)

Fast Wake-Up From Standby Mode : Less than 6 μs

Core


ARM Cortex™-M0 core running up to 32 MHz

One 24-bit system timer

Supports Low Power Sleep mode

Single-cycle 32-bit hardware multiplier

NVIC for the 32 interrupt inputs, each with 4-levels of priority

Serial Wire Debug supports with 2 watchpoints/4 breakpoints
Flash EPROM Memory

Runs up to 32 MHz with zero wait state for discontinuous address read access.

16/32 Kbytes application program memory (APROM)

4 Kbytes In System Programming (ISP) loader program memory (LDROM)

Programmable data flash start address and memory size with 512 bytes page
erase unit

In System Program (ISP)/In Application Program (IAP) to update on chip Flash
EPROM
SRAM Memory

4/8 Kbytes embedded SRAM

Supports DMA mode
DMA : Supports 5 channels: 4 PDMA channels, and one CRC channel


PDMA

Peripheral-to-memory,
transfer

Supports word boundary address

Supports word alignment transfer length in memory-to-memory mode

Supports word/half-word/byte alignment transfer length in peripheral-tomemory and memory-to-peripheral mode

Supports word/half-word/byte transfer data width from/to peripheral

Supports address direction: increment, fixed, and wrap around
and
memory-to-memory
CRC

Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and
CRC-32

May 08, 2013
memory-to-peripheral,
CRC-CCITT: X
16
+X
12
5
+X +1
Page 15 of 100
Revision 1.01
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET

®

NuMicro Nano102/112 Datasheet



CRC-16: X

CRC-32: X + X
4
2
X +X +X+1
16
32
+X
15
+X +1
2
26
+X
23
+X
22
+X
16
+X
12
+X
11
+X
10
8
7
5
+X +X +X +

Flexible selection for different applications

Built-in 12/16 MHz OSC, can be trimmed to 1 % deviation within all temperature
range when turning on auto-trim function (system must have external 32.768
kHz crystal input) otherwise 12/16 MHz OSC has 2 % deviation within all
temperarure range.

Low power 10 kHz OSC for watchdog and low power system operation

Supports one PLL, up to 32 MHz, for high performance system operation

External 4~24 MHz crystal input for precise timing operation

External 32.768 kHz crystal input for RTC function and low power system
operation
GPIO
Three I/O modes:

Push-Pull output

Open-Drain output

Input only with high impendence

All inputs with Schmitt trigger

I/O pin configured as interrupt source with edge/level setting

Supports High Driver and High Sink I/O mode

Supports input 5V tolerance, except PA.0 ~ PA.7, PA.12, PA.13, P.0(X32I),
PF.1(X32O)
Timer

Supports 4 sets of 32-bit timers, each with 24-bit up-timer and one 8-bit prescale counter

Independent Clock Source for each timer

Provides one-shot,periodic, output toggle and continuous operation modes

Internal trigger event to ADC and PDMA

Supports PDMA mode

Wake system up from Power-down mode
Watchdog Timer

Clock Source from LIRC (Internal 10 kHz Low Speed Oscillator Clock)

Selectable time-out period from 1.6 ms ~ 26 sec (depending on clock source)

Interrupt or reset selectable when watchdog time-out

Wake system up from Power-down mode
Window Watchdog Timer(WWDT)

May 08, 2013

6-bit down counter and 6-bit compare value to make the window period flexible
Page 16 of 100
Revision 1.01
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET

2
CRC-8: X + X + X + 1
Clock Control


8

NuMicro Nano102/112 Datasheet




May 08, 2013
RTC

Supports software compensation by setting frequency compensate register
(FCR)

Supports RTC counter (second, minute, hour) and calendar counter (day,
month, year)

Supports Alarm registers (second, minute, hour, day, month, year)

Selectable 12-hour or 24-hour mode

Automatic leap year recognition

Supports periodic time tick interrupt with 8 periodic options 1/128, 1/64, 1/32,
1/16, 1/8, 1/4, 1/2 and 1 second

Wake system up from Power-down mode

Supports 80 bytes spare registers and a snoop pin to clear the content of these
spare registers

Supports 1, 1/2, 1/4, 1/8, 1/16 Hz clock output
PWM/Capture

Supports 1 PWM module with two 16-bit PWM generators

Provides four PWM outputs or two complementary paired PWM outputs

Each PWM generator equipped with one clock divider, one 8-bit prescaler, two
clock selectors, and one Dead-zone generator for complementary paired PWM

(Shared with PWM timers) with four 16-bit digital capture timers provides four
rising/ falling/both capture inputs.

Supports Capture interrupt
UART

Up to 1 Mbit/s baud rate and support 9600 baud rate @ 32kHz, low power mode

Up to two 16-byte FIFO UART controllers

UART ports with flow control (TX, RX, CTSn and RTSn)

Supports IrDA (SIR) function

Supports LIN function

Supports RS-485 9 bit mode and direction control (Low Density Only)

Programmable baud rate generator

Supports PDMA mode

Wake system up (CTS, received data or RS-485 address matched) from Powerdown mode
SPI

Up to two sets of SPI controller

Master up to 32 MHz, and Slave up to 16 MHz

Supports SPI/MICROWIRE Master/Slave mode

Full duplex synchronous serial data transfer
Page 17 of 100
Revision 1.01
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET

Selectable WWDT clock pre-scale counter to make WWDT time-out interval
variable.
NuMicro Nano102/112 Datasheet

May 08, 2013
Variable length of transfer data from 4 to 32 bits

MSB or LSB first data transfer

RX and TX on both rising or falling edge of serial clock independently

Two slave/device select lines when SPI controller is as the master, and 1
slave/device select line when SPI controller is as the slave

Supports byte suspend mode in 32-bit transmission

Supports two channel PDMA requests, one for transmit and another for receive

Supports three wire mode, no slave select signal, bi-direction interface

Wake system up (SPI clock toggle) from Power-down mode
2
IC
2

Up to two sets of I C devices

Master/Slave up to 1Mbit/s

Bidirectional data transfer between masters and slaves

Multi-master bus (no central master)

Arbitration between simultaneously transmitting masters without corruption of
serial data on the bus

Serial clock synchronization allowing devices with different bit rates to
communicate via one serial bus

Serial clock synchronization used as a handshake mechanism to suspend and
resume serial transfer

Built-in 14-bit time-out counter requestING the I C interrupt if the I C bus hangs
up and timer-out counter overflows

Programmable clocks allow versatile rate control

Supports 7-bit addressing mode

Supports multiple address recognition (four slave address with mask option)

Wake system up (address match) from Power-down mode
2
2
ADC

12-bit SAR ADC up to 1Msps conversion rate

Up to 7-ch single-ended input from external pin (PA.0 ~ PA.6)

Four internal channels from internal reference voltage (Int_VREF), Temperature
sensor, AVDD, and AVSS

Supports three reference voltage sources from VREF pin, internal reference
voltage (Int_VREF), and AVDD.

Single scan/single cycle scan/continuous scan

Each channel with individual result register

Only scan on enabled channels

Threshold voltage detection (comparator function)

Conversion start by software programming or external input

Supports PDMA mode

Supports up to four timer time-out events (TMR0, TMR1, TMR2, and TMR3) to
Page 18 of 100
Revision 1.01
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET


NuMicro Nano102/112 Datasheet
enable ADC



Compliant to ISO-7816-3 T=0, T=1

Supports up to two ISO-7816-3 ports

Separates receive / transmit 4 bytes entry FIFO for data payloads

Programmable transmission clock frequency

Programmable receiver buffer trigger level

Programmable guard time selection (11 ETU ~ 267 ETU)

A 24-bit and two 8-bit time-out counter for Answer to Request (ATR) and waiting
times processing

Supports auto inverse convention function

Supports transmitter and receiver error retry and error limit function

Supports hardware activation sequence process

Supports hardware warm reset sequence process

Supports hardware deactivation sequence process

Supports hardware auto deactivation sequence when detect the card is removal

Supports UART mode (full-duplex)
ACMP

Suuports up to 2 analog comparators

Analog input voltage range: 0 ~ AVDD

Supports Hysteresis function

Two analog comparators with optional internal reference voltage input at
negative end
Wake-up source



May 08, 2013
Support RTC, WDT, I²C, Timer, UART, SPI, BOD, GPIO
LCD

LCD driver for up to 4 COM x 36 SEG or 6 COM x 34 SEG

Supports Static,1/2 bias and 1/3 bias voltage

Six display modes; Static, 1/2 duty, 1/3 duty, 1/4 duty, 1/5 duty and 1/6 duty.

Selectable LCD frequency by frequency divider

Configurable frame frequency

Internal Charge pump, adjustable contrast adjustment

Configurable Charge pump frequency

Blinking capability

Supports R-type/C-type/External C-type method

Configurable internal R-ladder resistor value (200K/300K/400K)

LCD frame interrupt
One built-in temperature sensor with 1℃ resolution
Page 19 of 100
Revision 1.01
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET

SmartCard (SC)
NuMicro Nano102/112 Datasheet

Brown-out

Built-in 2.5V/2.0V/1.7V BOD for wide operating voltage range operation

96-bit unique ID

128-bit unique customer ID

Operating Temperature: -40℃~85℃

Packages:

All Green package (RoHS)

LQFP 100-pin(14x14) / 64-pin(10x10) / 64-pin(7x7) / 48-pin(7x7)
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
May 08, 2013
Page 20 of 100
Revision 1.01
NuMicro Nano102/112 Datasheet
3
ABBREVIATIONS
Description
ACMP
Analog Comparator Controller
ADC
Analog-to-Digital Converter
AES
Advanced Encryption Standard
APB
Advanced Peripheral Bus
AHB
Advanced High-Performance Bus
BOD
Brown-out Detection
CAN
Controller Area Network
DAP
Debug Access Port
DES
Data Encryption Standard
EBI
External Bus Interface
EPWM
Enhanced Pulse Width Modulation
FIFO
First In, First Out
FMC
Flash Memory Controller
FPU
Floating-point Unit
GPIO
General-Purpose Input/Output
HCLK
The Clock of Advanced High-Performance Bus
HIRC
12/16 MHz Internal High Speed RC Oscillator
HXT
4~24 MHz External High Speed Crystal Oscillator
IAP
In Application Programming
ICP
In Circuit Programming
ISP
In System Programming
LDO
Low Dropout Regulator
LIN
Local Interconnect Network
LIRC
10 kHz internal low speed RC oscillator (LIRC)
MPU
Memory Protection Unit
NTC
Negative Temperature Coefficient
NVIC
Nested Vectored Interrupt Controller
PCLK
The Clock of Advanced Peripheral Bus
PDMA
Peripheral Direct Memory Access
PLL
Phase-Locked Loop
PTC
Positive Temperature Coefficient
PT1000
Thermal Resistance
PWM
Pulse Width Modulation
May 08, 2013
Page 21 of 100
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
Acronym
Revision 1.01
NuMicro Nano102/112 Datasheet
QEI
Quadrature Encoder Interface
SDIO
Secure Digital Input/Output
SPI
Serial Peripheral Interface
SPS
Samples per Second
TDES
Triple Data Encryption Standard
TMR
Timer Controller
UART
Universal Asynchronous Receiver/Transmitter
UCID
Unique Customer ID
USB
Universal Serial Bus
WDT
Watchdog Timer
WWDT
Window Watchdog Timer
Table 3‑1 List of Abbreviations
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
May 08, 2013
Page 22 of 100
Revision 1.01
NuMicro Nano102/112 Datasheet
4
PARTS INFORMATION LIST AND PIN CONFIGURATION
4.1
NuMicro Nano102/112 Series Selection Code
NANO 1 X 2 - X X X A N
Temperature
N : - 40 ℃ ~ +85℃
E : - 40 ℃ ~ +105℃
C : - 40 ℃ ~ +125℃
Version
A : Version
Ultra-low Power M0
Product Line Function
102 : Base Line
112 : LCD Line
Package Type
Z : QFN 33 (5x5mm.0.5mm pitch)
L : LQFP 48 (7x7mm,0.5mm pitch)
S : LQFP 64 (7x7mm,0.4mm pitch)
R : LQFP 64 (10x10mm,0.5mm pitch)
V : LQFP 100 (14x14mm,0.5mm pitch)
Figure 4-1 NuMicro
Flash ROM
A: 8KB
B: 16KB
C: 32KB
Nano112 Series Selection Code
NuMicro Nano112 Products Selection Guide
4.2.1
NuMicro Nano102 Base Line Selection Guide
Connectivity
Part No.
NANO102ZB1AN
NANO102ZC2AN
NANO102LB1AN
NANO102LC2AN
NANO102SC2AN
QFN33: 5x5mm
LQFP48: 7x7mm
LQFP64*: 7x7mm
Flash SRAM
16K
32K
16K
32K
32K
May 08, 2013
4K
8K
4K
8K
8K
Data
Flash
ISP
ROM
I/O
Configurable
Configurable
Configurable
Configurable
Configurable
4K
4K
4K
4K
4K
up to 27
up to 27
up to 40
up to 40
up to 58
Timer
(32-bit)
4
4
4
4
4
Comp
UART
SPI
I2C
3
3
4
4
4
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
PWM ADC
RTC
(16-bit) (12-bit)
4
4
4
4
4
2
2
7
7
7
Page 23 of 100
√
√
√
√
√
IRC
10 kHz /
12 MHz /
16 MHz
PDMA
LCD
ISO7816-3
ISP
ICP
Package
Maximum
Operating Temp.
Range (°C )
√
√
√
√
√
4
4
4
4
4
-
1
1
2
2
2
√
√
√
√
√
QFN33
QFN33
LQFP48
LQFP48
LQFP64*
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
Revision 1.01
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
4.2
TM
SRAM Size
0 : 2KB
1 : 4KB
2 : 8KB
NuMicro Nano102/112 Datasheet
4.2.2
NuMicro Nano112 LCD Line Selection Guide
UART
SPI
IC
NANO112LB1AN
16K
4K
Configurable
4K
up to 40
4
4
2
2
2
4
7
√
IRC
10KHz /
12MHz /
16MHz
√
4
4x20, 6x18
2
√
LQFP48
-40 to +85
NANO112LC2AN
32K
8K
Configurable
4K
up to 40
4
4
2
2
2
4
7
√
√
4
4x20, 6x18
2
√
LQFP48
-40 to +85
NANO112SB1AN
16K
4K
Configurable
4K
up to 58
4
4
2
2
2
4
7
√
√
4
4x32, 6x30
2
√
LQFP64
-40 to +85
NANO112SC2AN
32K
8K
Configurable
4K
up to 58
4
4
2
2
2
4
7
√
√
4
4x32, 6x30
2
√
LQFP64
-40 to +85
NANO112RB1AN
16K
4K
Configurable
4K
up to 58
4
4
2
2
2
4
7
√
√
4
4x32, 6x30
2
√
LQFP64*
-40 to +85
NANO112RC2AN
32K
8K
Configurable
4K
up to 58
4
4
2
2
2
4
7
√
√
4
4x32, 6x30
2
√
LQFP64*
-40 to +85
NANO112VC2AN
LQFP48: 7x7mm
LQFP64: 7x7mm
LQFP64*: 10x10mm
32K
8K
Configurable
4K
up to 80
4
4
2
2
2
4
8
√
√
4
4x36, 6x34
2
√
LQFP100
-40 to +85
Part No.
Flash SRAM
Data
Flash
ISP
ROM
I/O
Timer
(32-bit)
Connectivity
Comp
2
PWM ADC
RTC
(16-bit) (12-bit)
PDMA
LCD
ISO7816-3
ISP
ICP
Package
Maximum
Operating Temp.
Range (°C )
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
May 08, 2013
Page 24 of 100
Revision 1.01
NuMicro Nano102/112 Datasheet
Pin Configuration
NuMicro Nano102 Pin Diagrams
PA.3/ADC3
PA.2/ADC2
PA.1/ADC1
PA.0/ADC0
AVSS
PF.3/XT1_OUT
PF.2/XT1_IN
VSS
PF.1/X32O
PF.0/X32I
VDD
LDO_CAP
nRESET
PD.15
PD.14
PD.13
46
45
44
43
42
41
40
39
38
37
36
35
34
33
NuMicro Nano102 LQFP 64-pin
47
4.3.1.1
48
4.3.1
ADC4/PA.4
49
32
NC
ADC5/PA.5
50
31
PD.12
ADC6/PA.6
51
30
PD.11
VREF
52
29
PD.10
AVDD
53
28
PD.9
54
27
PD.8
55
26
PD.7
PA.12
56
25
PD.6
PA.13
57
24
PD.5
PA.14
58
23
PD.4
PA.15
59
22
PD.3
PB.0
60
21
PD.2
PB.1
61
20
PD.1
PB.2
62
19
PD.0
PB.3
63
18
PC.15
PB.6
64
17
PC.14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PB.11
PB.12
PB.13
PB.14
PB.15
PC.0
PC.1
PC.2
PC.3
PC.4
PC.5
PC.6
PC.7
PC.8
PC.9
Nano102
LQFP 64-pin
Figure 4‑ 2 NuMicro
May 08, 2013
TM
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
ICE_CLK/PF.4
ICE_DAT/PF.5
PB.10
4.3
Nano102 LQFP 64-pin Diagram
Page 25 of 100
Revision 1.01
NuMicro Nano102/112 Datasheet
PA.2/ADC2
PA.1/ADC1
PA.0/ADC0
AVSS
PF.3/XT1_OUT
PF.2/XT1_IN
VSS
PF.1/X32O
PF.0/X32I
VDD
LDO_CAP
nRESET
36
35
34
33
32
31
30
29
28
27
26
25
NuMicro Nano102 LQFP 48-pin
ADC3/PA.3
37
24
PD.15
ADC4/PA.4
38
23
PD.14
ADC5/PA.5
39
22
PD.13
ADC6/PA.6
40
21
NC
VREF
41
20
PD.10
AVDD
42
19
PD.9
ICE_CLK/PF.4
43
18
PD.8
ICE_DAT/PF.5
44
17
PD.7
PA.12
45
16
PC.15
PA.13
46
15
PC.14
PA.14
47
14
PC.9
PA.15
48
13
PC.8
2
3
4
5
6
7
8
9
10
11
12
PB.13
PB.14
PB.15
PC.0
PC.1
PC.2
PC.3
PC.4
PC.5
PC.6
PC.7
Figure 4‑3 NuMicro
May 08, 2013
TM
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
1
NANO102
LQFP 48-pin
PB.12
4.3.1.2
Nano102 LQFP 48-pin Diagram
Page 26 of 100
Revision 1.01
NuMicro Nano102/112 Datasheet
nRESET
LDO_CAP
VDD
PF.0/X32I
PF.1/X32O
VSS
PF.2/XT1_IN
NuMicro Nano102 QFN 33-pin
PF.3/XT1_OUT
4.3.1.3
24 23 22 21 20 19 18 17
PA.4
25
16 PD.12
PA.5
26
15 PD.11
AVDD
27
14 PD.10
ICE_CLK/PF.4
28
ICE_DAT/PF.5
29
PA.12
30
PA.13
31
12 PC.13
10 PC.11
33 VSS
5
6
7
8
PC.6
PC.7
PC.8
PB.14
4
PC.4
3
PB.15
2
9 PC.10
TM
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
1
PB.13
32
Figure 4‑4 NuMicro
May 08, 2013
13 PD.9
11 PC.12
PB.12
PA.14
NANO102
QFN 33-pin
Nano102 QFN 32-pin Diagram
Page 27 of 100
Revision 1.01
NuMicro Nano102/112 Datasheet
NuMicro Nano112 Pin Diagrams
PE.3
PE.2
PE.1
PE.0
NC
PF.3/XT1_OUT
PF.2/XT1_IN
VSS
VSS
VSS_PLL
PF.1/X32O
PF.0/X32I
VDD
LDO_CAP
nRESET
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PE.4
65
PE.5
66
AVSS
67
AVSS
70
PE.7
PA.0/ADC0
71
PE.6
PA.1/ADC1
72
68
PA.2/ADC2
73
69
PA.3/ADC3
NuMicro Nano112 LQFP 100-pin
74
4.3.2.1
75
4.3.2
76
50
PD.15/V3
ADC5/PA.5
77
49
PD.14/V2
ADC6/PA.6
78
48
PD.13/V1
ADC7/PA.7
79
47
NC
VREF
80
46
VLCD
AVDD
81
45
NC
ICE_CLK/PF.4
82
44
PD.12/DH1
ICE_DAT/PF.5
83
43
PD.11/DH2
PA.8
84
42
PD.10/COM0
PA.9
85
41
PD.9/COM1
PA.10
86
40
PD.8/COM2
PA.11
87
39
PD.7/COM3
PA.12
88
38
PD.6/SEG0
PA.13
89
37
PD.5/SEG1
PA.14
90
36
PD.4/SEG2
PA.15
91
35
PD.3/SEG3
PB.0
92
34
PD.2/SEG4
PB.1
93
33
PD.1/SEG5
PB.2
94
32
PD.0/SEG6
PB.3
95
31
PC.15/SEG7
VDD
96
30
PC.14/SEG8
VSS
97
29
PC.13/SEG9
PB.4
98
28
PC.12/SEG10
SEG35/PB.5
99
27
PC.11/SEG11
SEG34/PB.6
100
26
PC.10/SEG12
May 08, 2013
18
19
20
21
22
23
24
25
SEG16/PC.6
SEG15/PC.7
SEG14/PC.8
SEG13/PC.9
VDD
VSS
VSS
12
SEG23/PB.15
SEG17/PC.5
11
NC
17
10
SEG24/PB.14
SEG18/PC.4
9
SEG25/PB.13
16
8
SEG26/PB.12
SEG19/8PC.3
7
SEG27/PB.11
15
6
SEG28/PB.10
SEG20/PC.2
5
SEG29/PE.9
14
4
SEG30/PE.8
13
3
SEG31/PB.9
TM
SEG21/PC.1
2
SEG32/PB.8
Figure 4‑5 NuMicro
SEG22/PC.0
1
SEG33/PB.7
NANO112
LQFP 100-pin
Nano112 LQFP 100-pin Diagram
Page 28 of 100
Revision 1.01
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
ADC4/PA.4
NuMicro Nano102/112 Datasheet
PA.3/ADC3
PA.2/ADC2
PA.1/ADC1
PA.0/ADC0
AVSS
PF.3/XT1_OUT
PF.2/XT1_IN
VSS
PF.1/X32O
PF.0/X32I
VDD
LDO_CAP
nRESET
PD.15/V3
PD.14/V2
PD.13/V1
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
NuMicro Nano112 LQFP 64-pin
48
4.3.2.2
49
32
VLCD
ADC5/PA.5
50
31
PD.12/DH1
ADC6/PA.6
51
30
PD.11/DH2
VREF
52
29
PD.10/COM0
AVDD
53
28
PD.9/COM1
ICE_CLK/PF.4
54
27
PD.8/COM2
ICE_DAT/PF.5
55
26
PD.7/COM3
PA.12
56
25
PD.6/SEG0
PA.13
57
24
PD.5/SEG1
SEG31/PA.14
58
23
PD.4/SEG2
SEG30/PA.15
59
22
PD.3/SEG3
SEG29/PB.0
60
21
PD.2/SEG4
SEG28/PB.1
61
20
PD.1/SEG5
SEG27/PB.2
62
19
PD.0/SEG6
SEG26/PB.3
63
18
PC.15/SEG7
SEG25/PB.6
64
17
PC.14/SEG8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SEG24/PB.10
SEG23/PB.11
SEG22/PB.12
SEG21/PB.13
SEG20/PB.14
SEG19/PB.15
SEG18/PC.0
SEG17/PC.1
SEG16/PC.2
SEG15/PC.3
SEG14/PC.4
SEG13/PC.5
SEG12/PC.6
SEG11/PC.7
SEG10/PC.8
SEG9/PC.9
Nano112
LQFP 64-pin
Figure 4‑6 NuMicro
May 08, 2013
TM
Nano112 LQFP 64-pin Diagram
Page 29 of 100
Revision 1.01
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
ADC4/PA.4
NuMicro Nano102/112 Datasheet
PA.2/ADC2
PA.1/ADC1
PA.0/ADC0
AVSS
PF.3/XT1_OUT
PF.2/XT1_IN
VSS
PF.1/X32O
PF.0/X32I
VDD
LDO_CAP
nRESET
36
35
34
33
32
31
30
29
28
27
26
25
NuMicro Nano112 LQFP 48-pin
ADC3/PA.3
37
24
PD.15/V3
ADC4/PA.4
38
23
PD.14/V2
ADC5/PA.5
39
22
PD.13/V1
ADC6/PA.6
40
21
VLCD
VREF
41
20
PD.10/COM0
AVDD
42
19
PD.9/COM1
ICE_CLK/PF.4
43
18
PD.8/COM2
ICE_DAT/PF.5
44
17
PD.7/COM3
SEG19/PA.12
45
16
PC.15/SEG0
SEG18/PA.13
46
15
PC.14/SEG1
SEG17/PA.14
47
14
PC.9/SEG2
SEG16/PA.15
48
13
PC.8/SEG3
May 08, 2013
7
8
9
10
11
12
SEG8/PC.3
SEG7/PC.4
SEG6/PC.5
SEG5/PC.6
SEG4/PC.7
5
SEG11/PC.0
SEG9/PC.2
4
SEG12/PB.15
SEG10/PC.1
3
SEG13/PB.14
TM
6
2
SEG14/PB.13
Figure 4‑7 NuMicro
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
1
NANO112
LQFP 48-pin
SEG15/PB.12
4.3.2.3
Nano112 LQFP 48-pin Diagram
Page 30 of 100
Revision 1.01
NuMicro Nano102/112 Datasheet
4.4
4.4.1
Pin Description
NuMicro Nano102 Pin Description
Pin No.
Pin Name
64-pin
48-pin
1
2
General purpose digital I/O pin
UART1_RXD
I
UART1 Data receiver input pin
SPI0_MOSI1
I/O
SPI0 2nd MOSI (Master Out, Slave In)
pin
PB.11
I/O
General purpose digital I/O pin
UART1_RTSn
O
UART1 Request to Send output pin
SPI0_MISO1
I/O
SPI0 2rd MISO (Master In, Slave Out)
pin
TM1
I/O
Timer1 external counter input or
Timer1 toggle out
PB.12
I/O
General purpose digital I/O pin
UART0_RTSn
O
UART0 Request to Send output pin
5
6
7
8
2
3
4
1
SPI0_MOSI0
I/O
SPI0 1st MOSI (Master Out, Slave In)
pin
TM0
I/O
Timer0 external counter input or
Timer0 toggle out.
FCLK0
O
Frequency Divider0 output pin
PB.13
I/O
General purpose digital I/O pin
2
UART0_RXD
I
UART0 Data receiver input pin
SPI0_MISO0
I/O
SPI0 1st MISO (Master In, Slave Out)
pin
PB.14
I/O
General purpose digital I/O pin
3
UART0_TXD
O
UART0 Data transmitter output pin
(This pin could be modulated with
PWM0 output.)
SPI0_CLK
I/O
SPI0 serial clock pin
PB.15
I/O
General purpose digital I/O pin
4
I
UART0 Clear to Send input pin
UART0_CTSn
SPI0_SS0
I/O
SPI0 1st slave select pin
PC.0
I/O
General purpose digital I/O pin
SPI0_SS1
I/O
SPI0 2nd slave select pin
I2C0_SCL
I/O
I2C0 clock pin
PWM0_CH0
I/O
PWM0 Channel0 output
PC.1
I/O
General purpose digital I/O pin
I2C0_SDA
I/O
I2C0 data I/O pin
5
6
May 08, 2013
Page 31 of 100
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
4
1
Description
I/O
PB.10
3
Pin Type
32-pin
Revision 1.01
NuMicro Nano102/112 Datasheet
Pin No.
Pin Name
64-pin
9
10
11
12
48-pin
7
8
9
I/O
PWM0 Channel1 output
PC.2
I/O
General purpose digital I/O pin
I2C1_SCL
O
I2C1 clock pin
PWM0_CH2
I/O
PWM0 Channel2 output
PC.3
I/O
General purpose digital I/O pin
I2C1_SDA
I/O
I2C1 data I/O pin
PWM0_CH3
I/O
PWM0 Channel3 output
PC.4
I/O
General purpose digital I/O pin
UART1_CTSn
I
UART1 Clear to Send input pin
SC0_CLK
O
SmartCard0 clock pin
(SC0_UART_TXD)
INT0
I
External interrupt0 input pin
PC.5
I/O
5
15
16
General purpose digital I/O pin
10
11
12
13
6
7
8
14
9
I/O
General purpose digital I/O pin
UART1_RTSn
O
UART1 Request to Send output pin
SC0_DAT
I/O
SmartCard0 DATA pin
(SC0_UART_RXD)
PC.7
I/O
General purpose digital I/O pin
UART1_RXD
I
UART1 Data receiver input pin
SC0_PWR
O
SmartCard0 Power pin
PC.8
I/O
General purpose digital I/O pin
UART1_TXD
O
UART1 Data transmitter output pin
(This pin could be modulated with
PWM0 output.)
SC0_RST
O
SmartCard0 RST pin
PC.9
I/O
General purpose digital I/O pin
PC.10
I/O
General purpose digital I/O pin
I2C1_SCL
I/O
I2C1 clock pin
I
SmartCard1 card detect
PC.11
I/O
General purpose digital I/O pin
I2C1_SDA
I/O
I2C 1 data I/O pin
SC1_PWR
O
SmartCard1 PWR pin
PC.12
I/O
General purpose digital I/O pin
SC1_CLK
O
SmartCard1 clock pin
(SC1_UART_TXD)
11
May 08, 2013
SmartCard0 card detect pin
PC.6
SC1_CD
10
I
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
14
Description
PWM0_CH1
SC0_CD
13
Pin Type
32-pin
Page 32 of 100
Revision 1.01
NuMicro Nano102/112 Datasheet
Pin No.
Pin Name
64-pin
48-pin
Pin Type
PC.13
I/O
General purpose digital I/O pin
SC1_DAT
I/O
SmartCard1 DATA pin
(SC1_UART_RXD)
PC.14
I/O
General purpose digital I/O pin
12
17
Description
32-pin
15
SC1_CD
I
SmartCard1 card detect
PC.15
I/O
General purpose digital I/O pin
SC1_PWR
O
SmartCard1 PWR pin
19
PD.0
I/O
General purpose digital I/O pin
20
PD.1
I/O
General purpose digital I/O pin
21
PD.2
I/O
General purpose digital I/O pin
22
PD.3
I/O
General purpose digital I/O pin
PD.4
I/O
General purpose digital I/O pin
SC1_RST
O
SmartCard1 RST pin
24
PD.5
I/O
General purpose digital I/O pin
25
PD.6
I/O
General purpose digital I/O pin
PD.7
I/O
General purpose digital I/O pin
SC1_CLK
O
SmartCard1 clock pin
(SC1_UART_TXD)
PD.8
I/O
General purpose digital I/O pin
SC1_DAT
I/O
SmartCard1 DATA pin
(SC1_UART_RXD)
PD.9
I/O
General purpose digital I/O pin
SC1_RST
O
SmartCard1 RST pin
PWM0_CH3
I/O
PWM0 Channel3 output
PD.10
I/O
General purpose digital I/O pin
PWM0_CH2
I/O
PWM0 Channel2 output
18
16
23
26
28
29
18
19
20
13
14
TC1
30
15
May 08, 2013
16
Timer1 capture input
PD.11
I/O
General purpose digital I/O pin
PWM0_CH1
I/O
PWM0 Channel1 output
TC0
31
I
I
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
27
17
Timer0 capture input
PD.12
I/O
General purpose digital I/O pin
CLK_Hz
O
1, 1/2, 1/4, 1/8, 1/16 Hz clock output
PWM0_CH0
I/O
PWM0 Channel0 output
TM1
I/O
Timer1 external counter input or
Timer1 toggle out
Page 33 of 100
Revision 1.01
NuMicro Nano102/112 Datasheet
Pin No.
Pin Name
64-pin
48-pin
FCLK0
32
21
33
22
Pin Type
Description
32-pin
O
Frequency Divider0 output pin
NC
PD.13
INT1
I/O
I
General purpose digital I/O pin
External interrupt 1 input pin
34
23
PD.14
I/O
General purpose digital I/O pin
35
24
PD.15
I/O
General purpose digital I/O pin
36
25
17
nRESET
I
External reset input: low active. Setting
this pin low will reset chip to initial
state. With internal pull-up.
37
26
18
LDO_CAP
P
LDO capacitor pin
38
27
19
VDD
P
Power supply for I/O ports and LDO
source
PF.0
I/O
X32I
I
TM3
I/O
Timer3 external counter input or
Timer3 toggle out.
PF.1
I/O
General purpose digital I/O pin
X32O
O
External 32.768 kHz crystal output pin
(default)
TM2
I/O
Timer2 external counter input or
Timer2 toggle out.
VSS
G
Ground for digital circuit
PF.2
I/O
General purpose digital I/O pin
XT1_IN
AI
External 4~24 MHz crystal input pin
(default)
39
41
42
43
29
30
31
32
20
21
22
23
24
External 32.768 kHz crystal input pin
(default)
UART1_RXD
I
UART1 Data receiver input pin
TC3
I
Timer3 capture input
INT1
I
External interrupt1 input pin
PF.3
I/O
General purpose digital I/O pin
XT1_OUT
AO
External 4~24 MHz crystal output pin
UART1_TXD
O
UART1 Data transmitter output pin
(This pin could be modulated with
PWM0 output.)
TC2
I
Timer2 capture input
INT0
I
External interrupt0 input pin
44
33
AVSS
G
Ground for ADC and comparators
45
34
PA.0
I/O
General purpose digital I/O pin
May 08, 2013
Page 34 of 100
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
40
28
General purpose digital I/O pin
Revision 1.01
NuMicro Nano102/112 Datasheet
Pin No.
Pin Name
64-pin
46
47
48
48-pin
AI
ADC analog input0
PA.1
I/O
General purpose digital I/O pin
AD1
AI
ADC analog input1
ACMP0_P3
AI
Comparator0 P-end input3
ACMP0_CHDIS
O
Comparator0 charge/discharge path
PA.2
I/O
General purpose digital I/O pin
SC0_CLK
O
SmartCard0 clock pin
(SC0_UART_TXD)
INT0
I
External interrupt0 input pin
AD2
AI
ADC analog input2
ACMP0_P2
AI
Comparator0 P-end input2
ACMP0_CHDIS
O
Comparator0 charge/discharge path
PA.3
I/O
General purpose digital I/O pin
SC0_DAT
I/O
SmartCard0 DATA
pin(SC0_UART_RXD)
35
36
37
INT1
I
External interrupt 1
AD3
AI
ADC analog input3
ACMP0_P1
AI
Comparator0 P-end input1
ACMP0_CHDIS
O
Comparator0 charge/discharge path
PA.4
I/O
General purpose digital I/O pin
51
38
39
40
May 08, 2013
25
26
I
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
50
Description
AD0
SC0_CD
49
Pin Type
32-pin
SmartCard0 card detect pin
AD4
AI
ADC analog input4
ACMP0_P0
AI
Comparator0 P-end input0
ACMP0_CHDIS
O
Comparator0 charge/discharge path
PA.5
I/O
General purpose digital I/O pin
SPI1_SS0
I/O
SPI1 1st slave select pin
I2C1_SDA
I/O
I2C1 data I/O pin
SC0_PWR
O
SmartCard0 Power pin
AD5
AI
ADC analog input5
ACMP0_N
AI
Comparator0 N-end input0
ACMP0_CHDIS
O
Comparator0 charge/discharge path
PA.6
I/O
General purpose digital I/O pin
ACMP0_CHDIS
O
Comparator0 charge/discharge path
SC0_RST
O
SmartCard0 RST pin
Page 35 of 100
Revision 1.01
NuMicro Nano102/112 Datasheet
Pin No.
Pin Name
64-pin
48-pin
52
41
53
42
54
55
57
58
59
44
45
46
47
27
ACMP0_OUT
O
Comparator0 output
AD6
AI
ADC analog input6
VREF
A
ADC/Comparator reference voltage
AVDD
P
Power supply for ADC and
comparators
PF.4
I/O
General purpose digital I/O pin
ICE_CLK
I
Serial Wired Debugger Clock pin
CLK_Hz
O
1, 1/2, 1/4, 1/8, 1/16 Hz clock output
PWM0_CH2
O
PWM0 Channel2 output
TC1
I
Timer1 capture input
FCLK1
O
Frequency Divider1 output pin
PF.5
I/O
General purpose digital I/O pin
ICE_DAT
I/O
Serial Wired Debugger Data pin
PWM0_CH3
I/O
PWM0 Channel3 output
28
29
TC0
I
Timer0 capture input
ACMP0_CHDIS
O
Comparator0 charge/discharge path
PA.12
I/O
General purpose digital I/O pin
UART0_TXD
O
UART0 Data transmitter output pin
(This pin could be modulated with
PWM0 output.)
SPI1_MOSI0
I/O
SPI1 1st MOSI (Master Out, Slave In)
pin
I2C0_SCL
I/O
I2C 0 clock pin
ACMP1_P
AI
Comparator1 P-end input
PA.13
I/O
General purpose digital I/O pin
UART0_RXD
I
UART0 Data receiver input pin
SPI1_MISO0
I/O
SPI1 1st MISO (Master In, Slave Out)
pin
I2C0_SDA
I/O
I2C0 data I/O pin
ACMP1_N
AI
Comparator1 N-end input
PA.14
I/O
General purpose digital I/O pin
SPI1_CLK
I/O
SPI1 serial clock pin
I2C1_SCL
I/O
I2C1 clock pin
ACMP0_CHDIS
O
Comparator0 charge/discharge path
PA.15
I/O
General purpose digital I/O pin
SPI1_SS0
I/O
SPI1 1st slave select pin
30
31
32
48
May 08, 2013
Description
Page 36 of 100
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
56
43
Pin Type
32-pin
Revision 1.01
NuMicro Nano102/112 Datasheet
Pin No.
64-pin
48-pin
60
Pin Name
Pin Type
I2C1_SDA
I/O
Description
32-pin
I2C1 data I/O pin
TC3
I
Timer3 capture input
ACMP1_OUT
O
Comparator1 output
PB.0
I/O
General purpose digital I/O pin
UART0_TXD
O
UART0 Data transmitter output
pin(This pin could modulate with
PWM0 output)
FCLK1
O
Frequency Divider1 output pin
PB.1
I/O
General purpose digital I/O pin
UART0_RXD
I
UART0 Data receiver input pin
TC2
I
Timer 2 capture input
INT1
I
External interrupt1 input pin
PB.2
I/O
General purpose digital I/O pin
UART0_RTSn
O
UART0 Request to Send output pin
SPI1_MOSI1
I/O
SPI1 2nd MOSI (Master Out, Slave In)
pin
I2C0_SCL
I/O
I2C0 clock pin
TM3
I/O
Timer3 external counter input or
Timer3 toggle out.
PB.3
I/O
General purpose digital I/O pin
UART0_CTSn
I
UART0 Clear to Send input pin
SPI1_MISO1
I/O
SPI1 2nd MISO (Master In, Slave Out)
pin
I2C0_SDA
I/O
I2C0 data I/O pin
TM2
I/O
Timer2 external counter input or
Timer2 toggle out.
PB.6
I/O
General purpose digital I/O pin
UART1_TXD
O
UART1 Data transmitter output pin
(This pin could be modulated with
PWM0 output.)
SPI1_SS1
I/O
SPI1 2nd slave select pin
FCLK0
O
Frequency Divider0 output pin
61
62
64
Note: Pin Type: I = Digital Input, O = Digital Output; AI = Analog Input; AO = Analog Output; P = Power Pin; AP = Analog
Power.
May 08, 2013
Page 37 of 100
Revision 1.01
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
63
NuMicro Nano102/112 Datasheet
4.4.2
NuMicro Nano112 Pin Description
Pin No.
Pin Name
100-pin 64-pin
Pin Type
Description
48-pin
PB.7
I/O
General purpose digital I/O pin
LCD_SEG33
O
LCD segment output 33 at 100-pin
UART1_CTSn
I
UART1 Clear to Send input pin
SC0_CD
I
SmartCard0 card detect
1
2
3
4
6
7
8
1
2
3
May 08, 2013
1
I/O
General purpose digital I/O pin
LCD_SEG32
O
LCD segment output 32 at 100-pin
SNOOPER
I
Snooper pin
PWM0_CH0
I/O
PWM0 Channel0 output
TM0
I/O
Timer0 external counter input or Timer0
toggle out.
INT1
I
PB.9
I/O
General purpose digital I/O pin
LCD_SEG31
O
LCD segment output 31 at 100-pin
PWM0_CH1
I/O
PWM0 Channel1 output
PE.8
I/O
General purpose digital I/O pin
LCD_SEG30
O
LCD segment output 30 at 100-pin
PWM0_CH2
I/O
PWM0 Channel2 output
PE.9
I/O
General purpose digital I/O pin
LCD_SEG29
O
LCD segment output 29 at 100-pin
PWM0_CH3
I/O
PWM0 Channel3 output
PB.10
I/O
General purpose digital I/O pin
LCD_SEG28
O
LCD segment output 28 at 100-pin
LCD_SEG24
O
LCD segment output 24 at 64-pin
UART1_RXD
I
UART1 Data receiver input pin
SPI0_MOSI1
I/O
SPI0 2nd MOSI (Master Out, Slave In) pin
PB.11
I/O
General purpose digital I/O pin
LCD_SEG27
O
LCD segment output 27 at 100-pin
LCD_SEG23
O
LCD segment output 23 at 64-pin
UART1_RTSn
O
UART1 Request to Send output pin
SPI0_MISO1
I/O
SPI0 2rd MISO (Master In, Slave Out) pin
TM1
I/O
Timer1 external counter input or Timer1
toggle out
PB.12
I/O
General purpose digital I/O pin
External interrupt1 input pin
Page 38 of 100
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
5
PB.8
Revision 1.01
NuMicro Nano102/112 Datasheet
Pin No.
Pin Name
100-pin 64-pin
9
5
13
LCD_SEG26
O
LCD segment output 26 at 100-pin
LCD_SEG22
O
LCD segment output 22 at 64-pin
LCD_SEG15
O
LCD segment output 15 at 48-pin
UART0_RTSn
O
UART0 Request to Send output pin
SPI0_MOSI0
I/O
SPI0 1st MOSI (Master Out, Slave In) pin
TM0
I/O
Timer0 external counter input or Timer0
toggle out.
FCLK0
O
Frequency Divider0 output pin
PB.13
I/O
General purpose digital I/O pin
LCD_SEG25
O
LCD segment output 25 at 100-pin
LCD_SEG21
O
LCD segment output 21 at 64-pin
LCD_SEG14
O
LCD segment output 14 at 48-pin
UART0_RXD
I
UART0 Data receiver input pin
SPI0_MISO0
I/O
SPI0 1st MISO (Master In, Slave Out) pin
PB.14
I/O
General purpose digital I/O pin
LCD_SEG24
O
LCD segment output 24 at 100-pin
LCD_SEG20
O
LCD segment output 20 at 64-pin
LCD_SEG13
O
LCD segment output 13 at 48-pin
UART0_TXD
O
UART0 Data transmitter output pin (This
pin could be modulated with PWM0
output.)
SPI0_CLK
I/O
SPI0 serial clock pin
PB.15
I/O
General purpose digital I/O pin
LCD_SEG23
O
LCD segment output 23 at 100-pin
LCD_SEG19
O
LCD segment output 19 at 64-pin
LCD_SEG12
O
LCD segment output 12 at 48-pin
UART0_CTSn
I
UART0 Clear to Send input pin
2
3
11
12
Description
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
10
4
Pin Type
48-pin
NC
6
7
May 08, 2013
4
SPI0_SS0
I/O
SPI0 1st slave select pin
PC.0
I/O
General purpose digital I/O pin
LCD_SEG22
O
LCD segment output 24 at 100-pin
LCD_SEG18
O
LCD segment output 18 at 64-pin
LCD_SEG11
O
LCD segment output 11 at 48-pin
SPI0_SS1
I/O
SPI0 2nd slave select pin
I2C0_SCL
I/O
I2C0 clock pin
5
Page 39 of 100
Revision 1.01
NuMicro Nano102/112 Datasheet
Pin No.
Pin Name
100-pin 64-pin
14
15
16
18
19
9
10
11
12
13
May 08, 2013
Description
PWM0_CH0
I/O
PWM0 Channel0 output
PC.1
I/O
General purpose digital I/O pin
LCD_SEG21
O
LCD segment output 21 at 100-pin
LCD_SEG17
O
LCD segment output 17 at 64-pin
LCD_SEG10
O
LCD segment output 10 at 48-pin
I2C0_SDA
I/O
I2C0 data I/O pin
PWM0_CH1
I/O
PWM0 Channel1 output
PC.2
I/O
General purpose digital I/O pin
LCD_SEG20
O
LCD segment output 20 at 100-pin
LCD_SEG16
O
LCD segment output 16 at 64-pin
LCD_SEG9
O
LCD segment output 9 at 48-pin
I2C1_SCL
O
I2C1 clock pin
PWM0_CH2
I/O
PWM0 Channel2 output
PC.3
I/O
General purpose digital I/O pin
LCD_SEG19
O
LCD segment output 19 at 100-pin
LCD_SEG15
O
LCD segment output 15 at 64-pin
LCD_SEG8
O
LCD segment output 8 at 48-pin
I2C1_SDA
I/O
I2C1 data I/O pin
PWM0_CH3
I/O
PWM0 Channel3 output
PC.4
I/O
General purpose digital I/O pin
LCD_SEG18
O
LCD segment output 18 at 100-pin
LCD_SEG14
O
LCD segment output 14 at 64-pin
LCD_SEG7
O
LCD segment output 7 at 48-pin
UART1_CTSn
I
UART1 Clear to Send input pin
SC0_CLK
O
SmartCard0 clock pin
(SC0_UART_TXD)
INT0
I
External interrupt0 input pin
PC.5
I/O
General purpose digital I/O pin
LCD_SEG17
O
LCD segment output 17 at 100-pin
LCD_SEG13
O
LCD segment output 13 at 64-pin
LCD_SEG6
O
LCD segment output 6 at 48-pin
SC0_CD
I
SmartCard0 card detect pin
6
7
8
9
10
PC.6
I/O
General purpose digital I/O pin
LCD_SEG16
O
LCD segment output 16 at 100-pin
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
17
8
Pin Type
48-pin
11
Page 40 of 100
Revision 1.01
NuMicro Nano102/112 Datasheet
Pin No.
Pin Name
100-pin 64-pin
Pin Type
Description
48-pin
LCD_SEG12
O
LCD segment output 12 at 64-pin
LCD_SEG5
O
LCD segment output 5 at 48-pin
UART1_RTSn
O
UART1 Request to Send output pin
SC0_DAT
I/O
SmartCard0 DATA pin
(SC0_UART_RXD)
PC.7
I/O
General purpose digital I/O pin
LCD_SEG15
O
LCD segment output 15 at 100-pin
LCD_SEG11
O
LCD segment output 11 at 64-pin
LCD_SEG4
O
LCD segment output 4 at 48-pin
UART1_RXD
I
UART1 Data receiver input pin
SC0_PWR
O
SmartCard0 Power pin
PC.8
I/O
General purpose digital I/O pin
LCD_SEG14
O
LCD segment output 14 at 100-pin
LCD_SEG10
O
LCD segment output 10 at 64-pin
LCD_SEG3
O
LCD segment output 3 at 48-pin
UART1_TXD
O
UART1 Data transmitter output pin (This
pin could be modulated with PWM0
output.)
SC0_RST
O
SmartCard0 RST pin
PC.9
I/O
General purpose digital I/O pin
LCD_SEG13
O
LCD segment output 13 at 100-pin
LCD_SEG9
O
LCD segment output 9 at 64-pin
LCD_SEG2
O
LCD segment output 2 at 48-pin
23
VDD
P
Power supply for I/O ports and LDO
source
24
VSS
G
Ground for digital circuit
25
VSS
G
Ground for digital circuit
PC.10
I/O
General purpose digital I/O pin
LCD_SEG12
O
LCD segment output 12 at 100-pin
I2C1_SCL
I/O
I2C1 clock pin
20
21
15
16
12
13
14
26
SC1_CD
I
SmartCard1 card detect pin
PC.11
I/O
General purpose digital I/O pin
LCD_SEG11
O
LCD segment output 11 at 100-pin
I2C1_SDA
I/O
I2C 1 data I/O pin
SC1_PWR
O
SmartCard1 PWR pin
27
May 08, 2013
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
22
14
Page 41 of 100
Revision 1.01
NuMicro Nano102/112 Datasheet
Pin No.
Pin Name
100-pin 64-pin
28
29
30
31
33
34
35
36
18
19
20
21
22
Description
15
16
PC.12
I/O
General purpose digital I/O pin
LCD_SEG10
O
LCD segment output 10 at 100-pin
SC1_CLK
O
SmartCard1 clock pin
(SC1_UART_TXD)
PC.13
I/O
General purpose digital I/O pin
LCD_SEG9
O
LCD segment output 9 at 100-pin
SC1_DAT
I/O
SmartCard1 DATA pin
(SC1_UART_RXD)
PC.14
I/O
General purpose digital I/O pin
LCD_SEG8
O
LCD segment output 8 at 100-pin
LCD_SEG8
O
LCD segment output 8 at 64-pin
LCD_SEG1
O
LCD segment output 1 at 48-pin
SC1_CD
I
SmartCard1 card detect
PC.15
I/O
General purpose digital I/O pin
LCD_SEG7
O
LCD segment output 7 at 100-pin
LCD_SEG7
O
LCD segment output 7 at 64-pin
LCD_SEG0
O
LCD segment output 0 at 48-pin
SC1_PWR
O
SmartCard1 PWR pin
PD.0
I/O
General purpose digital I/O pin
LCD_SEG6
O
LCD segment output 6 at 100-pin
LCD_SEG6
O
LCD segment output 6 at 64-pin
PD.1
I/O
General purpose digital I/O pin
LCD_SEG5
O
LCD segment output 5 at 100-pin
LCD_SEG5
O
LCD segment output 5 at 64-pin
PD.2
I/O
General purpose digital I/O pin
LCD_SEG4
O
LCD segment output 4 at 100-pin
LCD_SEG4
O
LCD segment output 4 at 64-pin
PD.3
I/O
General purpose digital I/O pin
LCD_SEG3
O
LCD segment output 3 at 100-pin
LCD_SEG3
O
LCD segment output 3 at 64-pin
PD.4
I/O
General purpose digital I/O pin
LCD_SEG2
O
LCD segment output 2 at 100-pin
LCD_SEG2
O
LCD segment output 2 at 64-pin
SC1_RST
O
SmartCard1 RST pin
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
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17
Pin Type
48-pin
23
May 08, 2013
Page 42 of 100
Revision 1.01
NuMicro Nano102/112 Datasheet
Pin No.
Pin Name
100-pin 64-pin
37
38
39
40
42
25
27
28
29
17
18
PD.5
I/O
General purpose digital I/O pin
LCD_SEG1
O
LCD segment output 1 at 100-pin (or as
LCD_COM5)
LCD_SEG1
O
LCD segment output 1 at 64-pin (or as
LCD_COM5)
PD.6
I/O
General purpose digital I/O pin
LCD_SEG0
O
LCD segment output 0 at 100-pin( or as
LCD_COM4)
LCD_SEG0
O
LCD segment output 0 at 64-pin (or as
LCD_COM4)
PD.7
I/O
General purpose digital I/O pin
LCD_COM3
O
LCD common output 3 at 100-pin
LCD_COM3
O
LCD common output 3 at 64-pin
LCD_COM3
O
LCD common output 3 at 48-pin
SC1_CLK
O
SmartCard1 clock pin
(SC1_UART_TXD)
PD.8
I/O
General purpose digital I/O pin
LCD_COM2
O
LCD common output 2 at 100-pin
LCD_COM2
O
LCD common output 2 at 64-pin
LCD_COM2
O
LCD common output 2 at 48-pin
SC1_DAT
I/O
SmartCard1 DATA pin
(SC1_UART_RXD)
PD.9
I/O
General purpose digital I/O pin
LCD_COM1
O
LCD common output 1 at 100-pin
LCD_COM1
O
LCD common output 1 at 64-pin
LCD_COM1
O
LCD common output 1 at 48-pin
SC1_RST
O
SmartCard1 RST pin
PWM0_CH3
I/O
PWM0 Channel3 output
PD.10
I/O
General purpose digital I/O pin
LCD_COM0
O
LCD common output 0 at 100-pin
LCD_COM0
O
LCD common output 0 at 64-pin
LCD_COM0
O
LCD common output 0 at 48-pin
PWM0_CH2
I/O
PWM0 Channel2 output
19
20
TC1
43
I
Timer1 capture input
PD.11
I/O
General purpose digital I/O pin
LCD_DH2
O
LCD external capacitor pin of charge
pump circuit at 100-pin
30
May 08, 2013
Description
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
41
24
26
Pin Type
48-pin
Page 43 of 100
Revision 1.01
NuMicro Nano102/112 Datasheet
Pin No.
100-pin 64-pin
Pin Name
Pin Type
LCD_DH2
O
LCD external capacitor pin of charge
pump circuit at 64-pin
PWM0_CH1
I/O
PWM0 Channel1 output
TC0
44
31
I
I/O
General purpose digital I/O pin
CLK_Hz
O
1, 1/2, 1/4, 1/8, 1/16 Hz clock output
LCD_DH1
O
LCD external capacitor pin of charge
pump circuit at 100-pin
LCD_DH1
O
LCD external capacitor pin of charge
pump circuit at 64-pin
PWM0_CH0
I/O
PWM0 Channel0 output
TM1
I/O
Timer1 external counter input
FCLK0
O
Frequency Divider0 output pin
NC
32
21
VLCD
P
47
22
34
I
Input pin of the 1st most positive LCD
level at 100-pin
LCD_V1
I
Input pin of the 1st most positive LCD
level at 64-pin
LCD_V1
I
Input pin of the 1st most positive LCD
level at 48-pin
INT1
I
External interrupt 1 input pin
35
May 08, 2013
I/O
General purpose digital I/O pin
LCD_V2
I
Input pin of the 2nd most positive LCD
level at 100-pin
LCD_V2
I
Input pin of the 2nd most positive LCD
level at 64-pin
LCD_V2
I
Input pin of the 2nd most positive LCD
level at 48-pin
23
PD.15
50
General purpose digital I/O pin
I/O
General purpose digital I/O pin
LCD_V3
I
Input pin of the 3rd most positive LCD
level at 100-pin
LCD_V3
I
Input pin of the 3rd most positive LCD
level at 64-pin
LCD_V3
I
Input pin of the 3rd most positive LCD
level at 48-pin
24
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
33
I/O
LCD_V1
PD.14
49
LCD power supply pin
NC
PD.13
48
Timer0 capture input
PD.12
45
46
Description
48-pin
Page 44 of 100
Revision 1.01
NuMicro Nano102/112 Datasheet
Pin No.
Pin Name
100-pin 64-pin
Pin Type
Description
48-pin
External reset input: low active. Setting
this pin low will reset chip to initial state.
With internal pull-up.
51
35
25
nRESET
52
37
26
LDO_CAP
P
LDO capacitor pin
53
38
27
VDD
P
Power supply for I/O ports and LDO
source
PF.0
I/O
X32I
I
TM3
I/O
Timer3 external counter input or Timer3
toggle out.
PF.1
I/O
General purpose digital I/O pin
X32O
O
External 32.768 kHz crystal output
pin(default)
TM2
I/O
Timer2 external counter input or Timer2
toggle out.
VSS_PLL
G
Ground for PLL
VSS
G
Ground for digital circuit
VSS
G
Ground for digital circuit
PF.2
I/O
General purpose digital I/O pin
XT1_IN
AI
External 4~24 MHz crystal input
pin(default)
UART1_RXD
I
UART1 Data receiver input pin
TC3
I
Timer3 capture input
INT1
I
External interrupt1 input pin
PF.3
I/O
General purpose digital I/O pin
XT1_OUT
AO
External 4~24 MHz crystal output pin
54
55
38
40
28
29
56
57
41
30
58
60
42
43
31
32
UART1_TXD
O
UART1 Data transmitter output pin (This
pin could be modulated with PWM0
output.)
TC2
I
Timer 2 capture input
INT0
I
External interrupt0 input pin
61
NC
PE.0
I/O
General purpose digital I/O pin
SPI0_MOSI0
I/O
SPI0 1st MOSI (Master Out, Slave In) pin
PE.1
I/O
General purpose digital I/O pin
SPI0_MISO0
I/O
SPI0 1st MISO (Master In, Slave Out) pin
PE.2
I/O
General purpose digital I/O pin
62
63
64
May 08, 2013
External 32.768 kHz crystal input
pin(default)
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
59
General purpose digital I/O pin
Page 45 of 100
Revision 1.01
NuMicro Nano102/112 Datasheet
Pin No.
100-pin 64-pin
Pin Name
Pin Type
Description
SPI0_CLK
I/O
SPI0 serial clock pin
PE.3
I/O
General purpose digital I/O pin
SPI0_SS0
I/O
SPI0 1st slave select pin
PE.4
I/O
General purpose digital I/O pin
SC1_RST
O
SmartCard1 RST pin
PE.5
I/O
General purpose digital I/O pin
SC1_PWR
O
SmartCard1 PWR pin
PE.6
I/O
General purpose digital I/O pin
SC1_CLK
O
SmartCard1 clock pin
(SC1_UART_TXD)
PE.7
I/O
General purpose digital I/O pin
SC1_DAT
I/O
SmartCard1 DATA pin
(SC1_UART_RXD)
AVSS
G
Ground for ADC and comparators
AVSS
G
Ground for ADC and comparators
PA.0
I/O
General purpose digital I/O pin
AD0
AI
ADC analog input0
PA.1
I/O
General purpose digital I/O pin
ACMP0_CHDIS
O
Comparator0 charge/discharge path
ACMP0_P3
AI
Comparator0 P-end input3
AD1
AI
ADC analog input1
PA.2
I/O
General purpose digital I/O pin
ACMP0_CHDIS
O
Comparator0 charge/discharge path
SC0_CLK
O
SmartCard0 clock pin
(SC0_UART_TXD)
ACMP0_P2
AI
Comparator0 P-end input2
AD2
AI
ADC analog input2
INT0
I
PA.3
I/O
General purpose digital I/O pin
ACMP0_CHDIS
O
Comparator0 charge/discharge path
SC0_DAT
I/O
SmartCard0 DATA pin
(SC0_UART_RXD)
ACMP0_P1
AI
Comparator0 P-end input1
AD3
AI
ADC analog input3
INT1
I
External interrupt 1
48-pin
65
66
67
68
69
70
44
33
71
72
74
75
46
47
48
May 08, 2013
34
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
73
45
35
36
37
External interrupt0 input pin
Page 46 of 100
Revision 1.01
NuMicro Nano102/112 Datasheet
Pin No.
Pin Name
100-pin 64-pin
76
77
78
49
50
51
Pin Type
Description
48-pin
38
39
40
I/O
General purpose digital I/O pin
ACMP0_CHDIS
O
Comparator0 charge/discharge path
SC0_CD
I
SmartCard0 card detect pin
ACMP0_P0
AI
Comparator0 P-end input0
AD4
AI
ADC analog input4
PA.5
I/O
General purpose digital I/O pin
ACMP0_CHDIS
O
Comparator0 charge/discharge path
SPI1_SS0
I/O
SPI1 1st slave select pin
I2C1_SDA
I/O
I2C1 data I/O pin
SC0_PWR
O
SmartCard0 Power pin
ACMP0_N
AI
Comparator0 N-end input0
AD5
AI
ADC analog input5
PA.6
I/O
General purpose digital I/O pin
ACMP0_CHDIS
O
Comparator0 charge/discharge path
SC0_RST
O
SmartCard0 RST pin
ACMP0_OUT
O
Comparator0 output
AD6
AI
ADC analog input6
PA.7
I/O
General purpose digital I/O pin
SC1_CD
I
SmartCard1 card detect
AD7
AI
ADC analog input7
80
52
41
VREF
A
ADC/Comparator reference voltage
81
53
42
AVDD
P
Power supply for ADC and comparators
PF.4
I/O
82
83
54
55
General purpose digital I/O pin
ICE_CLK
I
Serial Wired Debugger Clock pin
CLK_Hz
O
1, 1/2, 1/4, 1/8, 1/16 Hz clock output
PWM0_CH2
O
PWM0 Channel2 output
TC1
I
Timer1 capture input
FCLK1
O
Frequency Divider1 output pin
PF.5
I/O
General purpose digital I/O pin
ICE_DAT
I/O
Serial Wired Debugger Data pin
ACMP0_CHDIS
O
Comparator0 charge/discharge path
PWM0_CH3
I/O
PWM0 Channel3 output
43
44
TC0
May 08, 2013
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
79
PA.4
I
Timer0 capture input
Page 47 of 100
Revision 1.01
NuMicro Nano102/112 Datasheet
Pin No.
Pin Name
100-pin 64-pin
Pin Type
Description
48-pin
PA.8
I/O
General purpose digital I/O pin
SC0_PWR
O
SmartCard0 Power pin
PA.9
I/O
General purpose digital I/O pin
SC0_RST
O
SmartCard0 RST pin
PA.10
I/O
General purpose digital I/O pin
SC0_CLK
O
SmartCard0 clock pin
(SC0_UART_TXD)
PA.11
I/O
General purpose digital I/O pin
SC0_DAT
I/O
SmartCard0 DATA
pin(SC0_UART_RXD)
84
85
86
87
STADC
88
90
91
57
58
59
May 08, 2013
ADC external trigger input.
PA.12
I/O
General purpose digital I/O pin
LCD_SEG19
O
LCD segment output 19 at 48-pin
UART0_TXD
O
UART0 Data transmitter output pin (This
pin could be modulated with PWM0
output.)
SPI1_MOSI0
I/O
SPI1 1st MOSI (Master Out, Slave In) pin
I2C0_SCL
I/O
I2C 0 clock pin
ACMP1_P
AI
Comparator1 P-end input
PA.13
I/O
General purpose digital I/O pin
LCD_SEG18
O
LCD segment output 18 at 48-pin
UART0_RXD
I
UART0 Data receiver input pin
SPI1_MISO0
I/O
SPI1 1st MISO (Master In, Slave Out) pin
I2C0_SDA
I/O
I2C0 data I/O pin
ACMP1_N
AI
Comparator1 N-end input
PA.14
I/O
General purpose digital I/O pin
ACMP0_CHDIS
O
Comparator0 charge/discharge path
LCD_SEG31
O
LCD segment output 31 at 64-pin
LCD_SEG17
O
LCD segment output 17 at 48-pin
SPI1_CLK
I/O
SPI1 serial clock pin
I2C1_SCL
I/O
I2C1 clock pin
PA.15
I/O
General purpose digital I/O pin
LCD_SEG30
O
LCD segment output 30 at 64-pin
LCD_SEG16
O
LCD segment output 16 at 48-pin
SPI1_SS0
I/O
SPI1 1st slave select pin
45
46
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
89
56
I
47
48
Page 48 of 100
Revision 1.01
NuMicro Nano102/112 Datasheet
Pin No.
Pin Name
Pin Type
I2C1_SDA
I/O
I2C1 data I/O pin
ACMP1_OUT
O
Comparator1 output
TC3
I
Timer3 capture input
PB.0
I/O
General purpose digital I/O pin
LCD_SEG29
O
LCD segment output 29 at 64-pin
UART0_TXD
O
UART0 Data transmitter output pin (This
pin could be modulated with PWM0
output.)
FCLK1
O
Frequency Divider1 output pin
PB.1
I/O
General purpose digital I/O pin
LCD_SEG28
O
LCD segment output 28 at 64-pin
UART0_RXD
I
UART0 Data receiver input pin
TC2
I
Timer 2 capture input
INT1
I
External interrupt1 input pin
PB.2
I/O
General purpose digital I/O pin
LCD_SEG27
O
LCD segment output 27 at 64-pin
UART0_RTSn
O
UART0 Request to Send output pin
SPI1_MOSI1
I/O
SPI1 2nd MOSI (Master Out, Slave In) pin
I2C0_SCL
O
I2C0 clock pin
TM3
I/O
Timer3 external counter input or Timer3
toggle out.
PB.3
I/O
General purpose digital I/O pin
LCD_SEG26
O
LCD segment output 26 at 64-pin
UART0_CTSn
I
UART0 Clear to Send input pin
SPI1_MISO1
I/O
SPI1 2nd MISO (Master In, Slave Out) pin
I2C0_SDA
I/O
I2C0 data I/O pin
TM2
I/O
Timer2 external counter input or Timer2
toggle out.
96
VDD
P
Power supply for I/O ports and LDO
source
97
VSS
G
Ground for digital circuit
PB.4
I/O
General purpose digital I/O pin
UART1_RTSn
O
UART1 Request to Send output pin
SPI1_MISO1
I/O
SPI1 2nd MISO (Master In, Slave Out) pin
PB.5
I/O
General purpose digital I/O pin
LCD_SEG35
O
LCD segment output 35 at 100-pin
100-pin 64-pin
92
93
94
62
63
98
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
95
60
61
Description
48-pin
99
May 08, 2013
Page 49 of 100
Revision 1.01
NuMicro Nano102/112 Datasheet
Pin No.
Pin Name
100-pin 64-pin
100
Pin Type
Description
48-pin
UART1_RXD
I
SPI1_MOSI1
I/O
SPI1 2nd MOSI (Master Out, Slave In) pin
PB.6
I/O
General purpose digital I/O pin
LCD_SEG34
O
LCD segment output 34 at 100-pin
LCD_SEG25
O
LCD segment output 25 at 64-pin
UART1_TXD
O
UART1 Data transmitter output pin (This
pin could be modulated with PWM0
output.)
SPI1_SS1
I/O
SPI1 2nd slave select pin
FCLK0
O
Frequency Divider0 output pin
64
UART1 Data receiver input pin
Note: Pin Type: I = Digital Input, O=Digital Output; AI=Analog Input; AO= Analog Output; P=Power Pin; AP=Analog Power.
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
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5
BLOCK DIAGRAM
5.1
Nano102 Block Diagram
Memory
12-bit ADC x 7
Watchdog Timer
PDMA
Cortex-M0
32 MHz
DataFlash
Configurable
Analog Interface
32-bit Timer x 4
LDROM
4 KB
APROM
32/16 KB
ARM
PWM / Timer
Window
Watchdog Timer
SRAM
4 KB
Analog
Comparator x 2
PWM/Capture
Timer x 4
Bridge
AHB Bus
APB Bus
Power Control
Clock Control
Connectivity
I/O Ports
LDO
PLL
UART x 4
(2 from ISO-7816-3)
General Purpose
I/O
SPI x 2
External
Interrupt
I2C x 2
Reset Pin
Power On Reset
High Speed
Oscillator
16/12 MHz
Low Speed
Crystal Osc.
32.768 kHz
Low Speed
Oscillator
10 kHz
Figure 5-1 NuMicro
May 08, 2013
ISO-7816-3 x 2
TM
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
LVR
High Speed
Crystal Osc.
4 ~ 24 MHz
Nano102 Block Diagram
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NuMicro Nano102/112 Datasheet
5.2
Nano112 Block Diagram
Memory
Window
Watchdog Timer
SRAM
4 KB
Bridge
Analog
Comparator x 2
LCD
4x36, 6x34
PWM/Capture
Timer x 4
AHB Bus
12-bit ADC x 8
Watchdog Timer
PDMA
Cortex-M0
32 MHz
DataFlash
Configurable
Analog Interface
32-bit Timer x 4
LDROM
4 KB
APROM
32/16 KB
ARM
PWM / Timer
APB Bus
Power Control
Clock Control
Connectivity
I/O Ports
LDO
PLL
UART x 4
(2 from ISO-7816-3)
General Purpose
I/O
SPI x 2
External
Interrupt
I2C x 2
Reset Pin
Power On Reset
LVR
High Speed
Crystal Osc.
4 ~ 24 MHz
High Speed
Oscillator
16/12 MHz
Low Speed
Crystal Osc.
32.768 kHz
Low Speed
Oscillator
10 kHz
May 08, 2013
TM
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
Figure 5-2 NuMicro
ISO-7816-3 x 2
Nano112 Block Diagram
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NuMicro Nano102/112 Datasheet
6
FUNCTIONAL DESCRIPTION
ARM® Cortex™-M0 Core
6.1
The Cortex™-M0 processor is a configurable, multistage, 32-bit RISC processor, which has an
AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug
functionality. The processor can execute Thumb code and is compatible with other Cortex™-M
profile processor. The profile supports two modes –Thread mode and Handler mode. Handler
mode is entered as a result of an exception. An exception return can only be issued in Handler
mode. Thread mode is entered on Reset, and can be entered as a result of an exception return.
The following figure shows the functional controller of processor.
Cortex-M0 Components
Cortex-M0 Processor
Nested
Vectored
Interrupt
Controller
(NVIC)
Interrupts
Wakeup
Interrupt
Controller
(WIC)
Debug
Cortex-M0
Processor
Core
Breakpoint
and
Watchpoint
Unit
Bus matrix
Debugger
interface
AHB-Lite interface
Debug
Access Port
(DAP)
Figure 6-1 Functional Block Diagram
The implemented device provides:

A low gate count processor:









May 08, 2013
ARMv6-M Thumb® instruction set
Thumb-2 technology
ARMv6-M compliant 24-bit SysTick timer
A 32-bit hardware multiplier
System interface supported with little-endian data accesses
Ability to have deterministic, fixed-latency, interrupt handling
Load/store-multiples and multicycle-multiplies that can be abandoned and restarted to
facilitate rapid interrupt handling
C Application Binary Interface compliant exception model. This is the ARMv6-M, C
Application Binary Interface (C-ABI) compliant exception model that enables the use of
pure C functions as interrupt handlers
Low Power Sleep mode entry using the Wait For Interrupt (WFI), Wait For Event
(WFE) instructions, or return from interrupt sleep-on-exit feature
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Serial Wire or
JTAG debug port
NuMicro Nano102/112 Datasheet

NVIC:





Debug support:





32 external interrupt inputs, each with four levels of priority
Dedicated Non-maskable Interrupt (NMI) input
Supports for both level-sensitive and pulse-sensitive interrupt lines
Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power Sleep
mode
Four hardware breakpoints
Two watchpoints
Program Counter Sampling Register (PCSR) for non-intrusive code profiling
Single step and vector catch capabilities
Bus interfaces:


Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration to all
system peripherals and memory
Single 32-bit slave port that supports the DAP (Debug Access Port)
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6.2
Memory Organization
6.2.1
Overview
The Nano112 provides 4G-byte addressing space. The memory locations assigned to each onchip modules are shown in following. The detailed register definition, memory space, and
programming detailed will be described in the following sections for each on-chip module. The
Nano112 series only supports little-endian data format.
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6.3
Nested Vectored Interrupt Controller (NVIC)
6.3.1
Overview
The Cortex-M0 provides an interrupt controller as an integral part of the exception mode, named
as “Nested Vectored Interrupt Controller (NVIC)”. It is closely coupled to the processor kernel and
provides following features:
6.3.2
Features

Nested and Vectored interrupt support

Automatic processor state saving and restoration

Dynamic priority changing

Reduced and deterministic interrupt latency
The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler
Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority.
All of the interrupts and most of the system exceptions can be configured to different priority
levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the
current running one’s priority. If the priority of the new interrupt is higher than the current one, the
new interrupt handler will override the current handler.
The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the
overhead of states saving and restoration and therefore reduces delay time in switching to
pending ISR at the end of current ISR. The NVIC also supports “Late Arrival” which improves the
efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current
ISR starts to execute (at the stage of state saving and starting address fetching), the NVIC will
give priority to the higher one without delay penalty. Thus it advances the real-time capability.
For more detailed information, please refer to the “ARM
®
Manual” and “ARM v6-M Architecture Reference Manual”.
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®
Cortex™-M0 Technical Reference
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When any interrupts is accepted, the starting address of the interrupt service routine (ISR) is
fetched from a vector table in memory. There is no need to determine which interrupt is accepted
and branch to the starting address of the correlated ISR by software. While the starting address is
fetched, NVIC will also automatically save processor state including the registers “PC, PSR, LR,
R0~R3, R12” to the stack. At the end of the ISR, the NVIC will restore the mentioned registers
from stack and resume the normal execution. Thus it will take less and deterministic time to
process the interrupt request.
NuMicro Nano102/112 Datasheet
6.4
6.4.1
System Manager
Overview
System manager mainly controls the power modes, wake-up sources, system resets, scalable LDO
and system memory map. It also provides information about product ID, chip reset, IP reset, and multifunction pin control.
6.4.2
Features

Power modes and wake-up sources

System Power Architecture

System resets

Scalable LDO

System Memory Map

System manager registers for :

Part Number ID

Chip and IP reset

Multi-functional pin control
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6.5
Clock Controller
6.5.1
Overview
The clock controller generates clocks for the whole chip, Iincluding system clocks (CPU clock,
HCLKx, and PCLKx) and all peripheral module clocks. HCLKx means AHB bus clock for
peripherals on AHB bus. PCLKx means APB bus clock for peripherals on APB bus. PCLKx can
be the same as HCLKx or devided from HCLKx. The clock controller also implements the power
control function with the individually clock ON/OFF control, clock source selection and a 4-bit
clock divider. The chip will not enter power-down mode until CPU sets the power down enable bit
PD_EN(PWRCTL[6]) and executes the WFI instruction. In the Power-down mode, clock controller
turns off the external high frequency crystal, internal high frequency oscillator, and system clocks
(CPU clock, HCLKx, and PCLKx) to reduce the power consumption.
The clock controller consists of 5 sources as listed below:
6.5.2

32768Hz external low speed crystal oscillator (LXT)

4~ 24 MHz external high speed crystal oscillator (HXT)

12/16 MHz internal high speed RC oscillator (HIRC)

One programmable PLL FOUT (PLL source can be selected from HXT or HIRC)

10 kHz internal low speed RC oscillator (LIRC)
Features
Generates clocks for system clocks and all peripheral module clocks.

Each peripheral module clock can be turned on/off.

High frequency crystal, internal high frequency oscillator, and system clocks will be
turned off when chip is in Power-down mode.
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
NuMicro Nano102/112 Datasheet
6.6
Flash Memory Controller (FMC)
6.6.1
Overview
This chip is equipped with 16/32 Kbytes on-chip embedded flash memory for application program
memory (APROM) that can be updated through ISP/IAP procedure. In System Programming
(ISP) function enables user to update program memory when chip is soldered on PCB. After chip
powered on Cortex-M0 CPU fetches code from APROM or LDROM decided by boot select (CBS)
in Config0. By the way, this chip also provides Data Flash Region, the Data Flash is shared with
original program memory and its start address is configurable and defined by user in Config1. The
Data Flash size is defined by user application request.
6.6.2
Features

16/32 Kbytes application program memory (APROM)

4 Kbytes in system programming (ISP) loader program memory (LDROM)

Programmable Data Flash start address and memory size with 512 bytes page erase
unit

512 bytes system program memory (SPROM)

In System Program (ISP)/In Application Program (IAP) to update on chip flash
memory
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6.7
General Purpose I/O Controller
6.7.1
Overview
TM
The NuMicro Nano112 series have up to 80 General Purpose I/O pins to be shared with other
function pins depending on the chip configuration. These 80 pins are arranged in 6 ports named
with GPIOA, GPIOB, GPIOC, GPIOD, GPIOE and GPIOF. Each one of the 80 pins is
independent and has the corresponding register bits to control the pin mode function and data.
The I/O type of each of I/O pins can be independently software configured as input, output, and
open-drain mode. Each I/O pin has a very weak individual pull-up resistor which is about 110
K~300 K for VDD from 1.8 V to 3.6 V.
6.7.2
Features

Three I/O modes:

Schmitt trigger Input-only with high impendence

Push-pull output

Open-drain output

I/O pin configured as interrupt source with edge/level setting

Enabling the pin interrupt function will also enable the pin wake-up function
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NuMicro Nano102/112 Datasheet
6.8
6.8.1
DMA Controller
Overview
The NuMicro NANO112 series DMA contains four-channel peripheral direct memory access (PDMA)
controller and a cyclic redundancy check (CRC) generator.
The PDMA that transfers data to and from memory or transfer data to and from peripherals. For PDMA
channel (PDMA CH1~CH4), there is one-word buffer as transfer buffer between the Peripherals APB
devices and Memory. User can stop the PDMA operation by disable PDMACEN (PDMA_CSRx[0]).
User can polling TD_IS (PDMA_ISRx[1]) or enable BLKD_IE (PDMA_IERx[1]) and wait interrupt to
check PDMA transfer complete . The DMA controller can increase source or destination address, fixed
or wrap around them as well.
The DMA controller contains a cyclic redundancy check (CRC) generator that can perform CRC
calculation with programmable polynomial settings. The CRC engine supports CPU mode and DMA
transfer mode.
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6.8.2
Features

Supports four PDMA channels (CH1 ~ CH4) and one CRC channel. Each PDMA
channel can support a unidirectional transfer

AMBA AHB master/slave interface compatible, for data transfer and register
read/write

Hardware round robin priority scheme. DMA channel 1 has the highest priority and
channel 4 has the lowest priority

PDMA


Peripheral-to-memory, memory-to-peripheral, and memory-to-memory transfer

Supports word boundary address

Supports word alignment transfer length in memory-to-memory mode

Supports word/half-word/byte alignment transfer length in peripheral-to-memory
and memory-to-peripheral mode

Supports word/half-word/byte transfer data width from/to peripheral

Supports address direction: increment, fixed, and wrap around

Supports time-out function in all channel
Cyclic Redundancy Check (CRC)

CRC-CCITT: X16 + X12 + X5 + 1

CRC-8: X8 + X2 + X + 1

CRC-16: X16 + X15 + X2 + 1

CRC-32: X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 +
X5 + X4 + X2 + X + 1
Programmable seed value

Supports programmable order reverse setting for input data and CRC checksum

Supports programmable 1’s complement setting for input data and CRC
checksum

Supports CPU mode or DMA transfer mode

Supports 8/16/32-bit of data width in CRC CPU mode

8-bit write mode: 1-AHB clock cycle operation

16-bit write mode: 2-AHB clock cycle operation

32-bit write mode: 4-AHB clock cycle operation
Supports byte alignment transfer length in CRC DMA mode
Page 62 of 100
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


May 08, 2013
Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32
NuMicro Nano102/112 Datasheet
6.9
Timer Controller
6.9.1
Overview
This chip is equipped with four timer modules including TIMER0, TIMER1, TIMER2 and TIMER3,
which allow user to easily implement a counting scheme or timing control for applications. The
timer can perform functions like frequency measurement, event counting, interval measurement,
clock generation, delay timing, and so on. The timer can generate an interrupt signal upon
timeout, or provide the current value of count during operation.
6.9.2
Features
Independent Clock Source for each Timer (TMRx_CLK, x= 0, 1,2,3)

Time-out period = (Period of timer clock input) * (8-bit pre-scale counter + 1) * (24-bit
TCMP)

Counting cycle time = (1 / TMRx_CLK) * (2^8) * (2^24)

Internal 8-bit pre-scale counter

Internal 24-bit up counter is readable through TDR (Timer Data Register)

Supports One-shot, Periodic, Output Toggle and Continuous Counting Operation
mode

Supports external pin capture for interval measurement

Supports external pin capture for timer counter reset

Supports Inter-Timer trigger

Supports event generator in TIMER 0 and TIMER 2 to generate event to TIMER1 and
TIMER3, respectively.

Supports Internal trigger event to ADC and PDMA
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
NuMicro Nano102/112 Datasheet
6.10 Pulse Width Modulation (PWM)
6.10.1 Overview
This chip has one PWM controller, which includes 4 independent PWM outputs, CH0~CH3, or as
2 complementary PWM pairs, (CH0, CH1), (CH2, CH3) with 2 programmable dead-zone
generators.
Each of the two PWM outputs, (CH0, CH1), (CH2, CH3), share the same 8-bit prescaler, clock
divider providing 5 divided frequencies (1, 1/2, 1/4, 1/8, 1/16). Each PWM output has independent
16-bit PWM counter which has two counting modes for PWM period control. The PWM counter
operates as down counting in edge-aligned mode and up-down counting in center-aligned mode
only. Each PWM output also has a 16-bit comparator for PWM duty control. Each dead-zone
generator has two outputs. The first dead-zone generator output is CH0 and CH1, and for the
second dead-zone generator, the output is CH2 and CH3. The PWM controller total provide four
independent PWM interrupt flags which are set by hardware when the corresponding PWM period
down counter in edge-aligned mode (or up-down counter in center-aligned mode) reaches 0.
PWM interrupt will be asserted when both PWM interrupt source and its corresponding enable bit
are active. Each PWM output can be configured as one-shot mode to produce only one PWM
cycle signal or continuous mode to output PWM waveform continuously.
When DZEN01(PWM_CTL[4]) is set, CH0 and CH1 perform complementary PWM paired
function; the paired PWM timing, period, duty and dead-time are determined by PWM channel 0
timer and Dead-zone generator 0. Similarly, When DZEN23(PWM_CTL[5]) is set the
complementary PWM pair of (CH2, CH3) is controlled by PWM channel 2.
When the 16-bit period down counter reaches 0, the interrupt request is generated. If PWM output
is set as continuous mode, when the down counter reaches 0, it is reloaded with CN of
PWM_DUTYy(y=0~3) Register automatically then start decreases, repeatedly. If the PWM output
is set as one-shot mode, the down counter will stop and generate one interrupt request when it
reaches 0.
The value of PWM counter comparator is used for pulse width modulation. The counter control
logic changes the output level when down-counter value matches the value of compare register.
The alternate feature of the PWM is digital input capture function. If capture function is enabled
the PWM output pin is switched as capture input pin. The capture channel 0 and PWM CH0 share
one timer; and the capture channel 1 and PWM CH1 share one timer, and etc. Therefore user
must set up the PWM timer before enabling capture feature. After capture feature of channel 0 is
enabled, the capture always latches PWM CH0 timer value to Capture Rising Latch Register CRL
(PWM_CRL0[15:0]) when input channel has a rising transition and latches PWM CH0 timer value
to Capture Falling Latch Register CFL (PWM_CFL0[15:0]) when input channel has a falling
transition. Capture channel 0 interrupt is programmable by setting CRL_IE0(PWM_CAPINTEN[0])
for rising transition or CFL_IE0 (PWM_CAPINTEN[1]) for falling transition. Whenever Capture
rising event latched for channel 0, the PWM CH0 timer will be reload at this moment if the
corresponding reload enable bit CAPRELOADREN0 (PWM_CAPCTL[6]) is set.
The maximum captured frequency that PWM can capture is dominated by the capture interrupt
latency. When capture interrupt occurs, software will do at least three steps, they are:
Read PWMINTSTS to tell it from interrupt source and Read PWM_CRLy/PWM_CFLy(y=0~3) to
get capture value and finally write 1 to clear PWM_INTSTS. If interrupt latency will take time T0 to
finish, the capture signal mustn’t transient during this interval. In this case, the maximum capture
frequency will be 1/T0.
May 08, 2013
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To prevent PWM driving output pin with unsteady waveform, the 16-bit period down counter and
16-bit comparator are implemented with double buffer. When user writes data to
counter/comparator buffer registers the updated value will be loaded into the 16-bit down counter/
comparator at the time down counter reaching 0. The double buffering feature avoids glitch at
PWM outputs.
NuMicro Nano102/112 Datasheet
6.10.2 Features
6.10.2.1 PWM Function:

PWM controllers has 4 independent PWM outputs, CH0~CH3, or as 2 complementary
PWM pairs, (CH0, CH1), (CH2, CH3) with 2 programmable dead-zone generators

Up to 4 PWM channels or 2 PWM paired channels

Up to 16 bits PWM counter width

PWM Interrupt request synchronous with PWM period

Single-shot or Continuous mode

Two Dead-Zone generators
6.10.2.2 Capture Function:

Timing control logic shared with PWM timer.

4 Capture input channels shared with 4 PWM output channels.

Each channel supports one rising latch register CRL (PWM_CRL0[15:0]), one falling
latch register CFL (PWM_CFL0[15:0]) and Capture interrupt flag CAPIF0
(PWM_CAPINTSTS[0]).

Four 16-bit counters for four capture channels or two 32-bit counter for two capture
channels when cascade is enabled: when CH01CASKEN (PWM_CAPCTL[13]) is set,
the original 16-bit counter of channel 1 will combine with channel 0’s 16 bit counter for
channel 0 input capture counting and so does CH23CASKEN(PWM_CAPCTL[29]) for
channel 2, 3

Supports PDMA transfer function for PWM channel 0, 2
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
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NuMicro Nano102/112 Datasheet
6.11 Watchdog Timer Controller
6.11.1 Overview
The purpose of Watchdog Timer is to perform a system reset after the software running into a
problem. This prevents system from hanging for an infinite period of time. Besides, this Watchdog
Timer supports the function to wake-up CPU from power-down mode. The watchdog timer
includes an 18-bit free running counter with programmable time-out intervals.
6.11.2 Features

18-bit free running WDT counter for Watchdog timer time-out interval.

Selectable time-out interval (2^4 ~ 2^18) and the time-out interval is 104 ms ~ 26.316
s (if WDT_CLK = 10 kHz).

Reset period = (1 / 10 kHz) * 63, if WDT_CLK = 10 kHz.
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
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NuMicro Nano102/112 Datasheet
6.12 Window Watchdog Timer Controller
6.12.1 Overview
The purpose of Window Watchdog Timer is to perform a system reset within a specified window
period to prevent software run to uncontrollable status by any unpredictable condition.
6.12.2 Features

6-bit down counter and 6-bit compare value to make the window period flexible

Selectable WWDT clock pre-scale counter to make WWDT time-out interval variable
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
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NuMicro Nano102/112 Datasheet
6.13 RTC
6.13.1 Overview
Real Time Clock (RTC) unit provides user the real time and calendar message. The Clock Source
(LXT) of RTC is from an external 32.768 kHz crystal connected at pins X32I and X32O (reference
to pin Description) or from an external 32.768 kHz oscillator output fed at pin X32I. The RTC unit
provides the time message (second, minute, hour) in Time Loading Register (TLR) as well as
calendar message (day, month, year) in Calendar Loading Register (CLR). The data message is
expressed in BCD format. This unit offers alarm function that user can preset the alarm time in
Time Alarm Register (TAR) and alarm calendar in Calendar Alarm Register (CAR).
The RTC unit supports periodic Time Tick and Alarm Match interrupts. The periodic interrupt has
8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second which are selected by TTR
(RTC_TTR[2:0]). When RTC counter in TLR and CLR is equal to alarm setting time registers TAR
and CAR, the alarm interrupt status (AIS (RTC_RIIR[0])) is set and the alarm interrupt is
requested if the alarm interrupt is enabled (AIER (RTC_RIER[0])=1). The RTC Time Tick (if wakeup CPU function is enabled, (TWKE (RTC_TTR[3]) high) and Alarm Match can cause CPU wakeup from idle or Power-down mode.
6.13.2 Features
One time counter (second, minute, hour) and calendar counter (day, month, year) for
user to check the time

Alarm register (second, minute, hour, day, month, year)

12-hour or 24-hour mode is selectable

Leap year compensation automatically

Day of week counter

Frequency compensate register (FCR)

All time and calendar message is expressed in BCD code

Supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8,
1/4, 1/2 and 1 second

Supports 1, 2, 4, 8 and 16 seconds clock output (CLK_Hz) for frequency measuring

Supports RTC Time Tick and Alarm Match interrupt

Supports wake-up CPU from Power-down mode

Supports 80 bytes spare registers and a snoop pin to clear the content of these spare
registers
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
NuMicro Nano102/112 Datasheet
6.14 UART Controller
6.14.1 Overview
The UART Controller provides up to two channels of Universal Asynchronous
Receiver/Transmitter (UART) modules and performs Normal Speed UART, and supports flow
control function. The Universal Asynchronous Receiver/Transmitter (UART) performs a serial-toparallel conversion on data received from the peripheral, and a parallel-to-serial conversion on
data transmitted from the CPU.
The UART controller also supports IrDA (SIR), LIN Master/Slave and RS-485 function modes.
There are four conditions to wake-up the system and it also supports PWM channel source
selection to modulate the PWM and the UART transmitter.
6.14.2 Features
Full duplex, asynchronous communications.

Separate receiving / transmitting 16 bytes entry FIFO for data payloads.

Supports hardware auto-flow control/flow control function (CTSn, RTSn) and
programmable (CTSn, RTSn) flow control trigger level.

Supports programmable baud rate generator.

Supports auto-baud rate detect and baud rate compensation function.

Supports programmable receiver buffer trigger level.

Supports incoming data or CTSn or received FIFO is equal to the RFITL or RS-485
AAD mode address matched to wake-up function.

Supports 9 bit receiver buffer time-out detection function.

All UART Controller can be served by the PDMA.

Programmable transmitting data delay time between the last stop bit leaving the TXFIFO and the de-assertion by setting DLY (UART_TMCTL[23:16]) register.

Supports IrDA SIR function mode

Supports LIN function mode.

Supports RS-485 function mode.

Supports PWM modulation
May 08, 2013
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NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET

NuMicro Nano102/112 Datasheet
6.15 Smart Card Host Interface (SC)
6.15.1 Overview
The Smart Card Interface controller (SC controller) is based on ISO/IEC 7816-3 standard and fully
compliant with PC/SC Specifications. It also provides status of card insertion/removal.
6.15.2 Features
ISO-7816-3 T = 0, T = 1 compliant.

EMV2000 compliant

Up to two ISO-7816-3 ports

Separates receive/transmit 4 byte entry FIFO for data payloads.

Programmable transmission clock frequency.

Programmable receiver buffer trigger level.

Programmable guard time selection (11 ETU ~ 267 ETU).

A 24-bit and two 8 bit timers for Answer to Request (ATR) and waiting times
processing.

Supports auto inverse convention function.

Supports transmitter and receiver error retry and error number limitation function.

Supports hardware activation sequence process.

Supports hardware warm reset sequence process.

Supports hardware deactivation sequence process.

Supports hardware auto deactivation sequence when detected the card removal.

Supports UART mode
May 08, 2013

Full duplex, asynchronous communications.

Separates receiving / transmitting 4 bytes entry FIFO for data payloads.

Supports programmable baud rate generator for each channel.

Supports programmable receiver buffer trigger level.

Programmable transmitting data delay time between the last stop bit leaving the
TX-FIFO and the de-assertion by setting SC_EGTR register.

Programmable even, odd or no parity bit generation and detection.

Programmable stop bit, 1 or 2 stop bit generation
Page 70 of 100
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NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET

NuMicro Nano102/112 Datasheet
6.16 I2C
6.16.1 Overview
2
I C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data
2
exchange between devices. The I C standard is a true multi-master bus including collision
detection and arbitration that prevents data corruption if two or more masters attempt to control
the bus simultaneously. Serial, 8-bit oriented bi-directional data transfers can be made up to 1
Mbps.
Data is transferred between a Master and a Slave synchronously to SCL on the SDA line on a
byte-by-byte basis. Each data byte is 8-bit long. There is one SCL clock pulse for each data bit
with the MSB being transmitted first. An acknowledge bit follows each transferred byte.
A transition on the SDA line while SCL is high is interpreted as a command (START or STOP).
Each bit is sampled during the high period of SCL; therefore, the SDA line may be changed only
during the low period of SCL and must be held stable during the high period of SCL.
2
2
The controller’s on-chip I C logic provides the serial interface that meets the I C bus standard
2
mode specification. The I C controller handles byte transfers autonomously. Pull up resistor is
2
needed for I C operation as these are open drain pins.
2
The I C controller is equipped with two slave address registers. The contents of the registers are
2
irrelevant when I C is in Master mode. In the Slave mode, the seven most significant bits must be
2
loaded with the user’s own slave address. The I C hardware will react if the contents of I2CADDR
are matched with the received slave address.
2
The I C-bus controller supports multiple address recognition with two address mask register.
When the bit in the address mask register is set to one, it means the received corresponding
address bit is don’t-care. If the bit is set to 0, that means the received corresponding register bit
should be exact the same as address register.
6.16.2 Features

Supports two I2C channels and both of them can acts as Master or Slave mode

Bidirectional data transfer between masters and slaves

Multi-master bus (no central master)

Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus

Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus

Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer

One built-in 14-bit time-out counter requesting the I C interrupt if the I C bus hangs up
and timer-out counter overflows.

Programmable clock divider allows versatile rate control

Supports 7-bit addressing mode
May 08, 2013
2
Page 71 of 100
2
Revision 1.01
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
This controller supports the “General Call (GC)” function. If the GCALL (I2CSADDR[0]) bit is set
this controller will respond to General Call address (00H). Clear GC bit to disable general call
2
function. When GCALL bit is set and the I C is in Slave mode, it can receive the general call
2
address which is equal to 00H after master sends general call address to the I C bus, then it will
follow status of GC mode. If it is in Master mode, the ACK bit must be cleared when it sends
2
general call address of 00H to the I C bus.
NuMicro Nano102/112 Datasheet

Supports multiple address recognition ( Two slave addresses with mask option)

Supports Power-down wake-up function

Supports two-Level FIFO
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
May 08, 2013
Page 72 of 100
Revision 1.01
NuMicro Nano102/112 Datasheet
6.17 SPI
6.17.1 Overview
The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol.
Devices communicate in Master/Slave mode with 4-wire bi-direction interface. It is used to
perform a serial-to-parallel conversion on data received from a peripheral device, and a parallelto-serial conversion on data transmitted to a peripheral device. The SPI controller can be
configured as a master or a slave device.
The SPI controller supports wake-up function. When this chip stays in Power-down mode, it can
be waked up by off-chip device.
This controller supports variable serial clock function for special application and 2-bit transfer
mode to connect 2 off-chip slave devices. The SPI controller also supports PDMA function to
access the data buffer.
6.17.2 Features
Up to two sets of SPI controllers

Supports Master (max. 32 MHz) or Slave (max. 16 MHz) mode operation

Supports 1 bit and 2 bit transfer mode

Support Dual IO transfer mode

Configurable bit length of a transaction from 8 to 32-bit

Supports MSB first or LSB first transfer sequence

Two slave select lines supported in Master mode

Configurable byte or word suspend mode

Supports byte re-ordering function

Supports variable serial clock in Master mode

Provide separate 8-level depth transmit and receive FIFO buffer

Supports wake-up function

Supports PDMA transfer

Supports 3-wires, no slave select signal, bi-direction interface
May 08, 2013
Page 73 of 100
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET

Revision 1.01
NuMicro Nano102/112 Datasheet
6.18 LCD Display Driver
6.18.1 Overview
The LCD driver can directly drive a LCD glass by creating the ac segment and common voltage
signals automatically. It can support static, 1/2 duty, 1/3 duty, 1/4 duty, 1/5 duty and 1/6 duty LCD
glass with up to 3 segments with 6 COM (segment 0 is used as LCD_COM4 and segment 1 is used as
LCD_COM5) or 36 segments with 4 COM (LCD_COM0 ~ LCD_COM3).
A built-in charge pump function can be enabled to provide the LCD glass with higher voltage than the
system voltage. The LCD driver would generate voltage higher than the threshold voltage in older to
darken a segment and a voltage lower than threshold to make a segment clear. However, the LCD
display segment will degrade if the applied voltage has a DC-component. To avoid this, the generated
waveform by LCD driver are arranged such that average voltage of each segment is 0 and the
RMS(root-mean-square) voltage applied on a LCD segment lower than the segment threshold making
LCD clear and RMS voltage higher than the segment threshold making LCD dark.
6.18.2 Features

Supports Segment/Com:

108 dots (6x18) or 80 dots (4x20) in LQFP48 package

108 dots (6x18) or 80 dots (4x20) or 132 dots (6x 22) or 96 dots (4x24) or 180
dots (6x30) or 128 dots (4x32) in LQFP64 package

204 dots (6x34) or 144 dots (4x36) in LQFP100 package
Common 0-5 multiplexing functions with GPI/O pins

Segment 0-35 multiplexing function with GPI/O pins

Supports Static,1/2 bias and 1/3 bias voltage

Six display modes: Static,1/2 duty, 1/3 duty, 1/4 duty, 1/5 duty or 1/6 duty Selectable
LCD frequency by frequency divider

Configurable frame frequency

Internal Charge pump, adjustable contrast adjustment

Embedded LCD bias reference ladder (R-Type, 200/300/400 kΩ resisters)

Configurable Charge pump frequency

Blinking capability

Supports R/C/Ext_C-type method

LCD frame interrupt
May 08, 2013
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NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET

NuMicro Nano102/112 Datasheet
6.19 Analog to Digital Converter (ADC)
6.19.1 Overview
The Nano112 series contains one 12-bit successive approximation analog-to-digital converter (SAR
A/D converter) with 8 external input channels and 4 internal channels. The A/D converter supports
three operation modes: Single, Single-cycle Scan and Continuous Scan mode, and can be started by
software, external STADC(PA.11) pin, timer event start and PWM trigger.
Note that the I/O pins used as ADC analog input pins must configure the Pin Function (PA_L_MFP) to
ADC input and off digital function (GPIOA_OFFD) should be turned on before ADC function is
enabled.
6.19.2 Features

Analog input voltage range: 0~VREF (Max to AVDD)

Selectable 12-bits, 10-bits, 8-bits and 6-bits resolution

Supports sampling time settings for channel 0~7 individually (ADCCHSAMP0 register) and
channel 14~17 share the same one sampling time setting (ADCCHSAMP1 register)

Supports two power-down modes:

Power-down mode

Standby mode
Up to 8 external analog input channels (channel0 ~ channel7), and 4 internal channels
(channel14~channel17) converting four voltage sources (internal band-gap voltage, internal
temperature sensor output, AVDD, and AVSS).

Maximum ADC clock frequency is 32 MHz and each conversion is 19 clocks+ sampling time
depending on the input resistance (Rin).

Three operating modes:


Single mode: A/D conversion is performed one time on a specified channel.

Single-cycle Scan mode: A/D conversion is performed one cycle on all specified channels
with the sequence from the lowest numbered channel to the highest numbered channel.

Continuous Scan mode: A/D converter continuously performs Single-cycle scan mode until
software stops A/D conversion.
An A/D conversion can be started by:

Software write 1 to ADST bit

External pin STADC

PWM trigger

Selects one from four timer events (TMR0, TMR1, TMR2 and TMR3) that enable ADC and
transfer AD results by PDMA

Conversion results held in data registers for each channel

Supports digital comparator: Conversion result can be compared with a specified value and user
can select whether to generate an interrupt when conversion result is equal to the compare
register setting.

Supports Calibration and load Calibration words capability.
May 08, 2013
Page 75 of 100
Revision 1.01
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET

NuMicro Nano102/112 Datasheet
6.20 Analog Comparator Controller (ACMP)
6.20.1 Overview
The Nano112 series contains two comparators. The comparator output is logic 1 when positive
input is greater than negative input; otherwise, the output is 0. Each comparator can be
configured to generate an interrupt when the comparator output value changes. The comparator
ACMP0 can be used as normal comparator or it can emulate ADC function. The comparator
ACMP1 can be used as normal comparator only.
6.20.2 Features

Analog input voltage range: 0 ~ AVDD

Supports hysteresis function

Supports wake-up function

Comparator ACMP0 supports

4 positive sources(ACMP0_Px)


4 negative sources

PA.5 (ACMP0_N)

Comparator Reference Voltage (CRV)

Int_VREF

AGND
Comparator ACMP1 supports

1 positive source



4 negative sources

PA.13(ACMP1_N)

Comparator Reference Voltage (CRV)

Int_VREF

AGND
Comparator ACMP0 supports three operation modes:

Normal Comparator mode

Single Slope ADC mode: Resistance measurement (e.g. PTC, NTC, PT1000)


Supports to measure 7 channels resistor
Sigma-Delta ADC mode

May 08, 2013
PA.12(ACMP1_P)
Supports up to 4 channel voltage input from ACMP0_Px
Page 76 of 100
Revision 1.01
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET

PA.1, PA.2, PA.3, or PA.4
NuMicro Nano102/112 Datasheet
7
APPLICATION CIRCUIT
Power
DVCC
[1]
SPISS
SPICLK
MISO
MOSI
AVDD
AVCC
In Case
VREF = AVDD
1uF//10nF
VREF
VREF
CS
CLK
MISO
MOSI
VDD
SPI Device
VSS
1uF//10nF
DVCC
AVSS
AVSS
VDD
VCC
4.7K
VSS
4.7K
CLK
SCL
VDD
ICE_DAT
ICE_CLK
/RESET
VSS
SWD
Interface
DVCC
SDA
DIO
VDD
I2C Device
VSS
20p
XT1_IN
Nano1x2AN
Crystal
20p
4~24 MHz
crystal
XT1_OUT
DVCC
Reset
Circuit
10K
RS232 Transceiver
nRESET
RX
ROUT
TX
TIN
RIN
TOUT
UART
LDO_CAP
1uF
Note: For the SPI device, the Nano1x2 chip supply
voltage must be equal to SPI device working voltage.
For example, when the SPI Flash working voltage is 3.3
V, the Nano1x2 chip supply voltage must also be 3.3V.
LDO
May 08, 2013
Page 77 of 100
Revision 1.01
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
10uF/25V
PC COM Port
NuMicro Nano102/112 Datasheet
8
POWER COMSUMPTION
Part No
Test Condition
Operating Mode:
CPU run while(1) in FLASH ROM
Clock = 12MHz Crystal Oscillator
Disable all peripheral
Set LDO output = 1.6V
Idle Mode:
CPU stop
Clock = 12MHz Crystal Oscillator
Disable all peripheral
Set LDO output = 1.6V
Operating Mode:
CPU run while(1) in FLASH ROM
Clock = 12MHz Internal RC Oscillator
Disable all peripheral
Set LDO output = 1.6V
Idle Mode:
CPU stop
Clock = 12MHz Internal RC Oscillator
Disable all peripheral
Set LDO output = 1.6V
3.3V
12 MHz
1.89mA
157uA/MHz
3.3V
12 MHz
800uA
67uA/MHz
3.3V
12 MHz
1.65mA
137uA/MHz
3.3V
12 MHz
560uA
46uA/MHz
InternL C-Type
(With internal Charge pump)
9.5uA
200kΩ
8.3uA
300kΩ
6.4uA
InternL R-Type
(With internal
resistor ladder)
400kΩ
3.3V
Stop
5.5uA
External C-Type
(With 0.1uF cap. ladder)
2.5uA
External R-type
(With 1MΩ resister ladder)
3.7uA
RTC Mode: (RAM retention)
(Power down with LXT enable)
CPU stop
Clock = 32.768KHz Crystal Oscillator
Disable all peripheral except RTC circuit
Set LDO output = 1.6V
Power Down Mode: (RAM retention)
CPU and all clocks stop
Set LDO output = 1.6V
Wake-Up time from Power Down Mode
Clock = Internal 12 MHz RC Oscillator
(from wake-up event to first CPU core valid clock)
Wake-Up time from Power Down Mode
Clock = Internal 12 MHz RC Oscillator
(from interrupt event to interrupt service routine first
instruction)
May 08, 2013
Current
Page 78 of 100
3.3V
Stop
1.5uA
3.3V
Stop
0.65uA
3.3V
12 MHz
6us
3.3V
12 MHz
7us
Revision 1.01
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
RTC + LCD Mode: (RAM retention)
(Power down with LXT and LCD
enable)
Nano102/112
CPU stop
series
Clock = 32.768KHz Crystal
Oscillator
Disable all peripheral except RTC
and LCD circuit. Without panel
loading
Set LDO output = 1.6V
Only for Nano112 LCD series
VDD CPU clock
NuMicro Nano102/112 Datasheet
9
9.1
ELECTRICAL CHARACTERISTIC
Absolute Maximum Ratings
SYMBOL
PARAMETER
MIN
MAX
UNIT
VDD-VSS
-0.3
+3.6
V
Input Voltage on 5V Tolerance Pin
VIN
VSS -0.3
5.5
V
Input Voltage on Any Other Pin without 5V
Tolerance Pin
VIN
VSS -0.3
VDD +0.3
V
1/tCLCL
4
24
MHz
Operating Temperature
TA
-40
+85
C
Storage Temperature
TST
-55
+150
C
Maximum Current into VDD
-
150
mA
Maximum Current out of VSS
-
150
mA
Maximum Current sunk by a I/O Pin
-
25
mA
Maximum Current Sourced by a I/O Pin
-
25
mA
Maximum Current Sunk by Total I/O Pins
-
100
mA
Maximum Current Sourced by Total I/O Pins
-
100
mA
DC Power Supply
Oscillator Frequency
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
May 08, 2013
Page 79 of 100
Revision 1.01
NuMicro Nano102/112 Datasheet
9.2
Nano102/Nano112 DC Electrical Characteristics
(VDD-VSS=3.3V, TA = 25C, FOSC = 32 MHz unless otherwise specified.)
SPECIFICATIONS
PARAMETER
Operation voltage
Power Ground
SYM.
VDD
VSS
AVSS
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
1.8
-
-0.3
-
1.62
1.8
1.98
V
MCU operating in Run or Idle mode
1.44
1.6
1.76
V
Set LDO_LEVEL(LDO_CTL[3:2]) = 0x1
1.49
1.66
1.83
V
MCU operating in Power-down mode
Connect to LDO_CAP pin
3.6
V
VDD =1.8V up to 32 MHz
V
VLDO1
LDO Output Voltage
VLDO2
Analog Operating
Voltage
VLDO1=1.8 V
1
uF
AVDD
VDD
V
IDD5
11.7
mA
VDD
HXT
HIRC
PLL
All digital
module
3.3 V
12 MHz
X
V
V
IDD6
5.8
mA
3.3 V
12 MHz
X
V
X
IDD7
10.9
mA
1.8 V
12 MHz
X
V
V
IDD8
5.6
mA
1.8 V
12 MHz
X
V
X
Operating Current
Normal Run Mode
HCLK =32 MHz
while(1){}executed
from flash
IDD9
3.9
mA
3.3 V
12 MHz
X
X
V
IDD10
1.9
mA
3.3 V
12 MHz
X
X
X
IDD11
3.8
mA
1.8 V
12 MHz
X
X
V
VLDO1=1.6 V
IDD12
1.9
mA
1.8 V
12 MHz
May 08, 2013
Page 80 of 100
Revision 1.01
NUMICRO™ NANO102/112 SERIES DATASHEET
Operating Current
Normal Run Mode
HCLK =32 MHz
wkhile(1){}executed
from flash
CLDO
NuMicro Nano102/112 Datasheet
IDD131
5.8
mA
3.3 V
X
16 MHz
X
V
IDD141
2.3
mA
3.3 V
X
16 MHz
X
X
IDD151
5.7
mA
1.8 V
X
16 MHz
X
V
VLDO1=1.6 V
IDD161
2.3
mA
1.8 V
X
16 MHz
X
X
Operating Current
Normal Run Mode
HCLK =12 MHz
while(1){}executed
from flash
IDD132
4.0
mA
3.3 V
X
12 MHz
X
V
IDD142
1.7
mA
3.3 V
X
12 MHz
X
X
IDD152
4.0
mA
1.8 V
X
12 MHz
X
V
VLDO1=1.6 V
IDD162
1.7
mA
1.8 V
X
12 MHz
X
X
Operating Current
Normal Run Mode
HCLK =12 MHz
while(1){}executed
from flash
IDD13
3.8
mA
3.3 V
12 MHz
X
X
V
IDD14
1.9
mA
3.3 V
12 MHz
X
X
X
IDD15
3.8
mA
1.8 V
12 MHz
X
X
V
VLDO1=1.6 V
IDD16
1.9
mA
1.8 V
12 MHz
X
X
X
Operating Current
Normal Run Mode
xHCLK =4 MHz
while(1){}executed
from flash
IDD17
1.3
mA
3.3 V
4 MHz
X
X
V
IDD18
0.7
mA
3.3 V
4 MHz
X
X
X
IDD19
1.3
mA
1.8 V
4 MHz
X
X
V
VLDO1=1.6 V
IDD20
0.7
mA
1.8 V
4 MHz
X
X
X
LXT (kHz)
HIRC
PLL
Operating Current
Normal Run Mode
HCLK =32.768 kHz
wkhile(1){}executed
from flash
99
uA
VDD
IDD21
All digital
module
3.3 V
32.768
X
X
V
VLDO1=1.6 V
Operating Current
kNormal Run Mode
HCLK =32 kHz
wkhile(1){}executed
from flash
VLDO1=1.6 V
Operating Current
Idle Mode
HCLK =32 MHz
VLDO1=1.8 V
May 08, 2013
IDD22
93
uA
3.3 V
32.768
X
X
X
IDD23
95
uA
1.8 V
32.768
X
X
V
IDD24
89
uA
1.8 V
32.768
X
X
X
uA
LIRC
(kHz)
PLL
91
VDD
HXT/LXT
IDD25
All digital
module
3.3 V
X
10
X
V
IDD26
90
uA
3.3 V
X
10
X
X
IDD27
87
uA
1.8 V
X
10
X
V
IDD28
85
uA
1.8 V
X
10
X
X
VDD
HXT
HIRC
PLL
IIDLE5
8.4
mA
All digital
module
3.3 V
12 MHz
X
V
V
IIDLE6
2.6
mA
3.3 V
12 MHz
X
V
X
IIDLE7
8.0
mA
1.8 V
12 MHz
X
V
V
IIDLE8
2.5
mA
1.8 V
12 MHz
X
V
X
Page 81 of 100
Revision 1.01
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
Operating Current
Normal Run Mode
HCLK =16 MHz
while(1){}executed
from flash
NuMicro Nano102/112 Datasheet
Operating Current
Idle Mode
HCLK =12 MHz
VLDO1=1.6 V
IIDLE9
2.8
mA
3.3 V
12 MHz
X
X
V
IIDLE10
0.8
mA
3.3 V
12 MHz
X
X
X
IIDLE11
2.8
mA
1.8 V
12 MHz
X
X
V
IIDLE12
0.8
mA
1.8 V
12 MHz
X
X
X
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
May 08, 2013
Page 82 of 100
Revision 1.01
NuMicro Nano102/112 Datasheet
Operating Current
Idle Mode
HCLK =16 MHz
VLDO1=1.6 V
Operating Current
Idle Mode
HCLK =12 MHz
VLDO1=1.6 V
Operating Current
Idle Mode
HCLK =12 MHz
VLDO1=1.6 V
Operating Current
Idle Mode
HCLK =4 MHz
VLDO1=1.6 V
Operating Current
Idle Mode
HCLK =32.768 kHz
Operating Current
Idle Mode
HCLK =10 kHz
VLDO1=1.6 V
4.2
mA
3.3 V
X
16 MHz
X
V
IIDLE141
0.7
mA
3.3 V
X
16 MHz
X
X
IIDLE151
4.1
mA
1.8 V
X
16 MHz
X
V
IIDLE161
0.7
mA
1.8 V
X
16 MHz
X
X
IIDLE132
2.9
mA
3.3 V
X
12 MHz
X
V
IIDLE142
0.6
mA
3.3 V
X
12 MHz
X
X
IIDLE152
2.9
mA
1.8 V
X
12 MHz
X
V
IIDLE162
0.6
mA
1.8 V
X
12 MHz
X
X
IIDLE13
2.8
mA
3.3 V
12 MHz
X
X
V
IIDLE14
0.8
mA
3.3 V
12 MHz
X
X
X
IIDLE15
2.8
mA
1.8 V
12 MHz
X
X
V
IIDLE16
0.8
mA
1.8 V
12 MHz
X
X
X
IIDLE17
1.0
mA
3.3 V
4 MHz
X
X
V
IIDLE18
0.3
mA
3.3 V
4 MHz
X
X
X
IIDLE19
1.0
mA
1.8 V
4 MHz
X
X
V
IIDLE20
0.3
mA
1.8 V
4 MHz
X
X
X
HIRC
PLL
96
uA
VDD
LXT (kHz)
IIDLE21
All digital
module
3.3 V
32.768
X
X
V
IIDLE22
90
uA
3.3 V
32.768
X
X
X
IIDLE23
92
uA
1.8 V
32.768
X
X
V
IIDLE24
86
uA
1.8 V
32.768
X
X
X
VDD
HXT/LXT
90
uA
LIRC
(kHz)
PLL
IIDLE25
All digital
module
3.3 V
X
10
X
V
IIDLE26
89
uA
3.3 V
X
10
X
X
IIDLE27
86
uA
1.8 V
X
10
X
V
IIDLE28
84
uA
1.8 V
X
10
X
X
HXT/HIRC
PLL
LXT
(kHz)
RTC
RAM retension
3.3 V
X
X
X
V
IPWD1
Standby Current
Power-down Mode
VLDO1=1.6 V
May 08, 2013
0.65
uA
VDD
I PWD2
0.65
uA
1.8 V
X
X
X
V
IPWD3
1.5
uA
3.3 V
X
32.768
V
V
IPWD4
1.5
uA
1.8 V
X
32.768
V
V
Page 83 of 100
Revision 1.01
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
VLDO1=1.6 V
IIDLE131
NuMicro Nano102/112 Datasheet
Input Pull Up Resistor
PA, PB, PC, PD, PE,
PF
RIN
Input Leakage Current
PA, PB, PC, PD, PE,
PF
ILK
Input Low Voltage PA,
PB, PC, PD, PE, PF
-0.1
VIL1
43
KΩ
VDD = 3.3V
108
KΩ
VDD = 1.8V
VDD = 3.3V, 0<VIN<VDD
-
+0.1
A
-
0.4VDD
V
5.5
V
(Schmitt input)
Input High Voltage PA,
PB, PC, PD, PE, PF
VIH1
0.6VDD
(Schmitt input)
ADC and DAC shared pins without Input
5V tolerance.
Hysteresis voltage of
PA~PF (Schmitt input)
VHY
Input Low Voltage
[*2]
XT1
VIL2
0
-
0.4
Input High Voltage
[*2]
XT1
VIH2
1.5
-
VDD
+0.2
V
Input Low Voltage
[*2]
X32I
VIL4
0
-
0.3
V
Input High Voltage
[*2]
X32I
VIH4
1.5
-
1.98
V
Negative going
threshold
(Schmitt input),
/RESET
VILS
1.03
1.08
1.13
V
VDD = 3.3V
Positive going
threshold
(SchmittIput), /RESET
VIHS
1.75
2.01
2.25
V
VDD = 3.3V
ISR21
-10
-14
-
mA
ISR22
-3
-5
-
mA
Sink Current PA, PB,
PC, PD, PE, PF
ISK21
10
15
-
mA
(Push-pull Mode)
ISK22
3
6
-
mA
(Push-pull Mode)
V
VDD = 3.3V
VDD = 3.3V
VDD = 3.3V,
VS = Vdd-0.7V
VDD = 1.8V,
VS = Vdd-0.45V
VDD = 3.3V,
VS = 0.7V
VDD = 1.8V,
VS = 0.45V
Note:
1. /RESET pin is a Schmitt trigger input.
2. Crystal Input is a CMOS input.
3. It is recommended that a 10uF or higher capacitor and a 100nF bypass capacitor are connected between VDD and
the closest VSS pin of the device.
4. For ensuring power stability, a 1uF or higher capacitor must be connected between LDO pin and the closest VSS pin
of the device. Also a 100nF bypass capacitor between LDO and VSS help suppressing output noise.
5. All peripherals’ clock source is from HXT (12 MHz), except SPI from HCLK.
May 08, 2013
Page 84 of 100
Revision 1.01
NUMICRO™ NANO102/112 SERIES PRELIMINARY DATASHEET
Source Current PA,
PB, PC, PD, PE, PF
0.2VDD
NuMicro Nano102/112 Datasheet
9.3
AC Electrical Characteristics
9.3.1
External Input Clock
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
TYP.
MAX. UNIT
Clock High Time
tCHCX
10
-
nS
Clock Low Time
tCLCX
10
-
nS
Clock Rise Time
tCLCH
2
-
15
nS
Clock Fall Time
tCHCL
2
-
15
nS
tCLCL
tCLCH
0.7 VDD
90%
tCLCX
10%
0.3 VDD
tCHCL
tCHCX
Note: Duty cycle is 50%.
External 4~24 MHz XTAL Oscillator
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
TYP.
MAX. UNIT
Oscillator frequency
fHXT
4
12
24
MHz
Temperature
THXT
-40
-
+85
C
Operating current
IHXT
9.3.2.1
0.3
VDD = 1.8V ~ 3.6V
mA
VDD = 3.0V
Typical Crystal Application Circuits
CRYSTAL
4MHz ~ 24 MHz
Jan 15, 2015
C1
C2
R1
20pF
20pF
without
Page 85 of 100
Revision 1.03
NUMICRO™ NANO102/112 SERIES DATASHEET
9.3.2
NuMicro Nano102/112 Datasheet
XT1_OUT
XT1_IN
R1
C2
C1
Figure 9‑1 Typical Crystal Application Circuit
9.3.3
External 32.768 kHz Crystal
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
Oscillator frequency
fLXT
Temperature
TLXT
Operating current
ILXT
NUMICRO™ NANO102/112 SERIES DATASHEET
9.3.3.1
TYP.
MAX. UNIT
32.768
-40
-
kHz
+85
VDD = 1.8V ~ 3.6V
C
A
1
VDD = 3.0V
Typical Crystal Application Circuits
CRYSTAL
32.768 kHz
C3
C4
R2
20pF
20pF
without
X32O
C4
X32I
R2
C3
Figure 9‑2 Typical Crystal Application Circuit
Jan 15, 2015
Page 86 of 100
Revision 1.03
NuMicro Nano102/112 Datasheet
9.3.4
Internal 12 MHz Oscillator
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
Supply voltage[1]
Calibrated Internal
Oscillator Frequency
VHRC
1.8
V
11.88
12
12.12
MHz
25C, VDD = 3.3V
11.76
12
12.24
MHz
-40C ~ +85C,
VDD = 1.8V~3.6V
-40C ~ +85 C,
VDD = 1.8V~3.6V
FHRC
11.88
Operating current
TYP. MAX. UNIT
IHRC
12
12.12
MHz
Enable 32.768K crystal
oscillator and set
TRIM_SEL[1:0]=”10”
A
250
Note: Internal oscillator operation voltage comes from LDO.
9.3.5
Internal 10 kHz Oscillator
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
Supply voltage[1]
Center Frequency
Operating current
VLRC
TYP. MAX. UNIT
1.8
V
7
10
13
kHz
25C, VDD = 3V
5
10
15
kHz
-40C ~+85 C,
VDD = 1.8V~3.6V
A
VDD = 3V
FLRC
ILRC
0.3
Note: Internal oscillator operation voltage comes from LDO.
9.4
9.4.1
Analog Characteristics
12-bit ADC
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
Operating voltage
AVDD
Operating current (AVDD
current)
IADC32
TYP.
1.8
MAX. UNIT
3.6
120
(Enable ADC and disable all
Jan 15, 2015
Page 87 of 100
V
AVDD = VDD
A
AVDD = VDD = 3.0V
ADC_VREF = AVDD
ADC Clock Rate = 32 MHz
Revision 1.03
NUMICRO™ NANO102/112 SERIES DATASHEET
MIN.
NuMicro Nano102/112 Datasheet
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
TYP.
MAX. UNIT
other analog modules)
IADC2
A
30
NUMICRO™ NANO102/112 SERIES DATASHEET
Resolution
RADC
Reference voltage
VREF
Reference input current (Avg.)
IREF
ADC input voltage
VIN
0
Conversion time
TCONV
1
Conversion Rate
FSPS
Integral Non-Linearity Error
INL
±1
LSB VREF is external Vref pin
Differential Non-Linearity
DNL
±0.8
LSB VREF is external Vref pin
Gain error
EG
±2
LSB VREF is external Vref pin
Offset error
EOFFSET
±1.5
LSB VREF is external Vref pin
Absolute error
EABS
-
ADC Clock frequency
FADC
0.25
ADCYC
20
CIN
-
Clock cycle
Internal Capacitance
Monotonic
9.4.2
-
1.8
12
Bit
AVDD
V
1
A
VREF
V
AVDD = VDD = 3.0V
ADC_VREF = AVDD
ADC Clock Rate = 2 MHz
S
1.5M
Hz
VDD = 3V
±6
LSB VREF is external Vref pin
32
MHz
Cycle
5
-
pF
Guaranteed
-
Brown-out Detector
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
AVDD
Supply Voltage
0
-
3.6
V
-
TA
Temperature
-40
25
85
℃
-
IBOD
Quiescent Current
-
1
μA
AVDD = 3V
2.4
2.5
2.6
V
BODCTL[2] = 1
1.9
2.0
2.1
V
BODCTL[1] = 1
1.6
1.7
1.8
V
BODCTL[0] = 1
Brown-out Voltage
VBOD
Jan 15, 2015
25℃
Page 88 of 100
Revision 1.03
NuMicro Nano102/112 Datasheet
9.4.3
Power-on Reset
Symbol
Parameter
Min
Typ
Max
Unit
Test Condition
TA
Temperature
-40
25
85
℃
-
VPOR
Reset Voltage
V
-
9.4.4
1.6
Temperature Sensor
SPECIFICATIONS
PARAMETER
TEST CONDITION
(supply voltage = 3V)
SYM.
MIN.
TYP.
MAX. UNIT
o
Detection Temperature
TDET
-40
+85
C
Operating current
ITEMP
-
5
-
A
Gain
VTG
-1.76
-1.68
-1.60
mV/ C
Offset
VTO
735
745
755
mV
o
o
Tempeature at 0 C
Note: Internal operation voltage comes form LDO.
9.4.5
LCD
SYM.
TEST CONDITION
MIN.
TYP. MAX. UNIT
Operating voltage
VDD
1.8
-
3.6
V
VLCD voltage
VLCD34
-
3.4
-
V
CPUMP_VOL_SET=111, no loading
VLCD voltage
VLCD33
-
3.3
-
V
CPUMP_VOL_SET=110, no loading
VLCD voltage
VLCD32
-
3.2
-
V
CPUMP_VOL_SET=101, no loading
VLCD voltage
VLCD31
-
3.1
-
V
CPUMP_VOL_SET=100, no loading
VLCD voltage
VLCD30
-
3.0
-
V
CPUMP_VOL_SET=011, no loading
VLCD voltage
VLCD29
-
2.9
-
V
CPUMP_VOL_SET=010, no loading
VLCD voltage
VLCD28
-
2.8
-
V
CPUMP_VOL_SET=001, no loading
VLCD voltage
VLCD27
-
2.7
-
V
CPUMP_VOL_SET=000, no loading
ILCDint
-
9.5
-
A
VDD = 3V, frame rate = 64Hz
Without loading (internal C type,
with 0.1uF)
ILCDext
ILCDint
2.5
-
A
VDD = 3V, frame rate = 64Hz
Without loading (external C type
with 0.1uF)
Operating current
(Include 32.768 KHz crystal
OSC and RTC operating)
Jan 15, 2015
Page 89 of 100
Revision 1.03
NUMICRO™ NANO102/112 SERIES DATASHEET
SPECIFICATIONS
PARAMETER
NuMicro Nano102/112 Datasheet
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
TYP. MAX. UNIT
A
VDD = 3V, frame rate = 64Hz
Without
loading (internal R type with
internal 200KΩresistor ladder)
A
VDD = 3V, frame rate = 64Hz
Without
loading (internal R type with
internal 300KΩresistor ladder)
5.5
A
VDD = 3V, frame rate = 64Hz
Without
loading (internal R type with
internal 400KΩresistor ladder)
3.7
A
VDD = 3V, frame rate = 64Hz
Without loading (external R type
with external 1MΩresistor ladder)
8.3
ILCDintR
6.4
ILCDextR
9.4.6
Internal Voltage Reference
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
NUMICRO™ NANO102/112 SERIES DATASHEET
MIN.
9.4.7
TYP. MAX. UNIT
Operating voltage
AVDD
1.8
-
3.6
V
1.5V voltage reference
VREF1
1.44
1.5
1.56
V
AVDD ≥ 1.8V (-40C ~85C)
1.8V voltage reference
VREF2
1.69
1.8
1.87
V
AVDD ≥ 2.0V (-40C ~85C)
2.5V voltage reference
VREF3
2.35
2.5
2.60
V
AVDD ≥ 2.8V (-40C ~85C)
Stable Time
TREFTAB
-
1
-
ms
Operating current
IVREF
-
30
-
A
AVDD = 3V
Comparator
Symbol
Parameter
Min
VCMP
Supply Voltage
1.8
TA
Temperature
-40
25
ICMP
Operation Current
-
40
VOFF
Input Offset Voltage
VSW
Output Swing
Jan 15, 2015
0.1
Typ
Max
Unit
3.6
V
85
℃
-
μA
AVDD = 3 V
10
20
-
AVDD - 0.1
Page 90 of 100
Test Condition
mV V
-
Revision 1.03
NuMicro Nano102/112 Datasheet
VCOM
Input Common Mode Range
0.1
-
AVDD – 0.1
V
-
-
DC Gain
40
70
-
dB
-
TPGD
Propagation Delay
-
200
-
ns
VDIFF = 100mV
VHYS
Hysteresis
-
±10
-
mV
TSTB
Stable time
-
-
1
μs
NUMICRO™ NANO102/112 SERIES DATASHEET
Jan 15, 2015
Page 91 of 100
Revision 1.03
NuMicro Nano102/112 Datasheet
10 PACKAGE DIMENSIONS
10.1 100L LQFP (14x14x1.4 mm footprint 2.0 mm)
HD
D
7
5
A
A2
51
7
6
50
100
26
A1
HE E
L
1
25
e
L1
c
b
NUMICRO™ NANO102/112 SERIES DATASHEET

Y
Controlling Dimension : Millimeters
Symbol
Dimension in inch
Min Nom
Max
A
A1
A
2b
c
0.063
0.002
0.053
0.007
0.004
D
0.547
E
0.547
0.055
0.009
0.006
0.551
0.551
0.05
1.35
0.057
0.011
0.17
0.008
0.10
0.556
0.556
13.90
13.90
e
HD
0.622
0.630
0.638
15.80
HE
L
0.622
0.018
0.630
0.024
0.638
0.030
15.80
0.020
L1
y

Jan 15, 2015
Dimension in mm
Min Nom
Max
1.60
0.45
0.039
7
Page 92 of 100
1.45
14.00
14.10
14.00
14.10
0.50
16.00
16.00
0.60
1.00
0.27
0.20
16.20
16.20
0.75
0.10
0.004
0
1.40
0.22
0.15
0
7
Revision 1.03
NuMicro Nano102/112 Datasheet
10.2 64R LQFP(10x10x1.4 mm footprint 2.0 mm)
NUMICRO™ NANO102/112 SERIES DATASHEET
Jan 15, 2015
Page 93 of 100
Revision 1.03
NuMicro Nano102/112 Datasheet
10.3 64S LQFP (7x7x1.4 mm footprint 2.0 mm)
NUMICRO™ NANO102/112 SERIES DATASHEET
Jan 15, 2015
Page 94 of 100
Revision 1.03
NuMicro Nano102/112 Datasheet
NUMICRO™ NANO102/112 SERIES DATASHEET
Jan 15, 2015
Page 95 of 100
Revision 1.03
NuMicro Nano102/112 Datasheet
10.4 48L LQFP (7x7x1.4 mm footprint 2.0 mm)
NUMICRO™ NANO102/112 SERIES DATASHEET
Jan 15, 2015
Page 96 of 100
Revision 1.03
NuMicro Nano102/112 Datasheet
10.5 33L QFN (5x5x1.4 mm footprint 2.0 mm)
NUMICRO™ NANO102/112 SERIES DATASHEET
Jan 15, 2015
Page 97 of 100
Revision 1.03
NuMicro Nano102/112 Datasheet
NUMICRO™ NANO102/112 SERIES DATASHEET
Jan 15, 2015
Page 98 of 100
Revision 1.03
NuMicro Nano102/112 Datasheet
11 REVISION HISTORY
Date
Revision
2014.03.28
1.00
1.
Initial release
2014.05.08
1.01
1.
Modified some typos and format.
1.
Modified the pin description for LCD_Vx in section 4.4.
2.
Modified all PWM1 group to PWM0 group in section 6.10.
3.
Modified “PWM1 channel 2 and 3” to “PWM0 channel 2 and 3” in section 6.10.
4.
Modified some typos and format.
1.
Updated ADC channel number in NANO102 feature list in Chapter 2.
2.
Corrected typo in NANO102 64-pin sequence in section 4.4.
3.
Updated all power related pins from “VDD, VSS, AVDD, AVSS, VTEMP and VLCD” to
“VDD, VSS, AVDD, AVSS, VTEMP and VLCD” in the Datashhet.
2014.09.02
2015.01.15
1.02
1.03
Description
NUMICRO™ NANO102/112 SERIES DATASHEET
Jan 15, 2015
Page 99 of 100
Revision 1.03
NuMicro Nano102/112 Datasheet
Important Notice
NUMICRO™ NANO102/112 SERIES DATASHEET
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Jan 15, 2015
Page 100 of 100
Revision 1.03