Fujitsu MB95F563HWQN-G-JNERE1 8-bit microcontroller Datasheet

FUJITSU SEMICONDUCTOR
DATA SHEET
DS702-00003-1v0-E
8-bit Microcontrollers
CMOS
New-8FX MB95560H/570H/580H Series
MB95F562H/F562K/F563H/F563K/F564H/F564K
MB95F572H/F572K/F573H/F573K/F574H/F574K
MB95F582H/F582K/F583H/F583K/F584H/F584K
■ DESCRIPTION
MB95560H/570H/580H is a series of general-purpose, single-chip microcontrollers. In addition to a compact
instruction set, the microcontrollers of these series contain a variety of peripheral resources.
■ FEATURES
• New-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instructions
• Bit manipulation instructions, etc.
• Clock
• Selectable main clock source
Main oscillation clock (up to 16.25 MHz, maximum machine clock frequency: 8.125 MHz)
External clock (up to 32.5 MHz, maximum machine clock frequency: 16.25 MHz)
Main CR clock (4 MHz ± 2%)
The main CR clock frequency becomes 8 MHz when the PLL multiplier is 2.
The main CR clock frequency becomes 10 MHz when the PLL multiplier is 2.5.
The main CR clock frequency becomes 12 MHz when the PLL multiplier is 3.
The main CR clock frequency becomes 16 MHz when the PLL multiplier is 4.
• Selectable subclock source
Sub-oscillation clock (32.768 kHz)
External clock (32.768 kHz)
Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 150 kHz)
• Timer
• 8/16-bit composite timer × 2 channels
• Time-base timer × 1 channel
• Watch prescaler × 1 channel
• LIN-UART (available only on MB95F562H/F562K/F563H/F563K/F564H/F564K/F582H/F582K/F583H/
F583K/F584H/F584K)
• Full duplex double buffer
• Capable of clock-synchronized serial data transfer and clock-asynchronized serial data transfer
(Continued)
For the information for microcontroller supports, see the following website.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2010.12
MB95560H/570H/580H Series
(Continued)
• External interrupt
• Interrupt by edge detection (rising edge, falling edge, and both edges can be selected)
• Can be used to wake up the device from different low power consumption (standby) modes
• 8/10-bit A/D converter
• 8-bit or 10-bit resolution can be selected.
• Low power consumption (standby) modes
• Stop mode
• Sleep mode
• Watch mode
• Time-base timer mode
• I/O port
• MB95F562H/F563H/F564H (maximum no. of I/O ports: 16)
General-purpose I/O ports (N-ch open drain)
:1
General-purpose I/O ports (CMOS I/O)
: 15
• MB95F562K/F563K/F564K (maximum no. of I/O ports: 17)
General-purpose I/O ports (N-ch open drain)
:2
General-purpose I/O ports (CMOS I/O)
: 15
• MB95F572H/F573H/F574H (maximum no. of I/O ports: 4)
General-purpose I/O ports (N-ch open drain)
:1
General-purpose I/O ports (CMOS I/O)
:3
• MB95F572K/F573K/F574K (maximum no. of I/O ports: 5)
General-purpose I/O ports (N-ch open drain)
:2
General-purpose I/O ports (CMOS I/O)
:3
• MB95F582H/F583H/F584H (maximum no. of I/O ports: 12)
General-purpose I/O ports (N-ch open drain)
:1
General-purpose I/O ports (CMOS I/O)
: 11
• MB95F582K/F583K/F584K (maximum no. of I/O ports: 13)
General-purpose I/O ports (N-ch open drain)
:2
General-purpose I/O ports (CMOS I/O)
: 11
• On-chip debug
• 1-wire serial control
• Serial writing supported (asynchronous mode)
• Hardware/software watchdog timer
• Built-in hardware watchdog timer
• Built-in software watchdog timer
• Low-voltage detection reset circuit (available only on MB95F562K/F563K/F564K/F572K/F573K/F574K/
F582K/F583K/F584K)
• Built-in low-voltage detector
• Clock supervisor counter
• Built-in clock supervisor counter function
• Dual operation Flash memory
• The erase/write operation and the read operation can be executed in different banks (upper bank/lower
bank) simultaneously.
• Flash memory security function
• Protects the content of the Flash memory
2
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ PRODUCT LINE-UP
• MB95560H Series
Part number
MB95F562H
MB95F563H
MB95F564H
MB95F562K
MB95F563K
MB95F564K
Parameter
Type
Flash memory product
Clock
supervisor
It supervises the main clock oscillation.
counter
Flash memory
8 Kbyte
12 Kbyte
20 Kbyte
8 Kbyte
12 Kbyte
20 Kbyte
capacity
RAM capacity
240 bytes
496 bytes
496 bytes
240 bytes
496 bytes
496 bytes
Low-voltage
No
Yes
detection reset
Reset input
Dedicated
Selected through software
• Number of basic instructions
: 136
• Instruction bit length
: 8 bits
• Instruction length
: 1 to 3 bytes
CPU functions
• Data bit length
: 1, 8 and 16 bits
• Minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 MHz)
• Interrupt processing time
: 0.6 µs (machine clock frequency = 16.25 MHz)
• I/O ports (Max) : 17
• I/O ports (Max) : 16
General• CMOS I/O
: 15
• CMOS I/O
: 15
purpose I/O
• N-ch open drain: 2
• N-ch open drain: 1
Time-base timer Interval time: 0.256 ms to 8.3 s (external clock frequency = 4 MHz)
• Reset generation cycle
Hardware/
software
- Main oscillation clock at 10 MHz: 105 ms (Min)
watchdog timer • The sub-CR clock can be used as the source clock of the hardware watchdog timer.
Wild register
It can be used to replace 3 bytes of data.
• A wide range of communication speed can be selected by a dedicated reload timer.
• It has a full duplex double buffer.
LIN-UART
• Clock-synchronized serial data transfer and clock-asynchronized serial data transfer is enabled.
• The LIN function can be used as a LIN master or a LIN slave.
6 channels
8/10-bit A/D
converter
8-bit or 10-bit resolution can be selected.
2 channels
• The timer can be configured as an "8-bit timer × 2 channels" or a "16-bit timer × 1 channel".
8/16-bit
• It has built-in timer function, PWC function, PWM function and input capture function.
composite timer
• Count clock: it can be selected from internal clocks (seven types) and external clocks.
• It can output square wave.
6 channels
External
• Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.)
interrupt
• It can be used to wake up the device from the standby mode.
• 1-wire serial control
On-chip debug
• It supports serial writing (asynchronous mode).
(Continued)
DS702-00003-1v0-E
3
MB95560H/570H/580H Series
(Continued)
Part number
MB95F562H
MB95F563H
MB95F564H
MB95F562K
MB95F563K
MB95F564K
Parameter
Watch prescaler Eight different time intervals can be selected.
• It supports automatic programming (Embedded Algorithm) and write/erase/erase-suspend/
erase-resume commands.
• It has a flag indicating the completion of the operation of Embedded Algorithm.
Flash memory • Flash security feature for protecting the content of the Flash memory
Number of program/erase cycles
Data retention time
1000
10000
100000
20 years
10 years
5 years
Standby mode Sleep mode, stop mode, watch mode, time-base timer mode
LCC-32P-M19
Package
FPT-20P-M09
FPT-20P-M10
4
DS702-00003-1v0-E
MB95560H/570H/580H Series
• MB95570H Series
Part number
MB95F572H
MB95F573H
MB95F574H
MB95F572K
MB95F573K
MB95F574K
Parameter
Type
Flash memory product
Clock
supervisor
It supervises the main clock oscillation.
counter
Flash memory
8 Kbyte
12 Kbyte
20 Kbyte
8 Kbyte
12 Kbyte
20 Kbyte
capacity
RAM capacity
240 bytes
496 bytes
496 bytes
240 bytes
496 bytes
496 bytes
Low-voltage
No
Yes
detection reset
Reset input
Dedicated
Selected through software
• Number of basic instructions
: 136
• Instruction bit length
: 8 bits
• Instruction length
: 1 to 3 bytes
CPU functions
• Data bit length
: 1, 8 and 16 bits
• Minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 MHz)
• Interrupt processing time
: 0.6 µs (machine clock frequency = 16.25 MHz)
• I/O ports (Max) : 5
• I/O ports (Max) : 4
General• CMOS I/O
:3
• CMOS I/O
:3
purpose I/O
• N-ch open drain: 2
• N-ch open drain: 1
Time-base timer Interval time: 0.256 ms to 8.3 s (external clock frequency = 4 MHz)
• Reset generation cycle
Hardware/
- Main oscillation clock at 10 MHz: 105 ms (Min)
software
watchdog timer • The sub-CR clock can be used as the source clock of the hardware watchdog timer.
Wild register
It can be used to replace 3 bytes of data.
LIN-UART
No LIN-UART
2 channels
8/10-bit A/D
converter
8-bit or 10-bit resolution can be selected.
1 channel
• The timer can be configured as an "8-bit timer × 2 channels" or a "16-bit timer × 1 channel".
8/16-bit
• It has built-in timer function, PWC function, PWM function and input capture function.
composite timer
• Count clock: it can be selected from internal clocks (seven types) and external clocks.
• It can output square wave.
2 channels
External
• Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.)
interrupt
• It can be used to wake up the device from standby modes.
• 1-wire serial control
On-chip debug
• It supports serial writing (asynchronous mode).
Watch prescaler Eight different time intervals can be selected.
• It supports automatic programming (Embedded Algorithm) and write/erase/erase-suspend/
erase-resume commands.
• It has a flag indicating the completion of the operation of Embedded Algorithm.
Flash memory • Flash security feature for protecting the content of the Flash memory
Number of program/erase cycles
Data retention time
1000
10000
100000
20 years
10 years
5 years
Standby mode Sleep mode, stop mode, watch mode, time-base timer mode
Package
FPT-8P-M08
DS702-00003-1v0-E
5
MB95560H/570H/580H Series
• MB95580H Series
Part number
MB95F582H
MB95F583H
MB95F584H
MB95F582K
MB95F583K
MB95F584K
Parameter
Type
Flash memory product
Clock
supervisor
It supervises the main clock oscillation.
counter
Flash memory
8 Kbyte
12 Kbyte
20 Kbyte
8 Kbyte
12 Kbyte
20 Kbyte
capacity
RAM capacity
240 bytes
496 bytes
496 bytes
240 bytes
496 bytes
496 bytes
Low-voltage
No
Yes
detection reset
Reset input
Dedicated
Selected through software
• Number of basic instructions
: 136
• Instruction bit length
: 8 bits
• Instruction length
: 1 to 3 bytes
CPU functions
• Data bit length
: 1, 8 and 16 bits
• Minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 MHz)
• Interrupt processing time
: 0.6 µs (machine clock frequency = 16.25 MHz)
• I/O ports (Max) : 13
• I/O ports (Max) : 12
General• CMOS I/O
: 11
• CMOS I/O
: 11
purpose I/O
• N-ch open drain: 2
• N-ch open drain: 1
Time-base timer Interval time: 0.256 ms to 8.3 s (external clock frequency = 4 MHz)
• Reset generation cycle
Hardware/
- Main oscillation clock at 10 MHz: 105 ms (Min)
software
watchdog timer • The sub-CR clock can be used as the source clock of the hardware watchdog timer.
Wild register
It can be used to replace 3 bytes of data.
• A wide range of communication speed can be selected by a dedicated reload timer.
• It has a full duplex double buffer.
LIN-UART
• Clock-synchronized serial data transfer and clock-asynchronized serial data transfer is enabled.
• The LIN function can be used as a LIN master or a LIN slave.
5 channels
8/10-bit A/D
converter
8-bit or 10-bit resolution can be selected.
1 channel
• The timer can be configured as an "8-bit timer × 2 channels" or a "16-bit timer × 1 channel".
8/16-bit
• It has built-in timer function, PWC function, PWM function and input capture function.
composite timer
• Count clock: it can be selected from internal clocks (seven types) and external clocks.
• It can output square wave.
6 channels
External
• Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.)
interrupt
• It can be used to wake up the device from standby modes.
• 1-wire serial control
On-chip debug
• It supports serial writing (asynchronous mode).
(Continued)
6
DS702-00003-1v0-E
MB95560H/570H/580H Series
(Continued)
Part number
MB95F582H
MB95F583H
MB95F584H
MB95F582K
MB95F583K
MB95F584K
Parameter
Watch prescaler Eight different time intervals can be selected.
• It supports automatic programming (Embedded Algorithm) and write/erase/erase-suspend/
erase-resume commands.
• It has a flag indicating the completion of the operation of Embedded Algorithm.
Flash memory • Flash security feature for protecting the content of the Flash memory
Number of program/erase cycles
Data retention time
1000
10000
100000
20 years
10 years
5 years
Standby mode Sleep mode, stop mode, watch mode, time-base timer mode
LCC-32P-M19
Package
FPT-16P-M08
FPT-16P-M23
DS702-00003-1v0-E
7
MB95560H/570H/580H Series
■ PACKAGES AND CORRESPONDING PRODUCTS
• MB95560H Series
Part number
MB95F562H
MB95F562K
MB95F563H
MB95F563K
MB95F564H
MB95F564K
LCC-32P-M19
O
O
O
O
O
O
FPT-20P-M09
O
O
O
O
O
O
FPT-20P-M10
O
O
O
O
O
O
FPT-16P-M08
X
X
X
X
X
X
FPT-16P-M23
X
X
X
X
X
X
FPT-8P-M08
X
X
X
X
X
X
MB95F572H
MB95F572K
MB95F573H
MB95F573K
MB95F574H
MB95F574K
LCC-32P-M19
X
X
X
X
X
X
FPT-20P-M09
X
X
X
X
X
X
FPT-20P-M10
X
X
X
X
X
X
FPT-16P-M08
X
X
X
X
X
X
FPT-16P-M23
X
X
X
X
X
X
FPT-8P-M08
O
O
O
O
O
O
MB95F582H
MB95F582K
MB95F583H
MB95F583K
MB95F584H
MB95F584K
LCC-32P-M19
O
O
O
O
O
O
FPT-20P-M09
X
X
X
X
X
X
FPT-20P-M10
X
X
X
X
X
X
FPT-16P-M08
O
O
O
O
O
O
FPT-16P-M23
O
O
O
O
O
O
FPT-8P-M08
X
X
X
X
X
X
Package
• MB95570H Series
Part number
Package
• MB95580H Series
Part number
Package
O: Available
X: Unavailable
8
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ DIFFERENCES AMONG PRODUCTS AND NOTES ON PRODUCT SELECTION
• Current consumption
When using the on-chip debug function, take account of the current consumption of flash erase/write.
For details of current consumption, see “■ ELECTRICAL CHARACTERISTICS”.
• Package
For details of information on each package, see “■ PACKAGES AND CORRESPONDING PRODUCTS” and
“■ PACKAGE DIMENSION”.
• Operating voltage
The operating voltage varies, depending on whether the on-chip debug function is used or not.
For details of the operating voltage, see “■ ELECTRICAL CHARACTERISTICS”.
• On-chip debug function
The on-chip debug function requires that VCC, VSS and 1 serial-wire be connected to an evaluation tool. For
details of the connection method, refer to “CHAPTER 21 EXAMPLE OF SERIAL PROGRAMMING
CONNECTION” in the hardware manual of the MB95560H/570H/580H Series.
DS702-00003-1v0-E
9
MB95560H/570H/580H Series
32
31
30
29
28
27
26
25
NC
NC
NC
NC
NC
NC
NC
NC
■ PIN ASSIGNMENT
X1/PF1
X0/PF0
1
2
VSS
X1A/PG2
3
4
X0A/PG1
Vcc
LCC-32P-M19
(MB95560H Series)
C
5
6
7
RST/PF2
8
* The number of usable pins is 20.
X0/PF0
X1/PF1
1
2
Vss
X1A/PG2
3
4
X0A/PG1
Vcc
C
RST/PF2
TO10/P62
TO11/P63
5
6
7
8
9
10
9
10
11
12
13
14
15
16
TO11/P63
TO10/P62
NC
NC
NC
NC
P00/AN00
P64/EC1
(TOP VIEW)
(TOP VIEW)
FPT-20P-M09
FPT-20P-M10
(MB95560H Series)
24
23
P07/INT07
P12/EC0/DBG
22
21
20
19
P06/INT06/TO01
P05/INT05/AN05/TO00
P04/INT04/AN04/SIN/EC0
P03/INT03/AN03/SOT
18
P02/INT02/AN02/SCK
17
P01/AN01
20
19
P12/EC0/DBG
P07/INT07
18
17
P06/INT06/TO01
P05/INT05/AN05/TO00
16
15
14
13
12
11
P04/INT04/AN04/SIN/EC0
P03/INT03/AN03/SOT
P02/INT02/AN02/SCK
P01/AN01
P00/AN00
P64/EC1
(Continued)
10
DS702-00003-1v0-E
MB95560H/570H/580H Series
X1/PF1
X0/PF0
1
2
VSS
X1A/PG2
3
4
NC
NC
NC
NC
NC
NC
NC
NC
25
(TOP VIEW)
24
23
P07/INT07
P12/EC0/DBG
22
6
19
P06/INT06/TO01
P05/INT05/AN05/TO00
P04/INT04/AN04/SIN/EC0
P03/INT03/AN03/SOT
7
8
18
17
P02/INT02/AN02/SCK
P01/AN01
21
LCC-32P-M19
5 (MB95580H Series) 20
X0/PF0
1
X1/PF1
Vss
2
3
X1A/PG2
X0A/PG1
Vcc
RST/PF2
C
4
5
6
7
8
Vss
Vcc
C
RST/PF2
1
2
3
4
14
15
16
NC
NC
NC
* The number of usable pins is 16.
9
10
11
12
13
C
RST/PF2
NC
NC
NC
NC
NC
X0A/PG1
Vcc
DS702-00003-1v0-E
32
31
30
29
28
27
26
(Continued)
(TOP VIEW)
FPT-16P-M08
FPT-16P-M23
(MB95580H Series)
(TOP VIEW)
FPT-8P-M08
(MB95570H Series)
16
P12/EC0/DBG
15
14
P07/INT07
P06/INT06/TO01
13
12
11
10
9
P05/INT05/AN05/TO00
P04/INT04/AN04/SIN/EC0
P03/INT03/AN03/SOT
P01/AN01
P02/INT02/AN02/SCK
8
7
6
5
P12/EC0/DBG
P06/INT06/TO01
P05/AN05/TO00
P04/INT04/AN04/EC0
11
MB95560H/570H/580H Series
■ PIN FUNCTIONS (MB95560H Series, 32 pins)
Pin no.
1
2
3
4
5
Pin name
PF1
X1
PF0
X0
VSS
PG2
X1A
PG1
X0A
I/O
circuit
type*
B
B
⎯
C
C
Function
General-purpose I/O port
Main clock I/O oscillation pin
General-purpose I/O port
Main clock input oscillation pin
Power supply pin (GND)
General-purpose I/O port
Subclock I/O oscillation pin
General-purpose I/O port
Subclock input oscillation pin
6
VCC
⎯
Power supply pin
7
C
⎯
Capacitor connection pin
PF2
8
9
RST
P63
General-purpose I/O port
A
E
TO11
10
P62
Reset pin
Dedicated reset pin in MB95F562H/F563H/F564H
General-purpose I/O port
High-current pin
8/16-bit composite timer ch. 1 output pin
E
TO10
General-purpose I/O port
High-current pin
8/16-bit composite timer ch. 1 output pin
11
NC
⎯
It is an internally connected pin. Always leave it unconnected.
12
NC
⎯
It is an internally connected pin. Always leave it unconnected.
13
NC
⎯
It is an internally connected pin. Always leave it unconnected.
14
NC
⎯
It is an internally connected pin. Always leave it unconnected.
D
General-purpose I/O port
High-current pin
15
P00
AN00
16
P64
A/D converter analog input pin
E
EC1
17
P01
8/16-bit composite timer ch. 1 clock input pin
D
AN01
INT02
General-purpose I/O port
High-current pin
A/D converter analog input pin
General-purpose I/O port
High-current pin
P02
18
General-purpose I/O port
High-current pin
D
External interrupt input pin
AN02
A/D converter analog input pin
SCK
LIN-UART clock I/O pin
(Continued)
12
DS702-00003-1v0-E
MB95560H/570H/580H Series
(Continued)
Pin no.
Pin name
I/O
circuit
type*
General-purpose I/O port
High-current pin
P03
19
20
21
INT03
D
A/D converter analog input pin
SOT
LIN-UART data output pin
P04
General-purpose I/O port
INT04
External interrupt input pin
AN04
D
LIN-UART data input pin
EC0
8/16-bit composite timer ch. 0 clock input pin
P05
General-purpose I/O port
High-current pin
INT05
D
External interrupt input pin
AN05
A/D converter analog input pin
TO00
8/16-bit composite timer ch. 0 output pin
General-purpose I/O port
High-current pin
INT06
E
EC0
External interrupt input pin
8/16-bit composite timer ch. 0 output pin
P12
24
A/D converter analog input pin
SIN
TO01
23
External interrupt input pin
AN03
P06
22
Function
General-purpose I/O port
F
8/16-bit composite timer ch. 0 clock input pin
DBG
DBG input pin
P07
General-purpose I/O port
High-current pin
E
INT07
External interrupt input pin
25
NC
⎯
It is an internally connected pin. Always leave it unconnected.
26
NC
⎯
It is an internally connected pin. Always leave it unconnected.
27
NC
⎯
It is an internally connected pin. Always leave it unconnected.
28
NC
⎯
It is an internally connected pin. Always leave it unconnected.
29
NC
⎯
It is an internally connected pin. Always leave it unconnected.
30
NC
⎯
It is an internally connected pin. Always leave it unconnected.
31
NC
⎯
It is an internally connected pin. Always leave it unconnected.
32
NC
⎯
It is an internally connected pin. Always leave it unconnected.
*: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”.
DS702-00003-1v0-E
13
MB95560H/570H/580H Series
■ PIN FUNCTIONS (MB95560H Series, 20 pins)
Pin no.
1
2
3
4
5
Pin name
PF0
X0
PF1
X1
VSS
PG2
X1A
PG1
X0A
I/O
circuit
type*
B
B
—
C
C
Function
General-purpose I/O port
Main clock input oscillation pin
General-purpose I/O port
Main clock I/O oscillation pin
Power supply pin (GND)
General-purpose I/O port
Subclock I/O oscillation pin
General-purpose I/O port
Subclock input oscillation pin
6
VCC
—
Power supply pin
7
C
—
Capacitor connection pin
PF2
8
9
RST
P62
General-purpose I/O port
A
E
TO10
10
P63
P64
E
P00
E
P01
D
D
15
General-purpose I/O port
High-current pin
A/D converter analog input pin
General-purpose I/O port
High-current pin
P02
INT02
General-purpose I/O port
High-current pin
A/D converter analog input pin
AN01
14
General-purpose I/O port
High-current pin
8/16-bit composite timer ch. 1 clock input pin
AN00
13
General-purpose I/O port
High-current pin
8/16-bit composite timer ch. 1 output pin
EC1
12
General-purpose I/O port
High-current pin
8/16-bit composite timer ch. 1 output pin
TO11
11
Reset pin
Dedicated reset pin in MB95F562H/F563H/F564H
D
External interrupt input pin
AN02
A/D converter analog input pin
SCK
LIN-UART clock I/O pin
P03
General-purpose I/O port
High-current pin
INT03
D
External interrupt input pin
AN03
A/D converter analog input pin
SOT
LIN-UART data output pin
(Continued)
14
DS702-00003-1v0-E
MB95560H/570H/580H Series
(Continued)
Pin no.
16
17
Pin name
I/O
circuit
type*
P04
General-purpose I/O port
INT04
External interrupt input pin
AN04
D
LIN-UART data input pin
EC0
8/16-bit composite timer ch. 0 clock input pin
P05
General-purpose I/O port
High-current pin
INT05
D
20
External interrupt input pin
AN05
A/D converter analog input pin
TO00
8/16-bit composite timer ch. 0 output pin
General-purpose I/O port
High-current pin
INT06
E
TO01
19
A/D converter analog input pin
SIN
P06
18
Function
P07
External interrupt input pin
8/16-bit composite timer ch. 0 output pin
E
General-purpose I/O port
High-current pin
INT07
External interrupt input pin
P12
General-purpose I/O port
EC0
DBG
F
8/16-bit composite timer ch. 0 clock input pin
DBG input pin
*: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”.
DS702-00003-1v0-E
15
MB95560H/570H/580H Series
■ PIN FUNCTIONS (MB95570H Series, 8 pins)
s
Pin no.
Pin name
I/O
circuit
type*
1
VSS
—
Power supply pin (GND)
2
VCC
—
Power supply pin
3
C
—
Capacitor connection pin
PF2
4
RST
General-purpose I/O port
A
P04
5
6
INT04
AN04
D
External interrupt input pin
A/D converter analog input pin
EC0
8/16-bit composite timer ch. 0 clock input pin
P05
General-purpose I/O port
High-current pin
AN05
D
INT06
General-purpose I/O port
High-current pin
E
TO01
DBG
External interrupt input pin
8/16-bit composite timer ch. 0 output pin
P12
EC0
A/D converter analog input pin
8/16-bit composite timer ch. 0 output pin
P06
8
Reset pin
Dedicated reset pin in MB95F572H/F573H/F574H
General-purpose I/O port
TO00
7
Function
General-purpose I/O port
F
8/16-bit composite timer ch. 0 clock input pin
DBG input pin
*: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”.
16
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ PIN FUNCTIONS (MB95580H Series, 32 pins)
Pin no.
1
2
3
4
5
Pin name
PF1
X1
PF0
X0
VSS
PG2
X1A
PG1
X0A
I/O
circuit
type*
B
B
⎯
C
C
Function
General-purpose I/O port
Main clock I/O oscillation pin
General-purpose I/O port
Main clock input oscillation pin
Power supply pin (GND)
General-purpose I/O port
Subclock I/O oscillation pin
General-purpose I/O port
Subclock input oscillation pin
6
VCC
⎯
Power supply pin
7
C
⎯
Capacitor connection pin
PF2
8
RST
General-purpose I/O port
A
Reset pin
Dedicated reset pin in MB95F582H/F583H/F584H
9
NC
⎯
It is an internally connected pin. Always leave it unconnected.
10
NC
⎯
It is an internally connected pin. Always leave it unconnected.
11
NC
⎯
It is an internally connected pin. Always leave it unconnected.
12
NC
⎯
It is an internally connected pin. Always leave it unconnected.
13
NC
⎯
It is an internally connected pin. Always leave it unconnected.
14
NC
⎯
It is an internally connected pin. Always leave it unconnected.
15
NC
⎯
It is an internally connected pin. Always leave it unconnected.
16
NC
⎯
It is an internally connected pin. Always leave it unconnected.
D
General-purpose I/O port
High-current pin
17
P01
AN01
A/D converter analog input pin
General-purpose I/O port
High-current pin
P02
18
19
INT02
D
External interrupt input pin
AN02
A/D converter analog input pin
SCK
LIN-UART clock I/O pin
P03
General-purpose I/O port
High-current pin
INT03
D
External interrupt input pin
AN03
A/D converter analog input pin
SOT
LIN-UART data output pin
(Continued)
DS702-00003-1v0-E
17
MB95560H/570H/580H Series
(Continued)
Pin no.
20
21
Pin name
I/O
circuit
type*
P04
General-purpose I/O port
INT04
External interrupt input pin
AN04
D
LIN-UART data input pin
EC0
8/16-bit composite timer ch. 0 clock input pin
P05
General-purpose I/O port
High-current pin
INT05
D
A/D converter analog input pin
TO00
8/16-bit composite timer ch. 0 output pin
General-purpose I/O port
High-current pin
INT06
E
EC0
External interrupt input pin
8/16-bit composite timer ch. 0 output pin
P12
24
External interrupt input pin
AN05
TO01
23
A/D converter analog input pin
SIN
P06
22
Function
General-purpose I/O port
F
8/16-bit composite timer ch. 0 clock input pin
DBG
DBG input pin
P07
General-purpose I/O port
High-current pin
E
INT07
External interrupt input pin
25
NC
⎯
It is an internally connected pin. Always leave it unconnected.
26
NC
⎯
It is an internally connected pin. Always leave it unconnected.
27
NC
⎯
It is an internally connected pin. Always leave it unconnected.
28
NC
⎯
It is an internally connected pin. Always leave it unconnected.
29
NC
⎯
It is an internally connected pin. Always leave it unconnected.
30
NC
⎯
It is an internally connected pin. Always leave it unconnected.
31
NC
⎯
It is an internally connected pin. Always leave it unconnected.
32
NC
⎯
It is an internally connected pin. Always leave it unconnected.
*: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”.
18
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ PIN FUNCTIONS (MB95580H Series, 16 pins)
Pin no.
1
2
3
4
5
6
Pin name
PF0
X0
PF1
X1
VSS
PG2
X1A
PG1
X0A
VCC
I/O
circuit
type*
B
B
—
C
C
—
PF2
7
8
RST
C
10
INT02
General-purpose I/O port
Main clock I/O oscillation pin
Power supply pin (GND)
General-purpose I/O port
Subclock I/O oscillation pin
General-purpose I/O port
Subclock input oscillation pin
Power supply pin
Reset pin
Dedicated reset pin in MB95F582H/F583H/F584H
—
Capacitor connection pin
General-purpose I/O port
High-current pin
D
External interrupt input pin
AN02
A/D converter analog input pin
SCK
LIN-UART clock I/O pin
P01
D
INT03
General-purpose I/O port
High-current pin
A/D converter analog input pin
General-purpose I/O port
High-current pin
P03
12
Main clock input oscillation pin
General-purpose I/O port
AN01
11
General-purpose I/O port
A
P02
9
Function
D
External interrupt input pin
AN03
A/D converter analog input pin
SOT
LIN-UART data output pin
P04
General-purpose I/O port
INT04
External interrupt input pin
AN04
D
A/D converter analog input pin
SIN
LIN-UART data input pin
EC0
8/16-bit composite timer ch. 0 clock input pin
(Continued)
DS702-00003-1v0-E
19
MB95560H/570H/580H Series
(Continued)
Pin no.
Pin name
I/O
circuit
type*
General-purpose I/O port
High-current pin
P05
13
INT05
D
A/D converter analog input pin
TO00
8/16-bit composite timer ch. 0 clock input pin
General-purpose I/O port
High-current pin
INT06
E
TO01
15
16
External interrupt input pin
AN05
P06
14
Function
P07
External interrupt input pin
8/16-bit composite timer ch. 0 clock input pin
E
General-purpose I/O port
High-current pin
INT07
External interrupt input pin
P12
General-purpose I/O port
EC0
DBG
F
8/16-bit composite timer ch. 0 clock input pin
DBG input pin
*: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”.
20
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ I/O CIRCUIT TYPE
Type
Circuit
A
Remarks
Reset input / Hysteresis input
Reset output / Digital output
• N-ch open drain output
• Hysteresis input
• Reset output
N-ch
B
P-ch
Port select
Digital output
N-ch
Digital output
Standby control
Hysteresis input
Clock input
• Oscillation circuit
• High-speed side
Feedback resistance:
approx. 1 MΩ
• CMOS output
• Hysteresis input
X1
X0
Standby control / Port select
P-ch
Port select
Digital output
N-ch
Digital output
Standby control
Hysteresis input
C
Port select
R
Pull-up control
P-ch
• Oscillation circuit
• Low-speed side
Feedback resistance:
approx.10 MΩ
Digital output
P-ch
N-ch
Digital output
Standby control
Hysteresis input
• CMOS output
• Hysteresis input
• Pull-up control available
Clock input
X1A
X0A
Standby control / Port select
Port select
R
Pull-up control
Digital output
Digital output
P-ch
N-ch
Digital output
Standby control
Hysteresis input
(Continued)
DS702-00003-1v0-E
21
MB95560H/570H/580H Series
(Continued)
Type
Circuit
Remarks
D
Pull-up control
R
P-ch
Digital output
P-ch
•
•
•
•
CMOS output
Hysteresis input
Pull-up control available
Analog input
Digital output
N-ch
Analog input
A/D control
Standby control
Hysteresis input
E
Pull-up control
R
P-ch
• CMOS output
• Hysteresis input
• Pull-up control available
Digital output
P-ch
Digital output
N-ch
Standby control
Hysteresis input
F
Standby control
Hysteresis input
• N-ch open drain output
• Hysteresis input
Digital output
N-ch
22
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ NOTES ON DEVICE HANDLING
• Preventing latch-ups
When using the device, ensure that the voltage applied does not exceed the maximum voltage rating.
In a CMOS IC, if a voltage higher than VCC or a voltage lower than VSS is applied to an input/output pin that
is neither a medium-withstand voltage pin nor a high-withstand voltage pin, or if a voltage out of the rating
range of power supply voltage mentioned in "1. Absolute Maximum Ratings" of "■ ELECTRICAL
CHARACTERISTICS" is applied to the VCC pin or the VSS pin, a latch-up may occur.
When a latch-up occurs, power supply current increases significantly, which may cause a component to be
thermally destroyed.
• Stabilizing supply voltage
Supply voltage must be stabilized.
A malfunction may occur when power supply voltage fluctuates rapidly even though the fluctuation is within
the guaranteed operating range of the VCC power supply voltage.
As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (p-p value)
at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient
fluctuation rate does not exceed 0.1 V/ms at a momentary fluctuation such as switching the power supply.
• Notes on using the external clock
When an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up
from subclock mode or stop mode.
■ PIN CONNECTION
• Treatment of unused pins
If an unused input pin is left unconnected, a component may be permanently damaged due to malfunctions
or latch-ups. Always pull up or pull down an unused input pin through a resistor of at least 2 kΩ. Set an
unused input/output pin to the output state and leave it unconnected, or set it to the input state and treat it
the same as an unused input pin. If there is an unused output pin, leave it unconnected.
• Power supply pins
To reduce unnecessary electro-magnetic emission, prevent malfunctions of strobe signals due to an increase
in the ground level, and conform to the total output current standard, always connect the VCC pin and the VSS
pin to the power supply and ground outside the device. In addition, connect the current supply source to the
VCC pin and the VSS pin with low impedance.
It is also advisable to connect a ceramic capacitor of approximately 0.1 µF as a bypass capacitor between
the VCC pin and the VSS pin at a location close to this device.
• DBG pin
Connect the DBG pin directly to an external pull-up resistor.
To prevent the device from unintentionally entering the debug mode due to noise, minimize the distance
between the DBG pin and the VCC or VSS pin when designing the layout of the printed circuit board.
The DBG pin should not stay at “L” level after power-on until the reset output is released.
• RST pin
Connect the RST pin directly to an external pull-up resistor.
To prevent the device from unintentionally entering the reset mode due to noise, minimize the distance
between the RST pin and the VCC or VSS pin when designing the layout of the printed circuit board.
The RST/PF2 pin functions as the reset input/output pin after power-on. In addition, the reset output of the
RST/PF2 pin can be enabled by the RSTOE bit in the SYSC register, and the reset input function and the
general purpose I/O function can be selected by the RSTEN bit in the SYSC register.
DS702-00003-1v0-E
23
MB95560H/570H/580H Series
• C pin
Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The bypass capacitor for
the VCC pin must have a capacitance larger than CS. For the connection to a smoothing capacitor CS, see
the diagram below. To prevent the device from unintentionally entering a mode to which the device is not set
to transit due to noise, minimize the distance between the C pin and CS and the distance between CS and
the VSS pin when designing the layout of a printed circuit board.
• DBG/RST/C pins connection diagram
DBG
C
RST
Cs
24
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ BLOCK DIAGRAM (MB95560H Series)
New-8FX CPU
PF2*1/RST*2
Dual operation Flash with
security function
(8/12/20 Kbyte)
Reset with LVD
PF1/X1*2
PF0/X0*2
PG2/X1A*2
Oscillator
circuit
CR
oscillator
RAM (240/496 bytes)
PG1/X0A*2
Interrupt controller
Clock control
On-chip debug
Wild register
P02*3/INT02 to P07*3/INT07
Internal bus
(P12*1/DBG)
(P05*3/TO00)
8/16-bit composite timer ch. 0
(P06*3/TO01)
P12*1/EC0, (P04/EC0)
8/10-bit A/D converter
(P00*3/AN00 to P05*3/AN05)
External interrupt
(P62*3/TO10)
(P02*3/SCK)
(P03*3/SOT)
8/16-bit composite timer ch. 1
LIN-UART
(P63*3/TO11)
P64*3/EC1
(P04/SIN)
C
Port
Vcc
*1: PF2 and P12 are N-ch open drain pins.
Vss
*2: Software option
Port
*3: P00 to P03, P05 to P07 and P62 to P64 are high-current pins.
Note: Pins in parentheses indicate that functions of those pins are shared among different resources.
DS702-00003-1v0-E
25
MB95560H/570H/580H Series
■ BLOCK DIAGRAM (MB95570H Series)
New-8FX CPU
PF2*1/RST*2
Dual operation Flash with
security function
(8/12/20 Kbyte)
Reset with LVD
RAM (240/496 bytes)
CR oscillator
Clock control
(P12*1/DBG)
On-chip debug
Internal bus
Interrupt controller
(P05*3/TO00)
8/16-bit composite timer ch. 0
(P06*3/TO01)
P12*1/EC0, (P04/EC0)
Wild register
8/10-bit A/D converter
P04/INT04, P06*3/INT06
P05*3/AN05, (P04/AN04)
External interrupt
C
Port
Vcc
*1: PF2 and P12 are N-ch open drain pins.
Vss
*2: Software option
Port
*3: P05 and P06 are high-current pins.
Note: Pins in parentheses indicate that functions of those pins are shared among different resources.
26
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ BLOCK DIAGRAM (MB95580H Series)
New-8FX CPU
PF2*1/RST*2
Dual operation Flash with
security function
(8/12/20 Kbyte)
Reset with LVD
PF1/X1*2
PF0/X0*2
PG2/X1A*2
Oscillator
circuit
CR
oscillator
RAM (240/496 bytes)
PG1/X0A*2
Interrupt controller
Clock control
On-chip debug
Wild register
P02*3/INT02 to P07*3/INT07
Internal bus
(P12*1/DBG)
(P05*3/TO00)
8/16-bit composite timer ch. 0
(P06*3/TO01)
P12*1/EC0, (P04/EC0)
8/10-bit A/D converter
(P01*3/AN01 to P05*3/AN05)
External interrupt
(P02*3/SCK)
(P03*3/SOT)
LIN-UART
(P04/SIN)
C
Port
Vcc
*1: PF2 and P12 are N-ch open drain pins.
Vss
*2: Software option
Port
*3: P01 to P03 and P05 to P07 are high-current pins.
Note: Pins in parentheses indicate that functions of those pins are shared among different resources.
DS702-00003-1v0-E
27
MB95560H/570H/580H Series
■ CPU CORE
• Memory Space
The memory space of the MB95560H/570H/580H Series is 64 Kbyte in size, and consists of an I/O area, a
data area, and a program area. The memory space includes areas intended for specific purposes such as
general-purpose registers and a vector table. The memory maps of the MB95560H/570H/580H Series are
shown below.
• Memory Maps
MB95F562H/F562K/F572H/
F572K/F582H/F582K
MB95F563H/F563K/F573H/
F573K/F583H/F583K
0000H
0000H
0000H
I/O
0080H
0090H
0100H
0180H
Access prohibited
RAM 240 bytes
Register
Access prohibited
0F80H
I/O
0080H
0090H
0100H
Extension I/O
C000H
Flash 4 Kbyte
Access prohibited
F000H
FFFFH
28
Access prohibited
Flash 4 Kbyte
I/O
0080H
0090H
0100H
0F80H
C000H
Access prohibited
Extension I/O
1000H
Access prohibited
B000H
Access prohibited
RAM 496 bytes
Register
0200H
0280H
Extension I/O
1000H
Access prohibited
B000H
Access prohibited
RAM 496 bytes
Register
0200H
0280H
0F80H
1000H
MB95F564H/F564K/F574H/
F574K/F584H/F584K
Flash 4 Kbyte
Access prohibited
B000H
Access prohibited
Flash 20 Kbyte
E000H
Flash 8 Kbyte
FFFFH
FFFFH
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ I/O MAP (MB95560H Series)
Address
Register
abbreviation
0000H
PDR0
Port 0 data register
R/W
00000000B
0001H
DDR0
Port 0 direction register
R/W
00000000B
0002H
PDR1
Port 1 data register
R/W
00000000B
0003H
DDR1
Port 1 direction register
R/W
00000000B
0004H
—
—
—
0005H
WATR
Oscillation stabilization wait time setting register
R/W
11111111B
0006H
PLLC
PLL control register
R/W
00000000B
0007H
SYCC
System clock control register
R/W
XXX11011B
0008H
STBC
Standby control register
R/W
00000000B
0009H
RSRR
Reset source register
R/W XXXXXXXXB
000AH
TBTC
Time-base timer control register
R/W
00000000B
000BH
WPCR
Watch prescaler control register
R/W
00000000B
000CH
WDTC
Watchdog timer control register
R/W
00XX0000B
000DH
SYCC2
System clock control register 2
R/W XXXX0011B
000EH
STBC2
Standby control register 2
R/W
00000000B
000FH
to
0015H
—
—
—
0016H
PDR6
Port 6 data register
R/W
00000000B
0017H
DDR6
Port 6 direction register
R/W
00000000B
0018H
to
0027H
—
—
—
0028H
PDRF
Port F data register
R/W
00000000B
0029H
DDRF
Port F direction register
R/W
00000000B
002AH
PDRG
Port G data register
R/W
00000000B
002BH
DDRG
Port G direction register
R/W
00000000B
002CH
PUL0
Port 0 pull-up register
R/W
00000000B
002DH
to
0032H
—
—
—
0033H
PUL6
R/W
00000000B
0034H
—
—
—
0035H
PULG
Port G pull-up register
R/W
00000000B
0036H
T01CR1
8/16-bit composite timer 01 status control register 1
R/W
00000000B
0037H
T00CR1
8/16-bit composite timer 00 status control register 1
R/W
00000000B
0038H
T11CR1
8/16-bit composite timer 11 status control register 1
R/W
00000000B
0039H
T10CR1
8/16-bit composite timer 10 status control register 1
R/W
00000000B
003AH
to
0048H
—
—
—
Register name
(Disabled)
(Disabled)
(Disabled)
(Disabled)
Port 6 pull-up register
(Disabled)
(Disabled)
R/W Initial value
(Continued)
DS702-00003-1v0-E
29
MB95560H/570H/580H Series
Address
Register
abbreviation
0049H
EIC10
External interrupt circuit control register ch. 2/ch. 3
R/W
00000000B
004AH
EIC20
External interrupt circuit control register ch. 4/ch. 5
R/W
00000000B
004BH
EIC30
External interrupt circuit control register ch. 6/ch. 7
R/W
00000000B
004CH,
004DH
—
—
—
004EH
LVDR
R/W
00000000B
004FH
—
—
—
0050H
SCR
LIN-UART serial control register
R/W
00000000B
0051H
SMR
LIN-UART serial mode register
R/W
00000000B
0052H
SSR
LIN-UART serial status register
R/W
00001000B
0053H
RDR/TDR
LIN-UART receive/transmit data register
R/W
00000000B
0054H
ESCR
LIN-UART extended status control register
R/W
00000100B
0055H
ECCR
LIN-UART extended communication control register
R/W
000000XXB
0056H
to
006BH
—
—
—
006CH
ADC1
8/10-bit A/D converter control register 1
R/W
00000000B
006DH
ADC2
8/10-bit A/D converter control register 2
R/W
00000000B
006EH
ADDH
8/10-bit A/D converter data register upper
R/W
00000000B
006FH
ADDL
8/10-bit A/D converter data register lower
R/W
00000000B
0070H
—
—
—
0071H
FSR2
Flash memory status register 2
R/W
00000000B
0072H
FSR
Flash memory status register
R/W
000X0000B
0073H
SWRE0
Flash memory sector write control register 0
R/W
00000000B
0074H
FSR3
Flash memory status register 3
R
000XXXXXB
0075H
FSR4
Flash memory status register 4
R/W
00000000B
0076H
WREN
Wild register address compare enable register
R/W
00000000B
0077H
WROR
Wild register data test setting register
R/W
00000000B
0078H
—
—
—
0079H
ILR0
Interrupt level setting register 0
R/W
11111111B
007AH
ILR1
Interrupt level setting register 1
R/W
11111111B
007BH
ILR2
Interrupt level setting register 2
R/W
11111111B
007CH
ILR3
Interrupt level setting register 3
R/W
11111111B
007DH
ILR4
Interrupt level setting register 4
R/W
11111111B
007EH
ILR5
Interrupt level setting register 5
R/W
11111111B
007FH
—
—
—
0F80H
WRARH0
Wild register address setting register (upper) ch. 0
R/W
00000000B
0F81H
WRARL0
Wild register address setting register (lower) ch. 0
R/W
00000000B
0F82H
WRDR0
Wild register data setting register ch. 0
R/W
00000000B
Register name
(Disabled)
LVDR reset voltage selection ID register
(Disabled)
(Disabled)
(Disabled)
Mirror of register bank pointer (RP) and direct bank pointer
(DP)
(Disabled)
R/W Initial value
(Continued)
30
DS702-00003-1v0-E
MB95560H/570H/580H Series
Address
Register
abbreviation
0F83H
WRARH1
Wild register address setting register (upper) ch. 1
R/W
00000000B
0F84H
WRARL1
Wild register address setting register (lower) ch. 1
R/W
00000000B
0F85H
WRDR1
Wild register data setting register ch. 1
R/W
00000000B
0F86H
WRARH2
Wild register address setting register (upper) ch. 2
R/W
00000000B
0F87H
WRARL2
Wild register address setting register (lower) ch. 2
R/W
00000000B
0F88H
WRDR2
Wild register data setting register ch. 2
R/W
00000000B
0F89H
to
0F91H
—
—
—
0F92H
T01CR0
8/16-bit composite timer 01 status control register 0
R/W
00000000B
0F93H
T00CR0
8/16-bit composite timer 00 status control register 0
R/W
00000000B
0F94H
T01DR
8/16-bit composite timer 01 data register
R/W
00000000B
0F95H
T00DR
8/16-bit composite timer 00 data register
R/W
00000000B
0F96H
TMCR0
8/16-bit composite timer 00/01 timer mode control register
R/W
00000000B
0F97H
T11CR0
8/16-bit composite timer 11 status control register 0
R/W
00000000B
0F98H
T10CR0
8/16-bit composite timer 10 status control register 0
R/W
00000000B
0F99H
T11DR
8/16-bit composite timer 11 data register
R/W
00000000B
0F9AH
T10DR
8/16-bit composite timer 10 data register
R/W
00000000B
0F9BH
TMCR1
8/16-bit composite timer 10/11 timer mode control register
R/W
00000000B
0F9CH
to
0FBBH
—
—
—
0FBCH
BGR1
LIN-UART baud rate generator register 1
R/W
00000000B
0FBDH
BGR0
LIN-UART baud rate generator register 0
R/W
00000000B
0FBEH
to
0FC2H
—
—
—
0FC3H
AIDRL
R/W
00000000B
0FC4H
to
0FE3H
—
—
—
0FE4H
CRTH
Main CR clock trimming register (upper)
R/W 000XXXXXB
0FE5H
CRTL
Main CR clock trimming register (lower)
R/W 000XXXXXB
0FE6H
—
0FE7H
CRTDA
0FE8H
Register name
(Disabled)
(Disabled)
(Disabled)
A/D input disable register (Lower)
(Disabled)
(Disabled)
R/W Initial value
—
—
Main CR clock temperature dependent adjustment register
R/W
00011111B
SYSC
System configuration register
R/W
11000011B
0FE9H
CMCR
Clock monitoring control register
R/W
00000000B
0FEAH
CMDR
Clock monitoring data register
R/W
00000000B
(Continued)
DS702-00003-1v0-E
31
MB95560H/570H/580H Series
(Continued)
Address
Register
abbreviation
0FEBH
WDTH
Watchdog timer selection ID register (upper)
R/W XXXXXXXXB
0FECH
WDTL
Watchdog timer selection ID register (lower)
R/W XXXXXXXXB
0FEDH
to
0FFFH
—
Register name
(Disabled)
R/W Initial value
—
—
• R/W access symbols
R/W : Readable / Writable
R
: Read only
• Initial value symbols
0
: The initial value of this bit is “0”.
1
: The initial value of this bit is “1”.
X
: The initial value of this bit is undefined.
Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value
is returned.
32
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ I/O MAP (MB95570H Series)
Address
Register
abbreviation
0000H
PDR0
Port 0 data register
R/W
00000000B
0001H
DDR0
Port 0 direction register
R/W
00000000B
0002H
PDR1
Port 1 data register
R/W
00000000B
0003H
DDR1
Port 1 direction register
R/W
00000000B
0004H
—
—
—
0005H
WATR
Oscillation stabilization wait time setting register
R/W
11111111B
0006H
PLLC
PLL control register
R/W
00000000B
0007H
SYCC
System clock control register
R/W
XXX11011B
0008H
STBC
Standby control register
R/W
00000000B
0009H
RSRR
Reset source register
R/W XXXXXXXXB
000AH
TBTC
Time-base timer control register
R/W
00000000B
000BH
WPCR
Watch prescaler control register
R/W
00000000B
000CH
WDTC
Watchdog timer control register
R/W
00XX0000B
000DH
SYCC2
System clock control register 2
R/W XXXX0011B
000EH
STBC2
Standby control register 2
R/W
00000000B
000FH
to
0027H
—
—
—
0028H
PDRF
Port F data register
R/W
00000000B
0029H
DDRF
Port F direction register
R/W
00000000B
002AH,
002BH
—
—
—
002CH
PUL0
R/W
00000000B
002DH
to
0032H
—
—
—
0033H
PUL6
R/W
00000000B
0034H,
0035H
—
—
—
0036H
T01CR1
8/16-bit composite timer 01 status control register 1
R/W
00000000B
0037H
T00CR1
8/16-bit composite timer 00 status control register 1
R/W
00000000B
0038H
to
0049H
—
—
—
004AH
EIC20
External interrupt circuit control register ch. 4
R/W
00000000B
004BH
EIC30
External interrupt circuit control register ch. 6
R/W
00000000B
004CH,
004DH
—
—
—
004EH
LVDR
R/W
00000000B
004FH
to
006BH
—
—
—
Register name
(Disabled)
(Disabled)
(Disabled)
Port 0 pull-up register
(Disabled)
Port 6 pull-up register
(Disabled)
(Disabled)
(Disabled)
LVDR reset voltage selection ID register
(Disabled)
R/W Initial value
(Continued)
DS702-00003-1v0-E
33
MB95560H/570H/580H Series
Address
Register
abbreviation
006CH
ADC1
8/10-bit A/D converter control register 1
R/W
00000000B
006DH
ADC2
8/10-bit A/D converter control register 2
R/W
00000000B
006EH
ADDH
8/10-bit A/D converter data register upper
R/W
00000000B
006FH
ADDL
8/10-bit A/D converter data register lower
R/W
00000000B
0070H
—
—
—
0071H
FSR2
Flash memory status register 2
R/W
00000000B
0072H
FSR
Flash memory status register
R/W
000X0000B
0073H
SWRE0
Flash memory sector write control register 0
R/W
00000000B
0074H
FSR3
Flash memory status register 3
R
000XXXXXB
0075H
FSR4
Flash memory status register 4
R/W
00000000B
0076H
WREN
Wild register address compare enable register
R/W
00000000B
0077H
WROR
Wild register data test setting register
R/W
00000000B
0078H
—
—
—
0079H
ILR0
Interrupt level setting register 0
R/W
11111111B
007AH
ILR1
Interrupt level setting register 1
R/W
11111111B
007BH,
007CH
—
—
—
007DH
ILR4
Interrupt level setting register 4
R/W
11111111B
007EH
ILR5
Interrupt level setting register 5
R/W
11111111B
007FH
—
—
—
0F80H
WRARH0
Wild register address setting register (upper) ch. 0
R/W
00000000B
0F81H
WRARL0
Wild register address setting register (lower) ch. 0
R/W
00000000B
0F82H
WRDR0
Wild register data setting register ch. 0
R/W
00000000B
0F83H
WRARH1
Wild register address setting register (upper) ch. 1
R/W
00000000B
0F84H
WRARL1
Wild register address setting register (lower) ch. 1
R/W
00000000B
0F85H
WRDR1
Wild register data setting register ch. 1
R/W
00000000B
0F86H
WRARH2
Wild register address setting register (upper) ch. 2
R/W
00000000B
0F87H
WRARL2
Wild register address setting register (lower) ch. 2
R/W
00000000B
0F88H
WRDR2
Wild register data setting register ch. 2
R/W
00000000B
0F89H
to
0F91H
—
—
—
0F92H
T01CR0
8/16-bit composite timer 01 status control register 0
R/W
00000000B
0F93H
T00CR0
8/16-bit composite timer 00 status control register 0
R/W
00000000B
0F94H
T01DR
8/16-bit composite timer 01 data register
R/W
00000000B
0F95H
T00DR
8/16-bit composite timer 00 data register
R/W
00000000B
0F96H
TMCR0
8/16-bit composite timer 00/01 timer mode control register
R/W
00000000B
0F97H
to
0FC2H
—
—
—
Register name
(Disabled)
Mirror of register bank pointer (RP) and direct bank pointer
(DP)
(Disabled)
(Disabled)
(Disabled)
(Disabled)
R/W Initial value
(Continued)
34
DS702-00003-1v0-E
MB95560H/570H/580H Series
(Continued)
Address
Register
abbreviation
0FC3H
AIDRL
0FC4H
to
0FE3H
—
0FE4H
CRTH
Main CR clock trimming register (upper)
R/W 000XXXXXB
0FE5H
CRTL
Main CR clock trimming register (lower)
R/W 000XXXXXB
0FE6H
—
0FE7H
CRTDA
0FE8H
Register name
A/D input disable register (lower)
(Disabled)
(Disabled)
R/W Initial value
R/W
00000000B
—
—
—
—
Main CR clock temperature dependent adjustment register
R/W
00011111B
SYSC
System configuration register
R/W
11000011B
0FE9H
CMCR
Clock monitoring control register
R/W
00000000B
0FEAH
CMDR
Clock monitoring data register
R/W
00000000B
0FEBH
WDTH
Watchdog timer selection ID register (upper)
R/W XXXXXXXXB
0FECH
WDTL
Watchdog timer selection ID register (lower)
R/W XXXXXXXXB
0FEDH
to
0FFFH
—
(Disabled)
—
—
• R/W access symbols
R/W : Readable / Writable
R
: Read only
• Initial value symbols
0
: The initial value of this bit is “0”.
1
: The initial value of this bit is “1”.
X
: The initial value of this bit is undefined.
Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value
is returned.
DS702-00003-1v0-E
35
MB95560H/570H/580H Series
■ I/O MAP (MB95580H Series)
Address
Register
abbreviation
0000H
PDR0
Port 0 data register
R/W
00000000B
0001H
DDR0
Port 0 direction register
R/W
00000000B
0002H
PDR1
Port 1 data register
R/W
00000000B
0003H
DDR1
Port 1 direction register
R/W
00000000B
0004H
—
—
—
0005H
WATR
Oscillation stabilization wait time setting register
R/W
11111111B
0006H
PLLC
PLL control register
R/W
00000000B
0007H
SYCC
System clock control register
R/W
XXX11011B
0008H
STBC
Standby control register
R/W
00000000B
0009H
RSRR
Reset source register
R/W XXXXXXXXB
000AH
TBTC
Time-base timer control register
R/W
00000000B
000BH
WPCR
Watch prescaler control register
R/W
00000000B
000CH
WDTC
Watchdog timer control register
R/W
00XX0000B
000DH
SYCC2
System clock control register 2
R/W XXXX0011B
000EH
STBC2
Standby control register 2
R/W
00000000B
000FH
to
0027H
—
—
—
0028H
PDRF
Port F data register
R/W
00000000B
0029H
DDRF
Port F direction register
R/W
00000000B
002AH
PDRG
Port G data register
R/W
00000000B
002BH
DDRG
Port G direction register
R/W
00000000B
002CH
PUL0
Port 0 pull-up register
R/W
00000000B
002DH
to
0032H
—
—
—
0033H
PUL6
R/W
00000000B
0034H
—
—
—
0035H
PULG
Port G pull-up register
R/W
00000000B
0036H
T01CR1
8/16-bit composite timer 01 status control register 1
R/W
00000000B
0037H
T00CR1
8/16-bit composite timer 00 status control register 1
R/W
00000000B
0038H
to
0048H
—
—
—
0049H
EIC10
External interrupt circuit control register ch. 2/ch. 3
R/W
00000000B
004AH
EIC20
External interrupt circuit control register ch. 4/ch. 5
R/W
00000000B
004BH
EIC30
External interrupt circuit control register ch. 6/ch. 7
R/W
00000000B
004CH,
004DH
—
—
—
004EH
LVDR
R/W
00000000B
004FH
—
—
—
Register name
(Disabled)
(Disabled)
(Disabled)
Port 6 pull-up register
(Disabled)
(Disabled)
(Disabled)
LVDR reset voltage selection ID register
(Disabled)
R/W Initial value
(Continued)
36
DS702-00003-1v0-E
MB95560H/570H/580H Series
Address
Register
abbreviation
0050H
SCR
LIN-UART serial control register
R/W
00000000B
0051H
SMR
LIN-UART serial mode register
R/W
00000000B
0052H
SSR
LIN-UART serial status register
R/W
00001000B
0053H
RDR/TDR
LIN-UART receive/transmit data register
R/W
00000000B
0054H
ESCR
LIN-UART extended status control register
R/W
00000100B
0055H
ECCR
LIN-UART extended communication control register
R/W
000000XXB
0056H
to
006BH
—
—
—
006CH
ADC1
8/10-bit A/D converter control register 1
R/W
00000000B
006DH
ADC2
8/10-bit A/D converter control register 2
R/W
00000000B
006EH
ADDH
8/10-bit A/D converter data register upper
R/W
00000000B
006FH
ADDL
8/10-bit A/D converter data register lower
R/W
00000000B
0070H
—
—
—
0071H
FSR2
Flash memory status register 2
R/W
00000000B
0072H
FSR
Flash memory status register
R/W
000X0000B
0073H
SWRE0
Flash memory sector write control register 0
R/W
00000000B
0074H
FSR3
Flash memory status register 3
R
000XXXXXB
0075H
FSR4
Flash memory status register 4
R/W
00000000B
0076H
WREN
Wild register address compare enable register
R/W
00000000B
0077H
WROR
Wild register data test setting register
R/W
00000000B
0078H
—
⎯
—
0079H
ILR0
Interrupt level setting register 0
R/W
11111111B
007AH
ILR1
Interrupt level setting register 1
R/W
11111111B
007BH
ILR2
Interrupt level setting register 2
R/W
11111111B
007CH
—
—
—
007DH
ILR4
Interrupt level setting register 4
R/W
11111111B
007EH
ILR5
Interrupt level setting register 5
R/W
11111111B
007FH
—
—
—
0F80H
WRARH0
Wild register address setting register (upper) ch. 0
R/W
00000000B
0F81H
WRARL0
Wild register address setting register (lower) ch. 0
R/W
00000000B
0F82H
WRDR0
Wild register data setting register ch. 0
R/W
00000000B
0F83H
WRARH1
Wild register address setting register (upper) ch. 1
R/W
00000000B
0F84H
WRARL1
Wild register address setting register (lower) ch. 1
R/W
00000000B
0F85H
WRDR1
Wild register data setting register ch. 1
R/W
00000000B
0F86H
WRARH2
Wild register address setting register (upper) ch. 2
R/W
00000000B
0F87H
WRARL2
Wild register address setting register (lower) ch. 2
R/W
00000000B
0F88H
WRDR2
Wild register data setting register ch. 2
R/W
00000000B
Register name
(Disabled)
(Disabled)
Mirror of register bank pointer (RP) and direct bank pointer
(DP)
(Disabled)
(Disabled)
R/W Initial value
(Continued)
DS702-00003-1v0-E
37
MB95560H/570H/580H Series
(Continued)
Address
Register
abbreviation
Register name
0F89H
to
0F91H
—
(Disabled)
0F92H
T01CR0
0F93H
R/W Initial value
—
—
8/16-bit composite timer 01 status control register 0
R/W
00000000B
T00CR0
8/16-bit composite timer 00 status control register 0
R/W
00000000B
0F94H
T01DR
8/16-bit composite timer 01 data register
R/W
00000000B
0F95H
T00DR
8/16-bit composite timer 00 data register
R/W
00000000B
0F96H
TMCR0
8/16-bit composite timer 00/01 timer mode control register
R/W
00000000B
0F97H
to
0FBBH
—
—
—
0FBCH
BGR1
LIN-UART baud rate generator register 1
R/W
00000000B
0FBDH
BGR0
LIN-UART baud rate generator register 0
R/W
00000000B
0FBEH
to
0FC2H
—
—
—
0FC3H
AIDRL
R/W
00000000B
0FC4H
to
0FE3H
—
—
—
0FE4H
CRTH
Main CR clock trimming register (upper)
R/W 000XXXXXB
0FE5H
CRTL
Main CR clock trimming register (lower)
R/W 000XXXXXB
0FE6H
—
0FE7H
CRTDA
0FE8H
(Disabled)
(Disabled)
A/D input disable register (Lower)
(Disabled)
(Disabled)
—
—
Main CR clock temperature dependent adjustment
R/W
00011111B
SYSC
System configuration register
R/W
11000011B
0FE9H
CMCR
Clock monitoring control register
R/W
00000000B
0FEAH
CMDR
Clock monitoring data register
R/W
00000000B
0FEBH
WDTH
Watchdog timer selection ID register (upper)
R/W XXXXXXXXB
0FECH
WDTL
Watchdog timer selection ID register (lower)
R/W XXXXXXXXB
0FEDH
to
0FFFH
—
(Disabled)
—
—
• R/W access symbols
R/W : Readable / Writable
R
: Read only
• Initial value symbols
0
: The initial value of this bit is “0”.
1
: The initial value of this bit is “1”.
X
: The initial value of this bit is undefined.
Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value
is returned.
38
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ INTERRUPT SOURCE TABLE (MB95560H Series)
Vector table address
Priority order of
Bit name of interrupt sources
interrupt level of the same level
(occurring
setting register
simultaneously)
Interrupt
request
number
Upper
Lower
External interrupt ch. 4
IRQ00
FFFAH
FFFBH
L00 [1:0]
External interrupt ch. 5
IRQ01
FFF8H
FFF9H
L01 [1:0]
IRQ02
FFF6H
FFF7H
L02 [1:0]
IRQ03
FFF4H
FFF5H
L03 [1:0]
IRQ04
FFF2H
FFF3H
L04 [1:0]
8/16-bit composite timer ch. 0
(lower)
IRQ05
FFF0H
FFF1H
L05 [1:0]
8/16-bit composite timer ch. 0
(upper)
IRQ06
FFEEH
FFEFH
L06 [1:0]
LIN-UART (reception)
IRQ07
FFECH
FFEDH
L07 [1:0]
LIN-UART (transmission)
IRQ08
FFEAH
FFEBH
L08 [1:0]
—
IRQ09
FFE8H
FFE9H
L09 [1:0]
—
IRQ10
FFE6H
FFE7H
L10 [1:0]
—
IRQ11
FFE4H
FFE5H
L11 [1:0]
—
IRQ12
FFE2H
FFE3H
L12 [1:0]
—
IRQ13
FFE0H
FFE1H
L13 [1:0]
IRQ14
FFDEH
FFDFH
L14 [1:0]
—
IRQ15
FFDCH
FFDDH
L15 [1:0]
—
IRQ16
FFDAH
FFDBH
L16 [1:0]
—
IRQ17
FFD8H
FFD9H
L17 [1:0]
8/10-bit A/D converter
IRQ18
FFD6H
FFD7H
L18 [1:0]
Time-base timer
IRQ19
FFD4H
FFD5H
L19 [1:0]
Watch prescaler
IRQ20
FFD2H
FFD3H
L20 [1:0]
IRQ21
FFD0H
FFD1H
L21 [1:0]
8/16-bit composite timer ch. 1
(lower)
IRQ22
FFCEH
FFCFH
L22 [1:0]
Flash memory
IRQ23
FFCCH
FFCDH
L23 [1:0]
Interrupt source
External interrupt ch. 2
External interrupt ch. 6
External interrupt ch. 3
External interrupt ch. 7
—
8/16-bit composite timer ch. 1
(upper)
—
DS702-00003-1v0-E
High
Low
39
MB95560H/570H/580H Series
■ INTERRUPT SOURCE TABLE (MB95570H Series)
Vector table address
Priority order of
Bit name of interrupt sources
interrupt level of the same level
(occurring
setting register
simultaneously)
Interrupt
request
number
Upper
Lower
IRQ00
FFFAH
FFFBH
L00 [1:0]
IRQ01
FFF8H
FFF9H
L01 [1:0]
IRQ02
FFF6H
FFF7H
L02 [1:0]
IRQ03
FFF4H
FFF5H
L03 [1:0]
IRQ04
FFF2H
FFF3H
L04 [1:0]
8/16-bit composite timer ch. 0
(lower)
IRQ05
FFF0H
FFF1H
L05 [1:0]
8/16-bit composite timer ch. 0
(upper)
IRQ06
FFEEH
FFEFH
L06 [1:0]
—
IRQ07
FFECH
FFEDH
L07 [1:0]
—
IRQ08
FFEAH
FFEBH
L08 [1:0]
—
IRQ09
FFE8H
FFE9H
L09 [1:0]
—
IRQ10
FFE6H
FFE7H
L10 [1:0]
—
IRQ11
FFE4H
FFE5H
L11 [1:0]
—
IRQ12
FFE2H
FFE3H
L12 [1:0]
—
IRQ13
FFE0H
FFE1H
L13 [1:0]
—
IRQ14
FFDEH
FFDFH
L14 [1:0]
—
IRQ15
FFDCH
FFDDH
L15 [1:0]
—
IRQ16
FFDAH
FFDBH
L16 [1:0]
—
IRQ17
FFD8H
FFD9H
L17 [1:0]
8/10-bit A/D converter
IRQ18
FFD6H
FFD7H
L18 [1:0]
Time-base timer
IRQ19
FFD4H
FFD5H
L19 [1:0]
Watch prescaler
IRQ20
FFD2H
FFD3H
L20 [1:0]
—
IRQ21
FFD0H
FFD1H
L21 [1:0]
—
IRQ22
FFCEH
FFCFH
L22 [1:0]
IRQ23
FFCCH
FFCDH
L23 [1:0]
Interrupt source
External interrupt ch. 4
—
—
External interrupt ch. 6
—
—
—
Flash memory
40
High
Low
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ INTERRUPT SOURCE TABLE (MB95580H Series)
Vector table address
Priority order of
Bit name of interrupt sources
interrupt level of the same level
(occurring
setting register
simultaneously)
Interrupt
request
number
Upper
Lower
External interrupt ch. 4
IRQ00
FFFAH
FFFBH
L00 [1:0]
External interrupt ch. 5
IRQ01
FFF8H
FFF9H
L01 [1:0]
IRQ02
FFF6H
FFF7H
L02 [1:0]
IRQ03
FFF4H
FFF5H
L03 [1:0]
IRQ04
FFF2H
FFF3H
L04 [1:0]
8/16-bit composite timer ch. 0
(lower)
IRQ05
FFF0H
FFF1H
L05 [1:0]
8/16-bit composite timer ch. 0
(upper)
IRQ06
FFEEH
FFEFH
L06 [1:0]
LIN-UART (reception)
IRQ07
FFECH
FFEDH
L07 [1:0]
LIN-UART (transmission)
IRQ08
FFEAH
FFEBH
L08 [1:0]
—
IRQ09
FFE8H
FFE9H
L09 [1:0]
—
IRQ10
FFE6H
FFE7H
L10 [1:0]
—
IRQ11
FFE4H
FFE5H
L11 [1:0]
—
IRQ12
FFE2H
FFE3H
L12 [1:0]
—
IRQ13
FFE0H
FFE1H
L13 [1:0]
—
IRQ14
FFDEH
FFDFH
L14 [1:0]
—
IRQ15
FFDCH
FFDDH
L15 [1:0]
—
IRQ16
FFDAH
FFDBH
L16 [1:0]
—
IRQ17
FFD8H
FFD9H
L17 [1:0]
8/10-bit A/D converter
IRQ18
FFD6H
FFD7H
L18 [1:0]
Time-base timer
IRQ19
FFD4H
FFD5H
L19 [1:0]
Watch prescaler
IRQ20
FFD2H
FFD3H
L20 [1:0]
—
IRQ21
FFD0H
FFD1H
L21 [1:0]
—
IRQ22
FFCEH
FFCFH
L22 [1:0]
IRQ23
FFCCH
FFCDH
L23 [1:0]
Interrupt source
External interrupt ch. 2
External interrupt ch. 6
External interrupt ch. 3
External interrupt ch. 7
—
Flash memory
DS702-00003-1v0-E
High
Low
41
MB95560H/570H/580H Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Symbol
Power supply voltage*1
1
Input voltage*
Output voltage*
1
Maximum clamp current
Total maximum clamp
current
“L” level maximum
output current
Rating
VCC
VSS − 0.3
VSS + 6
V
VI
VSS − 0.3
VSS + 6
V
*2
VO
VSS − 0.3
VSS + 6
V
*2
ICLAMP
−2
+2
mA
Applicable to specific pins*3
Σ|ICLAMP|
—
20
mA
Applicable to specific pins*3
IOL1
IOL2
“L” level average current
—
“H” level maximum
output current
15
—
mA
mA
12
ΣIOL
—
48
mA
ΣIOLAV
—
50
mA
IOH1
IOH2
—
“H” level average
current
− 15
− 15
mA
−4
IOHAV1
—
mA
−8
IOHAV2
“H” level total maximum
output current
15
4
IOLAV2
“L” level total average
output current
ΣIOH
—
48
mA
ΣIOHAV
—
− 50
mA
Power consumption
Pd
—
320
mW
Operating temperature
TA
− 40
+ 85
°C
Tstg
− 55
+ 150
°C
“H” level total average
output current
Storage temperature
Remarks
Max
IOLAV1
“L” level total maximum
output current
Unit
Min
Other than P05, P06, P62 and P63*4
P05, P06, P62 and P63*4
Other than P05, P06, P62 and P63*4
Average output current=
operating current × operating ratio
(1 pin)
P05, P06, P62 and P63*4
Average output current=
operating current × operating ratio
(1 pin)
Total average output current=
operating current × operating ratio
(Total number of pins)
Other than P05, P06, P62 and P63*4
P05, P06, P62 and P63*4
Other than P05, P06, P62 and P63*4
Average output current=
operating current × operating ratio
(1 pin)
P05, P06, P62 and P63*4
Average output current=
operating current × operating ratio
(1 pin)
Total average output current=
operating current × operating ratio
(Total number of pins)
(Continued)
42
DS702-00003-1v0-E
MB95560H/570H/580H Series
(Continued)
*1: The parameter is based on VSS = 0.0 V.
*2: VI and VO must not exceed VCC + 0.3 V. VI must not exceed the rated voltage. However, if the maximum
current to/from an input is limited by means of an external component, the ICLAMP rating is used instead of
the VI rating.
*3: Applicable to the following pins: P00 to P07, P62 to P64, PF0, PF1, PG1, PG2 (P00, and P62 to P64 are
only available on MB95F562H/F562K/F563H/F563K/F564H/F564K. P01, P02, P03, P07, PF0. PF1, PG1
and PG2 are only available on MB95F562H/F562K/F563H/F563K/F564H/F564K/F582H/F582K/F583H/
F583K/F584H/F584K.)
• Use under recommended operating conditions.
• Use with DC voltage (current).
• The HV (High Voltage) signal is an input signal exceeding the VCC voltage. Always connect a limiting resistor
between the HV (High Voltage) signal and the microcontroller before applying the HV (High Voltage) signal.
• The value of the limiting resistor should be set to a value at which the current to be input to the microcontroller
pin when the HV (High Voltage) signal is input is below the standard value, irrespective of whether the
current is transient current or stationary current.
• When the microcontroller drive current is low, such as in low power consumption modes, the HV (High
Voltage) input potential may pass through the protective diode to increase the potential of the VCC pin,
affecting other devices.
• If the HV (High Voltage) signal is input when the microcontroller power supply is off (not fixed at 0 V), since
power is supplied from the pins, incomplete operations may be executed.
• If the HV (High Voltage) input is input after power-on, since power is supplied from the pins, the voltage
of power supply may not be sufficient to enable a power-on reset.
• Do not leave the HV (High Voltage) input pin unconnected.
• Example of a recommended circuit:
• Input/Output equivalent circuit
Protective diode
VCC
P-ch
Limiting
resistor
HV(High Voltage) input (0 V to 16 V)
N-ch
R
*4: P62 and P63 are only available on MB95F562H/F562K/F563H/F563K/F564H/F564K.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
DS702-00003-1v0-E
43
MB95560H/570H/580H Series
2. Recommended Operating Conditions
(VSS = 0.0 V)
Parameter
Symbol
Power supply
voltage
VCC
Smoothing
capacitor
CS
Operating
temperature
TA
Value
Min
Max
2.4*1*2
5.5*1
2.3
5.5
2.9
5.5
2.3
5.5
0.022
1
− 40
+ 85
+5
+ 35
Unit
Remarks
In normal operation
Other than on-chip debug
Hold condition in stop mode mode
V
In normal operation
Hold condition in stop mode
On-chip debug mode
µF *3
°C
Other than on-chip debug mode
On-chip debug mode
*1: The value varies depending on the operating frequency, the machine clock and the analog guaranteed range.
*2: The value is 2.88 V when the low-voltage detection reset is used.
*3: Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The bypass capacitor for
the VCC pin must have a capacitance larger than CS. For the connection to a smoothing capacitor CS, see
the diagram below. To prevent the device from unintentionally entering an unknown mode due to noise,
minimize the distance between the C pin and CS and the distance between CS and the VSS pin when designing
the layout of a printed circuit board.
• DBG / RST / C pins connection diagram
*
DBG
C
RST
Cs
*: Since the DBG pin becomes a communication pin in on-chip debug mode,
set a pull-up resistor value suiting the input/output specifications of P12/EC0/DBG.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
44
DS702-00003-1v0-E
MB95560H/570H/580H Series
3. DC Characteristics
(VCC = 5.0 V ± 10%, VSS = 0.0 V, TA = − 40°C to + 85°C)
Parameter Symbol
Pin name
“H” level
output
voltage
“L” level
output
voltage
Input leak
current (Hi-Z
output leak
current)
Pull-up
resistance
Input
capacitance
Remarks
Max*2
—
0.7 VCC
—
VCC + 0.3
V
Hysteresis input
VIHS
P00 to P03 ,
P05 to P07*4,
P12,
P62 to P64*3,
PF0*4, PF1*4,
PG1*4, PG2*4
—
0.8 VCC
—
VCC + 0.3
V
Hysteresis input
VIHM
PF2
—
0.8 VCC
—
VCC + 0.3
V
Hysteresis input
VIL
P04
—
VSS − 0.3
—
0.3 VCC
V
Hysteresis input
VILS
P00 to P03 ,
P05 to P07*4,
P12,
P62 to P64*3,
PF0*4, PF1*4,
PG1*4, PG2*4
—
VSS − 0.3
—
0.2 VCC
V
Hysteresis input
VILM
PF2
—
VSS − 0.3
—
0.2 VCC
V
Hysteresis input
VD
P12, PF2
—
VSS − 0.3
—
Vss + 5.5
V
P04
*3
Open-drain
output
application
voltage
Unit
Typ*1
*3
“L” level
input voltage
Value
Min
VIH
"H" level
input voltage
Condition
*4
*4
VOH1
P04, PF0*4,
PF1*4, PG1*4,
PG2*4
IOH = −4 mA
VCC − 0.5
—
—
V
VOH2
P00*3 to P03*4,
P05 to P07*4,
P62 to P64*3
IOH = −8 mA
VCC − 0.5
—
—
V
VOL1
P04, P12
PF0 to PF2*4,
PG1*4, PG2*4
IOL = 4 mA
—
—
0.4
V
VOL2
P00*3 to P03*4,
P05 to P07*4,
P12,
P62 to P64*3
IOL = 12 mA
—
—
0.4
V
All input pins
0.0 V < VI < VCC
−5
—
+5
When pull-up
µA resistance is
disabled
P00*3 to P07*4,
P62 to P64*3,
PG1*4, PG2*4*5
VI = 0 V
25
50
100
When pull-up
kΩ resistance is
enabled
—
5
15
pF
ILI
RPULL
CIN
Other than VCC
f = 1 MHz
and VSS
(Continued)
DS702-00003-1v0-E
45
MB95560H/570H/580H Series
(VCC = 5.0 V ± 10%, VSS = 0.0 V, TA = − 40°C to + 85°C)
Parameter
Symbol
Pin name
Value
Min
Typ*1 Max*2
Unit
Remarks
—
3.6
5.8
Except during
mA Flash memory
writing and erasing
—
7.5
13.8
During Flash
mA memory writing
and erasing
—
4.1
9.1
mA At A/D conversion
—
1.3
3
mA
VCC
FCL = 32 kHz
(External clock FMPL = 16 kHz
operation)
Subclock mode
(divided by 2)
TA = + 25°C
—
49
145
µA
ICCLS*6
FCL = 32 kHz
FMPL = 16 kHz
Subsleep mode
(divided by 2)
TA = + 25°C
—
6
10
µA
CCT*6
FCL = 32 kHz
Watch mode
Main stop mode
TA = + 25°C
—
5
9
µA
FCRH = 4 MHz
FMP = 4 MHz
Main CR clock mode
—
1.1
4.6
mA
ICCSCR
Sub-CR clock mode
(divided by 2)
TA = + 25°C
—
58.1
230
µA
ICCTS
FCH = 32 MHz
Time-base timer
mode
TA = + 25°C
—
330
370
µA
15
Main stop mode
for a single
µA
external clock
product
FCH = 32 MHz
FMP = 16 MHz
Main clock mode
(divided by 2)
ICC
FCH = 32 MHz
FMP = 16 MHz
Main sleep mode
(divided by 2)
ICCS
ICCL
Power supply
current*5
Condition
I
ICCMCR
VCC
VCC
(External clock
operation)
ICCH
Substop mode
TA = + 25°C
—
4
(Continued)
46
DS702-00003-1v0-E
MB95560H/570H/580H Series
(Continued)
Parameter
Power supply
current*5
Symbol
Pin name
(VCC = 5.0 V ± 10%, VSS = 0.0 V, TA = − 40°C to + 85°C)
Value
Condition
Unit
Remarks
Min Typ*1 Max*2
ILVD
Current
consumption for
low-voltage
detection circuit only
—
4
7
µA
ICRH
Current
consumption for the
main CR oscillator
—
240
320
µA
Current
consumption for the
sub-CR oscillator
oscillating at
100 kHz
—
7
20
µA
VCC
ICRL
*1: VCC = 5.0 V, TA = + 25°C
*2: VCC = 5.5 V, TA = + 25°C
*3: P00, P62, P63 and P64 are available only on MB95F562H/F562K/F563H/F563K/F564H/F564K.
*4: P01, P02, P03, P07, PF0, PF1, PG1 and PG2 are available only on MB95F562H/F562K/F563H/F563K/
F564H/F564K/F582H/F582K/F583H/F583K/F584H/F584K.
*5: • The power supply current is determined by the external clock. When the low-voltage detection option is
selected, the power-supply current will be the sum of adding the current consumption of the low-voltage
detection circuit (ILVD) to one of the value from ICC to ICCH. In addition, when both the low-voltage detection
option and the CR oscillator are selected, the power supply current will be the sum of adding up the current
consumption of the low-voltage detection circuit, the current consumption of the CR oscillators (ICRH, ICRL)
and a specified value. In on-chip debug mode, the CR oscillator (ICRH) and the low-voltage detection circuit
are always enabled, and current consumption therefore increases accordingly.
• See "4. AC Characteristics: (1) Clock Timing" for FCH and FCL.
• See "4. AC Characteristics: (2) Source Clock / Machine Clock" for FMP and FMPL.
*6: In sub-CR clock mode, the power supply current value will become the sum of adding ICRL to ICCLS or ICCT. In
addition, when the sub-CR clock mode is selected with FMPL being 50 kHz, the current consumption will
increase accordingly.
DS702-00003-1v0-E
47
MB95560H/570H/580H Series
4. AC Characteristics
(1) Clock Timing
(VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = − 40°C to + 85°C)
Parameter
Symbol Pin name Condition
X0, X1
FCH
X0
X0, X1
—
X1 : open
*
Min
Value
Typ
1
—
16.25 MHz
1
1
—
—
12
32.5
3.92
3.8
7.84
7.6
9.8
Clock
frequency
FCRH
⎯
—
9.5
11.76
11.4
15.68
15.2
—
FCL
X0A, X1A
—
—
FCRL
⎯
—
50
Max
Unit
Remarks
When the main oscillation
circuit is used
MHz When the main external clock
MHz is used
Operating conditions
4
4.08 MHz • The main CR clock is used.
• 0°C < TA < +70°C
Operating conditions
• The main CR clock is used.
4
4.2 MHz
• − 40 °C ≤ TA < 0 °C,
+ 70 °C < TA ≤ + 85 °C
Operating conditions
8
8.16 MHz • PLL multiplier: 2
• 0°C < TA < +70°C
Operating conditions
• PLL multiplier: 2
8
8.4 MHz
• − 40 °C ≤ TA < 0 °C,
+ 70 °C < TA ≤ + 85 °C
Operating conditions
10
10.2 MHz • PLL multiplier: 2.5
• 0°C < TA < +70°C
Operating conditions
• PLL multiplier: 2.5
10
10.5 MHz
• − 40 °C ≤ TA < 0 °C,
+ 70 °C < TA ≤ + 85 °C
Operating conditions
12
12.24 MHz • PLL multiplier: 3
• 0°C < TA < +70°C
Operating conditions
• PLL multiplier: 3
12
12.6 MHz
• − 40 °C ≤ TA < 0 °C,
+ 70 °C < TA ≤ + 85 °C
Operating conditions
16
16.32 MHz • PLL multiplier: 4
• 0°C < TA < +70°C
Operating conditions
• PLL multiplier: 4
16
16.8 MHz
• − 40 °C ≤ TA < 0 °C,
+ 70 °C < TA ≤ + 85 °C
When the sub-oscillation
32.768 —
kHz
circuit is used
When the sub-external clock is
32.768 —
kHz
used
When the sub-CR clock is
100
150 kHz
used
(Continued)
48
DS702-00003-1v0-E
MB95560H/570H/580H Series
(Continued)
Parameter
(VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = − 40°C to + 85°C)
X0, X1
Clock cycle
time
tHCYL
tLCYL
Input clock
pulse width
Input clock rise
time and fall
time
CR oscillation
start time
Min
Value
Typ
Max
61.5
—
1000
ns
83.4
30.8
—
33.4
14.4
—
—
30.5
—
—
1000
1000
—
—
—
ns
ns
µs
ns
ns
—
15.2
—
When an external clock is
used, the duty ratio should
µs range between 40% and 60%.
—
—
5
ns
*
—
—
5
When an external clock is
ns used
µs
Symbol Pin name Condition
tWH1
tWL1
tWH2
tWL2
tCR
tCF
—
X0
X1 : open
X0, X1
*
X0A, X1A
—
X0
X1 : open
X0, X1
*
X0A
—
X0
X1 : open
X0, X1
tCRHWK
—
—
—
—
50
tCRLWK
—
—
—
—
30
Unit
Remarks
When the main oscillation
circuit is used
When an external clock is
used
When the subclock is used
When the main CR clock is
used
When the sub-CR clock is
µs
used
*: The external clock signal is input to X0 and the inverted external clock signal to X1.
DS702-00003-1v0-E
49
MB95560H/570H/580H Series
• Input waveform generated when an external clock (main clock) is used
tHCYL
tWH1
tWL1
tCR
X0, X1
tCF
0.8 VCC 0.8 VCC
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of main clock input port external connection
When a crystal oscillator or
a ceramic oscillator is used
X0
When an external clock is used When an external clock
(X1 is open)
is used
X0
X1
X1
X0
X1
Open
FCH
FCH
FCH
• Input waveform generated when an external clock (subclock) is used
tLCYL
tWH2
tCR
X0A
tWL2
tCF
0.8 VCC 0.8 VCC
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of subclock input port external connection
When a crystal oscillator or
a ceramic oscillator is used
X0A
X1A
FCL
When an external clock
is used
X0A
X1A
Open
FCL
50
DS702-00003-1v0-E
MB95560H/570H/580H Series
(2) Source Clock / Machine Clock
(VCC = 5.0 V ± 10%, VSS = 0.0 V, TA = − 40°C to + 85°C)
Parameter
Source clock
cycle time*1
Symbol
tSCLK
Pin
name
—
FSP
Source clock
frequency
—
FSPL
Machine clock
cycle time*2
(minimum
instruction
execution
time)
tMCLK
—
FMPL
Unit
Remarks
Min
Typ
Max
61.5
—
2000
ns
When the main external clock is used
Min: FCH = 32.5 MHz, divided by 2
Max: FCH = 1 MHz, divided by 2
62.5
—
1000
ns
When the main CR clock is used
Min: FCRH = 4 MHz, multiplied by 4
Max: FCRH = 4 MHz, divided by 4
—
61
—
µs
When the sub-oscillation clock is used
FCL = 32.768 kHz, divided by 2
—
20
—
µs
When the sub-CR clock is used
FCRL = 100 kHz, divided by 2
0.5
—
16.25
—
4
—
MHz When the main CR clock is used
—
16.384
—
kHz When the sub-oscillation clock is used
—
50
—
kHz
61.5
—
32000
ns
When the main oscillation clock is used
Min: FSP = 16.25 MHz, no division
Max: FSP = 0.5 MHz, divided by 16
250
—
1000
ns
When the main CR clock is used
Min: FSP = 4 MHz, no division
Max: FSP = 4 MHz, divided by 4
61
—
976.5
µs
When the sub-oscillation clock is used
Min: FSPL = 16.384 kHz, no division
Max: FSPL = 16.384 kHz, divided by 16
20
—
320
µs
When the sub-CR clock is used
Min: FSPL = 50 kHz, no division
Max: FSPL = 50 kHz, divided by 16
0.031
—
16.25
0.25
—
16
1.024
—
16.384
3.125
—
50
MHz When the main oscillation clock is used
—
FMP
Machine clock
frequency
Value
When the sub-CR clock is used
FCRL = 100 kHz, divided by 2
MHz When the main oscillation clock is used
MHz When the main CR clock is used
kHz When the sub-oscillation clock is used
kHz
When the sub-CR clock is used
FCRL = 100 kHz
*1: This is the clock before it is divided according to the division ratio set by the machine clock division ratio
select bits (SYCC:DIV1, DIV0). This source clock is divided to become a machine clock according to the
division ratio set by the machine clock division ratio select bits (SYCC:DIV1, DIV0). In addition, a source
clock can be selected from the following.
• Main clock divided by 2
• PLL multiplication of main clock (Select a multiplier from 2, 2.5, 3 and 4.)
• Main CR clock
• Subclock divided by 2
• Sub-CR clock divided by 2
*2: This is the operating clock of the microcontroller. A machine clock can be selected from the following.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
DS702-00003-1v0-E
51
MB95560H/570H/580H Series
• Schematic diagram of the clock generation block
FCH
(Main oscillation clock)
Divided by 2
FMPLL
(Main CR PLL)
SCLK
(Source clock)
FCRH
(Main CR clock)
FCL
(Sub-oscillation clock)
Division circuit
×
1
× 1/4
× 1/8
× 1/16
MCLK
(Machine clock)
Divided by 2
Machine clock divide ratio select bits
(SYCC:DIV1, DIV0)
FCRL
(Sub-CR clock)
Divided by 2
Clock mode select bits
(SYCC2: RCS1, RCS0)
• Operating voltage - Operating frequency (When TA = − 40°C to + 85°C)
MB95560H/570H/580H (without the on-chip debug function)
5.5
Operating voltage (V)
5.0
A/D converter operation range
4.0
3.5
3.0
2.7
2.4
16 kHz
3 MHz
10 MHz
16.25 MHz
Source clock frequency (FSP/FSPL)
• Operating voltage - Operating frequency (When TA = − 40°C to + 85°C)
MB95560H/570H/580H (with the on-chip debug function)
5.5
Operating voltage (V)
5.0
A/D converter operation range
4.0
3.5
2.9
3.0
16 kHz
3 MHz
12.5 MHz
16.25 MHz
Source clock frequency (FSP)
52
DS702-00003-1v0-E
MB95560H/570H/580H Series
(3) External Reset
(VCC = 5.0 V ± 10%, VSS = 0.0 V, TA = − 40°C to + 85°C)
Parameter
RST “L” level
pulse width
Symbol
tRSTL
Value
Unit
Remarks
Min
Max
2 tMCLK*1
—
ns
In normal operation
Oscillation time of the
oscillator*2 + 200
—
µs
In stop mode, subclock mode,
subsleep mode, watch mode, and
power-on
200
—
µs
In time-base timer mode
*1: See “(2) Source Clock / Machine Clock” for tMCLK.
*2: The oscillation time of an oscillator is the time for it to reach 90% of its amplitude. The crystal oscillator has
an oscillation time of between several ms and tens of ms. The ceramic oscillator has an oscillation time of
between hundreds of µs and several ms. The external clock has an oscillation time of 0 ms. The CR oscillator
clock has an oscillation time of between several µs and several ms.
• In normal operation
tRSTL
RST
0.2 VCC
0.2 VCC
• In stop mode, subclock mode, subsleep mode, watch mode and power-on
tRSTL
RST
X0
0.2 VCC
0.2 VCC
90% of
amplitude
Internal
operating
clock
Oscillation
time of
oscillator
Internal reset
DS702-00003-1v0-E
200 μs
Oscillation stabilization wait time
Execute instruction
53
MB95560H/570H/580H Series
(4) Power-on Reset
(VSS = 0.0 V, TA = − 40°C to + 85°C)
Parameter
Symbol
Condition
Power supply rising time
tR
Power supply cutoff time
tOFF
tR
Value
Unit
Min
Max
—
—
50
ms
—
1
—
ms
Remarks
Wait time until power-on
tOFF
2.5 V
VCC
0.2 V
0.2 V
0.2 V
Note: A sudden change of power supply voltage may activate the power-on reset function. When changing the
power supply voltage during the operation, set the slope of rising to a value below within 30 mV/ms as
shown below.
VCC
2.3 V
Set the slope of rising to
a value below 30 mV/ms.
Hold condition in stop mode
VSS
54
DS702-00003-1v0-E
MB95560H/570H/580H Series
(5) Peripheral Input Timing
(VCC = 5.0 V ± 10%, VSS = 0.0 V, TA = − 40°C to + 85°C)
Parameter
Peripheral input “H” pulse width
Peripheral input “L” pulse width
Symbol
tILIH
tIHIL
Value
Pin name
INT02 to INT07*2,*3, EC0*2, EC1*4
tILIH
0.8 VCC
Unit
Min
Max
2 tMCLK*1
—
ns
MCLK*1
—
ns
2t
tIHIL
0.8 VCC
INT02 to INT07*2, *3,
EC0*2, EC1*4
0.2 VCC
0.2 VCC
*1: See “(2) Source Clock / Machine Clock” for tMCLK.
*2: INT04, INT06 and EC0 are available on all products.
*3: INT02, INT03, INT05 and INT07 are available only on MB95F562H/F562K/F563H/F563K/F564H/F564K/
F582H/F582K/F583H/F583K/F584H/F584K.
*4: EC1 is available only on MB95F562H/F562K/F563H/F563K/F564H/F564K.
DS702-00003-1v0-E
55
MB95560H/570H/580H Series
(6) LIN-UART Timing (available only on MB95F562H/F562K/F563H/F563K/F564H/F564K/F582H/F582K/
F583H/F583K/F584H/F584K)
Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is disabled*2.
(ESCR register: SCES bit = 0, ECCR register: SCDE bit = 0)
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = − 40°C to + 85°C)
Parameter
Serial clock cycle time
SCK ↓→ SOT delay time
Symbol Pin name
tSCYC
SCK
tSLOVI
SCK, SOT Internal clock
operation output pin:
SCK, SIN CL = 80 pF + 1 TTL
SCK, SIN
Valid SIN → SCK ↑
tIVSHI
SCK ↑→ valid SIN hold time
tSHIXI
Serial clock “L” pulse width
Serial clock “H” pulse width
tSLSH
tSHSL
SCK ↓→ SOT delay time
tSLOVE
Valid SIN → SCK ↑
tIVSHE
SCK ↑→ valid SIN hold time
tSHIXE
Value
Condition
SCK
SCK
SCK, SOT External clock
SCK, SIN operation output pin:
SCK, SIN CL = 80 pF + 1 TTL
t
Max
5 tMCLK*3
—
ns
− 50
+ 50
ns
MCLK 3
* + 80
—
ns
0
—
ns
* − tR
—
ns
* + 10
—
ns
MCLK 3
3t
t
MCLK 3
* + 60
MCLK 3
ns
30
—
ns
* + 30
—
ns
—
t
Unit
Min
MCLK 3
2t
SCK fall time
tF
SCK
—
10
ns
SCK rise time
tR
SCK
—
10
ns
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or
a falling edge of the serial clock.
*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.
*3: See “(2) Source Clock / Machine Clock” for tMCLK.
56
DS702-00003-1v0-E
MB95560H/570H/580H Series
• Internal shift clock mode
tSCYC
0.8 VCC
SCK
0.2 VCC
0.2 VCC
tSLOVI
0.8 VCC
SOT
0.2 VCC
tIVSHI
tSHIXI
0.7 VCC 0.7 VCC
SIN
0.3 VCC 0.3 VCC
• External shift clock mode
tSLSH
tSHSL
0.8 VCC
0.8 VCC
0.8 VCC
SCK
0.2 VCC
tF
0.2 VCC
tR
tSLOVE
0.8 VCC
SOT
0.2 VCC
tIVSHE
tSHIXE
0.7 VCC 0.7 VCC
SIN
0.3 VCC 0.3 VCC
DS702-00003-1v0-E
57
MB95560H/570H/580H Series
Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is disabled*2.
(ESCR register: SCES bit = 1, ECCR register: SCDE bit = 0)
(VCC = 5.0 V ± 10%, VSS = 0.0 V, TA = − 40°C to + 85°C)
Parameter
Serial clock cycle time
SCK ↑→ SOT delay time
Symbol Pin name
tSCYC
SCK
tSHOVI
SCK, SOT Internal clock
operation output pin:
SCK, SIN CL = 80 pF + 1 TTL
SCK, SIN
Valid SIN → SCK ↓
tIVSLI
SCK ↓→ valid SIN hold time
tSLIXI
Serial clock “H” pulse width
Serial clock “L” pulse width
tSHSL
tSLSH
SCK ↑→ SOT delay time
tSHOVE
Valid SIN → SCK ↓
tIVSLE
SCK ↓→ valid SIN hold time
tSLIXE
Value
Condition
SCK
SCK
SCK, SOT External clock
SCK, SIN operation output pin:
SCK, SIN CL = 80 pF + 1 TTL
t
Max
5 tMCLK*3
—
ns
− 50
+ 50
ns
MCLK 3
* + 80
—
ns
0
—
ns
* − tR
—
ns
* + 10
—
ns
MCLK 3
3t
t
MCLK 3
* + 60
MCLK 3
ns
30
—
ns
* + 30
—
ns
—
t
Unit
Min
MCLK 3
2t
SCK fall time
tF
SCK
—
10
ns
SCK rise time
tR
SCK
—
10
ns
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or
a falling edge of the serial clock.
*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.
*3: See “(2) Source Clock / Machine Clock” for tMCLK.
58
DS702-00003-1v0-E
MB95560H/570H/580H Series
• Internal shift clock mode
tSCYC
0.8 VCC
0.8 VCC
SCK
0.2 VCC
tSHOVI
0.8 VCC
SOT
0.2 VCC
tIVSLI
tSLIXI
0.7 VCC 0.7 VCC
SIN
0.3 VCC 0.3 VCC
• External shift clock mode
tSHSL
0.8 VCC
tSLSH
0.8 VCC
SCK
0.2 VCC
tR
tF
0.2 VCC
0.2 VCC
tSHOVE
0.8 VCC
SOT
0.2 VCC
tIVSLE
tSLIXE
0.7 VCC 0.7 VCC
SIN
0.3 VCC 0.3 VCC
DS702-00003-1v0-E
59
MB95560H/570H/580H Series
Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is enabled*2.
(ESCR register: SCES bit = 0, ECCR register: SCDE bit = 1)
(VCC = 5.0 V ± 10%, VSS = 0.0 V, TA = − 40°C to + 85°C)
Parameter
Symbol Pin name
Value
Condition
Serial clock cycle time
tSCYC
SCK
SCK ↑→ SOT delay time
tSHOVI
SCK, SOT Internal clock
SCK, SIN operation output pin:
SCK, SIN CL = 80 pF + 1 TTL
Valid SIN → SCK ↓
tIVSLI
SCK ↓→ valid SIN hold time
tSLIXI
SOT → SCK ↓ delay time
tSOVLI
SCK, SOT
t
Unit
Min
Max
5 tMCLK*3
—
ns
− 50
+ 50
ns
MCLK 3
* + 80
—
ns
0
—
ns
* − 70
—
ns
3t
MCLK 3
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or
a falling edge of the serial clock.
*2: The serial clock delay function is a function that delays the output signal of the serial clock for half clock.
*3: See “(2) Source Clock / Machine Clock” for tMCLK.
tSCYC
0.8 VCC
SCK
0.2 VCC
SOT
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tIVSLI
SIN
60
0.2 VCC
tSHOVI
tSOVLI
tSLIXI
0.7 VCC
0.7 VCC
0.3 VCC
0.3 VCC
DS702-00003-1v0-E
MB95560H/570H/580H Series
Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is enabled*2.
(ESCR register: SCES bit = 1, ECCR register: SCDE bit = 1)
(VCC = 5.0 V ± 10%, VSS = 0.0 V, TA = − 40°C to + 85°C)
Parameter
Symbol Pin name
Value
Condition
Serial clock cycle time
tSCYC
SCK
SCK ↓→ SOT delay time
tSLOVI
SCK, SOT Internal clock
SCK, SIN operating output pin:
SCK, SIN CL = 80 pF + 1 TTL
Valid SIN → SCK ↑
tIVSHI
SCK ↑→ valid SIN hold time
tSHIXI
SOT → SCK ↑ delay time
tSOVHI
t
SCK, SOT
Unit
Min
Max
5 tMCLK*3
—
ns
− 50
+ 50
ns
MCLK 3
* + 80
—
ns
0
—
ns
* − 70
—
ns
3t
MCLK 3
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or
a falling edge of the serial clock.
*2: The serial clock delay function is a function that delays the output signal of the serial clock for half clock.
*3: See “(2) Source Clock / Machine Clock” for tMCLK.
tSCYC
0.8 VCC
SCK
0.8 VCC
0.2 VCC
tSOVHI
SOT
0.8 VCC
0.2 VCC
0.2 VCC
tIVSHI
SIN
DS702-00003-1v0-E
tSLOVI
0.8 VCC
tSHIXI
0.7 VCC
0.7 VCC
0.3 VCC
0.3 VCC
61
MB95560H/570H/580H Series
(7) Low-voltage Detection
(VSS = 0.0 V, TA = − 40°C to + 85°C)
Parameter
Release voltage*
Detection voltage*
Symbol
VDL+
VDL−
Value
Min
Typ
Max
2.52
2.7
2.88
2.61
2.8
2.99
2.89
3.1
3.31
3.08
3.3
3.52
2.43
2.6
2.77
2.52
2.7
2.88
2.80
3
3.20
2.99
3.2
3.41
Unit
Remarks
V
At power supply rise
V
At power supply fall
Hysteresis width
VHYS
—
—
100
mV
Power supply start voltage
Voff
—
—
2.3
V
Power supply end voltage
Von
4.9
—
—
V
Power supply voltage
change time
(at power supply rise)
tr
650
—
—
µs
Slope of power supply that the reset
release signal generates within the
rating (VDL+)
Power supply voltage
change time
(at power supply fall)
tf
650
—
—
µs
Slope of power supply that the reset
detection signal generates within the
rating (VDL-)
Reset release delay time
td1
—
—
30
µs
Reset detection delay time
td2
—
—
30
µs
LVD threshold voltage
transition stabilization time
tstb
10
—
—
µs
*: The release voltage and the detection voltage can be selected by using the LVD reset voltage selection ID
register (LVDR) in the low-voltage detection reset circuit. For details of the LVDR register, refer to
“CHAPTER 18 LOW-VOLTAGE DETECTION RESET CIRCUIT” in the hardware manual of the MB95560H/
570H/580H Series.
62
DS702-00003-1v0-E
MB95560H/570H/580H Series
VCC
Von
Voff
time
tf
tr
VDL+
VHYS
VDL-
Internal reset signal
time
td2
DS702-00003-1v0-E
td1
63
MB95560H/570H/580H Series
5. A/D Converter
(1) A/D Converter Electrical Characteristics
(VCC = 2.7 V to 5.5 V, VSS = 0.0 V, TA = − 40°C to + 85°C)
Parameter
Symbol
Resolution
Total error
Linearity error
—
Differential linear
error
Value
Unit
Min
Typ
Max
—
—
10
bit
−3
—
+3
LSB
− 2.5
—
+ 2.5
LSB
− 1.9
—
+ 1.9
LSB
Zero transition
voltage
VOT
VSS − 7.2 LSB VSS + 0.5 LSB VSS + 8.2 LSB
V
Full-scale transition
voltage
VFST
VCC − 6.2 LSB VCC − 1.5 LSB VCC + 9.2 LSB
V
Remarks
Compare time
—
3
—
10
µs
2.7 V ≤ VCC ≤ 5.5 V
Sampling time
—
0.517
—
∞
µs
2.7 V ≤ VCC ≤ 5.5 V,
with external
impedance < 3.3 kΩ
Analog input current
IAIN
− 0.3
—
+ 0.3
µA
Analog input voltage
VAIN
VSS
—
VCC
V
64
DS702-00003-1v0-E
MB95560H/570H/580H Series
(2) Notes on Using the A/D Converter
• External impedance of analog input and its sampling time
• The A/D converter has a sample and hold circuit. If the external impedance is too high to keep sufficient
sampling time, the analog voltage charged to the capacitor of the internal sample and hold circuit is
insufficient, adversely affecting A/D conversion precision. Therefore, to satisfy the A/D conversion precision
standard, considering the relationship between the external impedance and minimum sampling time, either
adjust the register value and operating frequency or decrease the external impedance so that the sampling
time is longer than the minimum value. In addition, if sufficient sampling time cannot be secured, connect
a capacitor of about 0.1 µF to the analog input pin.
• Analog input equivalent circuit
Analog input
Comparator
R
C
During sampling: ON
VCC
R
C
4.5 V ≤ VCC ≤ 5.5 V
3.3 kΩ (Max)
2.7 V ≤ VCC < 5.5 V
15.7 kΩ (Max)
14.89 pF (Max)
14.89 pF (Max)
Note: The values are reference values.
• Relationship between external impedance and minimum sampling time
[External impedance = 0 kΩ to 100 kΩ]
[External impedance = 0 kΩ to 20 kΩ]
100000
20000
External impedance [kΩ]
External impedance [kΩ]
80000
60000
40000
15000
10000
5000
20000
0
0
0
2
4
6
8
10
12
0
0.5
Minimum sampling time [μs]
1
1.5
2
2.5
Minimum sampling time [μs]
Minimum sampling time with VCC > 2.7 V
Minimum sampling time with VCC > 2.4 V
• A/D conversion error
As |VCC − VSS| decreases, the A/D conversion error increases proportionately.
DS702-00003-1v0-E
65
MB95560H/570H/580H Series
(3) Definitions of A/D Converter Terms
• Resolution
It indicates the level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit: LSB)
It indicates how much an actual conversion value deviates from the straight line connecting
the zero transition point (“00 0000 0000” ← → “00 0000 0001”) of a device to
the full-scale transition point (“11 1111 1111” ← → “11 1111 1110”) of the same device.
• Differential linear error (unit: LSB)
It indicates how much the input voltage required to change the output code by 1 LSB deviates from an
ideal value.
• Total error (unit: LSB)
It indicates the difference between an actual value and a theoretical value. The error can be caused by a
zero transition error, a full-scale transition errors, a linearity error, a quantum error, or noise.
Ideal I/O characteristics
Total error
VFST
3FFH
3FFH
2 LSB
3FDH
Digital output
Digital output
3FDH
004H
003H
Actual conversion
characteristic
3FEH
3FEH
VOT
{1 LSB × (N-1) + 0.5 LSB}
004H
VNT
003H
1 LSB
002H
002H
001H
Actual conversion
characteristic
Ideal characteristic
001H
0.5 LSB
VSS
Analog input
1 LSB =
VCC - VSS
(V)
1024
N
VCC
VSS
Analog input
VCC
VNT - {1 LSB × (N - 1) + 0.5 LSB}
Total error of
=
[LSB]
digital output N
1 LSB
: A/D converter digital output value
VNT : Voltage at which the digital output transits from (N - 1)H to NH
(Continued)
66
DS702-00003-1v0-E
MB95560H/570H/580H Series
(Continued)
Zero transition error
Full-scale transition error
004H
Ideal characteristic
Actual conversion
characteristic
3FFH
Actual conversion
characteristic
002H
Digital output
Digital output
003H
Actual conversion
characteristic
Ideal
characteristic
3FEH
VFST
(measurement
value)
3FDH
Actual conversion
characteristic
001H
3FCH
VOT (measurement value)
VSS
Analog input
VCC
VSS
Linearity error
3FEH
Ideal characteristic
(N+1)H
Actual conversion
characteristic
{1 LSB × N + VOT}
VFST
(measurement
value)
VNT
004H
Digital output
Digital output
3FDH
Ideal
characteristic
002H
V(N+1)T
NH
VNT
(N-1)H
Actual conversion
characteristic
003H
VCC
Differential linearity error
Actual conversion
characteristic
3FFH
Analog input
Actual conversion
characteristic
(N-2)H
001H
VOT (measurement value)
VSS
Analog input
VCC
VNT - {1 LSB × N + VOT}
Linearity error
=
of digital output N
1 LSB
N
VSS
Analog input
VCC
V(N+1)T - VNT
Differential linear error
=
- 1
of digital output N
1 LSB
: A/D converter digital output value
VNT : Voltage at which the digital output transits from (N - 1)H to NH
VOT (ideal value) = VSS + 0.5 LSB [V]
VFST (ideal value) = VCC - 2 LSB [V]
DS702-00003-1v0-E
67
MB95560H/570H/580H Series
6. Flash Memory Program/Erase Characteristics
Value
Parameter
Unit
Remarks
Min
Typ
Max
Sector erase time
(2 Kbyte sector)
—
0.3*1
1.6
s
The time of writing 00H prior to
erasure is excluded.
Sector erase time
(16 Kbyte sector)
—
0.6*1
3.1
s
The time of writing 00H prior to
erasure is excluded.
Byte writing time
—
17
272
µs
System-level overhead is excluded.
100000
—
—
cycle
Power supply voltage at
program/erase
2.4
—
5.5
V
Flash memory data retention
time
5*2
—
—
Program/erase cycle
year Average TA = + 85°C
*1: VCC = 5.5 V, TA = + 25°C, 0 cycle
*2: This value is converted from the result of a technology reliability assessment. (The value is converted from
the result of a high temperature accelerated test using the Arrhenius equation with the average temperature
being + 85°C).
68
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ SAMPLE CHARACTERISTICS
• Power supply current temperature characteristics
ICC − VCC
TA = +25°C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Main clock mode with the external clock operating
ICC − TA
VCC = 5.5 V, FMP = 10, 16 MHz (divided by 2)
Main clock mode with the external clock operating
20
20
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
15
ICC[mA]
ICC[mA]
15
FMP = 16 MHz
FMP = 10 MHz
10
10
5
5
0
−50
0
2
3
4
5
6
7
0
ICCS − VCC
TA = +25°C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Main sleep mode with the external clock operating
+150
10
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
8
FMP = 16 MHz
FMP = 10 MHz
8
6
ICCS[mA]
ICCS[mA]
+100
ICCS − TA
VCC = 5.5 V, FMP = 10, 16 MHz (divided by 2)
Main sleep mode with the external clock operating
10
6
4
4
2
2
0
−50
0
2
3
4
5
6
7
0
+50
+100
+150
TA[°C]
VCC[V]
ICCL − VCC
TA = +25°C, FMPL = 16 kHz (divided by 2)
Subclock mode with the external clock operating
ICCL − TA
VCC = 5.5 V, FMPL = 16 kHz (divided by 2)
Subclock mode with the external clock operating
100
100
75
75
ICCL[μA]
ICCL[μA]
+50
TA[°C]
VCC[V]
50
25
50
25
0
2
3
4
5
VCC[V]
6
7
0
−50
0
+50
+100
+150
TA[°C]
(Continued)
DS702-00003-1v0-E
69
MB95560H/570H/580H Series
ICCLS − TA
VCC = 5.5 V, FMPL = 16 kHz (divided by 2)
Subsleep mode with the external clock operating
80
80
70
70
60
60
50
50
ICCLS[μA]
ICCLS[μA]
ICCLS − VCC
TA = +25°C, FMPL = 16 kHz (divided by 2)
Subsleep mode with the external clock operating
40
40
30
30
20
20
10
10
0
0
2
3
4
5
6
−50
7
0
+100
+150
ICCT − TA
VCC = 5.5 V, FMPL = 16 kHz (divided by 2)
Watch mode with the external clock operating
20
20
16
16
12
12
ICCT[μA]
ICCT[μA]
ICCT − VCC
TA = +25°C, FMPL = 16 kHz (divided by 2)
Watch mode with the external clock operating
8
8
4
4
0
0
2
3
4
5
6
−50
7
0
VCC[V]
+50
+100
+150
TA[°C]
ICTS − VCC
TA = +25°C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Time-base timer mode with the external clock
operating
ICTS − TA
VCC = 5.5 V, FMP = 10, 16 kHz (divided by 2)
Time-base timer mode with the external clock
operating
1.4
1.4
FMP = 16 MHz
FMP = 10 MHz
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
1.2
1.2
1.0
1.0
0.8
0.8
ICTS[mA]
ICTS[mA]
+50
TA[°C]
VCC[V]
0.6
0.6
0.4
0.4
0.2
0.2
0.0
2
3
4
5
VCC[V]
6
7
0.0
−50
0
+50
+100
+150
TA[°C]
(Continued)
70
DS702-00003-1v0-E
MB95560H/570H/580H Series
(Continued)
ICCH − TA
VCC = 5.5 V, FMPL = (stop)
Substop mode with the external clock stopping
20
20
15
15
ICCH[μA]
ICCH[μA]
ICCH − VCC
TA = +25°C, FMPL = (stop)
Substop mode with the external clock stopping
10
5
5
0
0
2
3
4
5
6
7
−50
VCC[V]
0
+100
+150
ICCMCR − TA
VCC = 5.5 V, FMP = 4 MHz (no division)
Main clock mode with the main CR clock operating
20
15
15
ICCMCR[mA]
20
10
5
10
5
0
0
2
3
4
5
6
−50
7
0
VCC[V]
+50
+100
+150
TA[°C]
ICCSCR − VCC
TA = +25°C, FMPL = 50 kHz (divided by 2)
Subclock mode with the sub-CR clock operating
ICCSCR − TA
VCC = 5.5 V, FMPL = 50 kHz (divided by 2)
Subclock mode with the sub-CR clock operating
200
200
150
150
ICCSCR[μA]
ICCSCR[μA]
+50
TA[°C]
ICCMCR − VCC
TA = +25°C, FMP = 4 MHz (no division)
Main clock mode with the main CR clock operating
ICCMCR[mA]
10
100
50
100
50
0
0
2
3
4
5
VCC[V]
DS702-00003-1v0-E
6
7
−50
0
+50
+100
+150
TA[°C]
71
MB95560H/570H/580H Series
• Input voltage characteristics
VIHI − VCC and VILI − VCC
TA = +25°C
VIHS − VCC and VILS − VCC
TA = +25°C
5
5
VIHS
VILS
4
4
3
3
VIHS/VILS[V]
VIHI/VILI[V]
VIHI
VILI
2
1
2
1
0
0
2
3
4
5
6
7
2
3
VCC[V]
4
5
6
7
VCC[V]
VIHM − VCC and VILM − VCC
TA = +25°C
5
VIHM
VILM
VIHM/VILM[V]
4
3
2
1
0
2
3
4
5
6
7
VCC[V]
72
DS702-00003-1v0-E
MB95560H/570H/580H Series
• Output voltage characteristics
(VCC − VOH2) − IOH
TA = +25°C
1.0
1.0
0.8
0.8
VCC − VOH2[V]
VCC − VOH1[V]
(VCC − VOH1) − IOH
TA = +25°C
0.6
0.4
0.2
0.6
0.4
0.2
0.0
0.0
0
−2
−6
−4
−8
−10
−2
0
−6
−4
IOH [mA]
−8
−10
IOH [mA]
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.5 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.5 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
VOL1 − IOL
TA = +25°C
VOL2 − IOL
TA = +25°C
1.0
0.6
0.8
0.4
VOL2[V]
VOL1[V]
0.6
0.4
0.2
0.2
0.0
0.0
0
2
6
4
IOL [mA]
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.5 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
DS702-00003-1v0-E
8
10
0
2
6
4
8
10
IOL [mA]
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.5 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
73
MB95560H/570H/580H Series
• Pull-up characteristics
RPULL − VCC
TA = +25°C
250
RPULL[kΩ]
200
150
100
50
0
2
3
4
5
6
VCC[V]
74
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ MASK OPTIONS
Part Number
No.
MB95F562K
MB95F563K
MB95F564K
MB95F572K
MB95F573K
MB95F574K
MB95F582K
MB95F583K
MB95F584K
MB95F562H
MB95F563H
MB95F564H
MB95F572H
MB95F573H
MB95F574H
MB95F582H
MB95F583H
MB95F584H
Selectable/Fixed
Fixed
1
Low-voltage detection reset Without low-voltage detection reset With low-voltage detection reset
2
Reset
DS702-00003-1v0-E
With dedicated reset input
Without dedicated reset input
75
MB95560H/570H/580H Series
■ ORDERING INFORMATION
Part Number
MB95F562HWQN-G-JNE1
MB95F562HWQN-G-JNERE1
MB95F562KWQN-G-JNE1
MB95F562KWQN-G-JNERE1
MB95F563HWQN-G-JNE1
MB95F563HWQN-G-JNERE1
MB95F563KWQN-G-JNE1
MB95F563KWQN-G-JNERE1
MB95F564HWQN-G-JNE1
MB95F564HWQN-G-JNERE1
MB95F564KWQN-G-JNE1
MB95F564KWQN-G-JNERE1
MB95F562HPF-G-JNE2
MB95F562KPF-G-JNE2
MB95F563HPF-G-JNE2
MB95F563KPF-G-JNE2
MB95F564HPF-G-JNE2
MB95F564KPF-G-JNE2
MB95F562HPFT-G-JNE2
MB95F562KPFT-G-JNE2
MB95F563HPFT-G-JNE2
MB95F563KPFT-G-JNE2
MB95F564HPFT-G-JNE2
MB95F564KPFT-G-JNE2
MB95F582HWQN-G-JNE1
MB95F582HWQN-G-JNERE1
MB95F582KWQN-G-JNE1
MB95F582KWQN-G-JNERE1
MB95F583HWQN-G-JNE1
MB95F583HWQN-G-JNERE1
MB95F583KWQN-G-JNE1
MB95F583KWQN-G-JNERE1
MB95F584HWQN-G-JNE1
MB95F584HWQN-G-JNERE1
MB95F584KWQN-G-JNE1
MB95F584KWQN-G-JNERE1
MB95F582HPFT-G-JNE2
MB95F582KPFT-G-JNE2
MB95F583HPFT-G-JNE2
MB95F583KPFT-G-JNE2
MB95F584HPFT-G-JNE2
MB95F584KPFT-G-JNE2
MB95F582HPF-G-JNE2
MB95F582KPF-G-JNE2
MB95F583HPF-G-JNE2
MB95F583KPF-G-JNE2
MB95F584HPF-G-JNE2
MB95F584KPF-G-JNE2
MB95F572HPF-G-JNE2
MB95F572KPF-G-JNE2
MB95F573HPF-G-JNE2
MB95F573KPF-G-JNE2
MB95F574HPF-G-JNE2
MB95F574KPF-G-JNE2
76
Package
32-pin plastic QFN
(LCC-32P-M19)
20-pin plastic SOP
(FPT-20P-M09)
20-pin plastic TSSOP
(FPT-20P-M10)
32-pin plastic QFN
(LCC-32P-M19)
16-pin plastic TSSOP
(FPT-16P-M08)
16-pin plastic SOP
(FPT-16P-M23)
8-pin plastic SOP
(FPT-8P-M08)
DS702-00003-1v0-E
MB95560H/570H/580H Series
■ PACKAGE DIMENSION
32-pin plastic QFN
Lead pitch
0.50 mm
Package width ×
package length
5.00 mm × 5.00 mm
Sealing method
Plastic mold
Mounting height
0.80 mm MAX
Weight
0.06 g
(LCC-32P-M19)
32-pin plastic QFN
(LCC-32P-M19)
3.50±0.10
(.138±.004)
5.00±0.10
(.197±.004)
5.00±0.10
(.197±.004)
3.50±0.10
(.138±.004)
INDEX AREA
0.25
(.010
(3-R0.20)
((3-R.008))
0.50(.020)
+0.05
–0.07
+.002
–.003
)
0.40±0.05
(.016±.002)
1PIN CORNER
(C0.30(C.012))
(TYP)
0.75±0.05
(.030±.002)
0.02
(.001
C
+0.03
–0.02
+.001
–.001
(0.20(.008))
)
2009-2010 FUJITSU SEMICONDUCTOR LIMITED C32071S-c-1-2
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
DS702-00003-1v0-E
77
MB95560H/570H/580H Series
20-pin plastic SOP
Lead pitch
1.27 mm
Package width ×
package length
7.50 mm × 12.70 mm
Lead shape
Gullwing
Lead bend
direction
Normal bend
Sealing method
Plastic mold
Mounting height
2.65 mm Max
(FPT-20P-M09)
20-pin plastic SOP
(FPT-20P-M09)
Note 1) Pins width and pins thickness include plating thickness.
Note 2) Pins width do not include tie bar cutting remainder.
Note 3) # : These dimensions do not include resin protrusion.
0.25
#12.70±0.10(.500±.004)
+0.07
–0.02
+.003
.010 –.001
20
11
BTM E-MARK
+0.40
#7.50±0.10 10.2 –0.20
(.295±.004) .402 +.016
–.008
INDEX
Details of "A" part
+0.13
2.52 –0.17
(Mounting height)
+.005
.099 –.007
1
"A"
10
1.27(.050)
0.40
.016
+0.09
–0.05
+.004
–.002
0.25(.010)
M
0~8°
+0.47
0.80 –0.30
+.019
.031 –.012
0.20±0.10
(.008±.004)
(Stand off)
0.10(.004)
C
2008-2010 FUJITSU SEMICONDUCTOR LIMITED F20030S-c-1-2
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
78
DS702-00003-1v0-E
MB95560H/570H/580H Series
20-pin plastic TSSOP
Lead pitch
0.65 mm
Package width ×
package length
4.40 mm × 6.50 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.20 mm MAX
Weight
0.08 g
(FPT-20P-M10)
20-pin plastic TSSOP
(FPT-20P-M10)
Note 1) Pins width and pins thickness include plating thickness.
Note 2) Pins width do not include tie bar cutting remainder.
Note 3) # : These dimensions do not include resin protrusion.
+0.05
0.14 –0.04
#6.50±0.10(.256±.004)
+.002
.006 –.002
11
20
BTM E-MARK
#4.40±0.10 6.40±0.20
(.173±.004) (.252±.008)
INDEX
Details of "A" part
LEAD No.
1
1.20(.047)
(Mounting height)
MAX
10
0.65(.026)
"A"
0.24±0.04
(.009±.002)
0~8°
0.60±0.15
(.024±.006)
0.10(.004)
C
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F20031S-c-1-2
0.10±0.05
(.004±.002)
(Stand off)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
DS702-00003-1v0-E
79
MB95560H/570H/580H Series
16-pin plastic TSSOP
Lead pitch
0.65 mm
Package width ×
package length
4.40 mm × 4.96 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.20 mm Max
Weight
0.06 g
(FPT-16P-M08)
16-pin plastic TSSOP
(FPT-16P-M08)
Note 1) Pins width and pins thickness include plating thickness.
Note 2) Pins width do not include tie bar cutting remainder.
Note 3) * : These dimensions do not include resin protrusion.
*4.96±0.10(.195±.004)
16
0.145±0.045
(.0057±.0018)
9
*4.40±0.10 6.40±0.20
(.173±.004) (.252±.008)
INDEX
Details of "A" part
+0.10
1.10 –0.15
(Mounting height)
+0.04
.043 –0.06
LEAD No.
1
8
0.65(.026)
"A"
0.24±0.08
(.009±.003)
0.13(.005)
M
0~8°
0.60±0.15
(.024±.006)
0.10±0.05
(.004±.002)
(Stand off)
0.10(.004)
C
2007-2010 FUJITSU SEMICONDUCTOR LIMITED F16021S-c-1-5
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
80
DS702-00003-1v0-E
MB95560H/570H/580H Series
16-pin plastic SOP
Lead pitch
1.27 mm
Package width ×
package length
3.90 mm × 9.96 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.75 mm MAX
Weight
0.12 g
(FPT-16P-M23)
16-pin plastic SOP
(FPT-16P-M23)
Note 1) Pins width and pins thickness include plating thickness.
Note 2) Pins width do not include tie bar cutting remainder.
Note 3) #: These dimensions do not include resin protrusion.
+0.20
#9.96±0.10(.392±.004)
0.60 –0.15
+0.08
.024 –0.06
9
16
8 ±2
8 ±2
BTM E-MARK
INDEX
(1.04 (.041))
#3.90±0.10 6.00±0.20
(.154±.004) (.236±.008)
0.40±0.10
(.016±.004)
1
0.40±0.10
(.016±.004)
8
+0.11
1.27(.050)
0.40 –0.04
(.016 +.004
–.002 )
0.25(.010)
M
0.65±0.10 (.026±.004)
1.45±0.20 (.057±.008)
7 ±2
+0.15
+0.06
1.60 –0.25 .063 –0.10
7 ±2
C
0.10(.004)
+0.10
+0.04
0.15 –0.05 .006 –0.02
2010 FUJITSU SEMICONDUCTOR LIMITED HMbF16-23Sc-1-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
DS702-00003-1v0-E
81
MB95560H/570H/580H Series
(Continued)
8-pin plastic SOP
Lead pitch
1.27 mm
Package width ×
package length
5.30 mm × 5.24 mm
Lead shape
Gullwing
Lead bend
direction
Normal bend
Sealing method
Plastic mold
Mounting height
2.10 mm Max
(FPT-8P-M08)
8-pin plastic SOP
(FPT-8P-M08)
Note 1) Pins width and pins thickness include plating thickness.
Note 2) Pins width do not include tie bar cutting remainder.
Note 3) # : These dimensions do not include resin protrusion.
#5.24±0.10
(.206±.004)
8
5
"A"
BTM E-MARK
#5.30±0.10
(.209±.004)
INDEX
7.80
.307
+0.45
–0.10
+.018
–.004
Details of "A" part
2.10(.083)
MAX
(Mounting height)
1
1.27(.050)
4
0.43±0.05
(.017±.002)
0.20±0.05
(.008±.002)
0~8°
+0.15
0.10 –0.05
+.006
.004 –.002
(Stand off)
C
2008-2010 FUJITSU SEMICONDUCTOR LIMITED F08016S-c-1-2
+0.10
0.75 –0.20
+.004
.030 –.008
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
82
DS702-00003-1v0-E
MB95560H/570H/580H Series
MEMO
DS702-00003-1v0-E
83
MB95560H/570H/580H Series
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
FUJITSU SEMICONDUCTOR AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://us.fujitsu.com/micro/
Asia Pacific
FUJITSU SEMICONDUCTOR ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fujitsu.com/sg/services/micro/semiconductor/
Europe
FUJITSU SEMICONDUCTOR EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/semiconductor/
FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fss/
Korea
FUJITSU SEMICONDUCTOR KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fsp/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does
not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any
third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right
by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or
other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations
of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department