austriamicrosystems AG is now ams AG The technical content of this austriamicrosystems datasheet is still valid. Contact information: Headquarters: ams AG Tobelbaderstrasse 30 8141 Unterpremstaetten, Austria Tel: +43 (0) 3136 500 0 e-Mail: [email protected] Please visit our website at www.ams.com Data Sheet NSD-1202 Dual Piezo Motor Driver IC for SQL Series SQUIGGLE Motors 1 General Description 2 Key Features The NSD-1202 is a dedicated piezo motor driver ASIC capable of driving two SQL Series SQUIGGLE motors from a single 2.8 to 5.5 VDC supply. Wide Input Supply Voltage Range: 2.8 to 5.5VDC The two motors can be controlled independently using a standard I²C interface. Minimum 65% efficiency (at VDD=2.8V, IOUT=25mA, freq=2MHz) An on-chip DC-DC step-up converter generates the high supply voltage (24 to 40 VDC) required by the piezoelectric elements of the SQUIGGLE motor. lv 4x output driver with defined rise/fall time al id Step-up converter to generate programmable high-voltage power supply (24 to 40V) I²C interface On chip registers store driver instructions Four half bridge drivers create pairs of phase-shifted square waves with ultrasonic frequency as required to drive SQL Series SQUIGGLE motors. am lc s on A te G nt st il Power-down mode for minimal power consumption in stand-by Small 4x4mm 16-Pin QFN Package This part supersedes and is backward-compatible with the NSD1102. 3 Applications Figure 1. NSD-1202 Functional Block Diagram The NSD-1202 is ideal for SQUIGGLE piezoelectric motor driver. L1 VIN (2.8-5.5V) C1 22µF ca Voltage reference C2 D1 LX VDD (2.8-5.5V) XPD VDDH (programmable 24V...40V) 4.7µH VDDH TRIM Step-up controller VSS I²C Interface CLK Te ch ni SDA SCL ADR www.austriamicrosystems.com/NSD-1202 LOGIC 1µF VSSP NSD-1202 Registers Levelshifter 1 DRV2P1 Levelshifter 1 DRV2P2 Levelshifter 1 DRV1P1 Levelshifter 1 DRV1P2 Revision 0.2 1 - 13 NSD-1202 Data Sheet - P i n A s s i g n m e n t s 4 Pin Assignments 14 13 VDDH 1 12 NC ADR 2 11 NC LX 3 10 VSSP VDD 4 9 XPD CLK 7 8 SCL 6 SDA 5 VSS am lc s on A te G nt st il NSD-1202 al id DRV1P2 15 lv DRV1P1 16 DRV2P2 DRV2P1 Figure 2. Pin Assignments (Top View) 4.1 Pin Descriptions Table 1. Pin Descriptions Pin Name Pin Number Pin Type Character 1 Supply pad Power High Voltage Supply 2 Digital input Input Slave address input 3 Analog I/O Output Power Output to Inductor Power Low Voltage Supply GND Signal Ground Digital input Input 20MHz Clock input Digital I/O BiDir 9 Digital input Input Power Down, active low VSSP 10 Supply pad GND Power Ground NC11 11 Digital I/O NC12 12 VDDH ADR LX VDD 4 5 CLK 6 1 1 Te ch XPD 7 ni SDA SCL ca VSS Supply pad 8 DRV1P2 13 DRV1P1 14 DRV2P2 15 DRV2P1 16 Description Data IO BiDir Data clock (400 kHz Max) Test mode pin, connect to VSS Test IO pin, connect to VSS Half Bridge 1 Phase2 Output Analog I/O Output Half Bridge 1 Phase 1 Output Half Bridge 2 Phase2 Output Half Bridge 2 Phase1 Output 1. SDA (Data IO) and SCL (Data clock) constitute an I²C interface. Both have open drain outputs. www.austriamicrosystems.com/NSD-1202 Revision 0.2 2 - 13 NSD-1202 Data Sheet - A b s o l u t e M a x i m u m R a t i n g s 5 Absolute Maximum Ratings Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 4 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings Min VVDD Voltage at low voltage supply pin VVDDH Max Units Comments -0.3 7 V Internal 3.3V supply (VDDA) Voltage at high voltage supply pin -0.3 50 V High voltage supply VLX Voltage at LX pin -0.6 VVDDH+0 .3 V VLV Voltage at CLK, SDA, SCL, XPD -0.3 7 V Iscr Input current (latchup immunity) -50 50 mA ESD Electrostatic discharge Typ ±1 Total power dissipation Thermal resistance QFN16 4x4mm 29.7 Tstrg Storage temperature -40 Low voltage pads Norm: Jedec 78 Norm: MIL 883 E method 3015 Human body model: R=1.5kΩ, C=100pF am lc s on A te G nt st il Ptot Rthja kV al id Parameter lv Symbol Tbody 33 1 W 36.3 K/W 150 ºC Soldering temperature 5 ºC 85 % Te ch ni ca Humidity non-condensing 260 Norm: IPC/JEDEC J-STD-020C. The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/JEDEC J-STD-020C “Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices”. www.austriamicrosystems.com/NSD-1202 Revision 0.2 3 - 13 NSD-1202 Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6 Electrical Characteristics Table 3. Operating Conditions Conditions Min VVDD Voltage at VDD VDD rise time is between 10µs and 100ms VVDDH Voltage at VDDH High voltage supply VLX Voltage at LX pin VVSSP Voltage at VSSP VVSS Max Units 2.8 5.5 V 24 40 V -0.6 VVDDH +0.3 V GND reference for step up converter -0.3 0.3 V Voltage at VSS GND reference potential 0 0 V VLV Voltage at CLK, SDA,SCL, XPD Low voltage pads -0.3 5.5 V TAMB Ambient temperature -40 6.1 Electrical System Specifications Parameter VDD 85 am lc s on A te G nt st il All system parameters are guaranteed up to 125ºC junction temperature unless explicitly mentioned. Table 4. Electrical System Specifications Typ al id Parameter lv Symbol Conditions ºC Min Typ Max Units 2.8 3.3 5.5 V Ambient temperature -40 +85 ºC Junction temperature -40 +125 ºC 5 μA Stand-by current consumption XPD=LOW, temp=27ºC; No activity on I²C interface and CLK static Operating current consumption XPD=HIGH, Step-up converter on but NOT RUNNING A MOTOR Output Voltage (VDDH) Default value is 35V after start-up 1.5 24 Output Voltage (VDDH) steps 0.5 Output Voltage accuracy -6 Hysteresis 0.325 Output current DC ca VIN=2.8V, Efficiency calculations assume the use of the components as specified in the Applications Description section (see page 6) 65 0.5 V V +6 % 0.675 V 25 mA % Te ch ni Efficiency 40 mA www.austriamicrosystems.com/NSD-1202 Revision 0.2 4 - 13 NSD-1202 Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6.2 DC/AC Characteristics for Digital Inputs and Outputs Table 5. CMOS Input: XPD, ADR, CLK Parameter VIH High level input voltage VIL Low level input voltage ILEAK Input leakage current CIN Capacitive Load Conditions Min Typ Max Units 1.2 VDD V VSS 0.3 V 1 µA Table 6. CMOS I²C Interface: SDA, SCL Parameter Min VIH High level input voltage 1.2 VIL Low level input voltage VSS ILEAK Input leakage current VOH High level output voltage Depending on external pull-up resistor VOL Low level output voltage @3mA output current CL Capacitive load: SDA, SCL RPU External pull-up resistor: SDA, SCL As defined by I²C spec SCL I²C write frequency Maximum clock frequency to write data VVDD -0.5 Typ pF Max Units VDD V 0.3 V 1 µA VVDD V VSS+0.4 V 50 pF 7.1 kΩ 400 kHz am lc s on A te G nt st il Conditions 15 lv Symbol al id Symbol 6.0 Te ch ni ca 1.2 www.austriamicrosystems.com/NSD-1202 Revision 0.2 5 - 13 NSD-1202 Data Sheet - D e t a i l e d D e s c r i p t i o n 7 Detailed Description Figure 1 shows the main building blocks of the system: Voltage reference Step up converter I²C interface al id Registers Selectable feedback Four (4) half bridge drivers lv Supplementary blocks such as biasing or power-on reset are not shown. The step-up converter is built as a hysteretic step-up converter. The half bridge drivers operate rail to rail (VSSP to VDDH). User supplied external components C1, C2, L1 and D1 provide voltage boost and regulation. The output voltage can be programmed via the I²C interface in 0.5V steps between 24V and 40V. This voltage, along with the duty cycle (or pulse width) of the drive signal, determines the speed of the motor. am lc s on A te G nt st il Registers define the switching frequency of the motor, which can be dynamically adjusted from 140 KHz to 180 KHz for optimum motor performance. Other registers control motor direction and the number of pulses the motor is active (correlating to distance traveled). The XPD input enables a stand-by mode. 7.1 Step Up Converter The internal switching converter, together with L1 and C2, form a step up DC/DC converter used to create the high level voltage VDDH in the range 24 to 40V. The switch includes an over-current detect circuit to ensure safe operation at all times. The output voltage can be programmed via I²C interface in steps of 0.5V from 24V to 40V. At power up the default output voltage is set to 35V. 7.2 I²C The I²C interface is used to control the NSD-1202 and set the value of several registers. These registers will define the output voltage (by changing the resistive feedback divider) as well as the direction and duration of the output driver signals. The period count. duty cycle (or pulse width) and pulse count registers can be set separately for each motor. Start/Stop Condition: A HIGH to LOW transition on the SDA line while SCL is HIGH is the start condition for the bus. A LOW to HIGH transition on the SDA line while SCL is HIGH is the stop condition. Every byte put on the SDA line must be 8-bits long. Each byte must be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first. Data transfer with acknowledge is obligatory. The acknowledge-related clock pulse is generated by the master. The receiver must pull down the SDA line during the acknowledge clock pulse. The NSD-1202 is a slave device on the bus. There are two different access modes: Te ch ni ca - Byte write - Page write The device can be addressed using 7-bit addressing. The first 6 bits are fixed. The last bit can be set via package pin. Provision will be made for data collision due to non-synchronization between the external clock and the internally generated clock. www.austriamicrosystems.com/NSD-1202 Revision 0.2 6 - 13 NSD-1202 Data Sheet - D e t a i l e d D e s c r i p t i o n 7.3 Register Map The table below shows the registers which can be addressed over the I²C interface. Data Byte Description Address Period count A 00h X X 01h h d Pulse count A (low byte) 02h X X X X X X Period count B 03h X X X X X X 04h h d Pulse count B (low byte) 05h X X Output voltage 06h Duty cycle A 07h Duty cycle B Reserved register X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X al id 1 X am lc s on A te G nt st il Pulse count B (high byte) 1 LSB lv Pulse count A (high byte) MSB 08h X X X X X X X X 10h X X X X X X X X 1. The master clock doubling bit (‘h’) of both registers 01h and 04h must set in order for the doubling to take affect (even if only driving one motor). Do not use clock doubling if the master clock has a frequency > 10 MHz. 7.4 Output Drivers The output drivers operate rail to rail and are capable of driving a large capacitive load. In power-down mode the output drivers are pulled to ground. The same applies when the motor is off. Symbol Parameter CLOAD Conditions Min Typ Max Units Rise/fall time CLOAD 600pF 25 100 250 ns Load capacitance The load capacitance may be lower than 500pF but the lower the value the shorter the rise time. 500 600 700 pF 140 170 180 kHz 0.98 1.45 1.61 kHz 1 50 % -1 +1 % Switching frequency Switching frequency step ca Switching frequency duty cycle Duty cycle accuracy Phase shift ni Phase shift error Clock doubling feature may be employed when using a 10MHz or less master clock frequency ±90 1 20 deg ±3 deg 20 MHz Te ch Master clock frequency (CLK) The accuracy of switching frequency and phase shift will be defined depending on master clock frequency; the given values are for 20MHz master clock. Lower master clock frequencies give higher deviations. For Squiggle applications 20MHz clock is required, 10 MHz can be used with the clock doubling feature. www.austriamicrosystems.com/NSD-1202 Revision 0.2 7 - 13 NSD-1202 Data Sheet - D e t a i l e d D e s c r i p t i o n 7.5 Period Counter The period counter is used to define the switching frequency of the motor. The pulse period is generated by dividing the clock input frequency by the given period counter value. The MSB of the high byte of the pulse counter (h) is used to enable the internal frequency doubler. This function should be used only for input clock frequencies of 10MHz or less. At 20MHz input clock a decimal period counter value of 111 gives an output frequency of 180.18 kHz. A period counter value of 112 results in a switching frequency of 178.75 kHz. This is equal to a maximum frequency step of 1.61 kHz. The frequency resolution gets better for lower output frequencies, assuming a fixed input clock frequency. Typ Unit 0110 1111 180.18 kHz 0111 0000 178.57 kHz 1000 0101 150.37 1000 0110 149.25 1000 1110 140.85 1000 1111 139.86 kHz kHz kHz am lc s on A te G nt st il 7.6 Pulse Counter lv Period Counter Value al id The following table presents examples of the period counter and output switching frequency relationship. The values are given for 20MHz and 10MHz clock input frequency. (At 10MHz the frequency doubler can be activated, which leads to the same results.) kHz The pulse counter sets the number of pulses the motor should be active. Writing all zeros to the pulse counter stops the motor, even if the previous set counter value is not completed. All outputs are then low. The same is valid for power-down mode. Bit 6 of the high byte in the pulse counter (d) is used to set the direction of motor motion. Pulse Counter Value Typ Unit Conditions XXXX X000 0000 0000 0 pulses Motor is off, driver outputs are low XXXX X100 0000 0000 1024 pulses XXXX X111 1111 1111 2047 pulses Maximum possible number of pulses 7.7 Output Voltage Register Typ Unit 0001 0001 24.0 V 0001 0010 24.5 V 0001 1111 31.0 V 0010 0111 35.0 V 0011 0000 39.5 V 0011 0001 40.0 V ch ca Output Voltage Register ni This register is used to define the output voltage of the boost converter. The register value is directly transferred to the analog part. The default value for this register set during power up or power down (XPD = LOW) is equal to 35V nominal output voltage. Conditions Default value Te Varying the output voltage can be used to vary the speed of the motor. However, if two motors are being driven, both motors use a common output voltage and therefore one setting applies to both motors. To control the speed of two motors independently, use the Duty Cycle Register. www.austriamicrosystems.com/NSD-1202 Revision 0.2 8 - 13 NSD-1202 Data Sheet - D e t a i l e d D e s c r i p t i o n 7.8 Duty Cycle Register A register is used to define the duty cycle (or pulse width) of the driver output signal for each motor. The register value is directly transferred to the analog part. Since changing the duty cycle will change the speed of the motor, this register can be used to control the speed of two motors independently. (Motor speed can also be controlled by varying the voltage; however, one setting applies to both motors. See the previous section, Output Voltage Register.) al id To provide motor independent speed control, the duty cycle may be adjusted from 50% (max speed) down to ~12% (minimum speed). A lower duty cycle could be used, but may not provide enough vibration amplitude to overcome the load. The default value for this register set during power up or power down (XPD = LOW) is equal to 00h. In this case the default duty cycle of 50% is generated. The resulting duty cycle and resolution of single steps is depending on the master clock frequency and the switching frequency of the driver output. Duty Cycle Register Min Typ 49.6/50.4 Max am lc s on A te G nt st il 0000 0000 lv In the following table an example for 20MHz clock input and 150kHz driver frequency is given. The value of the duty cycle register should not exceed 50% of the period counter value. Unit % 0.8 % 0000 1101 9.8 % 0001 1011 20.3 % 0010 1000 30.1 % 0011 0101 39.8 % 0100 0010 49.6 % 0100 0011 50.4 % Te ch ni ca 0000 0001 www.austriamicrosystems.com/NSD-1202 Revision 0.2 9 - 13 NSD-1202 Data Sheet - A p p l i c a t i o n I n f o r m a t i o n 8 Application Information The NSD-1202 is designed to drive two SQL-1.8 SQUIGGLE motors. Recommended external components are as follows: Description C1 22µF Cap 6.3V C2 1µF Cap 50V L1 4.7µH Inductance D1 Diode Manufacturer Part Number WxLxH [mm] GRM21BR60J226ME39 1.25x2.0x1.25 GRM21BR71H105KA12 1.25x2.0x1.25 www.coilcraft.com EPL2014-472 2.0x2.0x1.4 www.nxp.com PMEG6010CEJ 1.25x2.5x0.80 www.murata.com al id Component lv New Scale offers a convenient MC-33DB evaluation board which includes these components, along with input and motor connectors, to take full advantage of the NSD-1202 ASIC. VIN (2.8-5.5V) C1 VDD (2.8-5.5V) XPD L1 VDDH (programmable 24V...40V) 4.7µH 22µF Voltage referenc e VSS SDA SCL ADR am lc s on A te G nt st il The XPD input can be used to place the ASIC in stand-by mode for minimal current consumption when the motor is not moving. Alternatively, the designer can implement an external switch to power off the ASIC completely when the motor is not moving: the SQUIGGLE motor holds its position with the power off. I²C Interface C2 D1 LX Step-up controlle r VDDH DRV1P2 VSSP NSD-1202 Register s shifter DRV2P1 DRV2P1 Levelshifter 1 DRV2P2 Levelshifter 1 DRV1P1 Levelshifter 1 DRV1P2 DRV2P2 Te ch ni ca CLK DRV1P1 TRIM NSD-1202 Level-Motor Driver Dual Piezo 1 LOGI C 1µF www.austriamicrosystems.com/NSD-1202 Revision 0.2 10 - 13 NSD-1202 Data Sheet - P a c k a g e D r a w i n g s a n d M a r k i n g s 9 Package Drawings and Markings The devices are available in a 16LD QFN (4x4mm) package. 5 6 7 8 9 lv 4 al id Figure 3. 16LD QFN (4x4mm) Package Drawings and Dimensions 3 10 2 11 12 am lc s on A te G nt st il #1 Nom 0.85 0.203 REF 0.30 4.00 BSC 4.00 BSC 2.40 2.40 ni Min 0.75 0.25 ch Symbol A A1 b D E D2 E2 ca 16 0.35 2.50 2.50 Symbol e L L1 P aaa ccc Min 0.40 14 13 Nom 0.65 BSC 0.50 Max 0.60 0.10 45º BSC 0.15 0.10 Te 2.30 2.30 Max 0.95 15 Notes: 1. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 2. All dimensions are in millimeters, angle is in degrees. 3. Dimension b applies to metallized terminal and is measured between 0.25mm and 0.30mm from terminal tip. Dimension L1 represents terminal full back from package edge up to 0.1mm is acceptable. 4. Coplanarity applies to the exposed heat slug as well as the terminal. 5. Radius on terminal is optional. www.austriamicrosystems.com/NSD-1202 Revision 0.2 11 - 13 NSD-1202 Data Sheet - O r d e r i n g I n f o r m a t i o n 10 Ordering Information The devices are available as the standard products shown in Table 7. Table 7. Ordering Information Description Delivery Form Package NSD-1202BQFT Dual Piezo Motor Driver IC Tape & Reel QFN-16 (4x4mm) Note: All products are RoHS compliant and Pb-free. Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect Te ch ni ca am lc s on A te G nt st il lv For further information and requests, please contact us mailto:[email protected] or find your local distributor at http://www.austriamicrosystems.com/distributor al id Ordering Code www.austriamicrosystems.com/NSD-1202 Revision 0.2 12 - 13 NSD-1202 Data Sheet - C o p y r i g h t s Copyrights Copyright © 1997-2010, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. al id Disclaimer lv Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. Contact Information Headquarters am lc s on A te G nt st il The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. austriamicrosystems AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 ca For Sales Offices, Distributors and Representatives, please visit: ch ni http://www.austriamicrosystems.com/contact Te Contact Information New Scale Technologies, Inc. 121 Victor Heights Parkway Victor, NY 14564 Tel: +1 585 924 4450 Fax: +1 585 924 4468 [email protected] www.newscaletech.com www.austriamicrosystems.com/NSD-1202 Revision 0.2 13 - 13