NCP81161 VR12.5 Compatible Synchronous Buck MOSFET Drivers The NCP81161 is a high performance dual MOSFET gate driver optimized to drive the gates of both high−side and low−side power MOSFETs in a synchronous buck converter. It can drive up to 3 nF load with a 25 ns propagation delay and 20 ns transition time. Adaptive anti−cross−conduction and power saving operation circuit can provide a low switching loss and high efficiency solution for notebook and desktop systems. Bidirectional EN pin can provide a fault signal to controller when the gate driver fault detect under OVP, UVLO occur. Also, an under−voltage lockout function guarantees the outputs are low when supply voltage is low. http://onsemi.com 1 DFN8 MN SUFFIX CASE 506AA Features • • • • • • • • • • • • Faster Rise and Fall Times Adaptive Anti−Cross−Conduction Circuit Integrated Bootstrap Diode Pre OV function ZCD Detect Floating Top Driver Accommodates Boost Voltages of up to 35 V Output Disable Control Turns Off Both MOSFETs Under−voltage Lockout Power Saving Operation Under Light Load Conditions Direct Interface to NCP6151 and Other Compatible PWM Controllers Thermally Enhanced Package These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Typical Applications • Power Solutions for Desktop Systems © Semiconductor Components Industries, LLC, 2013 August, 2013 − Rev. 2 MARKING DIAGRAM 1 A4 M G A4MG G = Specific Device Code = Date Code = Pb−Free Device ORDERING INFORMATION Device Package Shipping† NCP81161MNTBG DFN8 3000 / Tape & Reel (Pb−Free) NCP81161MNTWG DFN8 3000 / Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 1 Publication Order Number: NCP81161/D NCP81161 BST DRVH 1 PWM SW FLAG 9 EN GND VCC DRVL (Top View) Figure 1. Pin Diagram BST VCC DRVH PWM Logic SW Anti−Cross Conduction VCC DRVL EN Fault ZCD Detection UVLO Pre−OV Figure 2. Block Diagram Table 1. Pin Descriptions Pin No. Symbol Description 1 BST Floating bootstrap supply pin for high side gate driver. Connect the bootstrap capacitor between this pin and the SW pin. 2 PWM Control input. The PWM signal has three distinctive states: Low = Low Side FET Enabled, Mid = Diode Emulation Enabled, High = High Side FET Enabled. 3 EN 4 VCC Power supply input. Connect a bypass capacitor (0.1 mF) from this pin to ground. 5 DRVL Low side gate drive output. Connect to the gate of low side MOSFET. 6 GND Bias and reference ground. All signals are referenced to this node (QFN Flag). 7 SW 8 DRVH High side gate drive output. Connect to the gate of high side MOSFET. 9 FLAG Thermal flag. There is no electrical connection to the IC. Connect to ground plane. Logic input. A logic high to enable the part and a logic low to disable the part. Switch node. Connect this pin to the source of the high side MOSFET and drain of the low side MOSFET. http://onsemi.com 2 NCP81161 12V_POWER TP1 R164 R1 1.02 R143 0.0 TP4 PWM C4 0.027uF HG PWM SW DRON TP2 0.0 NCP81161TP3 BST EN LG C1 4.7uF C2 4.7uF + CE9 390uF 0.0 VREG_SW1_HG TP5 TP6 235nH TP7 Q9 NTMFS4851N VREG_SW1_LG VCCP L VREG_SW1_OUT Q10 NTMFS4851N R3 2.2 JP13_ETCH CSN11 PAD TP8 C5 1uF C3 4.7uF R142 GND VCC Q1 NTMFS4821N C6 2700pF JP14_ETCH CSP11 Figure 3. Application Circuit Table 2. ABSOLUTE MAXIMUM RATINGS Pin Symbol Pin Name VMAX VMIN VCC Main Supply Voltage Input 15 V −0.3 V BST Bootstrap Supply Voltage 35 V wrt/ GND 40 V ≤ 50 ns wrt/ GND 15 V wrt/ SW −0.3 V wrt/SW SW Switching Node (Bootstrap Supply Return) 35 V 40 V ≤ 50 ns −5 V −10 V (200 ns) DRVH High Side Driver Output BST+0.3 V −0.3 V wrt/SW −2 V (<200 ns) wrt/SW DRVL Low Side Driver Output VCC+0.3 V −0.3 V DC −5 V (<200 ns) PWM DRVH and DRVL Control Input 6.5 V −0.3 V EN Enable Pin 6.5 V −0.3 V GND Ground 0V 0V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 3. THERMAL INFORMATION (All signals referenced to AGND unless noted otherwise) Symbol RqJA Parameter Thermal Characteristic (Note 1) Value Unit 74 °C/W 0 to 150 °C TJ Operating Junction Temperature Range (Note 2) TA Operating Ambient Temperature Range −10 to +125 °C TSTG Maximum Storage Temperature Range −55 to +150 °C MSL Moisture Sensitivity Level 1 * The maximum package power dissipation must be observed. 1. I in2 Cu, 1 oz thickness. 2. Operation at −40°C to −10°C guaranteed by design, not production tested. http://onsemi.com 3 NCP81161 Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise stated: −10°C < TA < +125°C; 4.5 V < VCC < 13.2 V, 4.5 V < BST−SWN < 13.2 V, 4.5 V < BST < 30 V, 0 V < SWN < 21 V) Parameter Test Conditions Min. Typ. Max. Units 13.2 V 3.2 V SUPPLY VOLTAGE 4.5 VCC Operation Voltage Power ON Reset Threshold 2.75 UNDERVOLTAGE LOCKOUT VCC Start Threshold 3.8 4.35 4.5 V VCC UVLO Hysteresis 150 200 250 mV 2.1 2.25 2.4 V Output Overvoltage Trip Threshold at Startup Power Startup time, VCC > POR SUPPLY CURRENT Normal Mode Icc + Ibst, EN = 5 V, PWM = OSC, Fsw = 100 KHz, Cload = 3 nF for DRVH, 3 nF for DRVL 10 mA Standby Current Icc + Ibst, EN = GND 0.5 Standby Current ICC + IBST, EN = HIGH, PWM = LOW, No loading on DRVH & DRVL 2.0 mA Standby Current ICC + IBST, EN = HIGH, PWM = HIGH, No loading on DRVH & DRVL 2.0 mA 1.4 mA BOOTSTRAP DIODE Forward Voltage VCC = 12 V, forward bias current = 2 mA 0.1 0.4 0.6 V PWM INPUT PWM Input High 3.4 PWM Mid−State 1.3 V PWM Input Low ZCD Blanking Timer 2.7 V 0.7 V 250 ns HIGH SIDE DRIVER (VCC = 12 V) Output Impedance, Sourcing Current VBST − VSW = 12 V 1.9 3.0 W Output Impedance, Sinking Current VBST − VSW = 12 V 1.0 1.7 W DRVH Rise Time trDRVH VVCC = 12 V, 3 nF load, VBST−VSW = 12 V 16 30 ns DRVH Fall Time tfDRVH VVCC = 12 V, 3 nF load, VBST−VSW = 12 V 11 25 ns DRVH Turn−Off Propagation Delay tpdlDRVH CLOAD = 3 nF 30 ns DRVH Turn−On Propagation Delay tpdhDRVH CLOAD = 3 nF 30 ns SW Pull Down Resistance SW to PGND 45 kW DRVH Pull Down Resistance DRVH to SW, BST−SW = 0 V 45 kW Output Impedance, Sourcing Current VBST − VSW = 5 V 2.5 W Output Impedance, Sinking Current VBST − VSW = 5 V 1.6 W DRVH Rise Time trDRVH VVCC = 5 V, 3 nF load, VBST − VSW = 5 V 30 ns DRVH Fall Time tfDRVH VVCC = 5 V, 3 nF load, VBST − VSW = 5 V 27 ns DRVH Turn−Off Propagation Delay tpdlDRVH CLOAD = 3 nF 20 ns DRVH Turn−On Propagation Delay tpdhDRVH CLOAD = 3 nF 27 ns SW Pull Down Resistance SW to PGND 45 kW 8.0 HIGH SIDE DRIVER (VCC = 5 V) http://onsemi.com 4 NCP81161 Table 4. ELECTRICAL CHARACTERISTICS (Unless otherwise stated: −10°C < TA < +125°C; 4.5 V < VCC < 13.2 V, 4.5 V < BST−SWN < 13.2 V, 4.5 V < BST < 30 V, 0 V < SWN < 21 V) Parameter Test Conditions Min. Typ. Max. Units HIGH SIDE DRIVER (VCC = 5 V) DRVH Pull Down Resistance DRVH to SW, BST−SW = 0 V 45 kW LOW SIDE DRIVER (VCC = 12 V) Output Impedance, Sourcing Current Output Impedance, Sinking Current 2.0 3.0 W 0.7 1.5 W DRVL Rise Time trDRVL CLOAD = 3 nF 16 35 ns DRVL Fall Time tfDRVL CLOAD = 3 nF 11 20 ns DRVL Turn−Off Propagation Delay tpdlDRVL CLOAD = 3 nF 35 ns DRVL Turn−On Propagation Delay tpdhDRVL CLOAD = 3 nF 30 ns DRVL Pull Down Resistance DRVL to PGND, VCC = PGND 8.0 45 kW Output Impedance, Sourcing Current 2.5 W Output Impedance, Sinking Current 1.0 W LOW SIDE DRIVER (VCC = 5 V) DRVL Rise Time trDRVL CLOAD = 3 nF 30 ns DRVL Fall Time tfDRVL CLOAD = 3 nF 22 ns DRVL Turn−Off Propagation Delay tpdlDRVL CLOAD = 3 nF 27 ns DRVL Turn−On Propagation Delay tpdhDRVL CLOAD = 3 nF 12 ns DRVL Pull Down Resistance DRVL to PGND, VCC = PGND 45 kW EN INPUT Input Voltage High 2.0 V Input Voltage Low 1.0 Hysteresis V 500 mV Normal Mode Bias Current −1 1 mA Enable Pin Sink Current 4 30 mA 40 ns Propagation Delay Time 20 SW Node SW Node Leakage Current Zero Cross Detection Threshold Voltage 20 SW to −20 mV, ramp slowly until BG goes off (Start in DCM mode) (Note 3) mA −6 mV Table 5. DECODER TRUTH TABLE PWM INPUT ZCD DRVL DRVH PWM High ZCD Reset Low High PWM Mid Positive current through the inductor High Low PWM Mid Zero current through the inductor Low Low PWM Low ZCD Reset High Low 3. Guaranteed by design; not production tested. http://onsemi.com 5 NCP81161 1V 1V Figure 4. PWM DRVH−SW DRVL IL Figure 5. Timing Diagram http://onsemi.com 6 NCP81161 APPLICATIONS INFORMATION The NCP81161 gate driver is a single phase MOSFET driver designed for driving N−channel MOSFETs in a synchronous buck converter topology. The NCP81161 is designed to work with ON Semiconductor’s NCP6131 multi−phase controller. This gate driver is optimized for desktop applications. turn on of the high–side MOSFET. When the PWM pull low, gate DRVH will go low after the propagation delay (tpd DRVH). The time to turn off the high side MOSFET is depending on the total gate charge of the high−side MOSFET. A timer will be triggered once the high side MOSFET is turn off to delay the turn on the low−side MOSFET. Undervoltage Lockout The DRVH and DRVL are held low until VCC reaches 4.5 V during startup. The PWM signals will control the gate status when VCC threshold is exceeded. If VCC decreases to 250 mV below the threshold, the output gate will be forced low until input voltage VCC rises above the startup threshold. Low−Side Driver Timeout In normal operation, the DRVH signal tracks the PWM signal and turns off the Q1 high−side switch with a few 10 ns delay (tpdlDRVH) following the falling edge of the input signal. When Q1is turned off, DRVL is allowed to go high, Q2 turns on, and the SW node voltage collapses to zero. But in a fault condition such as a high−side Q1 switch drain−source short circuit, the SW node cannot fall to zero, even when DRVH goes low. This driver has a timer circuit to address this scenario. Every time the PWM goes low, a DRVL on−time delay timer is triggered. If the SW node voltage does not trigger a low−side turn−on, the DRVL on−time delay circuit does it instead, when it times out with tSW(TO) delay. If Q1 is still turned on, that is, its drain is shorted to the source, Q2 turns on and creates a direct short circuit across the VDCIN voltage rail. The crowbar action causes the fuse in the VDCIN current path to open. The opening of the fuse saves the load (CPU) from potential damage that the high−side switch short circuit could have caused. Power−On Reset Power−On Reset feature is used to protect a gate driver avoid abnormal status driving the startup condition. When the initial soft−start voltage is higher than 2.75 V, the gate driver will monitor the switching node SW pin. If SW pin high than 2.25 V, bottom gate will be force to high for discharge the output capacitor. The fault mode will be latch and EN pin will force to be low, unless the driver is recycle. When input voltage is higher than 4.5 V, and EN goes high, the gate driver will normal operation, top gate driver DRVH and bottom gate driver will follow the PWM signal decode to a status. Bi−directional EN Signal Fault modes such as Power−On Reset and Undervoltage Lockout will de−assert the EN pin, which will pull down the DRON pin of controller as well. Thus the controller will be shut down consequently. Layout Guidelines Layout for DC−DC converter is very important. The bootstrap and VCC bypass capacitors should be placed as close as to the driver IC. Connect GND pin to local ground plane. The ground plane can provide a good return path for gate drives and reduce the ground noise. The thermal slug should be tied to the ground plane for good heat dissipation. To minimize the ground loop for low side MOSFET, the driver GND pin should be close to the low−side MOSFET source pin. The gate drive trace should be routed to minimize the length, the minimum width is 20 mils. PWM Input and Zero Cross Detect (ZCD) The PWM input, along with EN and ZCD, control the state of DRVH and DRVL. When PWM is set high, DRVH will be set high after the adaptive non−overlap delay. When PWM is set low, DRVL will be set high after the adaptive non−overlap delay. When the PWM is set to the mid state, DRVH will be set low, and after the adaptive non−overlap delay, DRVL will be set high. DRVL remains high during the ZCD blanking time. When the timer is expired, the SW pin will be monitored for zero cross detection. After the detection, the DRVL will be set low. Gate Driver Power Loss Calculation The gate driver power loss consists of the gate drive loss and quiescent power loss. The equation below can be used to calculate the power dissipation of the gate driver. Where QGMF is the total gate charge for each main MOSFET and QGSF is the total gate charge for each synchronous MOSFET. Adaptive Nonoverlap The nonoverlap dead time control is used to avoid the shoot through damage the power MOSFETs. When the PWM signal pull high, DRVL will go low after a propagation delay, the controller will monitors the switching node (SWN) pin voltage and the gate voltage of the MOSFET to know the status of the MOSFET. When the low side MOSFET status is off an internal timer will delay PDRV + [ 2 fSW n ǒn MF QGMF ) n SF QGSFǓ ) ICC] VCC Also shown is the standby dissipation factor (ICC ⋅ VCC) of the driver. http://onsemi.com 7 NCP81161 PACKAGE DIMENSIONS DFN8 2x2 CASE 506AA ISSUE E D PIN ONE REFERENCE 2X 0.15 C 2X A B DETAIL A E OPTIONAL CONSTRUCTIONS DIM A A1 A3 b D D2 E E2 e K L L1 ÉÉ ÉÉ EXPOSED Cu TOP VIEW A DETAIL B 0.10 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 . 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L1 ÇÇ ÇÇ 0.15 C L MOLD CMPD DETAIL B OPTIONAL CONSTRUCTION 0.08 C (A3) NOTE 4 SIDE VIEW DETAIL A A1 D2 1 4 C 8X SEATING PLANE MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 1.10 1.30 2.00 BSC 0.70 0.90 0.50 BSC 0.30 REF 0.25 0.35 −−− 0.10 RECOMMENDED SOLDERING FOOTPRINT* L 1.30 PACKAGE OUTLINE 8X 0.50 E2 0.90 K 8 5 e/2 e 8X b 1 0.10 C A B 0.05 C 2.30 8X NOTE 3 0.30 BOTTOM VIEW 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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