IS62LV1024L IS62LV1024L/LL IS62LV1024LL 128K x 8 LOW POWER and LOW Vcc CMOS STATIC RAM FEATURES Access times of 45, 55, and 70 ns Low active power: 60 mW (typical) Low standby power: 15 µW (typical) CMOS standby Low data retention voltage: 2V (min.) Available in Low Power (-L) and Ultra Low Power (-LL) Output Enable (OE) and two Chip Enable (CE1 and CE2) inputs for ease in applications TTL compatible inputs and outputs Single 2.7V to 3.6V power supply DESCRIPTION The 1+51 IS62LV1024L and IS62LV1024LL are low power and low Vcc,131,072-word by 8-bit CMOS static RAMs. They are fabricated using 1+51's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced by using CMOS input levels. Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS62LV1024L and IS62LV1024LL are available in 32-pin 8*20mm TSOP-1, 8*13.4mm TSOP-1, 450mil SOP and 48-pin 6*8mm TF-BGA. FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 512 X 2048 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VCC GND I/O0-I/O7 CE1 CE2 OE WE CONTROL CIRCUIT ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. Integrated Circuit Solution Inc. LPSR018-0D 07/06/2001 1 IS62LV1024L/LL PIN CONFIGURATION PIN CONFIGURATION 32-Pin SOP 32-Pin 8x20mm TSOP-1 and 8x13.4mm TSOP-1 NC 1 32 VCC A16 2 31 A15 A14 3 30 CE2 A12 4 29 WE A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 OE A2 10 23 A10 A1 11 22 CE1 A0 12 21 I/O7 I/O0 13 20 I/O6 I/O1 14 19 I/O5 I/O2 15 18 I/O4 GND 16 17 I/O3 A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48-Pin 6x8mm TF-BGA OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 PIN DESCRIPTIONS A0-A16 Address Inputs CE1 Chip Enable 1 Input 1 2 3 4 5 6 CE2 Chip Enable 2 Input A A0 A1 CE2 A3 A6 A8 OE Output Enable Input B I/O5 A2 WE A4 A7 I/O1 WE Write Enable Input C I/O6 NC A5 I/O2 I/O0-I/O7 Input/Output D GND Vcc NC No Connection E Vcc GND Vcc Power F I/O7 I/O3 GND Ground G I/O8 H A9 NC NC OE CE1 A16 A15 I/O4 A10 A11 A12 A13 A14 OPERATING RANGE Range Commercial Industrial 2 Ambient Temperature 0°C to +70°C VCC 2.7V to 3.6V 40°C to +85°C 2.7V to 3.6V Integrated Circuit Solution Inc. LPSR018-0D 07/06/2001 IS62LV1024L/LL TRUTH TABLE Mode Not Selected (Power-down) Output Disabled Read Write WE CE1 CE2 OE X X H H L H X L L L X L H H H X X H L X I/O Operation High-Z High-Z High-Z DOUT DIN Vcc Current ISB, ISB ISB, ISB ICC ICC ICC ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM VCC TBIAS TSTG PT Parameter Terminal Voltage with Respect to GND Vcc related to GND Temperature Under Bias Storage Temperature Power Dissipation Value 0.5 to Vcc + 0.5 0.3 to +4.6 40 to +85 65 to +150 0.7 Unit V V °C °C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1,2) Symbol Parameter CIN Input Capacitance COUT Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.0V. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH VOL VIH VIL ILI ILO Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage VCC = Min., IOH = 1.0 mA VCC = Min., IOL = 2.1 mA 2.2 2.2 0.3 1 1 0.4 VCC + 0.3 0.4 1 1 V V V V µA µA GND ≤ VIN ≤ VCC GND ≤ VOUT ≤ VCC Notes: 1. VIL = 3.0V for pulse width less than 10 ns. Integrated Circuit Solution Inc. LPSR018-0D 07/06/2001 3 IS62LV1024L/LL IS62LV1024L POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -45L ns Min. Max. -55L ns Min. Max. -70L ns Min. Max. Symbol Parameter Test Conditions Unit ICC Vcc Dynamic Operating Supply Current VCC = Max., CE = VIL IOUT = 0 mA, f = fMAX Com. Ind. 40 45 35 40 30 35 mA ISB TTL Standby Current (TTL Inputs) VCC = Max., Com. VIN = VIH or VIL, CE1 ≥ VIH Ind. or CE2 ≤ VIL, f = 0 0.3 0.4 0.3 0.4 0.3 0.4 mA ISB CMOS Standby Current (CMOS Inputs) VCC = Max., f = 0 Com. CE1 ≥ VCC 0.2V, Ind. CE2 ≤ 0.2V, or VIN ≥ VCC 0.2V, VIN ≤ 0.2V 50 75 50 75 50 75 µA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. IS62LV1024LL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -45LL ns Min. Max. -55LL ns Min. Max. -70LL ns Min. Max. Symbol Parameter Test Conditions Unit ICC Vcc Dynamic Operating Supply Current VCC = Max., CE = VIL IOUT = 0 mA, f = fMAX Com. Ind. 40 45 35 40 30 35 mA ISB TTL Standby Current (TTL Inputs) VCC = Max., Com. VIN = VIH or VIL, CE1 ≥ VIH Ind. or CE2 ≤ VIL, f = 0 0.2 0.3 0.2 0.3 0.2 0.3 mA ISB CMOS Standby Current (CMOS Inputs) VCC = Max., f = 0 Com. CE1 ≥ VCC 0.2V, Ind. CE2 ≤ 0.2V, or VIN ≥ VCC 0.2V, VIN ≤ 0.2V 5 10 5 10 5 10 µA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 4 Integrated Circuit Solution Inc. LPSR018-0D 07/06/2001 IS62LV1024L/LL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -45 Symbol Parameter -55 -70 Min. Max. Min. Max. Min. Max. Unit tRC Read Cycle Time 45 55 70 ns tAA Address Access Time 45 55 70 ns tOHA Output Hold Time 10 10 10 ns tACE CE1 Access Time 45 55 70 ns tACE CE2 Access Time 45 55 70 ns OE Access Time 20 25 35 ns OE to Low-Z Output 0 5 5 ns OE to High-Z Output 0 15 0 20 0 25 ns tLZCE CE1 to Low-Z Output 5 7 10 ns tLZCE CE2 to Low-Z Output 5 7 10 ns CE1 or CE2 to High-Z Output 0 15 0 20 0 25 ns tDOE tLZOE tHZOE tHZCE Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to 2.2V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0.4V to 2.2V 5 ns 1.5V See Figures 1 AC TEST LOADS 1 TTL OUTPUT 1 TTL OUTPUT 100 pF Including jig and scope Figure 1. Integrated Circuit Solution Inc. LPSR018-0D 07/06/2001 5 pF Including jig and scope Figure 2. 5 IS62LV1024L/LL AC WAVEFORMS READ CYCLE NO. 1(1,2) tRC ADDRESS tAA tOHA tOHA DOUT DATA VALID READ CYCLE NO. 2(1,3) tRC ADDRESS tAA tOHA OE tDOE CE1 tHZOE tLZOE tACE1/tACE2 CE2 DOUT tLZCE1/ tLZCE2 HIGH-Z tHZCE DATA VALID Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions. 6 Integrated Circuit Solution Inc. LPSR018-0D 07/06/2001 IS62LV1024L/LL WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range, Standard and Low Power) -45 Symbol Parameter -55 -70 Min. Max. Min. Max. Min. Max. Unit tWC Write Cycle Time 45 55 70 ns tSCE CE1 to Write End 35 50 60 ns tSCE CE2 to Write End 35 50 60 ns tAW Address Setup Time to Write End 35 50 60 ns tHA Address Hold from Write End 0 0 0 ns Address Setup Time 0 0 0 ns tPWE WE Pulse Width 35 40 55 ns tSD Data Setup to Write End 25 25 30 ns tSA " tHD Data Hold from Write End 0 0 0 ns tHZWE WE LOW to High-Z Output 15 20 0 25 ns tLZWE WE HIGH to Low-Z Output 5 5 5 ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to 2.2V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 4. Tested with OE HIGH. AC WAVEFORMS WRITE CYCLE NO. 1 (99- Controlled)(1,2) tWC ADDRESS tHA tSCE1 CE1 tSCE2 CE2 tAW tPWE(4) WE tSA DOUT DATA UNDEFINED tHZWE tLZWE HIGH-Z tSD DIN Integrated Circuit Solution Inc. LPSR018-0D 07/06/2001 tHD DATA-IN VALID 7 IS62LV1024L/LL WRITE CYCLE NO. 2 (+- +-, CE2 Controlled)(1,2) +- tWC ADDRESS tSA tHA tSCE1 CE1 tSCE2 CE2 tAW tPWE(4) WE tHZWE DOUT tLZWE HIGH-Z DATA UNDEFINED tHD tSD DIN DATA-IN VALID Notes: 1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE = VIH. DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Test Condition Min. Max. Unit VDR Vcc for Data Retention See Data Retention Waveform 2.0 3.6 V IDR Data Retention Current Vcc = 2.0V, CE1 ≥ Vcc 0.2V 30 5 50 10 µA µA µA µA tSDR Data Retention Setup Time See Data Retention Waveform 0 ns tRDR Recovery Time See Data Retention Waveform tRC ns Com. (-L) Com. (-LL) Ind. (-L) Ind. (-LL) DATA RETENTION WAVEFORM (+- +- Controlled) tSDR 3.0V 2.2V tRDR VCC VDR CE1 GND 8 Data Retention Mode CE1 ≥ VCC - 0.2V Integrated Circuit Solution Inc. LPSR018-0D 07/06/2001 IS62LV1024L/LL DATA RETENTION WAVEFORM (CE2 Controlled) Data Retention Mode 3.0V VCC tSDR CE2 2.2V tRDR VDR CE2 ≤ 0.2V 0.4V GND IS62LV1024L ORDERING INFORMATION Commercial Range: 0°C to +70°C IS62LV1024L ORDERING INFORMATION Industrial Range: 40°C to +85°C Speed (ns) Order Part No. Speed (ns) Order Part No. Package Package 45 IS62LV1024L-45Q IS62LV1024L-45T IS62LV1024L-45H IS62LV1024L-45B 450mil SOP 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm TF-BGA 45 IS62LV1024L-45QI IS62LV1024L-45TI IS62LV1024L-45HI IS62LV1024L-45BI 450mil SOP 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm TF-BGA 55 IS62LV1024L-55Q IS62LV1024L-55T IS62LV1024L-55H IS62LV1024L-55B 450mil SOP 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm TF-BGA 55 IS62LV1024L-55QI IS62LV1024L-55TI IS62LV1024L-55HI IS62LV1024L-55BI 450mil SOP 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm TF-BGA 70 IS62LV1024L-70Q IS62LV1024L-70T IS62LV1024L-70H IS62LV1024L-70B 450mil SOP 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm TF-BGA 70 IS62LV1024L-70QI IS62LV1024L-70TI IS62LV1024L-70HI IS62LV1024L-70BI 450mil SOP 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm TF-BGA Integrated Circuit Solution Inc. LPSR018-0D 07/06/2001 9 IS62LV1024L/LL IS62LV1024LL ORDERING INFORMATION Commercial Range: 0°C to +70°C IS62LV1024LL ORDERING INFORMATION Industrial Range: 40°C to +85°C Speed (ns) Order Part No. Speed (ns) Order Part No. Package Package 45 IS62LV1024LL-45Q IS62LV1024LL-45T IS62LV1024LL-45H IS62LV1024LL-45B 450mil SOP 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm TF-BGA 45 IS62LV1024LL-45QI IS62LV1024LL-45TI IS62LV1024LL-45HI IS62LV1024LL-45BI 450mil SOP 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm TF-BGA 55 IS62LV1024LL-55Q IS62LV1024LL-55T IS62LV1024LL-55H IS62LV1024LL-55B 450mil SOP 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm TF-BGA 55 IS62LV1024LL-55QI IS62LV1024LL-55TI IS62LV1024LL-55HI IS62LV1024LL-55BI 450mil SOP 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm TF-BGA 70 IS62LV1024LL-70Q IS62LV1024LL-70T IS62LV1024LL-70H IS62LV1024LL-70B 450mil SOP 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm TF-BGA 70 IS62LV1024LL-70QI IS62LV1024LL-70TI IS62LV1024LL-70HI IS62LV1024LL-70BI 450mil SOP 8*20mm TSOP-1 8*13.4mm TSOP-1 6*8mm TF-BGA Integrated Circuit Solution Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw 10 Integrated Circuit Solution Inc. LPSR018-0D 07/06/2001