Cypress CY7C1353G-133AXC 4-mbit (256k x 18) flow-through sram with noblâ ¢ architecture Datasheet

CY7C1353G
4-Mbit (256K x 18) Flow-through SRAM
with NoBL™ Architecture
Functional Description[1]
Features
• Supports up to 133-MHz bus operations with zero wait
states
— Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self timed output buffer control to eliminate the
need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
The CY7C1353G is a 3.3V, 256K x 18 Synchronous
Flow-through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1353G is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to
enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
• 256K x 18 common IO architecture
• 2.5V/3.3V IO power supply (VDDQ)
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
Write operations are controlled by the two Byte Write Select
(BW[A:B]) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self timed write circuitry.
• Clock Enable (CEN) pin to suspend operation
• Synchronous self timed writes
• Asynchronous Output Enable
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
• Available in Pb-free 100-Pin TQFP package
• Burst Capability — linear or interleaved burst order
• Low standby power
Logic Block Diagram
ADDRESS
REGISTER
A0, A1, A
A1
D1
A0
D0
MODE
CLK
CEN
C
CE
ADV/LD
C
BURST
LOGIC
Q1 A1'
A0'
Q0
WRITE ADDRESS
REGISTER
ADV/LD
BWA
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BWB
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
WE
OE
CE1
CE2
CE3
ZZ
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQPA
DQPB
E
INPUT
E
REGISTER
READ LOGIC
SLEEP
CONTROL
Note:
1.For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05515 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 09, 2007
CY7C1353G
Selection Guide
133 MHz
6.5
225
40
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
100 MHz
8.0
205
40
Unit
ns
mA
mA
Pin Configuration
1
VDDQ
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
4
5
6
7
8
9
WE
CEN
OE
ADV/LD
NC/18M
88
87
86
85
84
A
CLK
89
81
VSS
90
NC/9M
VDD
91
A
CE3
92
82
BWA
93
83
NC
NC
96
BWB
CE2
97
94
A
CE1
99
98
A
95
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
2
3
10
11
12
13
14
15
16
17
18
19
CY7C1353G
20
21
22
23
24
25
57
56
26
27
55
54
53
52
51
28
29
Document #: 38-05515 Rev. *E
47
48
49
50
A
A
A
A
41
46
40
VSS
VDD
45
39
NC/144M
A
38
NC/288M
A
37
A0
A
36
A1
44
35
A
43
34
A
NC/36M
33
A
42
32
A
NC/72M
31
30
MODE
BYTE B
NC
NC
NC
100
100-Pin TQFP Pinout
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
BYTE A
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
NC
NC
Page 2 of 13
CY7C1353G
Pin Definitions
Name
IO
Description
A0, A1, A
InputAddress Inputs used to select one of the 256K address locations. Sampled at the rising edge
Synchronous of the CLK. A[1:0] are fed to the two-bit burst counter.
BW[A:B]
InputByte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
Synchronous the rising edge of CLK.
WE
InputWrite Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
Synchronous signal must be asserted LOW to initiate a write sequence.
ADV/LD
InputAdvance/Load Input. Used to advance the on-chip address counter or load a new address. When
Synchronous HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new
address can be loaded into the device for an access. After being deselected, ADV/LD must be
driven LOW to load a new address.
CLK
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK
is only recognized if CEN is active LOW.
CE1
InputChip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE2, and CE3 to select/deselect the device.
CE2
InputChip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE3 to select/deselect the device.
CE3
InputChip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE2 to select/deselect the device.
OE
InputOutput Enable, asynchronous input, Active LOW. Combined with the synchronous logic block
Asynchronous inside the device to control the direction of the IO pins. When LOW, the IO pins are allowed to
behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data pins. OE
is masked during the data portion of a write sequence, during the first clock when emerging from
a deselected state, when the device has been deselected.
CEN
InputClock Enable Input, Active LOW. When asserted LOW the Clock signal is recognized by the
Synchronous SRAM. When deasserted HIGH the Clock signal is masked. While deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
ZZ
InputZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
Asynchronous with data integrity preserved. During normal operation, this pin has to be low or left floating. ZZ pin
has an internal pull down.
DQs
IOBidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered by
Synchronous the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by address during the clock rise of the read cycle. The direction of the pins is controlled by OE and
the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH,
DQs and DQP[A:B] are placed in a tri-state condition. The outputs are automatically tri-stated during
the data portion of a write sequence, during the first clock when emerging from a deselected state,
and when the device is deselected, regardless of the state of OE.
DQP[A:B]
IOBidirectional Data Parity IO Lines. Functionally, these signals are identical to DQs. During write
Synchronous sequences, DQP[A:B] is controlled by BWx correspondingly.
MODE
VDD
VDDQ
VSS
NC,NC/9M,
NC/18M,
NC/36M
NC/72M,
NC/144M,
NC/288M,
Input
Strap Pin
MODE Input. Selects the burst order of the device.
When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects interleaved
burst sequence.
Power Supply Power supply inputs to the core of the device.
IO Power
Supply
Ground
–
Power supply for the IO circuitry.
Ground for the device.
No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/72M, NC/144M, NC/288M,
are address expansion pins are not internally connected to the die.
Document #: 38-05515 Rev. *E
Page 3 of 13
CY7C1353G
Functional Overview
The CY7C1353G is a synchronous flow-through burst SRAM
designed specifically to eliminate wait states during
Write-Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. Maximum access delay from the clock
rise (tCDV) is 6.5 ns (133-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device is latched. The access
can either be a read or write operation, depending on the
status of the Write Enable (WE). BW[A:B] can be used to
conduct byte write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipe lined.
ADV/LD must be driven LOW after the device has been
deselected to load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and 4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory array
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within 6.5
ns (133-MHz device) provided OE is active LOW. After the first
clock of the read access, the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output is tri-stated
immediately.
Burst Read Accesses
The CY7C1353G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW to load a new address into the SRAM, as
described in the Single Read Access section. The sequence
of the burst counter is determined by the MODE input signal.
A LOW input on MODE selects a linear burst mode, a HIGH
selects an interleaved burst sequence. Both burst counters
use A0 and A1 in the burst sequence, and wraps around when
incremented sufficiently. A HIGH input on ADV/LD increments
the internal burst counter regardless of the state of chip enable
inputs or WE. WE is latched at the beginning of a burst cycle.
Document #: 38-05515 Rev. *E
Therefore, the type of access (Read or Write) is maintained
throughout the burst sequence.
Single Write Accesses
Write access are initiated when these conditions are satisfied
at clock rise:
• CEN is asserted LOW
• CE1, CE2, and CE3 are ALL asserted active
• The write signal WE is asserted LOW.
The address presented to the address bus is loaded into the
Address Register. The write signals are latched into the
Control Logic block. The data lines are automatically tri-stated
regardless of the state of the OE input signal. This allows the
external logic to present the data on DQs and DQP[A:B].
On the next clock rise the data presented to DQs and DQP[A:B]
(or a subset for byte write operations, see truth table for
details) inputs is latched into the device and the write is
complete. Additional accesses (Read/Write/Deselect) can be
initiated on this cycle.
The data written during the Write operation is controlled by
BW[A:B] signals. The CY7C1353G provides byte write
capability that is described in the truth table. Asserting the
Write Enable input (WE) with the selected Byte Write Select
input selectively writes to only the desired bytes. Bytes not
selected during a byte write operation remains unaltered. A
synchronous self timed write mechanism has been provided
to simplify the write operations. Byte write capability has been
included to greatly simplify Read/Modify/Write sequences,
which can be reduced to simple byte write operations.
Because the CY7C1353G is a common IO device, data must
not be driven into the device while the outputs are active. The
Output Enable (OE) can be deasserted HIGH before
presenting data to the DQs and DQP[A:B] inputs. Doing so
tri-states the output drivers. As a safety precaution, DQs and
DQP[A:B].are automatically tri-stated during the data portion of
a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1353G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD must be driven LOW to load the initial address, as
described in the Single Write Access section. When ADV/LD
is driven HIGH on the subsequent clock rise, the Chip Enables
(CE1, CE2, and CE3) and WE inputs are ignored and the burst
counter is incremented. The correct BW[A:B] inputs must be
driven in each cycle of the burst write, to write the correct bytes
of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive
for the duration of tZZREC after the ZZ input returns LOW.
Page 4 of 13
CY7C1353G
Interleaved Burst Address Table
(MODE = Floating or VDD)
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
IDDZZ
Sleep mode standby current
ZZ > VDD − 0.2V
tZZS
Device operation to ZZ
ZZ > VDD − 0.2V
tZZREC
ZZ recovery time
ZZ < 0.2V
tZZI
ZZ active to sleep current
This parameter is sampled
tRZZI
ZZ inactive to exit sleep current
This parameter is sampled
Min
Max
Unit
40
mA
2tCYC
ns
2tCYC
ns
2tCYC
0
ns
ns
Truth Table [2, 3, 4, 5, 6, 7, 8]
Address
Used
CE1
CE2
CE3
ZZ
ADV/LD
WE
Deselect Cycle
None
H
X
X
L
L
X
X
Deselect Cycle
None
X
X
H
L
L
X
Deselect Cycle
None
X
L
X
L
L
X
Continue Deselect Cycle
None
X
X
X
L
H
External
L
H
L
L
L
Operation
READ Cycle (Begin Burst)
READ Cycle (Continue Burst)
NOP/DUMMY READ (Begin
Burst)
DUMMY READ (Continue Burst)
BWX OE
CEN
CLK
DQ
X
L
L->H
Tri-State
X
X
L
L->H
Tri-State
X
X
L
L->H
Tri-State
X
X
X
L
L->H
Tri-State
H
X
L
L
L->H Data Out (Q)
Next
X
X
X
L
H
X
X
L
L
L->H Data Out (Q)
External
L
H
L
L
L
H
X
H
L
L->H
Tri-State
Tri-State
Next
X
X
X
L
H
X
X
H
L
L->H
External
L
H
L
L
L
L
L
X
L
L->H Data In (D)
WRITE Cycle (Continue Burst)
Next
X
X
X
L
H
X
L
X
L
L->H Data In (D)
NOP/WRITE ABORT (Begin
Burst)
None
L
H
L
L
L
L
H
X
L
L->H
Tri-State
WRITE ABORT (Continue Burst)
Next
X
X
X
L
H
X
H
X
L
L->H
Tri-State
Current
X
X
X
L
X
X
X
X
H
L->H
–
None
X
X
X
H
X
X
X
X
X
X
Tri-State
WRITE Cycle (Begin Burst)
IGNORE CLOCK EDGE (Stall)
SLEEP MODE
Notes:
2. X =”Don't Care.” H = Logic HIGH, L = Logic LOW. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write
selects are asserted, see truth table for details.
3. Write is defined by BWX, and WE. See truth table for Read/Write.
4. When a write cycle is detected, all IOs are tri-stated, even during byte writes.
5. The DQs and DQP[A:B] pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device powers up deselected and the IOs in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP[A:B] = tri-state when OE
is inactive or when the device is deselected, and DQs and DQP[A:B] = data when OE is active.
Document #: 38-05515 Rev. *E
Page 5 of 13
CY7C1353G
Partial Truth Table for Read/Write[2, 3, 9]
WE
BWA
BWB
Read
Function
H
X
X
Write – No bytes written
L
H
H
Write Byte A – (DQA and DQPA)
L
L
H
Write Byte B – (DQB and DQPB)
L
H
L
Write All Bytes
L
L
L
Note:
9. Table only lists a partial listing of the byte write combinations. Any combination of BW[A:D] is valid. Appropriate write is based on which byte write is active.
Document #: 38-05515 Rev. *E
Page 6 of 13
CY7C1353G
Maximum Ratings
DC Input Voltage ................................... –0.5V to VDD + 0.5V
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Current into Outputs (LOW)......................................... 20 mA
Storage Temperature ................................. –65°C to +150°C
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
Latch up Current.................................................... > 200 mA
Operating Range
Supply Voltage on VDDQ Relative to GND ...... –0.5V to +VDD
DC Voltage Applied to Outputs
in tri-state ............................................ –0.5V to VDDQ + 0.5V
Range
Ambient
Temperature (TA)
Commercial
0°C to +70°C
Industrial
VDD
VDDQ
3.3V – 5%/+10% 2.5V – 5%
to VDD
−40°C to +85°C
Electrical Characteristics Over the Operating Range [10,11]
Parameter
Description
Test Conditions
Min
Max
Unit
VDD
Power Supply Voltage
3.135
3.6
V
VDDQ
IO Supply Voltage
2.375
VDD
V
VOH
Output HIGH Voltage
VOL
VIH
VIL
IX
Output LOW Voltage
for 3.3V IO, IOH = –4.0 mA
2.4
V
for 2.5V IO, IOH = –1.0 mA
2.0
V
for 3.3V IO, IOH = 8.0 mA
0.4
V
for 2.5V IO, IOH = 1.0 mA
0.4
V
Input HIGH Voltage
for 3.3V IO
2.0
VDD + 0.3V
V
Input HIGH Voltage
for 2.5V IO
1.7
VDD + 0.3V
V
Voltage[10]
for 3.3V IO
–0.3
0.8
V
Input LOW Voltage[10]
for 2.5V IO
–0.3
0.7
V
Input Leakage Current
except ZZ and MODE
GND ≤ VI ≤ VDDQ
−5
5
µA
Input Current of MODE
Input = VSS
–30
5
µA
30
µA
Input LOW
Input = VDD
Input Current of ZZ
Input = VSS
µA
–5
Input = VDD
IOZ
Output Leakage Current
GND ≤ VI ≤ VDDQ, Output Disabled
IDD
VDD Operating Supply
Current
VDD = Max., IOUT = 0 mA,
f = fMAX= 1/tCYC
ISB1
Automatic CE Power down
Current—TTL Inputs
ISB2
Automatic CE Power down
Current—CMOS Inputs
ISB3
ISB4
µA
5
µA
7.5-ns cycle, 133 MHz
225
mA
10-ns cycle, 100 MHz
205
mA
VDD = Max, Device Deselected, 7.5-ns cycle, 133 MHz
VIN ≥ VIH or VIN ≤ VIL, f = fMAX, 10-ns cycle, 100 MHz
inputs switching
90
mA
80
mA
VDD = Max, Device Deselected, All speeds
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
40
mA
Automatic CE Power down
Current—CMOS Inputs
VDD = Max, Device Deselected, 7.5-ns cycle, 133 MHz
VIN ≥ VDDQ – 0.3V or VIN ≤ 0.3V, 10-ns cycle, 100 MHz
f = fMAX, inputs switching
75
mA
65
mA
Automatic CE Power down
Current—TTL Inputs
VDD = Max, Device Deselected, All speeds
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
45
mA
–5
Notes:
10. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> –2V (Pulse width less than tCYC/2).
11. TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document #: 38-05515 Rev. *E
Page 7 of 13
CY7C1353G
Capacitance[12]
Parameter
Description
CIN
Input Capacitance
CCLOCK
Clock Input Capacitance
CIO
IO Capacitance
Test Conditions
100 TQFP
Max
TA = 25°C, f = 1 MHz,
VDD = 3.3V
VDDQ=3.3V
5
pF
5
pF
5
pF
Unit
Thermal Resistance[12]
Parameters
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
100 TQFP
Package
Unit
30.32
°C/W
6.85
°C/W
Test conditions follow standard test methods and
procedures for measuring thermal impedance,
according to EIA/JESD51.
AC Test Loads and Waveforms
.
3.3V IO Test Load
R = 317Ω
3.3V
OUTPUT
OUTPUT
RL = 50Ω
Z0 = 50Ω
VT = 1.5V
(a)
2.5V IO Test Load
OUTPUT
GND
5 pF
INCLUDING
JIG AND
SCOPE
2.5V
R = 351Ω
VT = 1.25V
(a)
5 pF
INCLUDING
JIG AND
SCOPE
10%
90%
10%
90%
≤ 1ns
≤ 1ns
(b)
(c)
R = 1667Ω
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50Ω
Z0 = 50Ω
ALL INPUT PULSES
VDDQ
GND
R =1538Ω
(b)
10%
90%
10%
90%
≤ 1ns
≤ 1ns
(c)
Note:
12.Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05515 Rev. *E
Page 8 of 13
CY7C1353G
Switching Characteristics Over the Operating Range [17, 18]
–133
Parameter
tPOWER
Description
[13]
VDD(Typical) to the first Access
Min
–100
Max
Min
Max
Unit
1
1
ms
Clock
tCYC
Clock Cycle Time
7.5
10
ns
tCH
Clock HIGH
2.5
4.0
ns
tCL
Clock LOW
2.5
4.0
ns
Output Times
tCDV
Data Output Valid After CLK Rise
tDOH
Data Output Hold After CLK Rise
[14, 15, 16]
6.5
2.0
8.0
2.0
ns
tCLZ
Clock to Low-Z
tCHZ
Clock to High-Z[14, 15, 16]
3.5
3.5
ns
tOEV
OE LOW to Output Valid
3.5
3.5
ns
tOELZ
tOEHZ
OE LOW to Output
Low-Z[14, 15, 16]
OE HIGH to Output
High-Z[14, 15, 16]
0
ns
0
0
ns
0
3.5
ns
3.5
ns
Setup Times
tAS
Address Setup Before CLK Rise
1.5
2.0
ns
tALS
ADV/LD Setup Before CLK Rise
1.5
2.0
ns
tWES
WE, BWX Setup Before CLK Rise
1.5
2.0
ns
tCENS
CEN Setup Before CLK Rise
1.5
2.0
ns
tDS
Data Input Setup Before CLK Rise
1.5
2.0
ns
tCES
Chip Enable Setup Before CLK Rise
1.5
2.0
ns
tAH
Address Hold After CLK Rise
0.5
0.5
ns
tALH
ADV/LD Hold after CLK Rise
0.5
0.5
ns
tWEH
WE, BWX Hold After CLK Rise
0.5
0.5
ns
Hold Times
tCENH
CEN Hold After CLK Rise
0.5
0.5
ns
tDH
Data Input Hold After CLK Rise
0.5
0.5
ns
tCEH
Chip Enable Hold After CLK Rise
0.5
0.5
ns
Notes:
13.This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a read or write operation
can be initiated.
14.tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
15.At any voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to
achieve tri-state prior to Low-Z under the same system conditions.
16.This parameter is sampled and not 100% tested.
17.Timing reference level is 1.5V when VDDQ=3.3V and is 1.25V when VDDQ=2.5V.
18.Test conditions shown in (a) of AC Test Loads, unless otherwise noted.
Document #: 38-05515 Rev. *E
Page 9 of 13
CY7C1353G
Switching Waveforms
Read/Write Waveforms[19, 20, 21]
1
2
3
tCYC
4
5
6
7
8
9
A5
A6
A7
10
CLK
tCENS tCENH
tCH
tCL
CEN
tCES
tCEH
CE
ADV/LD
WE
BW[A:B]
A1
ADDRESS
tAS
A2
A4
A3
tCDV
tAH
tDOH
tCLZ
DQ
D(A1)
tDS
D(A2)
Q(A3)
D(A2+1)
tOEV
Q(A4+1)
Q(A4)
tOELZ
WRITE
D(A1)
WRITE
D(A2)
D(A5)
Q(A6)
D(A7)
WRITE
D(A7)
DESELECT
tOEHZ
tDH
OE
COMMAND
tCHZ
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
tDOH
WRITE
D(A5)
READ
Q(A6)
UNDEFINED
Notes:
19.For this waveform ZZ is tied low.
20.When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
21.Order of the Burst sequence is determined by the status of the MODE (0= Linear, 1= Interleaved). Burst operations are optional.
Document #: 38-05515 Rev. *E
Page 10 of 13
CY7C1353G
Switching Waveforms
NOP, STALL and DESELECT Cycles[19, 20, 22]
1
2
A1
A2
3
4
5
A3
A4
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BW[A:B]
ADDRESS
A5
tCHZ
D(A1)
DQ
Q(A2)
Q(A3)
D(A4)
Q(A5)
tDOH
COMMAND
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
DON’T CARE
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
UNDEFINED
ZZ Mode Timing[23,24]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes:
22.The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
23.Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.
24.DQs are in high-Z when exiting ZZ sleep mode
Document #: 38-05515 Rev. *E
Page 11 of 13
CY7C1353G
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
133
Package
Diagram
Ordering Code
CY7C1353G-133AXC
Operating
Range
Part and Package Type
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Commercial
CY7C1353G-133AXI
100
lndustrial
CY7C1353G-100AXC
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Commercial
CY7C1353G-100AXI
lndustrial
Package Diagrams
100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050)
16.00±0.20
1.40±0.05
14.00±0.10
100
81
80
1
20.00±0.10
22.00±0.20
0.30±0.08
0.65
TYP.
30
12°±1°
(8X)
SEE DETAIL
A
51
31
50
0.20 MAX.
0.10
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
0.25
NOTE:
1. JEDEC STD REF MS-026
GAUGE PLANE
0°-7°
R 0.08 MIN.
0.20 MAX.
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0.60±0.15
0.20 MIN.
51-85050-*B
1.00 REF.
DETAIL
A
ZBT is a trademark of Integrated Device Technology, Inc. NoBL and No Bus Latency are trademarks of Cypress Semiconductor.
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05515 Rev. *E
Page 12 of 13
© Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for
the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended
to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1353G
Document History Page
Document Title: CY7C1353G 4-Mbit (256K x 18) Flow-through SRAM with NoBL™ Architecture
Document Number: 38-05515
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
224363
See ECN
RKF
New data sheet
*A
288431
See ECN
VBL
Deleted 66 MHz
Changed TQFP package in Ordering Information section to Pb-free TQFP
*B
333626
See ECN
SYT
Removed 117-MHz speed bin
Modified Address Expansion balls in the pinouts for 100 TQFP Packages
according to JEDEC standards and updated the Pin Definitions accordingly
Modified VOL, VOH test conditions
Replaced ‘Snooze’ with ‘Sleep’
Replaced TBD’s for ΘJA and ΘJC to their respective values on the Thermal
Resistance table
Updated the Ordering Information by shading and unshading MPNs
according to availability
*C
418633
See ECN
RXU
Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Modified test condition from VIH < VDD to VIH < VDD
Modified test condition from VDDQ < VDD to VDDQ < VDD
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering
Information table
Replaced Package Diagram of 51-85050 from *A to *B
Updated the Ordering Information
*D
480124
See ECN
VKN
Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.
Updated the Ordering Information table.
*E
1274724
See ECN
Document #: 38-05515 Rev. *E
VKN/AESA Corrected typo in the Ordering Information table
Page 13 of 13