ISSI IS24C02D-3GLA1-TR 2k-bit 2-wire automotive serial cmos eeprom Datasheet

IS24C02D
IS24C02D
2-WIRE (I2C)
2K-bit
Automotive
SERIAL EEPROM
Copyright © 2009 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for critical medical or surgical
equipment, aerospace or military, or other applications planned to support or sustain life. It is the customer's obligation to optimize the design in their own products for
the best performance and optimization on the functionality and etc. ISSI assumes no liability arising out of the application or use of any information, products or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and prior placing orders for
products.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00A
07/27/09
1
IS24C02D
Table of Contents
Features ……………………………………………………….…………….................3
Description ………………………………………………...……………….................3
Functional Block Diagram ……………………………………………….................4
Pin Configuration & Description ………………………………………..................5
Device Operations …..…………………………………………………….................5
Absolute Maximum Ratings ……………………………………………..................13
Operating Range …………………………………………………………..................13
DC Characteristics ………………………………………………………...................14
AC Characteristics ………………………………………………………...................14
Ordering Information ……………………………………………………...................16
Packaging Information ….………………………………………………...................17
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Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00A
07/27/09
IS24C02D
2K-bit 2-WIRE Automotive SERIAL CMOS EEPROM
ADVANCED INFORMATION
AUGUST 2009
FEATURES
Description
• Two-Wire Serial Interface, I2CTM compatible
The IS24C02D is an electrically erasable programmable
read only memory device that utilizes the standard
serial 2-wire interface for communications. This
EEPROM operates in a wide voltage range of 2.7V to
3.6V to be compatible with most application voltages.
The IS24C02D has an embedded memory array of
2,048-bits (256 x 8), and is organized in 16 pages of 16
bytes each. So page-write mode is capable of up to 16
bytes. In addition, software write-protection feature is
initiated with a unique irreversible instruction. After this
command is transmitted, the first 128 bytes of the array
become permanently read-only. This feature is designed
for specific applications such as, DIMMs. ISSI designed
the IS24C02D as a low-cost and low-power 2-wire
EEPROM solution. The device is offered in lead-free,
RoHS, halogen free or Green. The available package
types are 8-pin SOIC and TSSOP.
– Bidirectional data transfer protocol
• Wide Voltage Operation
– Vcc = 2.7V to 3.6V
• Speed
– 400 kHz (2.7V)
• Memory: 256 x 8-bit (2Kb)
• Data Protection Features
– Write Protect Pin
– Permanent Software Protection
• Page Write Mode (up to 16 bytes)
• Low Power
– Operating Current: 2 mA (3.6V)
– Standby Current: 6 µA (3.6V)
• Random or Sequential Read Modes
• Filtered Inputs for Noise Suppression
• Self timed Write cycle with auto clear
– 5 ms max. @ 2.7V
• High Reliability
– Endurance: 1,000,000 Cycles
– Data Retention: 100 Years
The IS24C02D maintains compatibility with the popular
2-wire bus protocol, so it is easy to use in applications
implementing this bus type. The simple bus consists
of the Serial Clock wire (SCL) and the Serial Data
wire (SDA). Using the bus, a Master device such as
a microcontroller is usually connected to one or more
Slave devices such as the IS24C02D. The bit stream
over the SDA line includes a series of bytes, which
identifies a particular Slave device, an instruction, an
address within that Slave device, and a series of data,
if appropriate. The IS24C02D has a Write Protect
pin (WP) to allow blocking of any write instruction
transmitted over the bus. • Automotive temperature grade
• Packages: SOIC and TSSOP
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00A
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3
IS24C02D
FUNCTIONAL BLOCK DIAGRAM
HIGH VOLTAGE
GENERATOR,
TIMING & CONTROL
Vcc
SDA
CONTROL
LOGIC
WP
SLAVE ADDRESS
REGISTER &
COMPARATOR
A0
00H-7FH
X
DECODER
SCL
ARRAY
80H-FFH
WORD ADDRESS
COUNTER
A1
Y
DECODER
A2
ACK
GND
nMOS
Clock
DI/O
>
DATA
REGISTER
For applications related inquiries, please refer to the EEPROM Application Support section of our website.
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Rev. 00A
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IS24C02D
PIN CONFIGURATION
8-Pin SOIC and TSSOP
A0
1
8
VCC
A1
2
7
WP
A2
3
6
SCL
GND
4
5
SDA
PIN DESCRIPTIONS
A0-A2
SDA
SCL
WP
Vcc
Address Inputs
Serial Address/Data I/O
Serial Clock Input
Write Protect Input
Power Supply
GND
Ground
WP
WP is the Write Protect pin. If the WP pin is tied to Vcc, the
entire array becomes Write Protected, and software writeprotection cannot be initiated. When WP is tied to GND or
left floating, normal read/write operations are allowed to the
device. If the device has already received a write-protection command, the memory in the range of 00h-7Fh is read
-only regardless of the setting of the WP pin.
SCL
DEVICE OPERATION
This input clock pin is used to synchronize the data transfer
to and from the device.
The IS24C02D features a serial communication and
supports a bi-directional 2-wire bus transmission protocol
called I2CTM.
SDA
The SDA is a Bi-directional pin used to transfer addresses
and data into and out of the device. The SDA pin is an
open drain output and can be wire Or'ed with other open
drain or open collector outputs. The SDA bus requires a
pullup resistor to Vcc.
A0, A1, A2
2-WIRE BUS
The two-wire bus is defined as a Serial Data line (SDA), and
a Serial Clock line (SCL). The protocol defines any device
that sends data onto the SDA bus as a transmitter, and
the receiving device as a receiver. The bus is controlled by
Master device which generates the SCL, controls the bus
access and generates the Stop and Start conditions. The
IS24C02D is the Slave device on the bus.
The A0, A1, and A2 are the device address inputs that
are hardwired or left unconnected for hardware flexibility.
When pins are hardwired, as many as eight devices may
be addressed on a single bus system. When the pins are
not hardwired, the default values of A0, A1, and A2 are
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Rev. 00A
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5
IS24C02D
The Bus Protocol:
DEVICE ADDRESSING
– Data transfer may be initiated only when the bus is not
busy
The Master begins a transmission by sending a Start
condition. The Master then sends the address of the
particular Slave devices it is requesting. The Slave device
(Fig. 5) address is 8 bits.
– During a data transfer, the SDA line must remain stable
whenever the SCL line is high. Any changes in the SDA
line while the SCL line is high will be interpreted as a
Start or Stop condition.
The state of the SDA line represents valid data after a Start
condition. The SDA line must be stable for the duration of
the High period of the clock signal. The data on the SDA
line may be changed during the Low period of the clock
signal. There is one clock pulse per bit of data. Each data
transfer is initiated with a Start condition and terminated
with a Stop condition.
Start Condition
The Start condition precedes all commands to the device
and is defined as a High to Low transition of SDA when
SCL is High. The IS24C02D monitors the SDA and SCL
lines and will not respond until the Start condition is met.
Stop Condition
The Stop condition is defined as a Low to High transition
of SDA when SCL is High. All operations must end with
a Stop condition.
Acknowledge (ACK)
After a successful data transfer, each receiving device is
required to generate an ACK. The Acknowledging device
pulls down the SDA line.
The four most significant bits of the Slave device address
are fixed as 1010 for normal read/write operations, and
0110 for permanent write-protection operations.
This device has three address bits (A1, A2, and A0) that
allow up to eight IS24C02D devices to share the 2-wire
bus. Upon receiving the Slave address, the device
compares the three address bits with the hardwired
A2, A1, and A0 input pins to determine if it is the
appropriate Slave. If any of the A2 - A0 pins is neither
biased to High nor Low, internal circuitry defaults the
value to Low. The last bit of the Slave address specifies whether a Read
or Write operation is to be performed. When this bit is set
to 1, a Read operation is selected, and when set to 0, a
Write operation is selected.
After the Master transmits the Start condition and Slave
address byte (Fig. 5), the appropriate 2-wire Slave (eg.
IS24C02D) will respond with ACK on the SDA line. The
Slave will pull down the SDA on the ninth clock cycle,
signaling that it received the eight bits of data. The
selected IS24C02D then prepares for a Read or Write
operation by monitoring the bus.
Reset
The IS24C02D contains a reset function in case the
2-wire bus transmission is accidentally interrupted (eg. a
power loss), or needs to be terminated mid-stream. The
reset is caused when the Master device creates a Start
condition. To do this, it may be necessary for the Master
device to monitor the SDA line while cycling the SCL up
to nine times. (For each clock signal transition to High,
the Master checks for a High level on SDA.) Standby Mode
Power consumption is reduced in standby mode. The
IS24C02D will enter standby mode: a) At Power-up, and
remain in it until SCL or SDA toggles; b) Following the Stop
signal if no write operation is initiated; or c) Following any
internal write operation.
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IS24C02D
WRITE OPERATION
Permanent Write Protection
Byte Write
The IS24C02D contains a permanent write protection
feature that is initiated by means of a software command.
After the command is transmitted, the protected area
becomes irreversibly read-only despite power removal and
re-application on the device. The address range of the 128
bytes of the array that is affected by this feature is 00h-7Fh.
Once enabled, the permanent protection is independent
of the status of the WP pin. (If WP is raised to High, the
entire array is read-only. If WP is low, the region 00h-7Fh
can still be read-only.)
In the Byte Write mode, the Master device sends the Start
condition and the Slave address information (with the R/W
set to Zero) to the Slave device. After the Slave generates
an ACK, the Master sends a byte address that is written
into the address pointer of the IS24C02D. After receiving
another ACK from the Slave, the Master device transmits
the data byte to be written into the address memory
location. The IS24C02D acknowledges once more and
the Master generates the Stop condition, at which time the
device begins its internal programming cycle. While this
internal cycle is in progress, the device will not respond
to any request from the Master device.
Page Write
The IS24C02D is capable of 16-byte Page-Write operation.
A Page-Write is initiated in the same manner as a Byte
Write, but instead of terminating the internal Write cycle
after the first data byte is transferred, the Master device can
transmit up to 15 more bytes. After the receipt of each data
byte, the IS24C02D responds immediately with an ACK
on SDA line, and the four lower order data byte address
bits are internally incremented by one, while the higher
order bits of the data byte address remain constant. If a
byte address is incremented from the last byte of a page,
it returns to the first byte of that page. If the Master device
should transmit more than 16 bytes prior to issuing the
Stop condition, the address counter will “roll over,” and the
previously written data will be overwritten. Once all 16
bytes are received and the Stop condition has been sent
by the Master, the internal programming cycle begins. At
this point, all received data is written to the IS24C02D in a
single Write cycle. All inputs are disabled until completion
of the internal Write cycle.
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The software command is initiated similarly to a normal
byte write operation; however, the slave address begins
with the bits 0110 (see Figure 5). The following three bits
are A2 - A0. The last bit of the slave address (R/W) is 0. If
the IS24C02D responds with ACK, the device has not yet
had its write-protection permanently enabled. To complete
the command, the Master must transmit a dummy address
byte, dummy data byte, and a Stop signal (see Figure 11).
The WP pin must be Low during this command. Before
resuming any other command, the internal write cycle
should be observed.
The status of the permanent write protection can be safely
determined without any changes by transmitting the same
Slave address as above, but with the last bit (R/W) set to
1 (see Figure 12). If the permanent write protection has
been enabled, the IS24C02D will not acknowledge any
slave address starting with bits 0110 (see Figure 5).
Acknowledge (ACK) Polling
The disabling of the inputs can be used to take advantage
of the typical Write cycle time. Once the Stop condition
is issued to indicate the end of the host's Write operation,
the IS24C02D initiates the internal Write cycle. ACK polling
can be initiated immediately. This involves issuing the Start
condition followed by the Slave address for a Write operation.
If the IS24C02D is still busy with the Write operation, no
ACK will be returned. If the IS24C02D has completed the
Write operation, an ACK will be returned and the host can
then proceed with the next Read or Write operation.
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IS24C02D
Read OPERATION
Sequential Read
Read operations are initiated in the same manner as
Write operations, except that the (R/W) bit of the Slave
address is set to “1”. There are three Read operation
options: current address read, random address read and
sequential read.
Sequential Reads can be initiated as either a Current
Address Read or Random Address Read. After the
IS24C02D sends the initial byte sequence, the Master
device responds with an ACK indicating it requires additional
data from the IS24C02D. The IS24C02D continues to
output data for each ACK received. The Master device
terminates the sequential Read operation by pulling SDA
High (no ACK) indicating the last data byte to be read,
followed by a Stop condition.
Current Address Read
The IS24C02D contains an internal address counter
which maintains the address of the last byte accessed,
incremented by one. For example, if the previous
operation is either a Read or Write operation addressed
to the address location n, the internal address counter
would increment to address location n+1. When the
IS24C02D receives the Device Addressing Byte with a
Read operation (R/W bit set to “1”), it will respond an
ACK and transmit the 8-bit data byte stored at address
location n+1. The Master should not acknowledge
the transfer but should generate a Stop condition so
the IS24C02D discontinues transmission. If the last
byte of the memory was the previous access, the data
from location '0' will be transmitted. (Refer to Figure 8.
Current Address Read Diagram.)
The data output is sequential, with the data from address n
followed by the data from address n+1, ... etc. The address
counter increments by one automatically, allowing the entire
memory contents to be serially read during sequential Read
operations. When the memory address boundary 255 is
reached, the address counter “rolls over” to address 0,
and the IS24C02D continues to output data for each ACK
received. (Refer to Figure 10. Sequential Read Operation
Starting with a Random Address Read Diagram.)
Random Address Read
Selective Read operations allow the Master device to select
at random any memory location for a Read operation. The
Master device first performs a 'dummy' Write operation
by sending the Start condition, Slave address and
word address of the location it wishes to read. After the
IS24C02D acknowledges the word address, the Master
device resends the Start condition and the Slave address,
this time with the R/W bit set to one. The IS24C02D then
responds with its ACK and sends the data requested. The
Master device does not send an ACK but will generate
a Stop condition. (Refer to Figure 9. Random Address
Read Diagram.)
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Rev. 00A
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IS24C02D
Figure 1. Typical System Bus Configuration
Vcc
SDA
SCL
Master
Transmitter/
Receiver
IS24C02D
Figure 2. Output Acknowledge
SCL from
Master
1
8
9
Data Output
from
Transmitter
tAA
Data Output
from
Receiver
tAA
ACK
STOP
Condition
SCL
START
Condition
Figure 3. Start and Stop Conditions
SDA
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9
IS24C02D
Figure 4. Data Validity Protocol
Data Change
SCL
Data Stable
Data Stable
SDA
Figure 5. Slave Address
BIT
BIT
7
6
5
4
3
2
1
0
1
0
1
0
A2
A1
A0
R/W
7
6
5
4
3
2
1
0
0
1
1
0
A2
A1
A0
R/W
Normal
Instruction
Permanent Write Protect
Instruction
Figure 6. Byte Write
SDA
Bus
Activity
S
T
A
R
T
Device
Address
M
S
B
W
R
I
T
E *
A
C
K
L
S
B
R/W
*
Word Address
Data
A
C
K
S
T
O
* P
A
C
K
M
S
B
* Acknowledges provided by the slave regardless of hardware or software Write Protection.
Figure 7. Page Write
SDA
Bus
Activity
S
T
A
R
T
Device
Address
M
S
B
W
R
I
T
E * Word Address (n) *
A
A
C
C
K
K
Data (n)
*
A
C
K
Data (n+1)
*
A
C
K
Data (n+15)
S
T
O
* P
A
C
K
L
S
B
R/W
* Acknowledges provided by the slave regardless of hardware or software Write Protection.
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IS24C02D
Figure 8. Current Address Read
SDA
Bus
Activity
S
T
A
R
T
R
E
A
D
Device
Address
S
T
O
P
Data
A
C
K
M
S
B
L
S
B
N
O
A
C
K
R/W
Figure 9. Random Address Read
SDA
Bus
Activity
S
T
A
R
T
W
R
I
T
E
Device
Address
M
S
B
Word
Address (n)
A
C
K
A
C
K
S
T
A
R
T
Device
Address
R
E
A
D
S
T
O
P
Data n
A
C
K
L
S
B
R/W
N
O
A
C
K
DUMMY WRITE
Figure 10. Sequential Read
Device
Address
SDA
Bus
Activity
R
E
A
D
Data Byte n
A
C
K
Data Byte n+1
A
C
K
Data Byte n+X
A
C
K
N
O
R/W
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Data Byte n+2
A
C
K
S
T
O
P
A
C
K
11
IS24C02D
fIGURE 11. Permanent Write Protection Initiation
SDA
Bus
Activity
S
T
A
R
T
W
R
I
Device
T
Data
Address
E * Word Address
A
A
A
C # # ## # # # #C # # # ## # # # C
K
K
K
M
L
M
S
S
S
B
B
B
R/W
S
T
O
P
* The slave does not provide an acknowledgement if the permanent write protection is already enabled.
# Don't care bits are required.
fIGURE 12. Permanent Write Protection Verification
SDA
Bus
Activity
S
T
A
R
T
R S
E T
A O
D * P
A
C
K
Device
Address
M
S
B
L
S
B
R/W
* The slave does not provide an acknowledgement if the permanent write protection is already enabled.
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IS24C02D
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vs
Vp
Tbias
Tstg
Iout
ParameterValueUnit
Supply Voltage
–0.5 to +6.5
V
Voltage on Any Pin
–0.5 to Vcc + 0.5
V
Temperature Under Bias
–55 to +125
°C
Storage Temperature
–65 to +150
°C
Output Current
5
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
OPERATING RANGE
(IS24C02D-3)
Vcc
2.7V to 3.6V
Ambient Temperature
–40°C to +85°C
Range
Automotive
CAPACITANCE(1,2)
Symbol
Cin
Cout
Parameter
Input Capacitance
Output Capacitance
Conditions
Vin = 0V
Vout = 0V
Max.Unit
6
pF
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: Ta = 25°C, f = 400 KHz, Vcc = 3.6V.
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13
IS24C02D
DC ELECTRICAL CHARACTERISTICS
Ta = -40oC to +85oC
Symbol
Icc1
Icc2
Isb
Vol
Vih
Vil
Ili
Ilo
Parameter
Operating Current
Operating Current
Standby Current
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
Test Conditions
Read at 400 KHz (Vcc = 3.6V)
Write at 400 KHz (Vcc = 3.6V)
Vcc = 3.6V
Vcc = 2.7V, Iol = 3 mA
Vin = Vcc max.
Min.
Max.Unit
—
2.0
mA
—
3.0
mA
—
6
µA
—
0.4
V
Vcc x 0.7 Vcc + 0.5
V
–1.0
Vcc x 0.3
V
—
3
µA
—
3
µA
Notes: Vil min and Vih max are reference only and are not tested
AC ELECTRICAL CHARACTERISTICS
Automotive (Ta = -40oC to +85oC)
2.7V ≤ Vcc < 3.6V
Symbol
Parameter
fscl
SCL Clock Frequency
T
Min. Max.Unit
0
400
KHz
Noise Suppression Time
—
50
ns
tlow
Clock Low Period
1.2
—
µs
thigh
Clock High Period
0.6
—
µs
tbuf
Bus Free Time Before New Transmission(1)
1.2
—
µs
tsu:sta
Start Condition Setup Time
0.6
—
µs
tsu:sto
Stop Condition Setup Time
0.6
—
µs
thd:sta
Start Condition Hold Time
0.6
—
µs
thd:sto
Stop Condition Hold Time
0.6
—
µs
tsu:dat
Data In Setup Time
100
—
ns
thd:dat
Data In Hold Time
0
—
ns
(1)
tsu:wp
WP pin Setup Time
0.6
—
µs
thd:wp
WP pin Hold Time
1.2
—
µs
tdh
Data Out Hold Time (SCL Low to SDA Data Out Change)
50
—
ns
taa
Clock to Output (SCL Low to SDA Data Out Valid)
50
900
ns
tr
SCL and SDA Rise Time
—
300
ns
tf
SCL and SDA Fall Time(1)
—
300
ns
twr
Write Cycle Time
—
10
ms
(1)
Note:
1. These parameters are characterized but not 100% tested.
14
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IS24C02D
figure 13. AC WAVEFORMS
tR
tF
tHIGH
tLOW
tSU:STO
SCL
tSU:STA
tBUF
tHD:DAT
tHD:STA
tSU:DAT
SDAIN
tAA
tDH
SDAOUT
tSU:WP
tHD:WP
WP
FIGURE 14. Write Cycle Timing
SCL
SDA
8th BIT
ACK
tWR
WORD n
STOP
Condition
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START
Condition
15
IS24C02D
ORDERING INFORMATION
Automotive (A1) Grade: –40°C to +85°C
Voltage Range
Part Number
2.7V to 3.6V
IS24C02D-3GLA1-TR 150-mil SOIC (JEDEC)
IS24C02D-3ZLA1-TR
Package Type (8-pin)
3 x 4.4 mm TSSOP
*
1. Contact ISSI Sales Representatives for availability and other package information.
2. The listed part numbers are packed in tape and reel “-TR” (4K per reel).
3. For tube/bulk packaging, remove “-TR” at the end of the P/N.
4. Refer to ISSI website for related declaration document on lead free, RoHS, halogen free, or Green, whichever is applicable.
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IS24C02D
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IS24C02D
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