July 2007 HYB18T C1G 80 0 BF HYB18T C1G 16 0 BF 1-Gbit Double-Data-Rate-Two SDRAM DDR2 SDRAM RoHS Compliant Products Internet Data Sheet Rev. 1.21 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM HYB18TC1G800BF, HYB18TC1G160BF Revision History: 2007-07, Rev. 1.21 Page Subjects (major changes since last revision) All Adapted internet edition 14 Corrected Table 9: Added Ball B2 and B8 Previous Revision: 2007-03, Rev. 1.2 136 Corrected package outline Editorial changes Previous Revision: 2007-03, Rev. 1.1 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] qag_techdoc_rev400 / 3.2 QAG / 2006-07-21 02282007-F8UP-4HSU 2 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM 1 Overview This chapter gives an overview of the 1-Gbit Double-Data-Rate-Two SDRAM product family and describes its main characteristics. 1.1 Features The 1-Gbit Double-Data-Rate-Two SDRAM offers the following key features: • Off-Chip-Driver impedance adjustment (OCD) and On• 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O Die-Termination (ODT) for better signal quality. • DRAM organizations with 8 and 16 data in/outputs • Auto-Precharge operation for read and write bursts • Double Data Rate architecture: two data transfers per • Auto-Refresh, Self-Refresh and power saving PowerDown modes clock cycle four internal banks for concurrent operation • Average Refresh Period 7.8 µs at a TCASE lower than • Programmable CAS Latency: 3, 4, 5 and 6 85 °C, 3.9 µs between 85 °C and 95 °C • Programmable Burst Length: 4 and 8 • Programmable self refresh rate via EMRS2 setting • Differential clock inputs (CK and CK) • Programmable partial array refresh via EMRS2 settings • Bi-directional, differential data strobes (DQS and DQS) are transmitted / received with data. Edge aligned with read • DCC enabling via EMRS2 setting • Full and reduced Strength Data-Output Drivers data and center-aligned with write data. • 1K page size for ×8, 2K page size for ×16 • DLL aligns DQ and DQS transitions with clock • Packages: PG-TFBGA-68 for ×8 components, PG• DQS can be disabled for single-ended data strobe operation TFBGA-84 for ×16 components • RoHS Compliant Products1) • Commands entered on each positive clock edge, data and data mask are referenced to both edges of DQS • All Speed grades faster than DDR2–400 comply with DDR2–400 timing specifications when run at a clock rate • Data masks (DM) for write data • Posted CAS by programmable additive latency for better of 200 MHz. command and data bus efficiency A list of the performance tables for the various speeds can be found below • Table 1 “Performance tables for –2.5” on Page 4 • Table 2 “Performance table for –3S” on Page 4 • Table 3 “Performance table for –3.7” on Page 4 • Table 4 “Performance Table for –5” on Page 5 1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. Rev. 1.21, 2007-07 02282007-F8UP-4HSU 3 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM TABLE 1 Performance tables for –2.5 Product Type Speed Code –2.5 Unit Speed Grade DDR2–800E 6–6–6 — 400 MHz 333 MHz 266 MHz 200 MHz 15 ns 15 ns 45 ns 60 ns Max. Clock Frequency @CL6 @CL5 @CL4 @CL3 Min. RAS-CAS-Delay Min. Row Precharge Time Min. Row Active Time Min. Row Cycle Time fCK6 fCK5 fCK4 fCK3 tRCD tRP tRAS tRC TABLE 2 Performance table for –3S Product Type Speed Code –3S Unit Speed Grade DDR2–667D 5–5–5 — 333 MHz 266 MHz 200 MHz 15 ns 15 ns 45 ns 60 ns Max. Clock Frequency @CL5 @CL4 @CL3 Min. RAS-CAS-Delay Min. Row Precharge Time Min. Row Active Time Min. Row Cycle Time Rev. 1.21, 2007-07 02282007-F8UP-4HSU fCK5 fCK4 fCK3 tRCD tRP tRAS tRC 4 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM TABLE 3 Performance table for –3.7 Product Type Speed Code –3.7 Unit Speed Grade DDR2–533C 4–4–4 — 266 MHz 266 MHz Max. Clock Frequency @CL5 @CL4 @CL3 Min. RAS-CAS-Delay Min. Row Precharge Time Min. Row Active Time Min. Row Cycle Time fCK5 fCK4 fCK3 tRCD tRP tRAS tRC 200 MHz 15 ns 15 ns 45 ns 60 ns TABLE 4 Performance Table for –5 Product Type Speed Code –5 Units Speed Grade DDR2–400B 3–3–3 — 200 MHz 200 MHz 200 MHz 15 ns 15 ns 40 ns 55 ns Max. Clock Frequency fCK5 fCK4 fCK3 tRCD tRP tRAS tRC @CL5 @CL4 @CL3 Min. RAS-CAS-Delay Min. Row Precharge Time Min. Row Active Time Min. Row Cycle Time Rev. 1.21, 2007-07 02282007-F8UP-4HSU 5 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM 1.2 Description latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchronous fashion. A 17 bit address bus for ×8 organised components and a 16 bit address bus for ×16 components is used to convey row, column and bank address information in a RAS-CAS multiplexing style. The DDR2 device operates with a 1.8 V ± 0.1 V power supply. An Auto-Refresh and Self-Refresh mode is provided along with various power-saving power-down modes. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation. The DDR2 SDRAM is available in PG-TFBGA package. The 1-Gbit DDR2 DRAM is a high-speed Double-Data-RateTwo CMOS Synchronous DRAM device containing 1,073,741,824 bits and internally configured as anoctal quadbank DRAM. The 1-Gb device is organized as either 16 Mbit ×8 I/O ×8 banks or 8 Mbit ×16 I/O ×8 banks chip. These synchronous devices achieve high speed transfer rates starting at 400 Mb/sec/pin for general applications. The device is designed to comply with all DDR2 DRAM key features: 1. Posted CAS with additive latency, 2. Write latency = read latency - 1, 3. Normal and weak strength data-output driver, 4. Off-Chip Driver (OCD) impedance adjustment 5. On-Die Termination (ODT) function. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are TABLE 5 Ordering Information for RoHS compliant products Product Type Org. Speed CAS-RCD-RP Latencies1)2)3) HYB18TC1G160BF-2.5 ×16 DDR2-800E 6-6-6 400 PG-TFBGA-84 HYB18TC1G800BF-2.5 ×8 DDR2-800E 6-6-6 400 PG-TFBGA-68 HYB18TC1G160BF-3S ×16 DDR2-667D 5-5-5 333 PG-TFBGA-84 HYB18TC1G800BF-3S ×8 DDR2-667D 5-5-5 333 PG-TFBGA-68 HYB18TC1G160BF-3.7 ×16 DDR2-533C 4-4-4 266 PG-TFBGA-84 HYB18TC1G800BF-3.7 ×8 DDR2-533C 4-4-4 266 PG-TFBGA-68 HYB18TC1G160BF-5 ×16 DDR2-400B 3-3-3 200 PG-TFBGA-84 HYB18TC1G800BF-5 ×8 DDR2-400B 3-3-3 200 PG-TFBGA-68 1) CAS: Column Address Strobe 2) RCD: Row Column Delay 3) RP: Row Precharge Note: For product nomenclature see Chapter 9 of this data sheet Rev. 1.21, 2007-07 02282007-F8UP-4HSU 6 Clock (MHz) Package Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM 2 Configuration This chapter contains the chip configuration and addressing. 2.1 Chip Configuration for PG-TFBGA-68 The chip configuration of a DDR2 SDRAM is listed by function in Table 6. The abbreviations used in the Ball# and Buffer Type columns are explained in Table 7 and Table 8 respectively. The ball numbering for the FBGA package is depicted in figures. TABLE 6 Chip Configuration of DDR2 SDRAM Ball# Name Ball Type Buffer Type Function Clock Signal CK, CK Clock Signals ×8 Organizations J8 CK I SSTL K8 CK I SSTL K2 CKE I SSTL Clock Enable Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE) Control Signals ×8 Organizations K7 RAS I SSTL L7 CAS I SSTL K3 WE I SSTL L8 CS I SSTL Chip Select Bank Address Bus 1:0 Address Signals ×8 Organizations L2 BA0 I SSTL L3 BA1 I SSTL L1 BA2 I SSTL Bank Address Bus 2 Note: 1 Gbit components and higher NC — — Note: 256 Mbit and 512 Mbit components Rev. 1.21, 2007-07 02282007-F8UP-4HSU 7 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM Ball# Name Ball Type Buffer Type Function M8 A0 I SSTL Address Signal 12:0, Address Signal 10/Autoprecharge M3 A1 I SSTL M7 A2 I SSTL N2 A3 I SSTL N8 A4 I SSTL N3 A5 I SSTL N7 A6 I SSTL P2 A7 I SSTL P8 A8 I SSTL P3 A9 I SSTL M2 A10 I SSTL AP I SSTL P7 A11 I SSTL R2 A12 I SSTL R8 A13 I SSTL Address Signal 13 Note: 1 Gbit ×4/×8 components NC — — Note: 256 Mbit Data Signal 3:0 Note: Bi-directional data bus DQ[7:0] for ×8 components Data Signals ×8 Organizations G8 DQ0 I/O SSTL G2 DQ1 I/O SSTL H7 DQ2 I/O SSTL H3 DQ3 I/O SSTL H1 DQ4 I/O SSTL H9 DQ5 I/O SSTL F1 DQ6 I/O SSTL F9 DQ7 I/O SSTL Data Signal 7:4 Data Strobe ×8 Organizations F7 DQS I/O SSTL E8 DQS I/O SSTL Data Strobe Data Strobe ×8 Organizations F3 RDQS O SSTL E2 RDQS O SSTL Read Data Strobe Data Mask ×8 Organizations F3 DM I SSTL Data Mask Power Supplies ×8 Organizations E9, G1, G3, G7, VDDQ G9 PWR — I/O Driver Power Supply VDD E7, F2, F8, H2, VSSQ PWR — Power Supply PWR — I/O Driver Power Supply PWR — Power Supply E1, J9, M9, R1 H8 E3, J3, N1, P9 VSS Rev. 1.21, 2007-07 02282007-F8UP-4HSU 8 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM Ball# Name Ball Type Buffer Type Function J2 VREF VDDL VSSDL Al — I/O Reference Voltage PWR — Power Supply PWR — Power Supply — Not Connected SSTL On-Die Termination Control J1 J7 Not Connected ×8 Organization A1, A2, A8, A9, NC R7, W1, W2, W8, W9, R3 NC Other Balls ×8 Organizations K9 ODT I TABLE 7 Abbreviations for Ball Type Abbreviation Description I Standard input-only ball. Digital levels. O Output. Digital levels. I/O I/O is a bidirectional input/output signal. AI Input. Analog levels. PWR Power GND Ground NC Not Connected TABLE 8 Abbreviations for Buffer Type Abbreviation Description SSTL Serial Stub Terminated Logic (SSTL_18) LV-CMOS Low Voltage CMOS CMOS CMOS Levels OD Open Drain. The corresponding ball has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR. Rev. 1.21, 2007-07 02282007-F8UP-4HSU 9 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM FIGURE 1 Ball Configuration for ×8 components, PG-TFBGA-68 (top view) 1& 1& $ 1& 1& % & ' 9'' 18 5'46 966 ( 9664 '46 9''4 '4 9664 '0 5'46 ) '46 9664 '4 9''4 '4 9''4 * 9''4 '4 9''4 '4 9664 '4 + '4 9664 '4 9''/ 95() 966 - 966'/ &. 9'' &.( :( . 5$6 &. 2'7 %$ %$ / &$6 &6 $$3 $ 0 $ $ $ $ 1 $ $ $ $ 3 $ $ $ 1& 5 1& 1&$ 1&%$ 966 9'' 9'' 966 7 8 9 1& 1& : 1& 1& 0337 Notes 1. 2. 3. 4. RDQS / RDQS are enabled by EMRS(1) command. If RDQS / RDQS is enabled, the DM function is disabled When enabled, RDQS & RDQS are used as strobe signals during reads. VDDL and VSSDL are power and ground for the DLL. They are connected on the device from VDD, VDDQ, VSS and VSSQ. Rev. 1.21, 2007-07 02282007-F8UP-4HSU 10 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM 2.2 Chip Configuration for PG-TFBGA-84 The chip configuration of a DDR2 SDRAM is listed by function in Table 9. The abbreviations used in the Ball#/Buffer Type columns are explained in Table 10 and Table 11 respectively. TABLE 9 Chip Configuration of DDR SDRAM Ball# Name Ball Type Buffer Type Function Clock Signal CK, CK Clock Signals ×16 Organization J8 CK I SSTL K8 CK I SSTL K2 CKE I SSTL Clock Enable Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE) Control Signals ×16 Organization K7 RAS I SSTL L7 CAS I SSTL K3 WE I SSTL L8 CS I SSTL Chip Select Bank Address Bus 2:0 Note: 1 Gbit components and higher Address Signals ×16 Organization L2 BA0 I SSTL L3 BA1 I SSTL L1 BA2 I SSTL M8 A0 I SSTL M3 A1 I SSTL M7 A2 I SSTL N2 A3 I SSTL N8 A4 I SSTL N3 A5 I SSTL N7 A6 I SSTL P2 A7 I SSTL P8 A8 I SSTL P3 A9 I SSTL M2 A10 I SSTL AP I SSTL P7 A11 I SSTL R2 A12 I SSTL Rev. 1.21, 2007-07 02282007-F8UP-4HSU Address Signal 12:0, Address Signal 10/Autoprecharge 11 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM Ball# Name Ball Type Buffer Type Function Data Signal 15:0 Note: Bi-directional data bus. DQ[15:0] for ×16 components Data Signals ×16 Organization G8 DQ0 I/O SSTL G2 DQ1 I/O SSTL H7 DQ2 I/O SSTL H3 DQ3 I/O SSTL H1 DQ4 I/O SSTL H9 DQ5 I/O SSTL F1 DQ6 I/O SSTL F9 DQ7 I/O SSTL C8 DQ8 I/O SSTL C2 DQ9 I/O SSTL D7 DQ10 I/O SSTL D3 DQ11 I/O SSTL D1 DQ12 I/O SSTL D9 DQ13 I/O SSTL B1 DQ14 I/O SSTL B9 DQ15 I/O SSTL Data Strobe ×16 Organization B7 UDQS I/O SSTL A8 UDQS I/O SSTL F7 LDQS I/O SSTL E8 LDQS I/O SSTL Data Strobe Upper Byte Data Strobe Lower Byte Data Mask ×16 Organization B3 UDM I SSTL Data Mask Upper Byte F3 LDM I SSTL Data Mask Lower Byte Power Supplies ×16 Organization VREF C1, C3, C7, C9, VDDQ AI — I/O Reference Voltage PWR — I/O Driver Power Supply VDDL A1, E1, J9, M9, VDD PWR — Power Supply PWR — Power Supply A7, D2, D8, E7, VSSQ F2, F8, H2, H8 PWR — Power Supply PWR — Power Supply PWR — Power Supply — Not Connected J2 E9, G1, G3, G7, G9, A9 J1 R1 J7 A3, E3, J3,N1,P9 VSSDL VSS Not Connected ×16 Organization A2, E2, R3, R7, NC R8 Rev. 1.21, 2007-07 02282007-F8UP-4HSU NC 12 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM Ball# Name Ball Type Buffer Type Function SSTL On-Die Termination Control Other Balls ×16 Organization K9 ODT I TABLE 10 Abbreviations for Ball Type Abbreviation Description I Standard input-only ball. Digital levels. O Output. Digital levels. I/O I/O is a bidirectional input/output signal. AI Input. Analog levels. PWR Power GND Ground NC Not Connected TABLE 11 Abbreviations for Buffer Type Abbreviation Description SSTL Serial Stub Terminated Logic (SSTL_18) LV-CMOS Low Voltage CMOS CMOS CMOS Levels OD Open Drain. The corresponding ball has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR. Rev. 1.21, 2007-07 02282007-F8UP-4HSU 13 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM FIGURE 2 Chip Configuration for x16 Components in PG–TFBGA–84 (Top view) 9'' 1& 966 $ 9664 8'46 9''4 '4 9664 8'0 % 8'46 9664 '4 9''4 '4 9''4 & 9''4 '4 9''4 '4 9664 '4 ' '4 9664 '4 9'' 1& 966 ( 9664 /'46 9''4 '4 9664 /'0 ) /'46 9664 '4 9''4 '4 9''4 * 9''4 '4 9''4 '4 9664 '4 + '4 9664 '4 9''/ 95() 966 - 966'/ &. 9'' &.( :( . 5$6 &. 2'7 %$ %$ / &$6 &6 $$3 $ 0 $ $ $ $ 1 $ $ $ $ 3 $ $ $ 1& 5 1& 1& %$ 966 9'' 9'' 966 03%7 Rev. 1.21, 2007-07 02282007-F8UP-4HSU 14 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM 2.3 1-Gbit DDR2 Addressing This chapter describes the 1-Gbit DDR2 addressing. TABLE 12 DDR2 Addressing for ×8 Organization 1) Configuration 128Mb x 8 Bank Address BA[2:0] Number of Banks 8 Auto-Precharge A10 / AP Row Address A[13:0] Column Address A[9:0] Number of Column Address Bits 10 Number of I/Os 8 Page Size [Bytes] 1024 (1K) Note 2) 3) 1) Referred to as ’org’ 2) Referred to as ’colbits’ 3) PageSize = 2colbits × org/8 [Bytes] TABLE 13 DDR2 Addressing for ×16 Organization Configuration 64Mb x 16 Bank Address BA[2:0] Number of Banks 8 Auto-Precharge A10 / AP Row Address A[12:0] Column Address A[9:0] Number of Column Address Bits 10 Number of I/Os 16 Page Size [Bytes] 2048 (2K) 1) Referred to as ’org’ 2) Referred to as ’colbits’ 3) PageSize = 2colbits × org/8 [Bytes] Rev. 1.21, 2007-07 02282007-F8UP-4HSU 15 1) Note 2) 3) Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM 3 Functional Description This chapter contains the functional description. %$ %$ %$ $ UHJDGGU $ $ $ $ $ $ $ $ $ $ $ $ 3' :5 '// 70 &/ %7 %/ Z Z Z Z Z Z Z $ 03%7 TABLE 14 Mode Register Definition (BA[2:0] = 000B) Field Bits Type1) Description BA2 16 reg. addr. Bank Address [2] Note: BA2 not available on 256 Mbit and 512 Mbit components 0B BA2 Bank Address BA1 15 Bank Address [1] BA1 Bank Address 0B BA0 14 Bank Address [0] 0B BA0 Bank Address A13 13 Address Bus[13] Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration 0B A13 Address bit 13 PD 12 w Active Power-Down Mode Select 0B PD Fast exit 1B PD Slow exit WR [11:9] w Write Recovery2) Note: All other bit combinations are illegal. 001B 010B 011B 100B 101B WR 2 WR 3 WR 4 WR 5 WR 6 DLL 8 w DLL Reset 0B DLL No 1B DLL Yes TM 7 w Test Mode 0B TM Normal Mode 1B TM Vendor specific test mode Rev. 1.21, 2007-07 02282007-F8UP-4HSU 16 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM Field Bits Type1) Description CL [6:4] w CAS Latency Note: All other bit combinations are illegal. 011B 100B 101B 110B 111B CL 3 CL 4 CL 5 CL 6 CL 7 BT 3 w Burst Type 0B BT Sequential BT Interleaved 1B BL [2:0] w Burst Length Note: All other bit combinations are illegal. 010B BL 4 011B BL 8 1) w = write only register bits 2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer: WR [cycles] ≥ tWR (ns) / tCK (ns). The mode register must be programmed to fulfill the minimum requirement for the analogue tWR timing WRMIN is determined by tCK.MAX and WRMAX is determined by tCK.MIN. %$ %$ %$ $ $ $ $ $ $ $ $ $ $ $ $ $ $ 4RII 5'4 6 '46 2&' 3URJUDP 5WW $/ 5WW ',& '// Z Z Z Z Z Z Z UHJ D GGU Z 03%7 TABLE 15 Extended Mode Register Definition (BA[2:0] = 001B) 1) Field Bits Type Description BA2 16 reg. addr. Bank Address [2] Note: BA2 not available on 256 Mbit and 512 Mbit components BA1 15 reg. addr. Bank Address [1] 0B BA1 Bank Address BA0 14 A13 13 w Qoff 12 w 0B BA2 Bank Address Bank Address [0] 1B BA0 Bank Address Address Bus [13] Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration 0B Rev. 1.21, 2007-07 02282007-F8UP-4HSU A13 Address bit 13 Output Disable 0B QOff Output buffers enabled 1B QOff Output buffers disabled 17 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM Field Bits Type1) Description RDQS 11 w Read Data Strobe Output (RDQS, RDQS) 0B RDQS Disable RDQS Enable 1B DQS 10 w Complement Data Strobe (DQS Output) DQS Enable 0B 1B DQS Disable OCD [9:7] Program w Off-Chip Driver Calibration Program 000B OCD OCD calibration mode exit, maintain setting 001B OCD Drive (1) 010B OCD Drive (0) 100B OCD Adjust mode 111B OCD OCD calibration default AL w Additive Latency Note: All other bit combinations are illegal. [5:3] 000B 001B 010B 011B 100B 101B RTT 6,2 w AL 0 AL 1 AL 2 AL 3 AL 4 AL 5 Nominal Termination Resistance of ODT Note: See Table 26 “ODT DC Electrical Characteristics” on Page 25 00B 01B 10B 11B RTT ∞ (ODT disabled) RTT 75 Ohm RTT 150 Ohm RTT 50 Ohm DIC 1 w Off-chip Driver Impedance Control 0B DIC Full (Driver Size = 100%) 1B DIC Reduced DLL 0 w DLL Enable DLL Enable 0B 1B DLL Disable 1) w = write only register bits Rev. 1.21, 2007-07 02282007-F8UP-4HSU 18 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM %$ %$ %$ $ $ $ $ $ $ $ $ 65) $ $ $ '&& UHJDGGU $ $ $ 3$65 03%7 TABLE 16 EMRS(2) Programming Extended Mode Register Definition (BA[2:0]=010B) Field Bits Type1) Description BA2 16 w Bank Address Note: BA2 is not available on 256 Mbit and 512 Mbit components 0B BA2 Bank Address BA [15:14] w Bank Adress 00B BA MRS 01B BA EMRS(1) 10B BA EMRS(2) 11B BA EMRS(3): Reserved A [13:8] w Address Bus Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration 000000B A Address bits SRF 7 w Address Bus, High Temperature Self Refresh Rate for TCASE > 85°C 0B A7 disable 1B A7 enable 2) A [6:4] w Address Bus 000B A Address bits DCC 3 w Address Bus, Duty Cycle Correction (DCC) A3 DCC disabled 0B 1B A3 DCC enabled Partial Self Refresh for 4 banks PASR [2:0] w Address Bus, Partial Array Self Refresh for 4 Banks3) Note: Only for 256 Mbit and 512 Mbit components 000B 001B 010B 011B 100B 101B 110B 111B Rev. 1.21, 2007-07 02282007-F8UP-4HSU PASR0 Full Array PASR1 Half Array (BA[1:0]=00, 01) PASR2 Quarter Array (BA[1:0]=00) PASR3 Not defined PASR4 3/4 array (BA[1:0]=01, 10, 11) PASR5 Half array (BA[1:0]=10, 11) PASR6 Quarter array (BA[1:0]=11) PASR7 Not defined 19 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM Field Bits Type1) Description Partial Self Refresh for 8 banks PASR [2:0] Address Bus, Partial Array Self Refresh for 8 Banks3) Note: Only for 1G and 2G components w 000B 001B 010B 011B 100B 101B 110B 111B PASR0 Full Array PASR1 Half Array (BA[2:0]=000, 001, 010 & 011) PASR2 Quarter Array (BA[2:0]=000, 001) PASR3 1/8 array (BA[2:0] = 000) PASR4 3/4 array (BA[2:0]= 010, 011, 100, 101, 110 & 111) PASR5 Half array (BA[2:0]=100, 101, 110 & 111) PASR6 Quarter array (BA[2:0]= 110 & 111) PASR7 1/8 array(BA[2:0]=111) 1) w = write only 2) When DRAM is operated at 85°C ≤ TCase ≤ 95°C the extended self refresh rate must be enabled by setting bit A7 to "1" before the self refresh mode can be entered. 3) If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified location will be lost if self refresh is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh command is issued %$ %$ %$ $ $ $ $ $ $ $ $ $ $ $ $ $ $ UHJD GG U 03%7 TABLE 17 EMR(3) Programming Extended Mode Register Definition( BA[2:0]=011B) 1) Field Bits Type Description BA2 16 reg.addr Bank Address Note: BA2 is not available on 256Mbit and 512Mbit components BA1 15 Bank Adress BA1 Bank Address 1B BA0 14 Bank Adress 1B BA0 Bank Address A [13:0] 0B w BA2 Bank Address Address Bus Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration 00000000000000B Address bits 1) w = write only Rev. 1.21, 2007-07 02282007-F8UP-4HSU 20 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM TABLE 18 ODT Truth Table Input Pin EMRS(1) Address Bit A10 EMRS(1) Address Bit A11 ×8 Components DQ[7:0] X DQS X DQS 0 X RDQS X 1 RDQS 0 1 DM X 0 ×16 Components DQ[7:0] X DQ[15:8] X LDQS X LDQS 0 UDQS X UDQS 0 LDM X UDM X X X Note: X = don’t care; 0 = bit set to low; 1 = bit set to high TABLE 19 Burst Length and Sequence Burst Length Starting Address (A2 A1 A0) Sequential Addressing (decimal) Interleave Addressing (decimal) 4 ×00 0, 1, 2, 3 0, 1, 2, 3 ×01 1, 2, 3, 0 1, 0, 3, 2 ×1 0 2, 3, 0, 1 2, 3, 0, 1 8 Rev. 1.21, 2007-07 02282007-F8UP-4HSU ×1 1 3, 0, 1, 2 3, 2, 1, 0 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 011 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 111 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 21 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM 4 Truth Tables This chapter describes the truth tables. TABLE 20 Command Truth Table Function CKE CS RAS CAS WE BA0 BA1 BA2 A[13:11] A10 A[9:0] Note1)2)3) Previous Cycle Current Cycle (Extended) Mode Register Set H H L L L L BA OP Code Auto-Refresh H H L L L H X X X X 4) Self-Refresh Entry H L L L L H X X X X 4)7) Self-Refresh Exit L H H X X X X X X X 4)7)8) L H H H 4)5)6) Single Bank Precharge H H L L H L BA X L X 4)5) Precharge all Banks H H L L H L X X H X 4)5) Bank Activate H H L L H H BA Row Address Write H H L H L L BA Column L Column 4)5)9) Write with AutoPrecharge H H L H L L BA Column H Column 4)5)9) Read H H L H L H BA Column L Column 4)5)9) Read with AutoPrecharge H H L H L H BA Column H Column 4)5)9) No Operation H X L H H H X X X X 4) Device Deselect H X H X X X X X X X 4) Power Down Entry H L H X X X X X X X 4)10) L H H H H X X X X X X X 4)10) L H H H Power Down Exit L H 4)5) 1) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. 2) “X” means H or L (but a defined logic level)”. 3) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4) All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock. 5) Bank addresses BA[2:0] determine which bank is to be operated upon. For (E)MRS BA[2:0] selects an (Extended) Mode Register. 6) All banks must be in a precharged idle state, CKE must be high at least for tXP and all read/write bursts must be finished before the (Extended) Mode Register set Command is issued. 7) VREF must be maintained during Self Refresh operation. 8) Self Refresh Exit is asynchronous. 9) Burst reads or writes at BL = 4 cannot be terminated. See Table 19 for details. 10) The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh requirements. Rev. 1.21, 2007-07 02282007-F8UP-4HSU 22 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM TABLE 21 Clock Enable (CKE) Truth Table for Synchronous Transitions Current State1) CKE Command Action (N)2) (N)2)3)RAS, CAS, WE, CS Note4)5) Previous Cycle6) (N-1) Current Cycle6) (N) L L X Maintain Power-Down 7)8)11) L H DESELECT or NOP Power-Down Exit 7)9)10)11) L L X Maintain Self Refresh 8)11)12) L H DESELECT or NOP Self Refresh Exit 9)12)13)14) Bank(s) Active H L DESELECT or NOP Active Power-Down Entry 7)9)10)11)15) All Banks Idle H L DESELECT or NOP Precharge Power-Down Entry 9)10)11)15) H L AUTOREFRESH Self Refresh Entry 7)11)14)16) H H Refer to the Command Truth Table Power-Down Self Refresh Any State other than listed above 1) 2) 3) 4) 5) 6) 7) 8) 9) 10) 11) 12) 13) 14) 15) 16) 17) 17) Current state is the state of the DDR2 SDRAM immediately prior to clock edge N. Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. CKE must be maintained HIGH while the device is in OCD calibration mode. Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge. The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefor limited by the refresh requirements “X” means “don’t care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven HIGH or LOW in Power Down if the ODT function is enabled (Bit A2 or A6 set to “1” in EMRS(1)). All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. Valid commands for Power-Down Entry and Exit are NOP and DESELECT only. tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2×tCK + tIH. VREF must be maintained during Self Refresh operation. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read commands may be issued only after tXSRD (200 clocks) is satisfied. Valid commands for Self Refresh Exit are NOP and DESELCT only. Power-Down and Self Refresh can not be entered while Read or Write operations, (Extended) mode Register operations, Precharge or Refresh operations are in progress. Self Refresh mode can only be entered from the All Banks Idle state. Must be a legal command as defined in the Command Truth Table. TABLE 22 Data Mask (DM) Truth Table Name (Function) DM DQs Note Write Enable L Valid 1) Write Inhibit H X 1) 1) Used to mask write data; provided coincident with the corresponding data. Rev. 1.21, 2007-07 02282007-F8UP-4HSU 23 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM 5 Electrical Characteristics This chapter describes the Electrical Characteristics. 5.1 Absolute Maximum Ratings Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Table 23 at any time. TABLE 23 Absolute Maximum Ratings Symbol VDD VDDQ VDDL VIN, VOUT TSTG Parameter Rating Unit Note Min. Max. Voltage on VDD pin relative to VSS –1.0 +2.3 V 1) Voltage on VDDQ pin relative to VSS –0.5 +2.3 V 1)2) Voltage on VDDL pin relative to VSS –0.5 +2.3 V 1)2) Voltage on any pin relative to VSS –0.5 +2.3 V 1) °C 1)2) Storage Temperature –55 +100 1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV. 2) Storage Temperature is the case surface temperature on the center/top side of the DRAM. Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. TABLE 24 DRAM Component Operating Temperature Range Symbol TOPER Parameter Rating Operating Temperature Min. Max. 0 95 Unit Note °C 1)2)3)4) 1) Operating Temperature is the case surface temperature on the center / top side of the DRAM. 2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case temperature must be maintained between 0 - 95 °C under all other specification parameters. 3) Above 85 °C the Auto-Refresh command interval has to be reduced to tREFI= 3.9 µs 4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50 % Rev. 1.21, 2007-07 02282007-F8UP-4HSU 24 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM 5.2 DC Characteristics TABLE 25 Recommended DC Operating Conditions (SSTL_18) Symbol VDD VDDDL VDDQ VREF VTT 1) 2) 3) 4) Parameter Rating Unit Note Min. Typ. Max. Supply Voltage 1.7 1.8 1.9 V 1) Supply Voltage for DLL 1.7 1.8 1.9 V 1) Supply Voltage for Output 1.7 1.8 1.9 V 1) Input Reference Voltage 0.49 × VDDQ 0.5 × VDDQ 0.51 × VDDQ V 2)3) 4) Termination Voltage VREF – 0.04 VREF VREF + 0.04 V VDDQ tracks with VDD, VDDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 × VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. Peak to peak ac noise on VREF may not exceed ± 2 % VREF (dc) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in die dc level of VREF. TABLE 26 ODT DC Electrical Characteristics Parameter / Condition Symbol Min. Nom. Max. Unit Note Termination resistor impedance value for EMRS(1)[A6,A2] = [0,1]; 75 Ohm Rtt1(eff) 60 75 90 Ω 1) Termination resistor impedance value for EMRS(1)[A6,A2] =[1,0]; 150 Ohm Rtt2(eff) 120 150 180 Ω 1) Termination resistor impedance value for EMRS(1)(A6,A2)=[1,1]; 50 Ohm Rtt3(eff) 40 50 60 Ω 1) 2) + 6.00 % 1) Measurement Definition for Rtt(eff): Apply VIH(ac) and VIL(ac) to test pin separately, then measure current I(VIHac) and I(VILac) respectively. Rtt(eff) = (VIH(ac) – VIL(ac)) /(I(VIHac) – I(VILac)). 2) Measurement Definition for VM: Turn ODT on and measure voltage (VM) at test pin (midpoint) with no load: delta VM = ((2 x VM / VDDQ) – Deviation of VM with respect to VDDQ / 2 delta VM –6.00 — 1) x 100 % TABLE 27 Input and Output Leakage Currents Symbol Parameter / Condition Min. Max. Unit Note IIL IOL Input Leakage Current; any input 0 V < VIN < VDD –2 +2 µA 1) Output Leakage Current; 0 V < VOUT < VDDQ –5 +5 µA 2) 1) All other pins not under test = 0 V 2) DQ’s, LDQS, LDQS, UDQS, UDQS, DQS, DQS, RDQS, RDQS are disabled and ODT is turned off Rev. 1.21, 2007-07 02282007-F8UP-4HSU 25 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM 5.3 DC & AC Characteristics DDR2 SDRAM pin timing are specified for either single ended or differential mode depending on the setting of the EMRS(1) “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timing are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is verified by design and characterization but not subject to production test. In single ended mode, the DQS (and RDQS) signals are internally disabled and don’t care. TABLE 28 DC & AC Logic Input Levels for DDR2-667 and DDR2-800 Symbol VIH(dc) VIL(dc) VIH(ac) VIL(ac) Parameter DDR2-667, DDR2-800 Units Min. Max. DC input logic high VREF + 0.125 –0.3 VDDQ + 0.3 VREF – 0.125 V DC input low AC input logic high VREF + 0.200 — V AC input low — VREF – 0.200 V V TABLE 29 DC & AC Logic Input Levels for DDR2-533 and DDR2-400 Symbol VIH(dc) VIL(dc) VIH(ac) VIL(ac) Parameter DDR2-533, DDR2-400 Units Min. Max. VREF + 0.125 V DC input low –0.3 VDDQ + 0.3 VREF - 0.125 AC input logic high VREF + 0.250 — V AC input low — VREF - 0.250 V DC input logic high Rev. 1.21, 2007-07 02282007-F8UP-4HSU 26 V Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM TABLE 30 Single-ended AC Input Test Conditions Symbol Condition Value Unit Note VREF VSWING.MAX Input reference voltage 0.5 x VDDQ V 1) Input signal maximum peak to peak swing 1.0 V 1) SLEW Input signal minimum Slew Rate 1.0 V / ns 2)3) 1) Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. 2) The input signal minimum Slew Rate is to be maintained over the range from VIH(ac).MIN to VREF for rising edges and the range from VREF to VIL(ac).MAX for falling edges as shown in Figure 3 3) AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions. FIGURE 3 Single-ended AC Input Test Conditions Diagram 9''4 9,+ DF PLQ 9,+ GF PLQ 96:,1* 0$; 95() 9,/ GF PD[ 9,/ DF PD[ 966 'HOWD7) )DOOLQJ6OHZ 'HOWD75 95()9,/ DF PD[ 5LVLQJ6OHZ 'HOWD7) 9,+ DF PLQ95() 'HOWD75 03(7 Rev. 1.21, 2007-07 02282007-F8UP-4HSU 27 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM TABLE 31 Differential DC and AC Input and Output Logic Levels Symbol Parameter Min. Max. Unit Note VIN(dc) VID(dc) VID(ac) VIX(ac) VOX(ac) DC input signal voltage –0.3 — 1) DC differential input voltage 0.25 — 2) AC differential input voltage 0.5 V 3) AC differential cross point input voltage 0.5 × VDDQ – 0.175 V 4) AC differential cross point output voltage 0.5 × VDDQ – 0.125 VDDQ + 0.3 VDDQ + 0.6 VDDQ + 0.6 0.5 × VDDQ + 0.175 0.5 × VDDQ + 0.125 V 5) 1) 2) 3) 4) VIN(dc) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS etc. VID(dc) specifies the input differential voltage VTR– VCP required for switching. The minimum value is equal to VIH(dc) – VIL(dc). VID(ac) specifies the input differential voltage VTR – VCP required for switching. The minimum value is equal to VIH(ac) – VIL(ac). The value of VIX(ac) is expected to equal 0.5 × VDDQ of the transmitting device and VIX(ac) is expected to track variations in VDDQ. VIX(ac) indicates the voltage at which differential input signals must cross. 5) The value of VOX(ac) is expected to equal 0.5 × VDDQ of the transmitting device and VOX(ac) is expected to track variations in VDDQ. VOX(ac) indicates the voltage at which differential input signals must cross. FIGURE 4 Differential DC and AC Input and Output Logic Levels Diagram 9'' 4 975 &URVVLQJ3RLQW 9,' 9&3 9,;RU9 2; 9664 Rev. 1.21, 2007-07 02282007-F8UP-4HSU 28 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM 5.4 Output Buffer Characteristics This chapter describes the Output Buffer Characteristics. TABLE 32 SSTL_18 Output DC Current Drive Symbol IOH IOL Parameter SSTL_18 Output Minimum Source DC Current –13.4 Unit Note mA 1)2) 2)3) Output Minimum Sink DC Current 13.4 mA 1) VDDQ = 1.7 V; VOUT = 1.42 V. (VOUT–VDDQ) / IOH must be less than 21 Ohm for values of VOUT between VDDQ and VDDQ – 280 mV. 2) The values of IOH(dc) and IOL(dc) are based on the conditions given in 1) and 3). They are used to test drive current capability to ensure VIH.MIN. plus a noise margin and VIL.MAX minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating points along 21 Ohm load line to define a convenient current for measurement. 3) VDDQ = 1.7 V; VOUT = 280 mV. VOUT / IOL must be less than 21 Ohm for values of VOUT between 0 V and 280 mV. TABLE 33 SSTL_18 Output AC Test Conditions Symbol Parameter SSTL_18 Unit Note VOH VOL VOTR Minimum Required Output Pull-up VTT + 0.603 VTT – 0.603 0.5 × VDDQ V 1) V 1) Maximum Required Output Pull-down Output Timing Measurement Reference Level V 1) SSTL_18 test load for VOH and VOL is different from the referenced load. The SSTL_18 test load has a 20 Ohm series resistor additionally to the 25 Ohm termination resistor into VTT. The SSTL_18 definition assumes that ± 335 mV must be developed across the effectively 25 Ohm termination resistor (13.4 mA × 25 Ohm = 335 mV). With an additional series resistor of 20 Ohm this translates into a minimum requirement of 603 mV swing relative to VTT, at the ouput device (13.4 mA × 45 Ohm = 603 mV). TABLE 34 OCD Default Characteristics Symbol Description Min. — Output Impedance — — Pull-up / Pull down mismatch 0 — — Output Impedance step size for OCD calibration 0 1.5 SOUT Output Slew Rate 1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V Nominal Max. Unit Note Ω 1)2) 4 Ω 1)2)3) — 1.5 Ω 4) — 5.0 V / ns 1)5)6)7) 2) Impedance measurement condition for output source dc current: VDDQ = 1.7 V, VOUT = 1420 mV; (VOUT–VDDQ) / IOH must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ – 280 mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7 V; VOUT = –280 mV; VOUT / IOL must be less than 23.4 Ohms for values of VOUT between 0 V and 280 mV. 3) Mismatch is absolute value between pull-up and pull-down, both measured at same temperature and voltage. 4) This represents the step size when the OCD is near 18 ohms at nominal conditions across all process parameters and represents only the DRAM uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is 18 ± 0.75 Ohms under nominal conditions. 5) The absolute value of the Slew Rate as measured from DC to DC is equal to or greater than the Slew Rate as measured from AC to AC. This is verified by design and characterization but not subject to production test. 6) Timing skew due to DRAM output Slew Rate mis-match between DQS / DQS and associated DQ’s is included in tDQSQ and tQHS specification. 7) DRAM output Slew Rate specification applies to 400, 533 and 667 MT/s speed bins. Rev. 1.21, 2007-07 02282007-F8UP-4HSU 29 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM 5.5 Input / Output Capacitance This chapter contains the input / output capacitance. TABLE 35 Input / Output Capacitance for DDR2-800 Symbol Parameter DDR2-800 Min. Max. Unit CCK Input capacitance, CK and CK 1.0 2.0 pF CDCK Input capacitance delta, CK and CK — 0.25 pF CI Input capacitance, all other input-only pins 1.0 1.75 pF CDI Input capacitance delta, all other input-only pins — 0.25 pF CIO Input/output capacitance, DQ, DM, DQS, DQS, RDQS, RDQS 2.5 3.5 pF CDIO Input/output capacitance delta, DQ, DM, DQS, DQS, RDQS, RDQS — 0.5 pF TABLE 36 Input / Output Capacitance for DDR2-667 Symbol Parameter DDR2-667 Min. Max. Unit CCK Input capacitance, CK and CK 1.0 2.0 pF CDCK Input capacitance delta, CK and CK — 0.25 pF CI Input capacitance, all other input-only pins 1.0 2.0 pF CDI Input capacitance delta, all other input-only pins — 0.25 pF CIO Input/output capacitance, DQ, DM, DQS, DQS, RDQS, RDQS 2.5 4.0 pF CDIO Input/output capacitance delta, DQ, DM, DQS, DQS, RDQS, RDQS — 0.5 pF Rev. 1.21, 2007-07 02282007-F8UP-4HSU 30 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM TABLE 37 Input / Output Capacitance for DDR2-533 Symbol Parameter DDR2-533 Min. Max. Unit CCK Input capacitance, CK and CK 1.0 2.0 pF CDCK Input capacitance delta, CK and CK — 0.25 pF CI Input capacitance, all other input-only pins 1.0 2.0 pF CDI Input capacitance delta, all other input-only pins — 0.25 pF CIO Input/output capacitance, DQ, DM, DQS, DQS, RDQS, RDQS 2.5 4.0 pF CDIO Input/output capacitance delta, DQ, DM, DQS, DQS, RDQS, RDQS — 0.5 pF TABLE 38 Input / Output Capacitance for DDR2-400 Symbol Parameter DDR2-400 Min. Max. Unit CCK Input capacitance, CK and CK 1.0 2.0 pF CDCK Input capacitance delta, CK and CK — 0.25 pF CI Input capacitance, all other input-only pins 1.0 2.0 pF CDI Input capacitance delta, all other input-only pins — 0.25 pF CIO Input/output capacitance, DQ, DM, DQS, DQS, RDQS, RDQS 2.5 4.0 pF CDIO Input/output capacitance delta, DQ, DM, DQS, DQS, RDQS, RDQS — 0.5 pF Rev. 1.21, 2007-07 02282007-F8UP-4HSU 31 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM 5.6 Overshoot and Undershoot Specification This chapter contains Overshoot and Undershoot Specification. TABLE 39 AC Overshoot / Undershoot Specification for Address and Control Pins Parameter DDR2-400 DDR2-533 DDR2-667 DDR2-800 Unit Maximum peak amplitude allowed for overshoot area 0.9 0.9 0.9 0.9 V Maximum peak amplitude allowed for undershoot area 0.9 0.9 0.9 0.9 V Maximum overshoot area above VDD 1.33 1.00 0.80 0.66 V.ns Maximum undershoot area below VSS 1.33 1.00 0.80 0.66 V.ns FIGURE 5 AC Overshoot / Undershoot Diagram for Address and Control Pins 0D[LPXP$PSOLWXGH 9ROWV 9 2YHUVKRRW$UHD 9'' 966 8QGHUVKRRW$UHD 0D[LPXP$PSOLWXGH 7LPH QV 03(7 Rev. 1.21, 2007-07 02282007-F8UP-4HSU 32 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM TABLE 40 AC Overshoot / Undershoot Spec. for Clock, Data, Strobe and Mask Pins Parameter DDR2-400 DDR2-533 DDR2-667 DDR2-800 Unit Maximum peak amplitude allowed for overshoot area 0.9 0.9 0.9 0.9 V Maximum peak amplitude allowed for undershoot area 0.9 0.9 0.9 0.9 V Maximum overshoot area above VDDQ 0.38 0.28 0.23 0.23 V.ns Maximum undershoot area below VSSQ 0.38 0.28 0.23 0.23 V.ns FIGURE 6 AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins 0D[LPXP$PSOLWXGH 9ROWV 9 2YHUVKRRW$UHD 9''4 9664 8QGHUVKRRW$UHD 0D[LPXP$PSOLWXGH 7LPH QV 03(7 Rev. 1.21, 2007-07 02282007-F8UP-4HSU 33 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM 6 Currents Measurement Conditions This chapter describes the Current Measurement, Specifications and Conditions. TABLE 41 IDD Measurement Conditions Parameter Symbol Note Operating Current - One bank Active - Precharge IDD0 tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are switching; Databus inputs are switching. 1)2)3)4)5) IDD1 1)2)3)4)5) Operating Current - One bank Active - Read - Precharge IOUT = 0 mA, BL = 4, tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), tRCD = tRCD(IDD), AL = 0, CL = CL(IDD); CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are switching; Databus inputs are switching. 6) 6) Precharge Power-Down Current IDD2P All banks idle; CKE is LOW; tCK = tCK(IDD);Other control and address inputs are stable; Data bus inputs are floating. 1)2)3)4)5) IDD2N 1)2)3)4)5) Precharge Quiet Standby Current IDD2Q All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are stable, Data bus inputs are floating. 1)2)3)4)5) Precharge Standby Current All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are switching, Data bus inputs are switching. 6) 6) 6) Active Power-Down Current All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable; Data bus inputs are floating. MRS A12 bit is set to “0” (Fast Power-down Exit). IDD3P(0) 1)2)3)4)5) Active Power-Down Current All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable, Data bus inputs are floating. MRS A12 bit is set to 1 (Slow Power-down Exit); IDD3P(1) 1)2)3)4)5) Active Standby Current All banks open; tCK = tCK(IDD); tRAS = tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are switching; Data Bus inputs are switching; IDD3N 1)2)3)4)5) Operating Current IDD4R Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD); tRAS = tRAS.MAX.(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are switching; Data Bus inputs are switching; IOUT = 0 mA. 1)2)3)4)5) Operating Current IDD4W Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD); tRAS = tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are switching; Data Bus inputs are switching; 1)2)3)4)5) IDD5B 1)2)3)4)5) Distributed Refresh Current IDD5D tCK = tCK(IDD), Refresh command every tREFI = 7.8 µs interval, CKE is LOW and CS is HIGH between valid commands, Other control and address inputs are switching, Data bus inputs are switching. 1)2)3)4)5) Burst Refresh Current tCK = tCK(IDD), Refresh command every tRFC = tRFC(IDD) interval, CKE is HIGH, CS is HIGH between valid commands, Other control and address inputs are switching, Data bus inputs are switching. Rev. 1.21, 2007-07 02282007-F8UP-4HSU 34 6) 6) 6) 6) 6) 6) 6) Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM Parameter Symbol Note Self-Refresh Current IDD6 CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are floating, Data bus inputs are floating. 1)2)3)4)5) Operating Bank Interleave Read Current IDD7 1. All banks interleaving reads, IOUT = 0 mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD) -1 × tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD); tFAW = tFAW(IDD); CKE is HIGH, CS is HIGH between valid commands. Address bus inputs are stable during deselects; Data bus is switching. 2. Timing pattern: 1)2)3)4)5) 6) 6)7) DDR2-400-333: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D (11 clocks) DDR2-533-333: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D (15 clocks) DDR2-667-555: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D (20 clocks) DDR2-800-555: A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D(22 clocks) 1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V 2) IDD specifications are tested after the device is properly initialized. 3) IDD parameter are specified with ODT disabled. 4) 5) 6) 7) Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS. Definitions for IDD: see Table 42 Timing parameter minimum and maximum values for IDD current measurements are defined in chapter 7.. A = Activate, RA = Read with Auto-Precharge, D=DESELECT TABLE 42 Definition for IDD Parameter Description LOW defined as VIN ≤ VIL(ac).MAX HIGH defined as VIN ≥ VIH(ac).MIN STABLE defined as inputs are stable at a HIGH or LOW level FLOATING defined as inputs are VREF = VDDQ / 2 SWITCHING defined as: Inputs are changing between high and low every other clock (once per two clocks) for address and control signals, and inputs changing between high and low every other clock (once per clock) for DQ signals not including mask or strobes Rev. 1.21, 2007-07 02282007-F8UP-4HSU 35 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM TABLE 43 IDD Specification Symbol IDD0 IDD1 IDD2P IDD2N IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7 -2.5 -3S -3.7 -5 DDR2 - 800 DDR2 - 667 DDR2 - 533 DDR2 - 400 125 110 100 95 Unit Note mA ×8 150 135 125 120 mA x16 135 120 105 100 mA ×8 160 145 130 125 mA x16 12 12 12 12 mA 70 65 55 50 mA 65 60 50 45 mA 48 45 38 35 mA 1) 15 15 15 15 mA 2) 90 70 60 55 mA 200 170 150 135 mA x8 240 205 175 150 mA x16 200 170 150 135 mA x8 240 205 175 150 mA x16 225 210 200 190 mA 13 13 13 13 mA 3) 10 10 10 10 mA 3) 270 230 225 215 mA x8 340 300 280 265 mA x16 1) MRS(12)=0 2) MRS(12)=1 3) 0° ≤ TCASE ≤ 85 °C. Rev. 1.21, 2007-07 02282007-F8UP-4HSU 36 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM 7 Timing Characteristics This chapter contains speed grade definition, AC timing parameter and ODT tables. 7.1 Speed Grade Definitions All Speed grades faster than DDR2-400B comply with DDR2-400B timing specifications (tCK = 5ns with tRAS = 40ns). TABLE 44 Speed Grade Definition Speed Bins for DDR2–800E Speed Grade DDR2–800E QAG Sort Name –2.5 CAS-RCD-RP latencies 6–6–6 Parameter Clock Frequency @ CL = 3 @ CL = 4 @ CL = 5 @ CL = 6 Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time Unit Note tCK Symbol Min. Max. — tCK tCK tCK tCK tRAS tRC tRCD tRP 5 8 ns 1)2)3)4) 3.75 8 ns 1)2)3)4) 3 8 ns 1)2)3)4) 2.5 8 ns 1)2)3)4) 45 70000 ns 1)2)3)4)5) 60 — ns 1)2)3)4) 15 — ns 1)2)3)4) 15 — ns 1)2)3)4) 1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) under the “Reference Load for Timing Measurements”. 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode; The input reference level for signals other than CK/CK, DQS / DQS, RDQS / RDQS is defined. 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI. Rev. 1.21, 2007-07 02282007-F8UP-4HSU 37 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM TABLE 45 Speed Grade Definition Speed Bins for DDR2–667D Speed Grade DDR2–667D QAG Sort Name –3S CAS-RCD-RP latencies 5–5–5 Parameter Clock Frequency @ CL = 3 @ CL = 4 @ CL = 5 Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time Unit Note tCK Symbol Min. Max. — tCK tCK tCK tRAS tRC tRCD tRP 5 8 ns 1)2)3)4) 3.75 8 ns 1)2)3)4) 3 8 ns 1)2)3)4) 45 70000 ns 1)2)3)4)5) 60 — ns 1)2)3)4) 15 — ns 1)2)3)4) 15 — ns 1)2)3)4) 1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) under the “Reference Load for Timing Measurements”. 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode; The input reference level for signals other than CK/CK, DQS / DQS, RDQS / RDQS is defined. 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI. TABLE 46 Speed Grade Definition Speed Bins for DDR2–533C Speed Grade DDR2–533C QAG Sort Name –3.7 CAS-RCD-RP latencies 4–4–4 Parameter Clock Frequency @ CL = 3 @ CL = 4 @ CL = 5 Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time Unit Note tCK Symbol Min. Max. — tCK tCK tCK tRAS tRC tRCD tRP 5 8 ns 1)2)3)4) 3.75 8 ns 1)2)3)4) 3.75 8 ns 1)2)3)4) 45 70000 ns 1)2)3)4)5) 60 — ns 1)2)3)4) 15 — ns 1)2)3)4) 15 — ns 1)2)3)4) 1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) under the “Reference Load for Timing Measurements”. 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode; The input reference level for signals other than CK/CK, DQS / DQS, RDQS / RDQS is defined. Rev. 1.21, 2007-07 02282007-F8UP-4HSU 38 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI. TABLE 47 Speed Grade Definition Speed Bins for DDR2-400B Speed Grade DDR2–400B QAG Sort Name –5 CAS-RCD-RP latencies 3–3–3 Parameter Clock Frequency @ CL = 3 @ CL = 4 @ CL = 5 Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time Unit Note tCK Symbol Min. Max. — tCK tCK tCK tRAS tRC tRCD tRP 5 8 ns 1)2)3)4) 5 8 ns 1)2)3)4) 5 8 ns 1)2)3)4) 40 70000 ns 1)2)3)4)5) 55 — ns 1)2)3)4) 15 — ns 1)2)3)4) 15 — ns 1)2)3)4) 1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) under the “Reference Load for Timing Measurements”. 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode; The input reference level for signals other than CK/CK, DQS / DQS, RDQS / RDQS is defined. 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI. Rev. 1.21, 2007-07 02282007-F8UP-4HSU 39 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM 7.2 Component AC Timing Parameters List of Timing Parameters Tables. TABLE 48 DRAM Component Timing Parameter by Speed Grade - DDR2–800 Parameter Symbol DDR2–800 Unit Note1)2)3)4)5)6)7) 8) Min. Max. tAC tCCD tCH.AVG tCK.AVG tCKE –400 +400 ps 2 — nCK 0.48 0.52 tCK.AVG 9)10) 2500 8000 ps 9)10) 3 — nCK 11) tCL.AVG Auto-Precharge write recovery + precharge time tDAL Minimum time clocks remain ON after CKE tDELAY 0.48 0.52 tCK.AVG 9)10) WR + tnRP — nCK 12)13) tIS + tCK .AVG + tIH –– ns tDH.BASE DQ and DM input pulse width for each input tDIPW DQS output access time from CK / CK tDQSCK DQS input high pulse width tDQSH DQS input low pulse width tDQSL DQS-DQ skew for DQS & associated DQ signals tDQSQ DQS latching rising transition to associated clock tDQSS 125 –– ps 0.35 — tCK.AVG –350 +350 ps 0.35 — 0.35 — tCK.AVG tCK.AVG — 200 ps 15) – 0.25 + 0.25 tCK.AVG 16) tDS.BASE DQS falling edge hold time from CK tDSH DQS falling edge to CK setup time tDSS Four Activate Window for 1KB page size products tFAW Four Activate Window for 2KB page size products tFAW CK half pulse width tHP 50 — ps 17)18)19) 16) tHZ Address and control input hold time tIH.BASE Control & address input pulse width for each input tIPW Address and control input setup time tIS.BASE DQ low impedance time from CK/CK tLZ.DQ DQS/DQS low-impedance time from CK / CK tLZ.DQS MRS command to ODT update delay tMOD Mode register set command cycle time tMRD tOIT OCD drive mode output delay DQ/DQS output hold time from DQS tQH DQ output access time from CK / CK CAS to CAS command delay Average clock high pulse width Average clock period CKE minimum pulse width ( high and low pulse width) Average clock low pulse width asynchronously drops LOW DQ and DM input hold time edges DQ and DM input setup time Data-out high-impedance time from CK / CK Rev. 1.21, 2007-07 02282007-F8UP-4HSU 40 18)19)14) 8) 0.2 — 0.2 — tCK.AVG tCK.AVG 35 — ns 30) 45 — ns 30) Min(tCH.ABS, tCL.ABS) — ps 20) — tAC.MAX ps 8)21) 250 — ps 22)24) 16) 0.6 — tCK.AVG 175 — ps 23)24) 2 x tAC.MIN tAC.MAX ps 8)21) tAC.MIN tAC.MAX ps 8)21) 0 12 ns 30) 2 — nCK 0 12 ns 30) tHP – tQHS — ps 25) Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM Parameter Symbol DDR2–800 Unit Note1)2)3)4)5)6)7) Min. Max. tQHS tRPRE tRPST tRRD — 300 ps 26) 0.9 1.1 27)28) 0.4 0.6 tCK.AVG tCK.AVG 7.5 — ns 30) Active to active command period for 2KB page size products tRRD 10 — ns 30) Internal Read to Precharge command delay tRTP tWPRE tWPST tWR tWTR tXARD tXARDS 7.5 — ns 30) 0.35 — 0.4 0.6 tCK.AVG tCK.AVG 15 — ns 30) 7.5 — ns 30)31) 2 — nCK 8 – AL — nCK Exit precharge power-down to any valid command (other than NOP or Deselect) tXP 2 — nCK Exit self-refresh to a non-read command tRFC +10 — ns Exit self-refresh to read command tXSNR tXSRD 200 — nCK Write command to DQS associated clock edges WL RL – 1 DQ hold skew factor Read preamble Read postamble Active to active command period for 1KB page size products Write preamble Write postamble Write recovery time Internal write to read command delay Exit power down to read command Exit active power-down mode to read command (slow exit, lower power) 27)29) 30) nCK 1) VDDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V. 2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. The input reference level for signals other than CK/CK, DQS/DQS, RDQS / RDQS is defined. 5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 6) The output timing reference voltage level is VTT. 7) New units, ‘tCK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘tCK.AVG‘ represents the actual tCK.AVG of the input clock under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and DDR2–533, ‘tCK‘ is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min). 8) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tERR(6-10PER).MIN = – 272 ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN – tERR(6-10PER).MAX = – 400 ps – 293 ps = – 693 ps and tDQSCK.MAX(DERATED) = tDQSCK.MAX – tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2–667 derates to tLZ.DQ.MIN(DERATED) = - 900 ps – 293 ps = – 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!) 9) Input clock jitter spec parameter. These parameters and the ones in Chapter 7.3 are referred to as 'input clock jitter spec parameters' and these parameters apply to DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution. 10) These parameters are specified per their average values, however it is understood that the relationship as defined in Chapter 7.3 between the average timing and the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations of Chapter 7.3). 11) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK + tIH. Rev. 1.21, 2007-07 02282007-F8UP-4HSU 41 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM 12) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For DDR2–533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 13) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR. 14) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and VIH.DC.MIN. See Figure 8. 15) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch between DQS / DQS and associated DQ in any given cycle. 16) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not. 17) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN. See Figure 8. 18) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed. 19) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal ((L/U/R)DQS / DQS) crossing. 20) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the minimum of the actual instantaneous clock low time. 21) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) . 22) Input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied to the device under test. See Figure 9. 23) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied to the device under test. See Figure 9. 24) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not. 25) tQH = tHP – tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.} Examples: 1) If the system provides tHP of 1315 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system provides tHP of 1420 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 1080 ps minimum. 26) tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation of the output drivers. 27) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). Figure 7 shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. 28) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.PER.MIN = – 72 ps and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG – 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX + tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!). 29) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.DUTY.MIN = – 72 ps and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG – 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX + tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!). Rev. 1.21, 2007-07 02282007-F8UP-4HSU 42 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM 30) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which tRP = 15 ns, the device will support tnRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter. 31) tWTR is at lease two clocks (2 x tCK) independent of operation frequency. TABLE 49 DRAM Component Timing Parameter by Speed Grade - DDR2–667 Parameter Symbol DDR2–667 Unit Note1)2)3)4)5)6)7) 8) Min. Max. tAC tCCD tCH.AVG tCK.AVG tCKE –450 +450 ps 2 — nCK 0.48 0.52 tCK.AVG 3000 8000 ps 3 — nCK 11) tCL.AVG Auto-Precharge write recovery + precharge time tDAL Minimum time clocks remain ON after CKE tDELAY 0.48 0.52 tCK.AVG 9)10) WR + tnRP — nCK 12)13) tIS + tCK .AVG + tIH — ns tDH.BASE DQ and DM input pulse width for each input tDIPW DQS output access time from CK / CK tDQSCK DQS input high pulse width tDQSH DQS input low pulse width tDQSL DQS-DQ skew for DQS & associated DQ signals tDQSQ DQS latching rising transition to associated clock tDQSS 175 –– ps 0.35 — tCK.AVG –400 +400 ps 0.35 — 0.35 — tCK.AVG tCK.AVG — 240 ps 15) – 0.25 + 0.25 tCK.AVG 16) tDS.BASE DQS falling edge hold time from CK tDSH DQS falling edge to CK setup time tDSS Four Activate Window for 1KB page size products tFAW Four Activate Window for 2KB page size products tFAW CK half pulse width tHP 100 –– ps 17)18)19) 0.2 — 16) 0.2 — tCK.AVG tCK.AVG 37.5 — ns 30) 50 — ns 30) Min(tCH.ABS, tCL.ABS) __ ps 20) tHZ Address and control input hold time tIH.BASE Control & address input pulse width for each input tIPW Address and control input setup time tIS.BASE DQ low impedance time from CK/CK tLZ.DQ DQS/DQS low-impedance time from CK / CK tLZ.DQS MRS command to ODT update delay tMOD Mode register set command cycle time tMRD — tAC.MAX ps 8)21) 275 — ps 24)22) DQ output access time from CK / CK CAS to CAS command delay Average clock high pulse width Average clock period CKE minimum pulse width ( high and low pulse width) Average clock low pulse width asynchronously drops LOW DQ and DM input hold time edges DQ and DM input setup time Data-out high-impedance time from CK / CK Rev. 1.21, 2007-07 02282007-F8UP-4HSU 43 9)10) 18)19)14) 8) 16) 0.6 — tCK.AVG 200 — ps 23)24) 2 x tAC.MIN ps 8)21) tAC.MIN tAC.MAX tAC.MAX ps 8)21) 0 12 ns 30) 2 — nCK Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM Parameter Symbol DDR2–667 Unit Note1)2)3)4)5)6)7) Min. Max. tOIT tQH tQHS tRPRE tRPST tRRD 0 12 ns 30) tHP – tQHS — ps 25) — 340 ps 26) 27)28) Active to active command period for 2KB page size products Internal Read to Precharge command delay OCD drive mode output delay DQ/DQS output hold time from DQS DQ hold skew factor 0.9 1.1 0.4 0.6 tCK.AVG tCK.AVG 7.5 — ns 30) tRRD 10 — ns 30) tRTP tWPRE tWPST tWR tWTR tXARD tXARDS 7.5 — ns 30) 0.35 — 0.4 0.6 tCK.AVG tCK.AVG 15 — ns 30) 7.5 — ns 30)31) 2 — nCK 7 – AL — nCK Exit precharge power-down to any valid command (other than NOP or Deselect) tXP 2 — nCK Exit self-refresh to a non-read command tXSNR tXSRD tRFC +10 — ns 200 — WL RL–1 Read preamble Read postamble Active to active command period for 1KB page size products Write preamble Write postamble Write recovery time Internal write to read command delay Exit power down to read command Exit active power-down mode to read command (slow exit, lower power) Exit self-refresh to read command Write command to DQS associated clock edges 1) VDDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V. 27)29) 30) nCK nCK 2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. The input reference level for signals other than CK/CK, DQS/DQS, RDQS / RDQS is defined. 5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 6) The output timing reference voltage level is VTT. 7) New units, ‘tCK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘tCK.AVG‘ represents the actual tCK.AVG of the input clock under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and DDR2–533, ‘tCK‘ is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min). 8) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tERR(6-10PER).MIN = – 272 ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN – tERR(6-10PER).MAX = – 400 ps – 293 ps = – 693 ps and tDQSCK.MAX(DERATED) = tDQSCK.MAX – tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2–667 derates to tLZ.DQ.MIN(DERATED) = - 900 ps – 293 ps = – 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!) 9) Input clock jitter spec parameter. These parameters and the ones in Chapter 7.3 are referred to as 'input clock jitter spec parameters' and these parameters apply to DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution. 10) These parameters are specified per their average values, however it is understood that the relationship as defined in Chapter 7.3 between the average timing and the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations of Chapter 7.3). Rev. 1.21, 2007-07 02282007-F8UP-4HSU 44 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM 11) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK + tIH. 12) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For DDR2–533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 13) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR. 14) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and VIH.DC.MIN. See Figure 8. 15) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch between DQS / DQS and associated DQ in any given cycle. 16) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not. 17) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN. See Figure 8. 18) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed. 19) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal ((L/U/R)DQS / DQS) crossing. 20) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the minimum of the actual instantaneous clock low time. 21) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) . 22) Input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied to the device under test. See Figure 9. 23) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied to the device under test. See Figure 9. 24) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not. 25) tQH = tHP – tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.} Examples: 1) If the system provides tHP of 1315 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system provides tHP of 1420 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 1080 ps minimum. 26) tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation of the output drivers. 27) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). Figure 7 shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. 28) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.PER.MIN = – 72 ps and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG – 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX + tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!). 29) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.DUTY.MIN = – 72 ps and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG – 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX + tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!). Rev. 1.21, 2007-07 02282007-F8UP-4HSU 45 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM 30) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which tRP = 15 ns, the device will support tnRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter. 31) tWTR is at lease two clocks (2 x tCK) independent of operation frequency. FIGURE 7 Method for calculating transitions and endpoint 92+[P9 977[P9 92+[P9 977[P9 W/= W+= W535(EHJLQSRLQW W5367 H QGSRLQW 92/[P9 977[P9 92/[P9 977[P9 7 7 7 7 W+=W5367 HQGSRLQW 77 W/=W535( E HJLQSRLQW 7 7 FIGURE 8 Differential input waveform timing - tDS and tDS '46 '46 W'6 W'+ W'6 W'+ 9''4 9,+ DF PL Q 9,+ GF PL Q 95() GF 9,/ GF PD [ 9,/ DF PD [ 966 Rev. 1.21, 2007-07 02282007-F8UP-4HSU 46 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM FIGURE 9 Differential input waveform timing - tlS and tlH &. &. W,6 W,+ W,6 W,+ 9''4 9,+DF PLQ 9,+GF PLQ 95() GF 9,/ GF PD[ 9,/ DF PD[ 966 TABLE 50 DRAM Component Timing Parameter by Speed Grade - DDR2–533 Parameter Symbol DDR2–533 Unit Note1)2)3)4)5) 6) Min. Max. tAC tCCD tCH tCKE tCL tDAL –500 +500 ps 2 — 0.45 0.55 3 — 0.45 0.55 WR + tRP — tCK tCK tCK tCK tCK Minimum time clocks remain ON after CKE asynchronously drops LOW tDELAY tIS + tCK + tIH –– ns 8) DQ and DM input hold time (differential data strobe) tDH(base) 225 –– ps 9) –25 — ps 10) tDIPW tDQSCK tDQSL,H tDQSQ 0.35 — tCK –450 +450 ps 0.35 — tCK — 300 ps tDQSS tDS(base) – 0.25 + 0.25 tCK 100 — ps 10) –25 — ps 10) DQ output access time from CK / CK CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time DQ and DM input hold time (single ended data tDH1(base) strobe) DQ and DM input pulse width (each input) DQS output access time from CK / CK DQS input low (high) pulse width (write cycle) DQS-DQ skew (for DQS & associated DQ signals) Write command to 1st DQS latching transition DQ and DM input setup time (differential data strobe) DQ and DM input setup time (single ended data tDS1(base) strobe) Rev. 1.21, 2007-07 02282007-F8UP-4HSU 47 7)17) 10) Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM Parameter Symbol DDR2–533 Unit Note1)2)3)4)5) 6) Min. Max. tDSH 0.2 — DQS falling edge to CK setup time (write cycle) tDSS 0.2 — tCK 37.5 — ns 50 — ns DQS falling edge hold time from CK (write cycle) Four Activate Window period Four Activate Window period Clock half period tFAW tFAW tHP tHZ tIH(base) tIPW tCK 12) 11) MIN. (tCL, tCH) — tAC.MAX ps 12) 375 — ps 10) 0.6 — tCK tIS(base) tLZ(DQ) tLZ(DQS) tMRD tOIT tQH tQHS tREFI tREFI tRFC 250 — ps 10) 2 × tAC.MIN ps 13) tAC.MIN tAC.MAX tAC.MAX ps 13) 2 — tCK 0 12 ns tHP –tQHS — — 400 ps — 7.8 µs 13)14) — 3.9 µs 15)17) 127.5 — ns 16) tRP tRP tRPRE tRPST tRRD tRP + 1tCK — ns 15 + 1tCK — ns 0.9 1.1 13) 0.40 0.60 tCK tCK 7.5 — ns 13)17) Active bank A to Active bank B command period tRRD 10 — ns 15)21) Internal Read to Precharge command delay tRTP tWPRE tWPST tWR 7.5 — ns 0.25 — 0.40 0.60 tCK tCK 15 — ns tWTR tXARD 7.5 — ns 19) 2 — tCK 20) Exit active power-down mode to Read command (slow exit, lower power) tXARDS 6 – AL — tCK 20) Exit precharge power-down to any valid command (other than NOP or Deselect) tXP 2 — tCK Data-out high-impedance time from CK / CK Address and control input hold time Address and control input pulse width (each input) Address and control input setup time DQ low-impedance time from CK / CK DQS low-impedance from CK / CK Mode register set command cycle time OCD drive mode output delay Data output hold time from DQS Data hold skew factor Average periodic refresh Interval Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Precharge-All (4 banks) command period Precharge-All (8 banks) command period Read preamble Read postamble Active bank A to Active bank B command period Write preamble Write postamble Write recovery time for write without AutoPrecharge Internal Write to Read command delay Exit power down to any valid command (other than NOP or Deselect) Rev. 1.21, 2007-07 02282007-F8UP-4HSU 48 13) 18) Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM Parameter Symbol DDR2–533 Unit Note1)2)3)4)5) 6) Exit Self-Refresh to non-Read command Exit Self-Refresh to Read command Write recovery time for write with AutoPrecharge 1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ±0.1 V. Min. Max. tXSNR tXSRD tRFC +10 — ns 200 — WR tWR/tCK tCK tCK 21) 2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. The input reference level for signals other than CK/CK, DQS/DQS, RDQS / RDQS is defined. 5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 6) The output timing reference voltage level is VTT. 7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MR. 8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. 9) For timing definition, refer to the Component data sheet. 10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle. 11) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). 12) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These parameters are verified by design and characterization, but not subject to production test. 13) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C and 95 °C. 14) 0 °C≤ TCASE ≤ 85 °C 15) 85 °C < TCASE ≤ 95 °C 16) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 17) The tRRD timing parameter depends on the page size of the DRAM organization. See Table 5 “Ordering Information for RoHS compliant products” on Page 6. 18) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 19) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz. 20) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active powerdown mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow power-down exit timing tXARDS has to be satisfied. 21) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MRS. Rev. 1.21, 2007-07 02282007-F8UP-4HSU 49 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM TABLE 51 DRAM Component Timing Parameter by Speed Grade - DDR2-400 Parameter Symbol DDR2–400 Unit Note1)2)3)4)5) 6) Min. Max. tAC tCCD tCH tCKE tCL tDAL –600 +600 ps 2 — 0.45 0.55 3 — 0.45 0.55 WR + tRP — tCK tCK tCK tCK tCK Minimum time clocks remain ON after CKE asynchronously drops LOW tDELAY tIS + tCK + tIH –– ns 8) DQ and DM input hold time (differential data strobe) tDH(base) 275 –– ps 9) –25 — ps 10) 0.35 — tCK –500 +500 ps 0.35 — tCK — 350 ps – 0.25 + 0.25 tCK DQ output access time from CK / CK CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time DQ and DM input hold time (single ended data tDH1(base) strobe) DQ and DM input pulse width (each input) DQS output access time from CK / CK DQS input low (high) pulse width (write cycle) DQS-DQ skew (for DQS & associated DQ signals) tDIPW tDQSCK tDQSL,H tDQSQ Write command to 1st DQS latching transition tDQSS 7)20) 10) DQ and DM input setup time (differential data strobe) tDS(base) 150 — ps 10) DQ and DM input setup time (single ended data strobe) tDS1(base) –25 — ps 10) DQS falling edge hold time from CK (write cycle) tDSH 0.2 — tCK DQS falling edge to CK setup time (write cycle) tDSS 0.2 — tCK 37.5 — ns 50 — ns Four Activate Window period Four Activate Window period Clock half period Data-out high-impedance time from CK / CK Address and control input hold time Address and control input pulse width (each input) Address and control input setup time DQ low-impedance time from CK / CK DQS low-impedance from CK / CK Mode register set command cycle time OCD drive mode output delay Data output hold time from DQS Rev. 1.21, 2007-07 02282007-F8UP-4HSU tFAW tFAW tHP tHZ tIH(base) tIPW 11) MIN. (tCL, tCH) tIS(base) tLZ(DQ) tLZ(DQS) tMRD tOIT tQH 50 12) — tAC.MAX ps 12) 475 — ps 10) 0.6 — tCK 350 — ps 10) 2 × tAC.MIN ps 13) tAC.MIN tAC.MAX tAC.MAX ps 13) 2 — tCK 0 12 ns tHP –tQHS — Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM Parameter Symbol DDR2–400 Unit Note1)2)3)4)5) 6) Min. Max. — 450 ps — 7.8 µs 13)14) — 3.9 µs 15)17) 127.5 — ns 16) tRP tRP tRPRE tRPST tRRD tRP + 1tCK 15 + 1tCK — ns — ns 0.9 1.1 13) 0.40 0.60 tCK tCK 7.5 — ns 13)17) Active bank A to Active bank B command period tRRD 10 — ns 15)21) Internal Read to Precharge command delay tRTP tWPRE tWPST tWR 7.5 — ns 0.25 — 0.40 0.60 tCK tCK 15 — ns tWTR tXARD 10 — ns 19) 2 — tCK 20) Exit active power-down mode to Read command (slow exit, lower power) tXARDS 6 – AL — tCK 20) Exit precharge power-down to any valid command (other than NOP or Deselect) tXP 2 — tCK Exit Self-Refresh to non-Read command tXSNR tXSRD tRFC +10 — ns 200 — WR tWR/tCK tCK tCK Data hold skew factor Average periodic refresh Interval Average periodic refresh Interval tQHS tREFI tREFI Auto-Refresh to Active/Auto-Refresh command period Precharge-All (4 banks) command period Precharge-All (8 banks) command period Read preamble Read postamble Active bank A to Active bank B command period Write preamble Write postamble Write recovery time for write without AutoPrecharge Internal Write to Read command delay Exit power down to any valid command (other than NOP or Deselect) Exit Self-Refresh to Read command Write recovery time for write with AutoPrecharge 1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ±0.1 V. 13) 18) 21) 2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. The input reference level for signals other than CK/CK, DQS/DQS, RDQS / RDQS is defined. 5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 6) The output timing reference voltage level is VTT. 7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MR. 8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. 9) For timing definition, refer to the Component data sheet. 10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle. Rev. 1.21, 2007-07 02282007-F8UP-4HSU 51 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM 11) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). 12) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These parameters are verified by design and characterization, but not subject to production test. 13) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C and 95 °C. 14) 0 °C≤ TCASE ≤ 85 °C 15) 85 °C < TCASE ≤ 95 °C 16) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 17) The tRRD timing parameter depends on the page size of the DRAM organization. See Table 5 “Ordering Information for RoHS compliant products” on Page 6. 18) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 19) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz. 20) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active powerdown mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow power-down exit timing tXARDS has to be satisfied. 21) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MRS. Rev. 1.21, 2007-07 02282007-F8UP-4HSU 52 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM 7.3 Jitter Definition and Clock Jitter Specification Generally, jitter is defined as “the short-term variation of a signal with respect to its ideal position in time”. The following table provides an overview of the terminology. TABLE 52 Average Clock and Jitter Symbols and Definition Symbol Parameter Description Units tCK.AVG Average clock period tCK.AVG is calculated as the average clock period within any consecutive 200-cycle window: ⎛ N ⎞ 1 tCK.AVG = ---- . ⎜ ∑ tCK j⎟ ⎟ N⎜ ⎝j = 1 ⎠ ps (1) N = 200 tJIT.PER Clock-period jitter tJIT(PER, LCK) Clock-period jitter during DLL-locking period tJIT.CC Cycle-to-cycle clock period jitter tJIT(CC, LCK) Cycle-to-cycle clock period jitter during DLL-locking period tERR.2PER Cumulative error across 2 cycles tJIT.PER is defined as the largest deviation of any single tCK from tCK.AVG: tJIT.PER = Min/Max of {tCKi – tCK.AVG} where i = 1 to 200 tJIT.PER defines the single-period jitter when the DLL is already locked. tJIT.PER is not guaranteed through final production testing. tJIT(PER,LCK) uses the same definition as tJIT.PER, during the DLL-locking ps period only. tJIT(PER,LCK) is not guaranteed through final production testing. tJIT.CC is defined as the absolute difference in clock period between two ps tJIT.CC defines the cycle- to- cycle jitter when the DLL is already locked. tJIT.CC is not guaranteed through final production testing. tJIT(CC,LCK) uses the same definition as tJIT.CC during the DLL-locking ps consecutive clock cycles: tJIT.CC = Max of ABS{tCKi+1 – tCKi} period only. tJIT(CC,LCK) is not guaranteed through final production testing. tERR.2PER is defined as the cumulative error across 2 consecutive cycles from tCK.AVG: ⎛i + n – 1 ⎞ ⎜ tERR ( 2per ) = tCK j⎟ – n × tCK ( avg ) ⎜ ∑ ⎟ ⎝ j=i ⎠ n = 2 for tERR(2per) where i = 1 to 200 Rev. 1.21, 2007-07 02282007-F8UP-4HSU ps 53 (2) ps Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM Symbol Parameter Description Units tERR.nPER Cumulative error across n cycles tERR.2PER is defined as the cumulative error across n consecutive cycles from tCK.AVG: ps ⎛i + n – 1 ⎞ tERR ( nper ) = ⎜ ∑ tCK j⎟ – n × tCK ( avg ) ⎜ ⎟ ⎝ j=i ⎠ (3) where, i = 1 to 200 and n = 3 for tERR.3PER n = 4 for tERR.4PER n = 5 for tERR.5PER 6 ≤ n ≤ 10 for tERR.6-10PER 11 ≤ n ≤ 50 for tERR.11-50PER tCH.AVG Average high-pulse width tCH.AVG is defined as the average high-pulse width, as calculated across any consecutive 200 high pulses: ⎛ N ⎞ 1 ⎜ . tCH ( avg ) = ---------------------------------------- ∑ tCH j⎟ ⎟ ( N × tCK ( avg ) ) ⎜ ⎝j = 1 ⎠ tCK.AVG (4) N = 200 tCL.AVG Average low-pulse width tCL.AVG is defined as the average low-pulse width, as calculated across any tCK.AVG consecutive 200 low pulses: ⎛ N ⎞ 1 tCL ( avg ) = ---------------------------------------- . ⎜ ∑ tCL j⎟ ⎟ ( N × tCK ( avg ) ) ⎜ ⎝j = 1 ⎠ (5) N = 200 tJIT.DUTY Duty-cycle jitter tJIT.DUTY = Min/Max of {tJIT.CH , tJIT.CL}, where: tJIT.CH is the largest deviation of any single tCH from tCH.AVG tJIT.CL is the largest deviation of any single tCL from tCL.AVG tJIT.CH = {tCHi - tCH.AVG × tCK.AVG} where i=1 to 200 tJIT.CL = {tCLi - tCL.AVG × tCK.AVG} where i=1 to 200 ps The following parameters are specified per their average values however, it is understood that the following relationship between the average timing and the absolute instantaneous timing holds all the time. Rev. 1.21, 2007-07 02282007-F8UP-4HSU 54 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM TABLE 53 Absolute Jitter Value Definitions Symbol Parameter Min. tCK.ABS tCH.ABS Clock period tCL.ABS Clock low-pulse width tCK.AVG(Min) + tJIT.PER(Min) tCK.AVG(Max) + tJIT.PER(Max) tCH.AVG(Min) x tCK.AVG(Min) + tJIT.DUTY(Min) tCH.AVG(Max) x tCK.AVG(Max) + tJIT.DUTY(Max) tCL.AVG(Min) x tCK.AVG(Min) + tJIT.DUTY(Min) tCL.AVG(Max) x tCK.AVG(Max) + tJIT.DUTY(Max) Clock high-pulse width Max. Unit ps ps ps Example: for DDR2-667, tCH.ABS.MIN = (0.48 x 3000ps) – 125 ps = 1315 ps = 0.438 x 3000 ps. Table 54 shows clock-jitter specifications. TABLE 54 Clock-Jitter Specifications for –667 and –800 Symbol Parameter DDR2 -667 DDR2 -800 Min. Max. Min. Max. Unit tCK.AVG tJIT.PER tJIT(PER,LCK) tJIT.CC tJIT(CC,LCK) Average clock period nominal w/o jitter 3000 8000 2500 8000 ps Clock-period jitter –125 +125 –100 +100 ps Clock-period jitter during DLL locking period –100 +100 –80 +80 ps Cycle-to-cycle clock-period jitter –250 +250 –200 +200 ps Cycle-to-cycle clock-period jitter during DLLlocking period –200 +200 –160 +160 ps tERR.2PER tERR.3PER tERR.4PER tERR.5PER tERR(6-10PER) Cumulative error across 2 cycles –175 +175 –150 +150 ps Cumulative error across 3 cycles –225 +225 –175 +175 ps Cumulative error across 4 cycles –250 +250 –200 +200 ps Cumulative error across 5 cycles –250 +250 –200 +200 ps Cumulative error across n cycles with n = 6 .. 10, inclusive –350 +350 –300 +300 ps tERR(11-50PER) Cumulative error across n cycles with n = 11 .. –450 50, inclusive +450 –450 +450 ps tCH.AVG tCL.AVG tJIT.DUTY Average high-pulse width 0.52 0.48 0.52 Average low-pulse width 0.48 0.52 0.48 0.52 tCK.AVG tCK.AVG Duty-cycle jitter –125 +125 –100 +100 ps Rev. 1.21, 2007-07 02282007-F8UP-4HSU 0.48 55 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM 7.4 ODT AC Electrical Characteristics This chapter describes the ODT AC electrical characteristics. TABLE 55 ODT AC Characteristics and Operating Conditions for DDR2-667 & DDR2-800 Symbol tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD Parameter / Condition Values Unit Note Min. Max. ODT turn-on delay 2 2 nCK 1) ODT turn-on tAC.MAX + 0.7 ns 2 tCK + tAC.MAX + 1 ns ns 1)2) ODT turn-on (Power-Down Modes) tAC.MIN tAC.MIN + 2 ns ns 1) ODT turn-off delay 2.5 2.5 nCK 1) ns 1)3) ns 1) nCK nCK 1) ODT turn-off (Power-Down Modes) tAC.MIN tAC.MIN + 2 ns tAC.MAX + 0.6 ns 2.5 tCK + tAC.MAX + 1 ns ODT to Power Down Mode Entry Latency 3 — ODT turn-off 1) ODT Power Down Exit Latency 8 — 1) New units, “tCK.AVG” and “nCK”, are introduced in DDR2-667 and DDR2-800. Unit “tCK.AVG” represents the actual tCK.AVG of the input clock under operation. Unit “nCK” represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and DDR2-533, “tCK” is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min). 2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-667/800, tAOND is 2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges. 3) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-667/800, if tCK(avg) = 3 ns is assumed, tAOFD is 1.5 ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the actual input clock edges. Rev. 1.21, 2007-07 02282007-F8UP-4HSU 56 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM TABLE 56 ODT AC Characteristics and Operating Conditions for DDR2-533 & DDR2-400 Symbol tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD Parameter / Condition Values Unit Min. Max. ODT turn-on delay 2 2 tCK ODT turn-on tAC.MAX + 1 ns 2 tCK + tAC.MAX + 1 ns ns ODT turn-on (Power-Down Modes) tAC.MIN tAC.MIN + 2 ns ODT turn-off delay 2.5 2.5 tCK ODT turn-off tAC.MAX + 0.6 ns 2.5 tCK + tAC.MAX + 1 ns ns ODT turn-off (Power-Down Modes) tAC.MIN tAC.MIN + 2 ns ODT to Power Down Mode Entry Latency 3 — ODT Power Down Exit Latency 8 — tCK tCK Note 1) ns 2) ns 1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-400/533, tAOND is 10 ns (= 2 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns. 2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-400/533, tAOFD is 12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns. Rev. 1.21, 2007-07 02282007-F8UP-4HSU 57 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM 8 Package Dimensions This chapter contains the Package Dimension figures. FIGURE 10 Package Outline PG-TFBGA-68 [ 0$; % $ [ 0 $; & 0 $; 0,1 & ¡ [ ¡ 0 & $ % ¡ 0 & 3 DFN DJ H2 ULHQ WD WLR Q0 DUN $ 0 LG GOH R I3 DFN DJ HV(G JHV ' XPP\3 DGVZ LWK R XW% DOO % DG8Q LW0 DUN LQJ %8 0 *3$ Notes 1. Drawing according to ISO 8015 2. Dimensions in mm 3. General tolerances +/- 0.15 Rev. 1.21, 2007-07 02282007-F8UP-4HSU & 6($7,1 *3 /$1( 58 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM FIGURE 11 Package Outline PG-TFBGA-84 -!8 X " ! X -!8 # -!8 -). # X - # ! " - # # 3%!4).' 0,!.% ,EAD FREE SOLDER BALLS GREEN SOLDER BALLS $UMMY PADS WITHOUT BALL -IDDLE OF PACKAGES EDGES 0ACKAGE ORIENTATION MARK ! "AD UNIT MARKING "5%MPTY BALL PADS FOR OPTIONAL SUPPORTING SOLDER BALLS X Notes 1. Drawing according to ISO 8015 2. Dimensions in mm 3. General tolerances +/- 0.15 Rev. 1.21, 2007-07 02282007-F8UP-4HSU 59 &0/?0' 4&"'!?? Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM 9 Product Nomenclature For reference the Qimonda SDRAM component nomenclature is enclosed in this chapter. TABLE 57 Nomenclature Fields and Examples Example for DDR2 DRAM Field Number 1 2 3 4 5 6 HYB 18 TC 1G 16 7 8 9 10 11 0 A F –3.7 — TABLE 58 DDR2 Memory Components Field Description Values Coding 1 Qimonda Component Prefix HYB Constant 2 Interface Voltage [V] 18 SSTL_18 3 DRAM Technology, consumer variant TC DDR2 4 Component Density [Mbit] 256 256 M 512 512 M 1G 1 Gb 40 x4 5+6 Number of I/Os 7 Product Variations 8 Die Revision 9 10 11 80 x8 16 x16 0 .. 9 look up table A First B Second C Third Package, Lead-Free Status C FBGA, lead-containing F FBGA, lead-free Speed Grade –1.9 DDR2–1066 –2.5F DDR2–800 5–5–5 –2.5 DDR2–800 6–6–6 –3 DDR2–667 4–4–4 –3S DDR2–667 5–5–5 –3.7 DDR2–533 4–4–4 –5 DDR2–400 3–3–3 N/A for Components Rev. 1.21, 2007-07 02282007-F8UP-4HSU 60 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Ball Configuration for ×8 components, PG-TFBGA-68 (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chip Configuration for x16 Components in PG–TFBGA–84 (Top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single-ended AC Input Test Conditions Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential DC and AC Input and Output Logic Levels Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Overshoot / Undershoot Diagram for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . . . . . . . . . . . . . . Method for calculating transitions and endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential input waveform timing - tDS and tDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential input waveform timing - tlS and tlH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline PG-TFBGA-68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline PG-TFBGA-84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rev. 1.21, 2007-07 02282007-F8UP-4HSU 61 10 14 27 28 32 33 46 46 47 58 59 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Performance tables for –2.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Performance table for –3S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Performance table for –3.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Performance Table for –5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Ordering Information for RoHS compliant products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chip Configuration of DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Abbreviations for Ball Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chip Configuration of DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations for Ball Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DDR2 Addressing for ×8 Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DDR2 Addressing for ×16 Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Mode Register Definition (BA[2:0] = 000B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Extended Mode Register Definition (BA[2:0] = 001B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 EMRS(2) Programming Extended Mode Register Definition (BA[2:0]=010B) . . . . . . . . . . . . . . . . . . . . . . . . . . 19 EMR(3) Programming Extended Mode Register Definition( BA[2:0]=011B) . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ODT Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Burst Length and Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Command Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Clock Enable (CKE) Truth Table for Synchronous Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Data Mask (DM) Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DRAM Component Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Recommended DC Operating Conditions (SSTL_18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 ODT DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Input and Output Leakage Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DC & AC Logic Input Levels for DDR2-667 and DDR2-800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DC & AC Logic Input Levels for DDR2-533 and DDR2-400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Single-ended AC Input Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Differential DC and AC Input and Output Logic Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 SSTL_18 Output DC Current Drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SSTL_18 Output AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 OCD Default Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Input / Output Capacitance for DDR2-800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Input / Output Capacitance for DDR2-667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Input / Output Capacitance for DDR2-533 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Input / Output Capacitance for DDR2-400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 AC Overshoot / Undershoot Specification for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 AC Overshoot / Undershoot Spec. for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 IDD Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Definition for IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 IDD Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Speed Grade Definition Speed Bins for DDR2–800E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Speed Grade Definition Speed Bins for DDR2–667D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Speed Grade Definition Speed Bins for DDR2–533C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Speed Grade Definition Speed Bins for DDR2-400B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 DRAM Component Timing Parameter by Speed Grade - DDR2–800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 DRAM Component Timing Parameter by Speed Grade - DDR2–667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Rev. 1.21, 2007-07 02282007-F8UP-4HSU 62 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 DRAM Component Timing Parameter by Speed Grade - DDR2–533 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DRAM Component Timing Parameter by Speed Grade - DDR2-400. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Average Clock and Jitter Symbols and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Jitter Value Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock-Jitter Specifications for –667 and –800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ODT AC Characteristics and Operating Conditions for DDR2-667 & DDR2-800 . . . . . . . . . . . . . . . . . . . . . . ODT AC Characteristics and Operating Conditions for DDR2-533 & DDR2-400 . . . . . . . . . . . . . . . . . . . . . . . Nomenclature Fields and Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DDR2 Memory Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rev. 1.21, 2007-07 02282007-F8UP-4HSU 63 47 50 53 55 55 56 57 60 60 Internet Data Sheet HYB18TC1G[80/16]0BF 1-Gbit Double-Data-Rate-Two SDRAM Table of Contents 1 1.1 1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 2.1 2.2 2.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chip Configuration for PG-TFBGA-68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chip Configuration for PG-TFBGA-84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1-Gbit DDR2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 5.1 5.2 5.3 5.4 5.5 5.6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC & AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Buffer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input / Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overshoot and Undershoot Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Currents Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7 7.1 7.2 7.3 7.4 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Jitter Definition and Clock Jitter Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9 Product Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Rev. 1.21, 2007-07 02282007-F8UP-4HSU 64 24 24 25 26 29 30 32 37 37 40 53 56 Internet Data Sheet Edition 2007-07 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 München, Germany © Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.qimonda.com