Cypress CY14B104N-BA25XCT 4 mbit (512k x 8/256k x 16) nvsram Datasheet

CY14B104L, CY14B104N
4 Mbit (512K x 8/256K x 16) nvSRAM
Features
Functional Description
■
20 ns, 25 ns, and 45 ns Access Times
■
Internally organized as 512K x 8 (CY14B104L) or 256K x 16
(CY14B104N)
■
Hands off Automatic STORE on power down with only a small
Capacitor
■
STORE to QuantumTrap® nonvolatile elements initiated by
software, device pin, or AutoStore® on power down
■
RECALL to SRAM initiated by software or power up
■
Infinite Read, Write, and Recall Cycles
■
200,000 STORE cycles to QuantumTrap
The Cypress CY14B104L/CY14B104N is a fast static RAM, with
a nonvolatile element in each memory cell. The memory is
organized as 512K bytes of 8 bits each or 256K words of 16 bits
each. The embedded nonvolatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while independent nonvolatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also available
under software control.
■
20 year data retention
■
Single 3V +20% to –10% operation
■
Commercial and Industrial Temperatures
■
48-ball FBGA and 44/54-pin TSOP II packages
■
Pb-free and RoHS compliance
Logic Block Diagram[1, 2, 3]
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Notes
1. Address A0 - A18 for x8 configuration and Address A0 - A17 for x16 configuration.
2. Data DQ0 - DQ7 for x8 configuration and Data DQ0 - DQ15 for x16 configuration.
3. BHE and BLE are applicable for x16 configuration only.
Cypress Semiconductor Corporation
Document #: 001-07102 Rev. *L
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 19, 2008
[+] Feedback
CY14B104L, CY14B104N
Pinouts
Figure 1. Pin Diagram - 48 FBGA
48-FBGA
48-FBGA
Top View
(not to scale)
Top View
(not to scale)
(x8)
(x16)
1
2
3
4
5
6
A
BLE
OE
A0
A1
A2
NC
A
NC
B
DQ8
BHE
A3
A4
CE
DQ0
B
NC
DQ4
C
DQ9 DQ10
A5
A6
DQ1
DQ2
C
A7
DQ5
VCC
D
VSS
A17
A7
DQ3
VCC
D
2
3
4
5
6
NC
OE
A0
A1
A2
NC
NC
NC
A3
A4
CE
DQ0
NC
A5
A6
VSS
DQ1
A17
1
DQ11
VCC
DQ2
VCAP
A16
DQ6
VSS
E
VCC DQ12
VCAP
A16
DQ4
VSS
E
DQ3
NC
A14
A15
NC
DQ7
F
DQ14 DQ13
A14
A15
DQ5
DQ6
F
A12
A13
WE
NC
G
DQ15 HSB
A12
A13
WE
DQ7
G
A9
A10
A11
H
NC
A9
A10
A11
[5]
NC
H
[5]
HSB
NC
A18
A8
NC
[4]
[4]
A8
Figure 2. Pin Diagram - 44 Pin TSOP II
44-TSOP II
44-TSOP II
(x16)[6]
(x8)
NC
[5]
NC
A0
A1
A2
A3
A4
CE
DQ0
DQ1
VCC
VSS
DQ2
DQ3
WE
A5
A6
A7
A8
A9
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 - TSOP II
(x8)
Top View
(not to scale)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
HSB
NC
[4]
NC
A18
A17
A16
A15
OE
DQ7
DQ6
VSS
VCC
DQ5
DQ4
30
29
28
27
26
25
24
23
VCAP
A14
A13
A12
A11
A10
NC
NC
A0
A1
A2
A3
A4
CE
DQ0
DQ1
DQ2
DQ3
VCC
VSS
DQ4
DQ5
DQ6
DQ7
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 - TSOP II
(x16)
Top View
(not to scale)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
BHE
BLE
DQ15
DQ14
DQ13
DQ12
VSS
VCC
DQ11
DQ10
DQ9
DQ8
VCAP
A14
A13
A12
A11
A10
Notes
4. Address expansion for 8 Mbit. NC pin not connected to die.
5. Address expansion for 16 Mbit. NC pin not connected to die.
6. HSB pin is not available in 44-TSOP II (x16) package.
Document #: 001-07102 Rev. *L
Page 2 of 25
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CY14B104L, CY14B104N
Pinouts
(continued)
Figure 3. Pin Diagram - 54 Pin TSOP II (x16)
NC
[5]
NC
A0
A1
A2
A3
A4
CE
DQ0
DQ1
DQ2
DQ3
VCC
VSS
DQ4
DQ5
DQ6
DQ7
WE
A5
A6
A7
A8
A9
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
54 - TSOP II
(x16)
Top View
(not to scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
HSB
NC [4]
A17
A16
A15
OE
BHE
BLE
DQ15
DQ14
DQ13
DQ12
VSS
VCC
DQ11
DQ10
DQ9
DQ8
VCAP
A14
A13
A12
A11
A10
NC
NC
NC
Pin Definitions
Pin Name
IO Type
A0 – A18
Input
A0 – A17
DQ0 – DQ7
Description
Address Inputs Used to Select one of the 524,288 bytes of the nvSRAM for x8 Configuration.
Address Inputs Used to Select one of the 262,144 words of the nvSRAM for x16 Configuration.
Input/Output Bidirectional Data IO Lines for x8 Configuration. Used as input or output lines depending on
operation.
DQ0 – DQ15
Bidirectional Data IO Lines for x16 Configuration. Used as input or output lines depending on
operation.
WE
Input
Write Enable Input, Active LOW. When selected LOW, data on the IO pins is written to the specific
address location.
CE
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. IO pins are tri-stated on deasserting OE HIGH.
BHE
Input
Byte High Enable, Active LOW. Controls DQ15 - DQ8.
BLE
Input
Byte Low Enable, Active LOW. Controls DQ7 - DQ0.
VSS
Ground
VCC
[6]
HSB
VCAP
NC
Ground for the Device. Must be connected to the ground of the system.
Power Supply Power Supply Inputs to the Device.
Input/Output Hardware Store Busy (HSB). When LOW this output indicates that a hardware store is in progress.
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull
up resistor keeps this pin HIGH if not connected (connection optional). After each store operation HSB
will be driven HIGH for short time with standard output high current.
Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
No Connect
No Connect. This pin is not connected to the die.
Document #: 001-07102 Rev. *L
Page 3 of 25
[+] Feedback
CY14B104L, CY14B104N
The CY14B104L/CY14B104N nvSRAM is made up of two
functional components paired in the same physical cell. They are
an SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM read and write operations are inhibited. The
CY14B104L/CY14B104N supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 200K STORE
operations. See the “Truth Table For SRAM Operations” on
page 15 for a complete description of read and write modes.
SRAM Read
The CY14B104L/CY14B104N performs a read cycle when CE
and OE are LOW and WE and HSB are HIGH. The address
specified on pins A0-18 or A0-17 determines which of the 524,288
data bytes or 262,144 words of 16 bits each are accessed. Byte
enables (BHE, BLE) determine which bytes are enabled to the
output, in the case of 16-bit words. When the read is initiated by
an address transition, the outputs are valid after a delay of tAA
(read cycle 1). If the read is initiated by CE or OE, the outputs
are valid at tACE or at tDOE, whichever is later (read cycle 2). The
data output repeatedly responds to address changes within the
tAA access time without the need for transitions on any control
input pins. This remains valid until another address change or
until CE or OE is brought HIGH, or WE or HSB is brought LOW.
Figure 4 shows the proper connection of the storage capacitor
(VCAP) for automatic store operation. Refer to DC Electrical
Characteristics on page 7 for the size of VCAP. The voltage on
the VCAP pin is driven to VCC by a regulator on the chip. A pull
up should be placed on WE to hold it inactive during power up.
This pull up is only effective if the WE signal is tri-state during
power up. Many MPU’s will tri-state their controls on power up.
This should be verified when using the pull up. When the
nvSRAM comes out of power-on-recall, the MPU must be active
or the WE held inactive until the MPU comes out of reset.
To reduce unnecessary nonvolatile stores, AutoStore and
hardware store operations are ignored unless at least one write
operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Figure 4. AutoStore Mode
Vcc
0.1uF
10kOhm
Device Operation
Vcc
WE
VCAP
VSS
VCAP
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common IO pins DQ0–15
are written into the memory if the data is valid tSD before the end
of a WE controlled write or before the end of an CE controlled
write. The Byte Enable inputs (BHE, BLE) determine which bytes
are written, in the case of 16bit words. It is recommended that
OE be kept HIGH during the entire write cycle to avoid data bus
contention on common IO lines. If OE is left LOW, internal
circuitry turns off the output buffers tHZWE after WE goes LOW.
AutoStore Operation
The CY14B104L/CY14B104N stores data to the nvSRAM using
one of the following three storage operations: Hardware Store
activated by HSB; Software Store activated by an address
sequence; AutoStore on device power down. The AutoStore
operation is a unique feature of QuantumTrap technology and is
enabled by default on the CY14B104L/CY14B104N.
During a normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Document #: 001-07102 Rev. *L
Hardware STORE Operation
The CY14B104L/CY14B104N provides the HSB[6] pin to control
and acknowledge the STORE operations. Use the HSB pin to
request a hardware STORE cycle. When the HSB pin is driven
LOW, the CY14B104L/CY14B104N conditionally initiates a
STORE operation after tDELAY. An actual STORE cycle only
begins if a write to the SRAM has taken place since the last
STORE or RECALL cycle. The HSB pin also acts as an open
drain driver that is internally driven LOW to indicate a busy
condition when the STORE (initiated by any means) is in
progress.
When HSB is driven LOW by any means, SRAM read and write
operations that are in progress are given time to complete before
the STORE operation is initiated. After HSB goes LOW, the
CY14B104L/CY14B104N continues SRAM operations for
tDELAY.
During any STORE operation, regardless of how it is initiated,
the CY14B104L/CY14B104N continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. Upon
completion
of
the
STORE
operation,
the
CY14B104L/CY14B104N remains disabled until the HSB pin
returns HIGH. Leave the HSB unconnected if it is not used.
Page 4 of 25
[+] Feedback
CY14B104L, CY14B104N
Hardware RECALL (Power Up)
The software sequence may be clocked with CE controlled reads
or OE controlled reads. After the sixth address in the sequence
is entered, the STORE cycle commences and the chip is
disabled. HSB will be driven LOW. It is important to use read
cycles and not write cycles in the sequence, although it is not
necessary that OE be LOW for a valid sequence. After the
tSTORE cycle time is fulfilled, the SRAM is activated again for the
read and write operation.
During power up or after any low power condition
(VCC< VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
During this time, HSB is driven LOW by the HSB driver.
Software STORE
Software RECALL
Transfer data from the SRAM to the nonvolatile memory with a
software address sequence. The CY14B104L/CY14B104N
software STORE cycle is initiated by executing sequential CE
controlled read cycles from six specific address locations in
exact order. During the STORE cycle an erase of the previous
nonvolatile data is performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Transfer the data from the nonvolatile memory to the SRAM with
a software address sequence. A software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled read operations must be
performed.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence. Further, no read or write
operations must be done after the sixth address read for a
duration of soft-sequence processing time (tSS). If these conditions are not met, the sequence is aborted and no STORE or
RECALL takes place.
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the nonvolatile information is transferred into the
SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for read and write operations. The RECALL operation
does not alter the data in the nonvolatile elements.
To initiate the software STORE cycle, the following addresses
and read sequence must be performed.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8FC0 Initiate STORE Cycle
Table 1. Mode Selection
CE
H
WE
X
OE, BHE, BLE[3]
X
A15 - A0[7]
Mode
IO
Power
X
Not Selected
Output High Z
Standby
L
H
L
X
Read SRAM
Output Data
Active
L
L
X
X
Write SRAM
Input Data
Active
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Disable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[8, 9]
Notes
7. While there are 19 address lines on the CY14B104L (18 address lines on the CY14B104N), only the 13 address lines (A14 - A2) are used to control software modes.
The rest of the address lines are don’t care.
8. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
9. IO state depends on the state of OE, BHE, and BLE. The IO table shown assumes OE, BHE, and BLE LOW.
Document #: 001-07102 Rev. *L
Page 5 of 25
[+] Feedback
CY14B104L, CY14B104N
Table 1. Mode Selection (continued)
CE
L
WE
H
OE, BHE, BLE[3]
L
A15 - A0[7]
Mode
IO
Power
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Enable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[8, 9]
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Store
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active ICC2[8, 9]
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active[8, 9]
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoStore Disable
The AutoStore is re-enabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the software RECALL initiation. To initiate the
AutoStore enable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoStore Enable
Document #: 001-07102 Rev. *L
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (hardware or software) must be issued to save
the AutoStore state through subsequent power down cycles. The
part comes from the factory with AutoStore enabled.
Data Protection
The CY14B104L/CY14B104N protects data from corruption
during low voltage conditions by inhibiting all externally initiated
STORE and write operations. The low voltage condition is
detected when VCC < VSWITCH. If the CY14B104L/CY14B104N
is in a write mode (both CE and WE are LOW) at power up, after
a RECALL or STORE, the write is inhibited until the SRAM is
enabled after tLZHSB (HSB to output active). This protects against
inadvertent writes during power up or brown out conditions.
Noise Considerations
Refer to CY application note AN1064.
Page 6 of 25
[+] Feedback
CY14B104L, CY14B104N
Maximum Ratings
Transient Voltage (<20 ns) on
Any Pin to Ground Potential .................. –2.0V to VCC + 2.0V
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Package Power Dissipation
Capability (TA = 25°C) ................................................... 1.0W
Storage Temperature ................................. –65°C to +150°C
Surface Mount Pb Soldering
Temperature (3 Seconds) .......................................... +260°C
Maximum Accumulated Storage Time
At 150°C Ambient Temperature ........................ 1000h
DC Output Current (1 output at a time, 1s duration).... 15 mA
At 85°C Ambient Temperature ...................... 20 Years
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Ambient Temperature with
Power Applied ............................................ –55°C to +150°C
Latch Up Current ................................................... > 200 mA
Operating Range
Supply Voltage on VCC Relative to GND ..........–0.5V to 4.1V
Voltage Applied to Outputs
in High-Z State....................................... –0.5V to VCC + 0.5V
Range
Ambient Temperature
VCC
0°C to +70°C
2.7V to 3.6V
–40°C to +85°C
2.7V to 3.6V
Commercial
Input Voltage.......................................... –0.5V to VCC + 0.5V
Industrial
DC Electrical Characteristics
Over the Operating Range (VCC = 2.7V to 3.6V)
Parameter
Description
ICC1
Average VCC Current
Test Conditions
Min
tRC = 20 ns
Commercial
tRC = 25 ns
tRC = 45 ns
Values obtained without output loads (IOUT = 0 mA) Industrial
All Inputs Don’t Care, VCC = Max
Average current for duration tSTORE
Max
Unit
65
65
50
mA
mA
mA
70
70
52
mA
mA
mA
10
mA
ICC2
Average VCC Current
during STORE
ICC3[10]
Average VCC Current at All inputs cycling at CMOS levels.
tRC= 200 ns, 3V, 25°C Values obtained without output loads (IOUT = 0 mA).
typical
35
mA
ICC4
Average VCAP Current All Inputs Don’t Care, VCC = Max
during AutoStore Cycle Average current for duration tSTORE
5
mA
ISB
VCC Standby Current
5
mA
IIX[11]
Input Leakage Current VCC = Max, VSS < VIN < VCC
(except HSB)
–1
+1
μA
Input Leakage Current VCC = Max, VSS < VIN < VCC
(for HSB)
–100
+1
μA
–1
+1
μA
2.0
VCC +
0.5
V
VSS – 0.5
0.8
V
CE > (VCC – 0.2V). All others VIN < 0.2V or > (VCC – 0.2V). Standby
current level after nonvolatile cycle is complete.
Inputs are static. f = 0 MHz.
IOZ
Off-State Output
Leakage Current
VCC = Max, VSS < VOUT < VCC, CE or OE > VIH or BHE/BLE > VIH
or WE < VIL
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VOH
Output HIGH Voltage
IOUT = –2 mA
VOL
Output LOW Voltage
IOUT = 4 mA
VCAP[12]
Storage Capacitor
Between VCAP pin and VSS, 5V Rated
2.4
61
V
0.4
V
180
μF
Notes
10. Typical conditions for the active current shown on the DC Electrical characteristics are average values at 25°C (room temperature), and VCC = 3V. Not 100% tested.
11. The HSB pin has IOUT = -2 μA for VOH of 2.4V when both active HIGH and LOW drivers are disabled. When they are enabled standard VOH and VOL are valid. This
parameter is characterized but not tested.
12. VCAP (Storage capacitor) nominal value is 68 μF.
Document #: 001-07102 Rev. *L
Page 7 of 25
[+] Feedback
CY14B104L, CY14B104N
Data Retention and Endurance
Parameter
Description
Min
Unit
DATAR
Data Retention
20
Years
NVC
Nonvolatile STORE Operations
200
K
Capacitance
In the following table, the capacitance parameters are listed.[13]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max
Unit
7
pF
7
pF
TA = 25°C, f = 1 MHz,
VCC = 0 to 3.0V
Thermal Resistance
In the following table, the thermal resistance parameters are listed. [13]
Parameter
ΘJA
ΘJC
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
48-FBGA 44-TSOP II 54-TSOP II
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, in accordance with EIA/JESD51.
Unit
28.82
31.11
30.73
°C/W
7.84
5.56
6.08
°C/W
Figure 5. AC Test Loads
577Ω
577Ω
3.0V
3.0V
R1
for tri-state specs
R1
OUTPUT
OUTPUT
30 pF
R2
789Ω
5 pF
R2
789Ω
AC Test Conditions
Input Pulse Levels.................................................... 0V to 3V
Input Rise and Fall Times (10% - 90%)........................ <3 ns
Input and Output Timing Reference Levels.................... 1.5V
Note
13. These parameters are guaranteed but not tested.
Document #: 001-07102 Rev. *L
Page 8 of 25
[+] Feedback
CY14B104L, CY14B104N
AC Switching Characteristics
Parameters
Cypress
Parameters
20 ns
Description
Alt
Parameters
Min
25 ns
Max
Min
45 ns
Max
Min
Max
Unit
SRAM Read Cycle
tACE
tACS
Chip Enable Access Time
tRC[14]
tRC
Read Cycle Time
tAA[15]
tAA
Address Access Time
20
25
45
ns
tDOE
tOE
Output Enable to Data Valid
10
12
20
ns
tOHA[15]
tOH
Output Hold After Address Change
3
3
3
ns
tLZCE[16]
tLZ
Chip Enable to Output Active
3
3
3
ns
tHZCE[16]
tLZOE[16]
tHZOE[16]
tPU[13]
tPD[13]
tHZ
Chip Disable to Output Inactive
tOLZ
Output Enable to Output Active
tOHZ
Output Disable to Output Inactive
tPA
Chip Enable to Power Active
tPS
Chip Disable to Power Standby
20
25
45
ns
tDBE
-
Byte Enable to Data Valid
10
12
20
ns
tLZBE
-
Byte Enable to Output Active
tHZBE
-
Byte Disable to Output Inactive
20
20
25
25
8
0
10
0
8
0
15
10
15
ns
ns
0
10
ns
ns
0
0
8
ns
ns
0
0
0
45
45
ns
15
ns
SRAM Write Cycle
tWC
tWC
Write Cycle Time
tPWE
tWP
Write Pulse Width
15
20
30
ns
tSCE
tCW
Chip Enable To End of Write
15
20
30
ns
tSD
tDW
Data Setup to End of Write
8
10
15
ns
tHD
tDH
Data Hold After End of Write
0
0
0
ns
tAW
tAW
Address Setup to End of Write
15
20
30
ns
tSA
tAS
Address Setup to Start of Write
0
0
0
ns
tHA
tWR
Address Hold After End of Write
0
tHZWE[16,17]
tWZ
Write Enable to Output Disable
tLZWE[16]
tOW
Output Active after End of Write
3
3
3
ns
tBW
-
Byte Enable to End of Write
15
20
30
ns
Switching Waveforms
20
25
45
0
8
ns
0
10
ns
15
ns
Figure 6. SRAM Read Cycle #1: Address Controlled[14, 15, 18]
W5&
$GGUHVV
$GGUHVV9DOLG
W$$
'DWD2XWSXW
3UHYLRXV'DWD9DOLG
2XWSXW'DWD9DOLG
W2+$
Notes
14. WE must be HIGH during SRAM read cycles.
15. Device is continuously selected with CE, OE and BHE / BLE LOW.
16. Measured ±200 mV from steady state output voltage.
17. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
18. HSB must remain HIGH during READ and WRITE cycles.
Document #: 001-07102 Rev. *L
Page 9 of 25
[+] Feedback
CY14B104L, CY14B104N
Figure 7. SRAM Read Cycle #2: CE and OE Controlled[3, 14, 18]
$GGUHVV
$GGUHVV9DOLG
W5&
W+=&(
W$&(
&(
W$$
W/=&(
W+=2(
W'2(
2(
W+=%(
W/=2(
W'%(
%+(%/(
W/=%(
'DWD2XWSXW
+LJK,PSHGDQFH
2XWSXW'DWD9DOLG
W38
,&&
W3'
$FWLYH
6WDQGE\
Figure 8. SRAM Write Cycle #1: WE Controlled[3, 17, 18, 19]
W:&
$GGUHVV
$GGUHVV9DOLG
W6&(
W+$
&(
W%:
%+(%/(
W$:
W3:(
:(
W6$
W6'
'DWD,QSXW
,QSXW'DWD9DOLG
W+=:(
'DWD2XWSXW
W+'
3UHYLRXV'DWD
W/=:(
+LJK,PSHGDQFH
Notes
19. CE or WE must be >VIH during address transitions.
Document #: 001-07102 Rev. *L
Page 10 of 25
[+] Feedback
CY14B104L, CY14B104N
Figure 9. SRAM Write Cycle #2: CE Controlled[3, 17, 18, 19]
tWC
Address Valid
Address
tSA
tSCE
tHA
CE
tBW
BHE, BLE
tPWE
WE
tHD
tSD
Input Data Valid
Data Input
High Impedance
Data Output
Figure 10. SRAM Write Cycle #3: BHE and BLE Controlled[3, 17, 18, 19]
W:&
$GGUHVV
$GGUHVV9DOLG
W6&(
&(
W6$
W+$
W%:
%+(%/(
W$:
W3:(
:(
W6'
'DWD,QSXW
W+'
,QSXW'DWD9DOLG
+LJK,PSHGDQFH
'DWD2XWSXW
Document #: 001-07102 Rev. *L
Page 11 of 25
[+] Feedback
CY14B104L, CY14B104N
AutoStore/Power Up RECALL
Parameters
tHRECALL [20]
tSTORE [21]
tDELAY [22]
VSWITCH
tVCCRISE
VHDIS[13]
tHHHD
tPURHH
tLZHSB
CY14B104L/CY14B104N
Min
Max
20
8
1
70
2.65
150
1.9
500
70
5
Description
Power Up RECALL Duration
STORE Cycle Duration
Time Allowed to Complete SRAM Cycle
Low Voltage Trigger Level
VCC Rise Time
HSB Output Driver Disable Voltage
HSB High Active Time
HSB Hold Time after Power-Up Recall Start
HSB To Output Active Time
Switching Waveforms
Unit
ms
ms
μs
V
μs
V
ns
μs
μs
Figure 11. AutoStore or Power Up RECALL[23]
9&&
96:,7&+
9+',6
95(6(7
W9&&5,6(
1RWH
W6725(
1RWH
W+++'
+6%
287
W+++'
W6725(
1RWH
W '(/$<
W385++
W/=+6%
W/=+6%
$XWR6WRUH
32:(583
5(&$//
W'(/$<
W +5(&$//
W+5(&$//
5HDG :ULWH
,QKLELWHG
32:(5'2:1
32:(583
%52:1287 32:(583
5HDG :ULWH
5HDG :ULWH
$XWR6WRUH
5(&$//
5(&$//
$XWR6WRUH
Notes
20. tHRECALL starts from the time VCC rises above VSWITCH.
21. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware Store takes place.
22. On a Hardware STORE, Software STORE/RECALL, AutoStore Enable/Disable and AutoStore initiation, SRAM operation continues to be enabled for time tDELAY.
23. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.
24. HSB pin is driven HIGH to VCC only by internal 100 kΩ resistor, HSB driver is disabled.
Document #: 001-07102 Rev. *L
Page 12 of 25
[+] Feedback
CY14B104L, CY14B104N
Software Controlled STORE/RECALL Cycle
In the following table, the software controlled STORE/RECALL cycle parameters are listed.[25, 26]
Parameters
tRC
tSA
tCW
tHA
tRECALL
tSS [27, 28]
20 ns
Min
Max
20
0
15
0
200
100
Description
STORE/RECALL Initiation Cycle Time
Address Setup Time
Clock Pulse Width
Address Hold Time
RECALL Duration
Soft Sequence Processing Time
25 ns
Min
Max
25
0
20
0
200
100
45 ns
Min
Max
45
0
30
0
200
100
Unit
ns
ns
ns
ns
μs
μs
Switching Waveforms
Figure 12. CE and OE Controlled Software STORE/RECALL Cycle[26]
W5&
$GGUHVV
W5&
$GGUHVV
W6$
$GGUHVV
W+$
W&:
W&:
&(
W+$
W6$
W+$
W66
W+$
2(
W+++'
W'(/$<
+6% 6725(RQO\
W+=&(
W/=&(
W/=+6%
'4 '$7$
W6725(
+LJK
,PSHGDQFH
W5(&$//
5:,
Figure 13. Autostore Enable / Disable Cycle
$GGUHVV
W6$
&(
W5&
W5&
$GGUHVV
$GGUHVV
W&:
W&:
W+$
W6$
W+$
W+$
W+$
2(
W/=&(
W+=&(
W66
W'(/$<
'4 '$7$
5:,
Notes
25. The software sequence is clocked with CE controlled or OE controlled reads.
26. The six consecutive addresses must be read in the order listed in Table 1 on page 5. WE must be HIGH during all six consecutive cycles. After the sixth address read
cycle, no further read or write operation must be performed for tSS duration. If these conditions are not met, the software sequence is aborted.
Document #: 001-07102 Rev. *L
Page 13 of 25
[+] Feedback
CY14B104L, CY14B104N
Hardware STORE Cycle
Parameters
CY14B104L/CY14B104N
Description
tPHSB
Hardware STORE Pulse Width
tHLBL
Hardware STORE LOW to STORE Busy
Switching Waveforms
Min
Max
15
Unit
ns
500
ns
Figure 14. Hardware STORE Cycle[21]
:ULWHODWFKVHW
W3+6%
+6% ,1
W6725(
W+++'
W+/%/
+6% 287
W'(/$<
W/=+6%
'4 'DWD2XW
:ULWHODWFKQRWVHW
W3+6%
+6% ,1
W+/%/
W+++'
+6% 287
W'(/$<
W/=+6%
'4 'DWD2XW
Figure 15. Soft Sequence Processing[27, 28]
6RIW6HTXHQFH
&RPPDQG
$GGUHVV
$GGUHVV
W6$
$GGUHVV
W&:
W66
6RIW6HTXHQFH
&RPPDQG
$GGUHVV
W66
$GGUHVV
W&:
&(
9&&
Notes
27. This is the amount of time it takes to take action on a soft sequence command. VCC power must remain HIGH to effectively register command.
28. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.
Document #: 001-07102 Rev. *L
Page 14 of 25
[+] Feedback
CY14B104L, CY14B104N
Truth Table For SRAM Operations
HSB should remain HIGH for SRAM Operations.
For x8 Configuration
Inputs/Outputs[2]
CE
WE
OE
H
X
X
High Z
Deselect/Power down
Mode
Standby
Power
L
H
L
Data Out (DQ0–DQ7);
Read
Active
L
H
H
High Z
Output Disabled
Active
L
L
X
Data in (DQ0–DQ7);
Write
Active
For x16 Configuration
CE
WE
OE
BHE
BLE
H
X
X
X
X
L
X
X
H
L
H
L
L
L
H
L
L
H
L
L
H
L
H
L
Inputs/Outputs[2]
Mode
Power
High-Z
Deselect/Power down
Standby
H
High-Z
Output Disabled
Active
L
Data Out (DQ0–DQ15)
Read
Active
H
L
Data Out (DQ0–DQ7);
DQ8–DQ15 in High-Z
Read
Active
L
H
Data Out (DQ8–DQ15);
DQ0–DQ7 in High-Z
Read
Active
H
L
L
High-Z
Output Disabled
Active
H
H
L
High-Z
Output Disabled
Active
H
H
L
H
High-Z
Output Disabled
Active
L
L
X
L
L
Data In (DQ0–DQ15)
Write
Active
L
L
X
H
L
Data In (DQ0–DQ7);
DQ8–DQ15 in High-Z
Write
Active
L
L
X
L
H
Data In (DQ8–DQ15);
DQ0–DQ7 in High-Z
Write
Active
Document #: 001-07102 Rev. *L
Page 15 of 25
[+] Feedback
CY14B104L, CY14B104N
Ordering Information
Speed
(ns)
20
25
Ordering Code
Package
Diagram
Package Type
Operating
Range
CY14B104L-ZS20XCT
51-85087
44-pin TSOP II
Commercial
CY14B104L-ZS20XIT
51-85087
44-pin TSOP II
Industrial
CY14B104L-ZS20XI
51-85087
44-pin TSOP II
CY14B104L-BA20XCT
51-85128
48-ball FBGA
Commercial
CY14B104L-BA20XIT
51-85128
48-ball FBGA
Industrial
CY14B104L-BA20XI
51-85128
48-ball FBGA
CY14B104L-ZSP20XCT
51-85160
54-pin TSOP II
Commercial
CY14B104L-ZSP20XIT
51-85160
54-pin TSOP II
Industrial
CY14B104L-ZSP20XI
51-85160
54-pin TSOP II
CY14B104N-ZS20XCT
51-85087
44-pin TSOP II
Commercial
Industrial
CY14B104N-ZS20XIT
51-85087
44-pin TSOP II
CY14B104N-ZS20XI
51-85087
44-pin TSOP II
CY14B104N-BA20XCT
51-85128
48-ball FBGA
Commercial
CY14B104N-BA20XIT
51-85128
48-ball FBGA
Industrial
CY14B104N-BA20XI
51-85128
48-ball FBGA
CY14B104N-ZSP20XCT
51-85160
54-pin TSOP II
Commercial
CY14B104N-ZSP20XIT
51-85160
54-pin TSOP II
Industrial
CY14B104N-ZSP20XI
51-85160
54-pin TSOP II
CY14B104L-ZS25XCT
51-85087
44-pin TSOP II
Commercial
CY14B104L-ZS25XIT
51-85087
44-pin TSOP II
Industrial
CY14B104L-ZS25XI
51-85087
44-pin TSOP II
CY14B104L-BA25XIT
51-85128
48-ball FBGA
CY14B104L-BA25XI
51-85128
48-ball FBGA
CY14B104N-BA25XCT
51-85128
48-ball FBGA
Commercial
CY14B104L-ZSP25XCT
51-85160
54-pin TSOP II
Commercial
CY14B104L-ZSP25XIT
51-85160
54-pin TSOP II
Industrial
CY14B104L-ZSP25XI
51-85160
54-pin TSOP II
CY14B104N-ZS25XCT
51-85087
44-pin TSOP II
Commercial
Industrial
CY14B104N-ZS25XIT
51-85087
44-pin TSOP II
CY14B104N-ZS25XI
51-85087
44-pin TSOP II
Industrial
CY14B104N-BA25XCT
51-85128
48-ball FBGA
Commercial
CY14B104N-BA25XIT
51-85128
48-ball FBGA
Industrial
CY14B104N-BA25XI
51-85128
48-ball FBGA
CY14B104N-ZSP25XCT
51-85160
54-pin TSOP II
Commercial
CY14B104N-ZSP25XIT
51-85160
54-pin TSOP II
Industrial
CY14B104N-ZSP25XI
51-85160
54-pin TSOP II
Document #: 001-07102 Rev. *L
Page 16 of 25
[+] Feedback
CY14B104L, CY14B104N
Ordering Information (continued)
Speed
(ns)
45
Ordering Code
Package
Diagram
Package Type
Operating
Range
CY14B104L-ZS45XCT
51-85087
44-pin TSOP II
Commercial
CY14B104L-ZS45XIT
51-85087
44-pin TSOP II
Industrial
CY14B104L-ZS45XI
51-85087
44-pin TSOP II
CY14B104L-BA45XCT
51-85128
48-ball FBGA
Commercial
Industrial
CY14B104L-BA45XIT
51-85128
48-ball FBGA
CY14B104L-BA45XI
51-85128
48-ball FBGA
CY14B104L-ZSP45XCT
51-85160
54-pin TSOP II
Commercial
CY14B104L-ZSP45XIT
51-85160
54-pin TSOP II
Industrial
CY14B104L-ZSP45XI
51-85160
54-pin TSOP II
CY14B104N-ZS45XCT
51-85087
44-pin TSOP II
Commercial
Industrial
CY14B104N-ZS45XIT
51-85087
44-pin TSOP II
CY14B104N-ZS45XI
51-85087
44-pin TSOP II
CY14B104N-BA45XCT
51-85128
48-ball FBGA
Commercial
CY14B104N-BA45XIT
51-85128
48-ball FBGA
Industrial
CY14B104N-BA45XI
51-85128
48-ball FBGA
CY14B104N-ZSP45XCT
51-85160
54-pin TSOP II
Commercial
CY14B104N-ZSP45XIT
51-85160
54-pin TSOP II
Industrial
CY14B104N-ZSP45XI
51-85160
54-pin TSOP II
All parts are Pb-free. The above table contains Preliminary information. Please contact your local Cypress sales representative for availability of these parts.
Document #: 001-07102 Rev. *L
Page 17 of 25
[+] Feedback
CY14B104L, CY14B104N
Part Numbering Nomenclature
CY 14 B 104 L - ZS P 20 X C T
Option:
T - Tape & Reel
Blank - Std.
Pb-Free
P - 54 Pin
Blank - 44 Pin
Package:
BA - 48 FBGA
ZS - TSOP II
Voltage:
B - 3.0V
Temperature:
C - Commercial (0 to 70°C)
I - Industrial (–40 to 85°C)
Speed:
20 - 20 ns
25 - 25 ns
45 - 45 ns
Data Bus:
L - x8
N - x16
Density:
104 - 4 Mb
NVSRAM
14 - Auto Store + Software Store + Hardware Store
Cypress
Document #: 001-07102 Rev. *L
Page 18 of 25
[+] Feedback
CY14B104L, CY14B104N
Package Diagrams
Figure 16. 44-Pin TSOP II (51-85087)
DIMENSION IN MM (INCH)
MAX
MIN.
PIN 1 I.D.
1
23
10.262 (0.404)
10.058 (0.396)
11.938 (0.470)
11.735 (0.462)
22
EJECTOR PIN
44
TOP VIEW
0.800 BSC
(0.0315)
OR E
K X A
SG
BOTTOM VIEW
0.400(0.016)
0.300 (0.012)
10.262 (0.404)
10.058 (0.396)
BASE PLANE
0.210 (0.0083)
0.120 (0.0047)
0°-5°
0.10 (.004)
Document #: 001-07102 Rev. *L
0.150 (0.0059)
0.050 (0.0020)
1.194 (0.047)
0.991 (0.039)
18.517 (0.729)
18.313 (0.721)
SEATING
PLANE
0.597 (0.0235)
0.406 (0.0160)
51-85087-*A
Page 19 of 25
[+] Feedback
CY14B104L, CY14B104N
Package Diagrams
(continued)
Figure 17. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm (51-85128)
BOTTOM VIEW
TOP VIEW
A1 CORNER
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30±0.05(48X)
2
3
4
5
6
6
5
4
3
2
1
C
C
E
F
G
D
E
2.625
D
0.75
A
B
5.25
A
B
10.00±0.10
10.00±0.10
1
F
G
H
H
1.875
A
A
B
0.75
6.00±0.10
0.53±0.05
B
0.15 C
0.21±0.05
0.25 C
3.75
6.00±0.10
0.15(4X)
Document #: 001-07102 Rev. *L
1.20 MAX
0.36
SEATING PLANE
C
51-85128-*D
Page 20 of 25
[+] Feedback
CY14B104L, CY14B104N
Package Diagrams
(continued)
Figure 18. 54-Pin TSOP II (51-85160)
51-85160-**
Document #: 001-07102 Rev. *L
Page 21 of 25
[+] Feedback
CY14B104L, CY14B104N
Document History Page
Document Title: CY14B104L/CY14B104N 4 Mbit (512K x 8/256K x 16) nvSRAM
Document Number: 001-07102
Rev.
ECN No.
Submission
Date
Orig. of
Change
**
431039
See ECN
TUP
New Data Sheet
*A
489096
See ECN
TUP
Removed 48 SSOP Package
Added 48 FBGA and 54 TSOPII Packages
Updated Part Numbering Nomenclature and Ordering Information
Added Soft Sequence Processing Time Waveform
*B
499597
See ECN
PCI
Removed 35 ns speed bin
Added 55 ns speed bin. Updated AC table for the same
Changed “Unlimited” read/write to “infinite” read/write
Features section: Changed typical ICC at 200-ns cycle time to 8 mA
Changed STORE cycles from 500K to 200K cycles
Shaded Commercial grade in operating range table
Modified Icc/Is specs
48 FBGA package nomenclature changed from BW to BV
Modified part nomenclature table. Changes reflected in ordering information
table
*C
517793
See ECN
TUP
Removed 55ns speed bin
Changed pinout for 44TSOPII and 54TSOPII packages
Changed ISB to 1mA
Changed ICC4 to 3mA
Changed VCAP min to 35μF
Changed VIH max to Vcc + 0.5V
Changed tSTORE to 15ms
Changed tPWE to 10ns
Changed tSCE to 15ns
Changed tSD to 5ns
Changed tAW to 10ns
Removed tHLBL
Added Timing Parameters for BHE and BLE - tDBE, tLZBE, tHZBE, tBW
Removed min specification for Vswitch
Changed tGLAX to 1ns
Added tDELAY max of 70us
Changed tSS specification from 70us min to 70us max
*D
774001
See ECN
UHA
Changed the data sheet from Advance information to Preliminary
48 FBGA package code changed from BV to BA
Removed 48 FBGA package in X8 configuration in ordering information.
Changed tDBE to 10ns in 15ns part
Changed tHZBE in 15ns part to 7ns and in 25ns part to10ns
Changed tBW in 15ns part to 15ns and in 25ns part to 20ns
Changed tGLAX to tGHAX
Changed the value of ICC3 to 25mA
Changed the value of tAW in 15ns part to15ns
Changed A18 and A19 Pins in FBGA Pin Configuration to NC
*E
914220
See ECN
UHA
Included all the information for 45 ns part in this data sheet
Document #: 001-07102 Rev. *L
Description of Change
Page 22 of 25
[+] Feedback
CY14B104L, CY14B104N
Document Title: CY14B104L/CY14B104N 4 Mbit (512K x 8/256K x 16) nvSRAM
Document Number: 001-07102
Rev.
ECN No.
Submission
Date
Orig. of
Change
Description of Change
*F
1889928
See ECN
vsutmp8/AESA
Added Footnotes 1, 2 and 3.
Updated logic block diagram
Added 48-FBGA (X8) Pin Diagram
Changed 8Mb Address expansion Pin from Pin 43 to Pin 42 for 44-TSOP II (x8).
Updated pin definitions table.
Corrected typo in VIL min spec
Changed the value of ICC3 from 25mA to 13mA
Changed ISB value from 1mA to 2mA
Rearranging of Footnotes.
Updated ordering information table
*G
2267286
See ECN
GVCH/PYRS
Added BHE and BLE Information in Pin Definitions Table
Updated Figure 4 (Autostore mode)
Updated footnote 6
Changed ICC2 & ICC4 from 3 mA to 6 mA
Changed ICC3 from 13 mA to 15 mA
Changed Vcap from 35uF min and 57uF max value to 54uF min and 82uF max
value
Changed ISB from 2 mA to 3 mA
Added input leakage current (IIX) for HSB in DC Electrical Characteristics table
Corrected typo in tDBE value from 22 ns to 20 ns for 45 ns part
Corrected typo in tHZBE value from 22 ns to 15 ns for 45 ns part
Corrected typo in tAW value from 15 ns to 10ns for 15 ns part
Changed tRECALL from 100 to 200 us
Added footnotes 9 and 25; Reframed footnote 14 and 21
Added footnote 14 to figure 7 (SRAM WRITE Cycle #1)
*H
2483627
See ECN
GVCH/PYRS
Removed 8 mA typical ICC at 200 ns cycle time in Feature section
Referenced footnote 8 to ICC3 in DC Characteristics table
Changed ICC3 from 15 mA to 35 mA
Changed Vcap minimum value from 54 uF to 61 uF
Changed tAVAV to tRC
Figure 11:Changed tSA to tAS and tSCE to tCW
*I
2519319
06/20/08
GVCH/PYRS
Added 20 ns access speed in “Features”
Added ICC1 for tRC=20 ns for both industrial and Commercial temperature
Grade
updated Thermal resistance table values for 48-FBGA, 44-TSOP II and
54-TSOP II Packages
Added AC Switching Characteristics specs for 20 ns access speed
Added software controlled STORE/RECALL cycle specs for 20 ns access
speed
Updated ordering information and part numbering nomenclature
Document #: 001-07102 Rev. *L
Page 23 of 25
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CY14B104L, CY14B104N
Document Title: CY14B104L/CY14B104N 4 Mbit (512K x 8/256K x 16) nvSRAM
Document Number: 001-07102
Rev.
ECN No.
Submission
Date
Orig. of
Change
Description of Change
*J
2600941
11/04/08
GVCH/PYRS
Removed 15 ns access speed
Updated Logic block diagram
Updated footnote 1
Added footnote 2 and 5
Pin definition: Updated WE, HSB and NC pin description
Page 4:Updated SRAM READ, SRAM WRITE, Autostore operation description
Page 4:Updated Hardware store operation and Hardware RECALL (Power-up)
description
Footnote 1 referenced for Mode selection Table
Page 6:updated Data protection description
Maximum Ratings: Added Max. Accumulated storage time
Changed ICC2 from 6mA to 10mA
Changed ICC4 from 6mA to 5mA
Changed ISB from 3mA to 5mA
Updated ICC1, ICC3 , ISBand IOZ Test conditions
Changed VCAP max value from 82uf to 180uF
Updated footnote 10 and 11
Added footnote 12
Added Data retention and Endurance Table
Updated Input Rise and Fall time in AC test Conditions
Referenced footnote 15 to tOHA parameter
Updated All switching waveforms
Added Figure 10 (SRAM WRITE CYCLE:BHE and BLE controlled)
Changed tDELAY to 20ns, 25ns, 25ns for 15ns, 20ns, 45ns part respectively
Changed tSTORE from 15ms to 8ms
Added VHDIS, tHHHD and tLZHSB parameters
Updated footnote 21
Added footnote 24
Software controlled STORE/RECALL cycle table: Changed tAS to tSA
Changed tGHAX to tHA
Added tDHSB parameter
Changed tHLHX to tPHSB
Updated tSS from 70us to 100us
Added Truth table for SRAM operations
Updated ordering information and part numbering nomenclature
*K
2612931
11/26/08
AESA
*L
2625431
12/19/08
GVCH/DSG
Document #: 001-07102 Rev. *L
Removed Preliminary form header.
Changed tDELAY to 1us (min) and 70us (max) for all three access time
Page 4: Removed the text relating to write requested after HSB goes LOW are
inhibited.
Page 5: modified software store description to indicate no further read/writes
permitted for tSS duration after sixth read cycle.
Added parameter tPURHH to AutoStore power-Up recall table
Updated Figures 11, 12 and 13.
Added tHLBL parameter
Removed tDHSB parameter
Updated Figure 14;Hardware store cycle
Changed Simtek trademarks to Cypress
Page 24 of 25
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CY14B104L, CY14B104N
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© Cypress Semiconductor Corporation, 2006-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-07102 Rev. *L
Revised December 19, 2008
Page 25 of 25
AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document are the trademarks of their respective
holders.
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