Intersil ISL90842 Quad digitally controlled variable resistor Datasheet

ISL90842
®
Quad Digitally Controlled Variable Resistors
Data Sheet
January 16, 2006
FN8096.1
Low Noise, Low Power I2C® Bus, 256 Taps
Features
The ISL90842 integrates four digitally controlled
potentiometers (DCP) configured as variable resistors on a
monolithic CMOS integrated circuit.
• Four variable resistors in one package
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
I2C bus interface. Each potentiometer has an associated
Wiper Register (WR) that can be directly written to and read
by the user. The contents of the WR controls the position of
the wiper.
The DCPs can be used as two-terminal variable resistors in
a wide variety of applications including control, parameter
adjustments, and signal processing.
• 256 resistor taps - 0.4% resolution
• I2C serial interface
• Wiper resistance: 70Ω typical @ 3.3V
• Standby current <5µA max
• Power supply: 2.7V to 5.5V
• 50kΩ, 10kΩ total resistance
• 14 Lead TSSOP
• Pb-free plus anneal available (RoHS compliant)
Pinout
ISL90842
(14 LEAD TSSOP)
TOP VIEW
RH3
1
14
RW0
RW3
2
13
RH0
SCL
3
12
VCC
SDA
4
11
A1
GND
5
10
A0
RW2
6
9
RH1
RH2
7
8
RW1
Ordering Information
PART NUMBER
PART MARKING
RESISTANCE OPTION
(Ω)
TEMP RANGE
(°C)
PACKAGE
ISL90842UIV1427Z (Notes 1 & 2)
90842UI27Z
50K
-40 to +85
14 Ld TSSOP (Pb-Free)
ISL90842WIV1427Z (Notes 1 & 2)
90842WI27Z
10K
-40 to +85
14 Ld TSSOP (Pb-Free)
NOTES:
1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. Add “-TK” suffix for Tape and Reel.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL90842
Functional Diagram
VCC
RH0
RH1
RH2
RH3
RL
RL
RL
RL
SCL
SDA
A0
I2C
INTERFACE
A1
GND
RW0
RW1
RW2
RW3
Block Diagram
VCC
WR3
DCP3
*
I2C INTERFACE
SDA
SCL
WR2
POWER-UP,
INTERFACE,
CONTROL
AND STATUS
LOGIC
DCP2
*
WR1
DCP1
*
A1
A0
WR0
DCP0
*
RH3
RW3
RH2
RW2
RH1
RW1
RH0
RW0
GND
* THE RL PINS OF EACH DCP ARE LEFT FLOATING
Pin Descriptions
TSSOP PIN
SYMBOL
1
RH3
“High” terminal of DCP3
2
RW3
“Wiper” terminal of DCP3
3
SCL
I2C interface clock
4
SDA
Serial data I/O for the I2C interface
5
GND
Device ground pin
6
RW2
“Wiper” terminal of DCP2
7
RH2
“High” terminal of DCP2
8
RW1
“Wiper” terminal of DCP1
9
RH1
“High” terminal of DCP1
10
A0
Device address for the I2C interface
11
A1
Device address for the I2C interface
12
VCC
Power supply pin
13
RH0
“High” terminal of DCP0
14
RW0
“Wiper” terminal of DCP0
2
DESCRIPTION
FN8096.1
January 16, 2006
ISL90842
Absolute Maximum Ratings
Recommended Operating Conditions
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage at any digital interface pin
with respect to GND . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
Voltage at any DCP pin with
respect to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC
Lead temperature (soldering, 10s). . . . . . . . . . . . . . . . . . . . . . 300°C
IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
Latchup . . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level B at +85°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >2kV Human Body Model
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Power rating of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW
Wiper current of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . ±3.0mA
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Analog Specifications
SYMBOL
RTOTAL
RW
CH/CL/CW
ILkgDCP
Over recommended operating conditions unless otherwise stated.
PARAMETER
RH to RW resistance
TEST CONDITIONS
MIN
MAX
UNIT
W option, wiper counter = 00h
10
kΩ
U option, wiper counter = 00h
50
kΩ
RH to RW resistance tolerance
Wiper counter = 00h
Wiper resistance
VCC = 3.3V @ 25°C, wiper current =
VCC/RTOTAL
-20
70
Potentiometer capacitance (Note 15)
Leakage on DCP pins (Note 15)
TYP
(NOTE 1)
+20
%
200
Ω
10/10/25
Voltage at pin from GND to VCC
0.1
pF
1
µA
-1
1
MI
(Note 2)
-0.5
0.5
MI
(Note 2)
RESISTOR MODE (Measurements between RWi and RHi, i = 0, 1, 2 or 3)
RINL
(Note 5)
Integral non-linearity
RDNL
(Note 4)
Differential non-linearity
Roffset
(Note 3)
Offset
DCP register set between 20 hex and FF
hex; monotonic over all tap positions
U option
0
1
7
MI
(Note 2)
W option
0
0.5
2
MI
(Note 2)
-2
2
MI
(Note 2)
RMATCH
(Note 6)
DCP to DCP matching
Any two DCPs at the same tap position with
the same terminal voltages
TCR
(Note 7)
Resistance temperature coefficient
DCP register set between 20 hex and FF hex
±45
ppm/°C
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL
ICC1
ISB
ILkgDig
PARAMETER
TEST CONDITIONS
MIN
= 400kHz; SDA = Open; (for I2C, active,
TYP
(NOTE 1)
MAX
UNIT
VCC supply current (volatile write/
read)
fSCL
read and write states)
1
mA
VCC current (standby)
VCC = +5.5V, I2C interface in standby state
5
µA
VCC = +3.6V, I2C interface in standby state
2
µA
10
µA
Leakage current, at pins A0, A1, SDA, Voltage at pin from GND to VCC
and SCL
3
-10
FN8096.1
January 16, 2006
ISL90842
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
tDCP
(Note 8)
PARAMETER
DCP wiper response time
TEST CONDITIONS
MIN
SCL falling edge of last bit of DCP data byte
to wiper change
TYP
(NOTE 1)
MAX
UNIT
1
µs
SERIAL INTERFACE SPECS
VIL
A1, A0, SDA, and SCL input buffer
LOW voltage
-0.3
0.3*VCC
V
VIH
A1, A0, SDA, and SCL input buffer
HIGH voltage
0.7*VCC
VCC+0.3
V
Hysteresis
(Note 8)
SDA and SCL input buffer hysteresis
VOL
(Note 8)
SDA output buffer LOW voltage,
sinking 4mA
Cpin
(Note 8)
fSCL
V
0.05*
VCC
0
0.4
V
A1, A0, SDA, and SCL pin
capacitance
10
pF
SCL frequency
400
kHz
tIN
(Note 8)
Pulse width suppression time at SDA
and SCL inputs
Any pulse narrower than the max spec is
suppressed
50
ns
tAA
(Note 8)
SCL falling edge to SDA output data
valid
SCL falling edge crossing 30% of VCC, until
SDA exits the 30% to 70% of VCC window
900
ns
tBUF
(Note 8)
Time the bus must be free before the
start of a new transmission
SDA crossing 70% of VCC during a STOP
condition, to SDA crossing 70% of VCC
during the following START condition
1300
ns
tLOW
Clock LOW time
Measured at the 30% of VCC crossing
1300
ns
tHIGH
Clock HIGH time
Measured at the 70% of VCC crossing
600
ns
tSU:STA
START condition setup time
SCL rising edge to SDA falling edge; both
crossing 70% of VCC
600
ns
tHD:STA
START condition hold time
From SDA falling edge crossing 30% of VCC
to SCL falling edge crossing 70% of VCC
600
ns
tSU:DAT
Input data setup time
From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge crossing 30% of
VCC
100
ns
tHD:DAT
Input data hold time
From SCL rising edge crossing 70% of VCC
to SDA entering the 30% to 70% of VCC
window
0
ns
tSU:STO
STOP condition hold time
From SCL rising edge crossing 70% of VCC,
to SDA rising edge crossing 30% of VCC
600
ns
tHD:STO
STOP condition hold time for read, or
volatile only write
From SDA rising edge to SCL falling edge.
Both crossing 70% of VCC
600
ns
tDH
(Note 8)
Output data hold time
From SCL falling edge crossing 30% of VCC,
until SDA enters the 30% to 70% of VCC
window
0
ns
tR
(Note 8)
SDA and SCL rise time
From 30% to 70% of VCC
20 +
0.1 * Cb
250
ns
tF
(Note 8)
SDA and SCL fall time
From 70% to 30% of VCC
20 +
0.1 * Cb
250
ns
Total on-chip and off-chip
10
400
pF
Cb (Note 8) Capacitive loading of SDA or SCL
Rpu
(Note 8)
SDA and SCL bus pull-up resistor off- Maximum is determined by tR and tF
chip
For Cb = 400pF, max is about 2~2.5kΩ
For Cb = 40pF, max is about 15~20kΩ
4
1
kΩ
FN8096.1
January 16, 2006
ISL90842
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(NOTE 1)
MAX
UNIT
tSU:A
A1 and A0 setup time
Before START condition
600
ns
tHD:A
A1 and A0 hold time
After STOP condition
600
ns
SDA vs SCL Timing
tHIGH
tF
SCL
tLOW
tR
tSU:DAT
tSU:STA
tHD:DAT
tHD:STA
SDA
(INPUT TIMING)
tSU:STO
tAA
tDH
tBUF
SDA
(OUTPUT TIMING)
A0 and A1 Pin Timing
STOP
START
SCL
CLK 1
SDA IN
tSU:A
tHD:A
A0, A1
NOTES:
1. Typical values are for TA = 25°C and 3.3V supply voltage.
2. MI = |R255 – R0| / 255. R255 and R0 are the measured resistances for the DCP register set to FF hex and 00 hex, respectively.
3. Roffset = R255 / MI, when measuring between RW and RH.
4. RDNL = (Ri – Ri-1) / MI, for i = 32 to 255.
5. RINL = [Ri – (MI • i) – R0] / MI, for i = 32 to 255.
6. RMATCH = (Ri,x – Ri,y) / MI, for i = 0 to 255, x = 0 to 3 and y = 0 to 3.
6
[ Max ( Ri ) – Min ( Ri ) ]
10
7. TC R = ---------------------------------------------------------------- × ----------------- for i = 32 to 255, T = -40°C to 85°C. Max ( ) is the maximum value of the resistance and Min ( ) is the
[ Max ( Ri ) + Min ( Ri ) ] ⁄ 2 125°C minimum value of the resistance over the temperature range.
8. This parameter is not 100% tested.
5
FN8096.1
January 16, 2006
ISL90842
Typical Performance Curves
160
1.8
VCC=2.7, T=+85°C
1.4
120 VCC=2.7, T=-40°C
100
80
60
40
1.2
1
-40°C
0.8
+85°C
0.6
0.4
VCC=5.5, T=-40°C
VCC=5.5, T=+85°C
VCC=5.5, T=+25°C
20
0
1.6
STANDBY ICC (µA)
WIPER RESISTANCE (Ω)
140
VCC=2.7, T=+25°C
0
50
100
150
200
0.2
0
2.7
250
+25°C
3.2
3.7
4.2
TAP POSITION (DECIMAL)
FIGURE 1. WIPER RESISTANCE vs TAP POSITION
[I(RW) = VCC / RTOTAL] FOR 50kΩ (U)
0.5
VCC=5.5, T=+25°C
VCC=2.7, T=+25°C
VCC=2.7, T=+25°C
0.3
VCC=5.5, T=-40°C
0.1
INL (LSB)
DNL (LSB)
0.2
0
VCC=5.5, T=+85°C
-0.2
VCC=2.7, T=-40°C
82
132
182
VCC=5.5, T=+85°C
0.1
VCC=2.7, T=+85°C
-0.1
-0.3
VCC=2.7, T=+85°C
VCC=5.5, T=-40°C
-0.3
32
-0.5
32
232
82
1
25
5.5V
TC (ppm/°C)
END TO END RTOTAL CHANGE (%)
35
0
182
232
FIGURE 4. INL vs TAP POSITION FOR 50kΩ (U)
1.5
2.7V
132
TAP POSITION (DECIMAL)
FIGURE 3. DNL vs TAP POSITION FOR 50kΩ (U)
0.5
VCC=2.7,
T=-40°C
VCC=5.5, T=+25°C
TAP POSITION (DECIMAL)
-0.5
-1
-1.5
-40
5.2
FIGURE 2. STANDBY ICC vs Vcc
0.3
-0.1
4.7
VCC (V)
15
5
-5
-15
-20
0
20
40
60
TEMPERATURE (°C)
FIGURE 5. END TO END RTOTAL % CHANGE vs
TEMPERATURE
6
80
-25
32
82
132
182
232
TAP POSITION (DECIMAL)
FIGURE 6. TC IN ppm
FN8096.1
January 16, 2006
ISL90842
Typical Performance Curves
(Continued)
SCL
INPUT
SIGNAL AT WIPER
(WIPER UNLOADED
MOVEMENT FROM
ffh TO 00h)
OUTPUT
TAP POSITION = MID POINT
RTOTAL=9.4K
FIGURE 7. FREQUENCY RESPONSE (2.2MHz)
FIGURE 8. LARGE SIGNAL SETTLING TIME
Principles of Operation
I2C Serial Interface
The ISL90842 is an integrated circuit incorporating four
DCPs with their associated registers, and an I2C serial
interface providing direct communication between a host
and the DCPs.
The ISL90842 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL90842
operates as a slave device in all applications.
DCP Description
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer. The RW pin of each DCP is connected to
intermediate nodes, and is equivalent to the wiper terminal
of a mechanical potentiometer. The position of the wiper
terminal within the DCP is controlled by an 8-bit volatile
Wiper Register (WR). Each DCP has its own WR. When the
WR of a DCP contains all zeroes (WR<7:0>: 00h), its wiper
terminal (RW) is closest to its RL terminal. When the WR of a
DCP contains all ones (WR<7:0>: FFh), its wiper terminal
(RW) is furthest from the RH terminal. As the value of the
WR increases from all zeroes (00h) to all ones (255
decimal), the wiper moves monotonically from the position
furthest from RH to a position closer to RH. At the same time,
the resistance between RH and RW decreases
monotonically. Note that the RL terminals for all four pots are
not connected (left floating).
While the ISL90842 is being powered up, all four WRs are
reset to 80h (128 decimal), which locates RW roughly at a
position which yields a rheostat setting that is about 1/2 of
RTOTAL.
The WRs can be read or written directly using the I2C serial
interface as described in the following sections. The I2C
interface Address Byte has to be set to 00h, 01h, 02h, and
03h to access the WR of DCP0, DCP1, DCP2, and DCP3,
respectively.
receiver pulls the SDA line LOW to acknowledge the
7
All communication over the I2C interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line must change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 9). On power-up of the ISL90842 the SDA pin is in the
input mode.
All I2C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL90842 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (See
Figure 9). A START condition is ignored during the power-up
of the device.
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 9). A STOP condition at the end of
a read operation, or at the end of a write operation places
the device in its standby mode.
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
reception of the eight bits of data (See Figure 10).
FN8096.1
January 16, 2006
ISL90842
The ISL90842 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL90842 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation
“1” for a Read operation, and “0” for a Write operation (See
Table 1).
TABLE 1. IDENTIFICATION BYTE FORMAT
Logic values at pins A1, and A0 respectively
0
A valid Identification Byte contains 01010 as the five MSBs,
and the following two bits matching the logic values present
at pins A1 and A0. The LSB is the Read/Write bit. Its value is
1
0
1
0
A1
(MSB)
A0
R/W
(LSB)
SCL
SDA
START
DATA
STABLE
DATA
CHANGE
DATA
STABLE
STOP
FIGURE 9. VALID DATA CHANGES, START, AND STOP CONDITIONS
SCL FROM
MASTER
1
8
9
SDA OUTPUT FROM
TRANSMITTER
HIGH IMPEDANCE
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
START
ACK
FIGURE 10. ACKNOWLEDGE RESPONSE FROM RECEIVER
WRITE
SIGNALS FROM
THE MASTER
SIGNAL AT SDA
SIGNALS FROM
THE ISL90842
S
T
A
R
T
IDENTIFICATION
BYTE
ADDRESS
BYTE
0 1 0 1 0 A1 A0 0
0 0 0 0 0 0
A
C
K
S
T
O
P
DATA
BYTE
A
C
K
A
C
K
FIGURE 11. BYTE WRITE SEQUENCE
8
FN8096.1
January 16, 2006
ISL90842
SIGNALS
FROM THE
MASTER
S
T
A
R
T
SIGNAL AT SDA
IDENTIFICATION
BYTE WITH
R/W=0
ADDRESS
BYTE
0 1 0 1 0 A1A0 0
A
C
K
S
T
O
P
A
C
K
0 1 0 1 0 A1A0 1
0 0 0 0 0 0
A
C
K
SIGNALS FROM
THE SLAVE
S
T
A IDENTIFICATION
R
BYTE WITH
T
R/W=1
A
C
K
A
C
K
FIRST READ
DATA BYTE
LAST READ
DATA BYTE
FIGURE 12. READ SEQUENCE
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL90842 responds with an ACK. At this time, the device
enters its standby state (See Figure 11).
Read Operation
A Read operation consist of a three byte instruction followed
by one or more Data Bytes (See Figure 12). The master
initiates the operation issuing the following sequence: a
START, the Identification byte with the R/W bit set to “0”, an
Address Byte, a second START, and a second Identification
byte with the R/W bit set to “1”. After each of the three bytes,
the ISL90842 responds with an ACK. Then the ISL90842
transmits Data Bytes as long as the master responds with an
ACK during the SCL cycle following the eighth bit of each
byte. The master terminates the read operation (issuing a
STOP condition) following the last bit of the last Data Byte
(See Figure 12).
The Data Bytes are from the registers indicated by an
internal pointer. This pointer initial value is determined by the
Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 03h the pointer “rolls
over” to 00h, and the device continues to output data for
each ACK received.
9
FN8096.1
January 16, 2006
ISL90842
Packaging Information
14-Lead Plastic, TSSOP, Package Code V14
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.193 (4.9)
.200 (5.1)
.041 (1.05)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
10
FN8096.1
January 16, 2006