Fairchild FAN5069MTCX Pwm and ldo controller combo Datasheet

FAN5069
PWM and LDO Controller Combo
Features
Description
■ General Purpose PWM Regulator and LDO Controller
The FAN5069 combines a high efficiency PWM controller and a
LDO (Low DropOut) linear regulator controller. Synchronous
rectification provides high efficiency over a wide range of load
currents. Efficiency is further enhanced by using the low-side
MOSFET's RDS(ON) to sense current.
■ Input Voltage Range: 3V to 24V
■ Output Voltage Range: 0.8V to 15V
■ VCC
- 5V
Both the linear and PWM regulator soft-start are controlled by a
single external capacitor, to limit in rush current from the supply
when the regulators are first enabled. Current limit for PWM is
also programmable.
- Shunt Regulator for 12V Operation
■ Support for Ceramic Cap on PWM Output
■ Programmable Current Limit for PWM Output
■ Programmable Switching Frequency (200KHz to 600KHz)
The PWM regulator employs a Summing-Current-Mode control
with external compensation to achieve fast load transient
response and provide system design optimization.
■ RDS(ON) Current Sensing
■ Internal Synchronous Boot Diode
■ Soft-Start for both PWM and LDO
FAN5069 is offered in both industrial temperature grade (-40°C
to +85°C) as well as commercial temperature grade (-10°C to
+85°C)
■ Multi-Fault Protection with Optional Auto-restart
■ 16-pin TSSOP Package
Applications
■ PC/Server Motherboard Peripherals
- VCC_MCH (1.5V), VDDQ (1.5V) and VTT_GTL(1.25V)
■ Power Supply for
- FPGA, DSP, Embedded Controllers, Graphic Card Processor, and Communication Processors
■ Industrial Power Supplies
■ High Power DC-to-DC Converters
Ordering Information
Part Number Operating Temp. Range Pb-Free
Package
Packing Method
Qty/Reel
FAN5069MTCX
-10°C to +85°C
Yes
16-Lead TSSOP
Tape and Reel
2500
FAN5069EMTCX
-40°C to +85°C
Yes
16-Lead TSSOP
Tape and Reel
2500
Note: Contact Fairchild Sales for availability of other package options.
FAN5069 Rev. 1.1.0
©2005 Fairchild Semiconductor Corporation
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FAN5069 PWM and LDO Controller Combo
October 2005
FAN5069 PWM and LDO Controller Combo
Typical Application
RVCC
+12V
3 TO 24V
VCC
15
C9
FAN5069
+5V
EN
SS
C3
R4
ILIM
R5
R(T)
AGND
11
7
3
Q1
10
PWM
2
9
C8
1
PWM OUT
Q2
12
FBLDO
L1
SW
6
ULDO
CONTROL
C6
LDRV
PGND
FB
C2
5
COMP
C1
R3
R2
R7
C7
HDRV
8
16
C4
R1
LDO OUT
BOOT
C5
13
GLDO
R8
R(RAMP)
4
PWM OUT
Q3
14
R6
Figure 1. Typical Application Diagram
FAN5069 Rev. 1.1.0
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FAN5069 PWM and LDO Controller Combo
Pin Assignment
Top View
FBLDO
1
16
GLDO
R(T)
2
15
VCC
ILIM
3
14
R(RAMP)
SS
4
13
LDRV
COMP
5
12
PGND
FB
6
11
BOOT
EN
7
10
HDRV
AGND
8
FAN5069
9
SW
16-Lead TSSOP
Figure 2. Pin Assignment
Pin Description
Pin No.
Pin Name
1
FBLDO
2
R(T)
Oscillator Set Resistor. This pin provides oscillator switching frequency adjustment. By placing
a resistor (RT) from this pin to GND, the nominal 200kHz switching frequency is increased.
3
ILIM
Current Limit. A resistor from this pin to GND sets the current limit.
4
SS
5
COMP
6
FB
Feedback. This pin is the inverting input of the internal error amplifier. Use this pin, in combination with the COMP pin, to compensate the feedback loop of the converter.
7
EN
Enable. Enables operation when pulled to logic high. Toggling EN will also reset the regulator
after a latched fault condition. This is a CMOS input whose state is indeterminate if left open and
hence needs to be properly biased at all times.
8
AGND
Analog Ground. The signal ground for the IC. All internal control voltages are referred to this pin.
Tie this pin to the ground island/plane through the lowest impedance connection available.
9
SW
Switching Node. Return for the high-side MOSFET driver and a current sense input. Connect to
source of high-side MOSFET and drain of low-side MOSFET.
10
HDRV
High-Side Gate Drive Output. Connect to the gate of the high-side power MOSFETs. This pin is
also monitored by the adaptive shoot-through protection circuitry to determine when the high-side
MOSFET is turned off.
11
BOOT
Bootstrap Supply Input. Provides a boosted voltage to the high-side MOSFET driver. Connect
to bootstrap capacitor as shown in Figure 1.
12
PGND
Power Ground. The return for the low-side MOSFET driver. Connect to source of low-side MOSFET.
13
LDRV
Low-Side Gate Drive Output. Connect to the gate of the low-side power MOSFETs. This pin is
also monitored by the adaptive shoot-through protection circuitry to determine when the lower
MOSFET is turned off.
14
R(RAMP)
Ramp Resistor. A resistor from this pin to VIN sets the ramp amplitude and provides voltage
feed-forward.
15
VCC
VCC. Provides bias power to the IC and the drive voltage for LDRV. Bypass with a ceramic
capacitor as close to this pin as possible. This pin has a shunt regulator which will draw current
when the input voltage is above 5.6V.
16
GLDO
FAN5069 Rev. 1.1.0
Pin Description
LDO Feedback. This node is regulated to VREF.
Soft-Start. A capacitor from this pin to GND programs the slew rate of the converter and the LDO
during initialization. It also sets the time by which the converter will delay when restarting after a
fault occurs. SS has to reach 1.2V before fault shut-down feature is enabled. The LDO is enabled
when SS reaches 2.2V.
COMP. The output of the error amplifier drives this pin.
Gate Drive for the LDO. Turned off (low) until SS is greater than 2.2V.
3
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Parameter
Min.
Max.
Unit
VCC to PGND
6
V
BOOT to PGND
33
V
SW to PGND
Continuous
Transient (t < 50nS, F < 500kHz)
-0.5
33
V
-3
33
V
HDRV (VBOOT--VSW)
6
V
LDRV
-0.5
6
V
All Other Pins
-0.3
VCC+0.3
V
150
mA
Maximum Shunt Current for VCC
Electrostatic Discharge Protection (ESD) Level (Note 2)
HBM
2
CDM
0.4
kV
Thermal Information
Parameter
Min.
Max.
Unit
150
°C
Lead Soldering Temperature, 10 Seconds
300
°C
Vapor Phase, 60 Second
215
°C
Infrared, 15 Seconds
220
°C
Power Dissipation (PD), TA = 25°C
715
mW
Storage Temperature
Typ.
-65
Thermal Resistance- Junction to Case(θJC)
37
°C/W
Thermal Resistance- Junction to Ambient (θJA) (Note 3)
100
°C/W
Recommended Operating Conditions
Conditions
Min.
Typ.
Max.
Unit
Supply Voltage (VCC)
Parameter
VCC to GND
4.5
5
5.5
V
Ambient Temperature (TA)
Commercial
-10
85
°C
Industrial
-40
85
°C
125
°C
Junction Temperature (TJ)
Notes:
1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational section of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified all other voltages are referenced
to AGND.
2. Using Mil Std. 883E, method 3015.7(Human Body Model) and EIA/JESD22C101-A (Charge Device Model).
3. Junction to ambient thermal resistance, θJA, is a strong function of PCB material, board thickness, thickness and number of copper
planes, number of vias used, diameter of vias used, available copper surface, and attached heat sink characteristics.
FAN5069 Rev. 1.1.0
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FAN5069 PWM and LDO Controller Combo
Absolute Maximum Ratings (Note1)
Unless otherwise noted, VCC = 5V, TA = 25°C, using circuit in Figure 1.
The ‘•’ denotes that the specifications apply to the full ambient operating temperature range. See Notes 4 and 5.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
2.6
3.2
3.8
mA
200
400
μA
10
15
mA
5.9
V
V
Supply Current
IVCC
VCC Current (Quiescent)
HDRV, LDRV Open
IVCC(SD)
VCC Current (Shutdown)
EN = 0V, VCC = 5.5V
IVCC(OP)
VCC Current (Operating)
EN = 5V, VCC = 5.0V
VSHUNT
VCC Voltage (Note 6)
Sinking 20mA to 100mA at VCC Pin
UVLO
UVLO(H)
Rising VCC UVLO Threshold
UVLO(L)
Falling VCC UVLO Threshold
•
•
5.5
•
•
4.0
4.25
4.5
3.6
3.75
4.0
V
VCC UVLO Threshold Hysteresis
0.5
V
Current
10
μA
VLDOSTART LDO Start threshold
2.2
V
1.2
V
Soft-Start
ISS
VSSOK
PWM Protection Enable
threshold
Oscillator
FOSC
Frequency
R(T) = 56KΩ ± 1%
240
300
360
KHz
R(T) = Open
160
200
240
KHz
600
KHz
Frequency Range
ΔVRAMP
160
Ramp Amplitude (Peak-toPeak)
R(RAMP) = 330KΩ
0.4
V
Minimum ON Time
F = 200kHz
200
nS.
Reference
VREF
•
•
Reference Voltage (Measured TA = 0°C to 70°C
at FB Pin)
TA = -40°C to 85°C
790
800
810
mV
788
800
812
mV
Current Amplifier Reference
(at SW node)
160
mV
Error Amplifier
GBWP
S/R
IFB
DC Gain
80
dB
Gain-BW Product
25
MHz
Slew Rate
10pF across COMP to GND
Output Voltage Swing
No Load
8
•
FB Pin Source Current
0.5
V/μS.
4.0
V
μA
1
Gate Drive
RHUP
HDRV Pull-up Resistor
Sourcing
RHDN
HDRV Pull-down Resistor
Sinking
RLUP
LDRV Pull-up Resistor
Sourcing
RLDN
LDRV Pull-down Resistor
Sinking
FAN5069 Rev. 1.1.0
•
•
•
•
5
1.8
3
Ω
1.8
3
Ω
1.8
3
Ω
1.2
2
Ω
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FAN5069 PWM and LDO Controller Combo
Electrical Characteristics
Unless otherwise noted, VCC = 5V, TA = 25°C, using circuit in Figure 1.
The ‘•’ denotes that the specifications apply to the full ambient operating temperature range. See Notes 4 and 5.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
10
11
Unit
Protection/Disable
9
μA
ILIM
ILIMIT Source Current
ISWPD
SW Pull-down Current
SW = 1V, EN = 0V
VUV
SW Pull-down Current
As % of set point.
2μS noise filter
•
65
75
80
%
VOV
Under-voltage Shutdown
As % of set point.
2μS noise filter
•
110
115
120
%
Enable Threshold Voltage
Enable Condition
Enable Threshold Voltage
Disable Condition
•
•
2.0
Enable Source Current
VCC = 5V
10
mA
Supply Current
Thermal Shutdown
160
°C
V
0.8
V
μA
50
LDO (See Note 7)
VLDOREF
VLDO_DO
•
•
•
Reference Voltage (measured TA = 0°C to 70°C
at FBLDO pin)
TA = -40°C to 85°C
Regulation
0A ≤ I LOAD ≤ 5A
Drop-out Voltage
I LOAD ≤ 5Aand R DS – ON < 50mΩ
External Gate Drive
VCC = 4.75V
VCC = 5.6V
775
800
825
mV
770
800
830
mV
1.17
1.2
1.23
V
0.3
V
4.5
V
5.3
V
•
•
Gate Drive Source Current
1.2
mA
Gate Drive Sink Current
400
μA
Notes:
4. All limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control.
5. AC specifications guaranteed by design/characterization (not production tested).
6. For a case when VCC is higher than the typical 5V VCC. Voltage observed at VCC pin when the internal shunt regulator is sinking
current to keep voltage on VCC pin constant.
7. Test Conditions: VLDO_IN = 1.5V and VLDO_OUT = 1.2V
FAN5069 Rev. 1.1.0
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FAN5069 PWM and LDO Controller Combo
Electrical Characteristics (Contd.)
Figure 3. Dead Time Waveform
Figure 6. PWM Load Transient (0 to 15A)
Figure 4. PWM Load Transient (0 to 5A)
Figure 7. LDO Load Transient (0 to 2A)
Figure 5. PWM Load Transient (0 to 10A)
Figure 8. LDO Load Transient (0 to 5A)
FAN5069 Rev. 1.1.0
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FAN5069 PWM and LDO Controller Combo
Typical Performance Characteristics
Figure 9. PWM/LDO Power Up
Figure 12. Enable ON (IPWM = 5A)
Figure 10. PWM/LDO Power Down
Figure 13. Enable OFF (IPWM = 5A)
Figure 11. Auto Restart
FAN5069 Rev. 1.1.0
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FAN5069 PWM and LDO Controller Combo
Typical Performance Characteristics (Contd.)
PWM Line Regulation (VOUT = 1.5V)
LDO Load Regulation (VOUT = 1.203V)
1.210
1.54
IL = 0A
IL = 10A
Output Voltage (V)
Output Voltage (V)
IL = 5A
1.52
1.50
1.48
1.205
1.200
VIN = 8V
1.195
VIN = 12V
VIN = 15V
VIN = 20V
1.46
1.190
6
8
10
12
14
16
18
0
20
1
2
3
4
5
Load Current (A)
Input Voltage (V)
Figure 17. LDO Load Regulation
Figure 14. PWM Line Regulation
Master Clock Frequency
LDO Line Regulation (VOUT = 1.203V)
700
1.210
IL = 0A
IL = 2A
600
IL = 5A
Frequency (kHz)
Output Voltage (V)
1.205
1.200
500
400
300
1.195
200
100
1.190
8
10
12
14
16
18
0
20
100
200
400
Figure 18. RT vs. Frequency
Figure 15. LDO Line Regulation
PWM Load Regulation (VOUT = 1.50V)
1.510
300
RT (KΩ)
Input Voltage (V)
Efficiency vs. Input Voltage
100
VIN = 8V
VIN = 12V
80
VIN = 20V
VIN = 8V
Efficiency (%)
Output Voltage (V)
VIN = 15V
1.505
1.500
1.495
VIN = 12V
VIN = 15V
60
VIN = 20V
40
20
0
1.490
2
0
2
4
6
8
Load Current (A)
6
8
10
Figure 19. 1.5V PWM Efficiency
Figure 16. PWM Load Regulation
FAN5069 Rev. 1.1.0
4
Load Current (A)
10
9
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FAN5069 PWM and LDO Controller Combo
Typical Performance Characteristics (Contd.)
Shunt Reg
RILIM
CBOOT
Internal Vcc 5.6V Max.
Vcc
BOOT
Internal
Boot Diode
10μA
Current Limit
Comparator
ILIM
VIN
COMP
PWM
Error
Amplifier
FB
R Q
PWM
Comparator
S
Vref
Vcc
10μA
HDRV
Adaptive
Gate Drive
Circuit
LO
SW
OSC
Vout
CO
SS
VIN
RRAMP
Summing
LDRV
Σ
Ramp
Generator
R(RAMP)
EN
Current
Sense
Amplifier
PGND
Amplifier
Enable
Figure 20. Block Diagram
Detailed Operation Description
FAN5069 combines a high efficiency fixed-frequency PWM controller designed for single phase synchronous buck Point-OfLoad converters with an integrated LDO controller to support
GTL type of loads. This controller is ideally suited to deliver low
voltage, high current power supplies needed in desktop computers, notebooks, workstations and servers. The controller comes
with an integrated boot diode which helps reduce component
cost and increase space savings. With this controller, the input
to the power supply can be varied from 3V to 24V and the output voltage can be set to regulate at 0.8V to 15V on the switcher
output. The LDO output can be configured to regulate between
0.8V to 3V and the input to the LDO can be from 1.5V to 5V,
respectively. An internal shunt regulator at the VCC pin facilitates
the controller operation from either a 5V or 12V power source.
PWM Operation
VCC Bias Supply
Initialization
Refer to Figure 20 for the PWM control mechanism. The
FAN5069 uses the summing mode method of control to generate the PWM pulses. The amplified output of the current sense
amplifier is summed with an internally generated ramp and the
combined signal is amplified and compared with the output of
the error amplifier to get the pulse width to drive the high-side
MOSFET. The sensed current from the previous cycle is used to
modulate the output of the summing block. The output of the
summing block is also compared against the voltage threshold
set by the RLIM resistor to limit the inductor current on a cycleby-cycle basis. The controller facilitates external compensation
for enhanced flexibility.
When the PWM is disabled, the SW node is connected to GND
through an internal 70Ω MOSFET to slowly discharge the output. As long as the PWM controller is enabled, this internal
MOSFET remains OFF.
The FAN5069 is capable of operating from either a 5V or 12V
supply. The internal shunt regulator at the VCC pin is capable of
sinking 150mA of current to ensure that the controller’s internal
VCC is maintained at 5.6V Max. To operate from a 12V supply,
an external resistor must be used between the 12V supply and
the Vcc pin as shown in Figure 1.
Soft-Start (PWM and LDO)
When VCC exceeds the UVLO threshold and EN is high, the circuit releases SS and enables the PWM regulator. The capacitor
connected to the SS pin and GND is now charged by a 10µA
internal current source causing the voltage on the capacitor to
rise. When this voltage exceeds 1.2V, all protection circuits are
enabled. When this voltage exceeds 2.2V, the LDO output is
enabled. The input to the error amplifier at the non-inverting pin
is clamped by the voltage on the SS pin until it crosses the reference voltage.
Select a resistor such that:
■ It is rated to handle the power dissipation
■ Current sunk within the controller is minimized to prevent
temperature rise.
PWM Section
The FAN5069’s PWM controller combines the conventional voltage mode control and current sensing through lower MOSFET
RDS_ON to generate the PWM signals. Although this method of
current sensing is loss-less and cost effective, for more accurate
current sense requirements an optional external resistor can be
connected with the bottom MOSFET in series.
FAN5069 Rev. 1.1.0
The time it takes the PWM output to reach regulation (TRise) is
calculated using the following equation:
T RISE = 8 × 10
10
–2
× C SS (CSS is in μf)
(EQ. 1)
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FAN5069 PWM and LDO Controller Combo
Block Diagram
Over Current Limit (PWM)
The clock frequency on the oscillator is set using an external
resistor, connected between R(T) pin and ground. The frequency follows the graph as shown in Figure 18. The minimum
clock frequency is 200KHz which is when R(T) pin is left open.
Select the value of R(T) as shown in the equation below. This
equation is valid for all FOSC > 200kHz.
The PWM converter is protected against overloading through a
cycle-by-cycle current limit set by selecting RILIM resistor. An
internal 10µA current source sets the threshold voltage for the
output of the summing amplifier. When the summing amplifier
output exceeds this threshold level, the current limit comparator
trips and the PWM starts skipping pulses. If the current limit tripping occurs for 16 continuous clock cycles, a fault latch is set
and the controller shuts down the converter. This shut down feature is disabled during the start-up until the voltage on the SS
capacitor crosses 1.2V.
9
5 × 10
R ( T ) = ---------------------------------------------------- Ω
( F OSC – 200 × 10 3 )
(EQ. 2)
Where FOSC is in Hz.
To achieve current limit, the FAN5069 monitors the inductor current during the OFF time by monitoring and holding the voltage
across the lower MOSFET. The voltage across the lower MOSFET is sensed between the PGND and the SW pins.
For example for FOSC = 300kHz, R(T) = 50KΩ.
RRAMP Selection and Feed Forward Operation
The output of the summing amplifier is a function of the inductor
current, RDS_ON of the bottom FET and the gain of the current
sense amplifier. With the RDS_ON method of current sensing,
the current limit can vary widely from unit to unit. RDS_ON not
only varies from unit to unit, but also has a typical junction temperature coefficient of about 0.4%/°C (consult the MOSFET
datasheet for actual values). Hence, the set point of the actual
current limit decreases in proportion to increase in MOSFET die
temperature. A factor of 1.6 in the current limit set point typically
compensates for all MOSFET RDS_ON variations, assuming the
MOSFET's heat sinking will keep its operating die temperature
below 125°C.
The FAN5069 provides for feed forward function through RRAMP.
The value of RRAMP effectively changes the slope of the internal
ramp keeping the gain of the modulator constant for changes in
input voltage. RRAMP also affects the current limit as explained
in the later sections. The minimum value recommended to use
for RRAMP is 400KΩ at maximum input voltage of 24V. For other
input voltages (E.g. 8V), calculate RRAMP resistor using the following equation:
V IN – 1.8
R RAMP = ------------------------–6
55 × 10
(EQ. 3)
For more accurate current limit setting, use resistor sensing. In
a resistor sensing scheme, an appropriate current sense resistor is connected between the source terminal of the bottom
MOSFET and PGND.
Gate Drive Section
The adaptive gate control logic translates the internal PWM
control signal into the MOSFET gate drive signals and provides
necessary amplification, level shifting, and shoot-through protection. Also, it has functions that help optimize the IC performance over a wide range of operating conditions. Since the
MOSFET switching time can vary dramatically from device to
device and with the input voltage, the gate control logic provides
adaptive dead time by monitoring the gate-to-source voltages of
both upper and lower MOSFETs. The lower MOSFET drive is
not turned on until the gate-to-source voltage of the upper MOSFET has decreased to less than approximately 1V. Similarly, the
upper MOSFET is not turned on until the gate-to-source voltage
of the lower MOSFET has decreased to less than approximately
1V. This allows a wide variety of upper and lower MOSFETs to
be used without a concern for simultaneous conduction, or
shoot-through.
Set the current limit by selecting RILIM as follows:
R
K1 × I
×R
V
× 33.2 × 10 11⎞
MAX
DS – ON ⎛
1.8
OUT
= 128 + -------------------------------------------------------------- + ⎜ ⎛ 1 – ----------⎞ × -------------------------------------------------------⎟ KΩ
0.0625
V ⎠
F
×R
⎝⎝
IN
SW
RAMP ⎠
(EQ. 4)
Where
RILIM is in KΩ, IMAX is the maximum load current.
K1 is a constant to compensate for the variation of MOSFET
RDS_ON. Typically, this value is 1.6.
With K1=1.6, IMAX=10A, RDS_ON=7mΩ, VIN=24V, VOUT=1.5V,
FSW = 300KHz, and RRAMP=400KΩ, RILIM equals 168.18 KΩ.
Auto Restart (PWM)
A low impedance path between the driver pin and the MOSFET
gate is recommended for the adaptive dead-time circuit to work
properly. Any delay along this path reduces the delay generated
by the adaptive dead-time circuit thereby increasing the
chances for shoot-through.
The FAN5069 supports two modes of response when the internal fault latch is set. The user can configure it to keep the power
supply latched in the OFF state OR in the Auto Restart mode.
When the EN pin is tied to VCC, the power supply is latched
OFF. When the EN pin is terminated with a 100nF to GND, the
power supply is in Auto Restart mode. The table below
describes the relationship between PWM restart and setting on
EN pin. Do not leave the EN pin open without any capacitor.
Protection
In the FAN5069, the converter is protected against extreme over
load, short circuit, over voltage, and under voltage conditions.
All of these extreme conditions generate an internal “fault latch”
which shuts down the converter. For all fault conditions both the
high-side and the low-side drives are off except in the case of
OVP where the low-side MOSFET is turned on until the voltage
on the FB pin goes below 0.4V. The fault latch can be reset
either by toggling the EN pin or recycling VCC to the chip.
FAN5069 Rev. 1.1.0
ILIM
EN Pin
11
PWM/Restart
Pull to GND
OFF
VCC
No restart after fault
Cap to GND
Restart after
TDELAY (Sec.) = 0.85 × C
Where C is in μF
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FAN5069 PWM and LDO Controller Combo
Oscillator Clock Frequency (PWM)
rent and the MOSFET chosen. It is recommended to use low
enhancement voltage MOSFETs for the LDO.
Under Voltage Protection (PWM)
The soft-start on the LDO output (ramp) is controlled by the
capacitor on the SS pin to GND. The LDO output is enabled
only when the voltage on the SS pin reaches 2.2V. Refer to figure 9 for startup waveform.
The PWM converter output is monitored constantly for under
voltage at the FB pin. If the voltage on the FB pin stays lower
than 75% of internal Vref for 16 clock cycles, the fault latch is set
and the converter shuts down. This shutdown feature is disabled during startup till the voltage on the SS capacitor reaches
1.2V.
Design Section
General Design Guidelines
Over Voltage Protection (PWM)
Establishing the input voltage range and the maximum current
loading on the converter before choosing the switching frequency and the inductor ripple current is highly recommended.
There are design tradeoffs in choosing an optimum switching
frequency and the ripple current.
The PWM converter output voltage is monitored constantly at
the FB pin for over voltage. If the voltage on the FB pin stays
higher than 115% of internal Vref for 2 clock cycles, the controller turns OFF the upper MOSFET and turns ON the lower MOSFET. This crowbar action stops when the voltage on the FB pin
comes down to 0.4V to prevent the output voltage from becoming negative. This OVP protection feature is active as soon as
the voltage on the EN pin becomes high.
The input voltage range should accommodate the worst-case
input voltage with which the converter may ever operate. This
voltage needs to account for the cable drop encountered from
the source to the converter. Typically, the converter efficiency
tends to be higher at lower input voltage conditions.
Turning ON the low-side MOSFETs on an OVP condition pulls
down the output resulting in a reverse current which starts to
build up in the inductor. If the output over-voltage is due to failure of the high-side MOSFET, this crowbar action pulls down the
input supply or blow its fuse, protecting the system which is very
critical.
When selecting maximum loading conditions, consider the transient and steady state (continuous) loading separately. The
transient loading affects the selection of the inductor and the
output capacitors. Steady state loading affects the selection of
MOSFETs, input capacitors, and other critical heat generating
components.
During soft-start, if the output overshoots beyond 115% of Vref,
then the output voltage is brought down by the low-side MOSFET till the voltage on the FB pin goes below 0.4V. The fault
latch is NOT set until the voltage on the SS pin reaches 1.2V.
Once the fault latch is set, the converter shuts down.
115% Vref
ILIM
UV
FB
S
OV
Delay
V SS>1.2V
2 Clks
Q
EN
The selection of switching frequency is tricky. While higher
switching frequency results in smaller components, it also
results in lower efficiency. Ideal selection of switching frequency
takes into account the maximum operating voltage. The MOSFET switching losses are directly proportional to FSW and the
square function of the input voltage.
Fault
Latch
When selecting the inductor, consider the min. and max. load
conditions. Lower inductor values produce better transient
response but result in higher ripple & lower efficiency due to
high RMS currents. Optimum minimum inductance value
enables the converter to operate at the boundary of continuous
and discontinuous conduction modes.
R
S
Q
0.4V
R
LS Drive
Figure 21. Over Voltage Protection
Setting the Output Voltage (PWM)
Thermal Fault Protection
The internal reference for the PWM controller is at 0.8V. The
output voltage of the PWM regulator can be set in the range of
0.8V to 90% of its power input by an external resistor divider.
The output is divided down by an external voltage divider to the
FB pin (for example, R1 and RBIAS as in Figure 24.). Thus the
output voltage is given by the following equation:
The FAN5069 features thermal protection where the IC temperature is monitored. When the IC junction temperature exceeds
+160°C, the controller shuts down and when the junction temperature gets down to +125°C, the converter restarts.
LDO Section
R1
V OUT = 0.8V × ⎛⎝ 1 + -----------------⎞⎠
R BIAS
The LDO controller is designed to provide ultra low voltages, as
low as, 0.8V for GTL type of loads. The regulating loop employs
a very fast response feedback loop. Hence, small capacitors
can be used to keep track of the changing output voltage during
transients. For stable operation, the minimum capacitance on
the output needs to be 100µF and the typical ESR needs to be
around 100mΩ.
To minimize noise pickup on this node, keep the resistor to GND
(RBIAS) below 10KΩ.
Inductor Selection (PWM)
When the ripple current, switching frequency of the converter,
and the input-output voltages are established, select the inductor using the following equation:
The maximum voltage at the gate drive for the MOSFET can
reach close to 0.5V below the VCC of the controller. For example, for a 1.2V output, the minimum enhancement voltage
required with 4.75V on VCC is 3.05V (4.75V-0.5V-1.2V = 3.05V).
The drop-out voltage for the LDO is dependent on the load cur-
FAN5069 Rev. 1.1.0
(EQ. 5)
V OUT 2⎞
⎛
⎜ V OUT – --------------- ⎟
V IN ⎠
⎝
L MIN = ---------------------------------------------I Ripple × F SW
12
(EQ. 6)
www.fairchildsemi.com
FAN5069 PWM and LDO Controller Combo
The fault latch can also be reset by recycling the VCC to the
controller.
Typically this number varies between 20% to 50% of the maximum steady state load on the converter.
High-Side Losses
When selecting an inductor from the vendors, select the inductance value which is close to the value calculated at the rated
current (including half the ripple current).
Losses in the MOSFET can be understood by following switching interval of the MOSFET as shown in Figure 22. MOSFET
Gate drive equivalent circuit is shown in Figure 23.
Input Capacitor Selection (PWM)
The input capacitors must have an adequate RMS current rating
to withstand the temperature rise caused by the internal power
dissipation. The combined RMS current rating for the input
capacitor should be greater than the value calculated using the
following equation:
⎛ V OUT ⎛ V OUT⎞ 2⎞
I INPUT ( RMS ) = I LOAD ( MAX ) × ⎜ --------------- – ⎜ ---------------⎟ ⎟
⎝ V IN ⎠ ⎠
⎝ V IN
C ISS
C GD
QGS
QGD
C ISS
VDS
ID
(EQ. 7)
Common capacitor types used for such application include aluminum, ceramic, POS CAP, and OSCON.
4.5V
VSP
Output Capacitor Selection (PWM)
VTH
The output capacitors chosen must have low enough ESR to
meet the output ripple and load transient requirements. The
ESR of the output capacitor should be lower than both of the
values calculated below to satisfy both the transient loading and
steady state ripple conditions as given by the following equation:
V STEP
ESR ≤ ------------------------------------- and
ΔI LOAD ( MAX )
V Ripple
ESR ≤ -------------------I Ripple
QG(SW)
VGS
t1
t2
t3
t4
t5
Figure 22. Switching Losses and QG
VIN
5V
(EQ. 8)
CGD
RD
Typically, in case of aluminum and polymer based capacitors,
the output capacitance is higher than normally required to meet
these requirements. While selecting the ceramic capacitors for
the output, although lower ESR can be achieved easily, higher
capacitance values are required to meet the VOUT(MIN) restrictions during a load transient. From the stability point of view, the
zero caused by the ESR of the output capacitor plays an important role in the stability of the converter.
HDRV
RGATE
G
CGS
SW
Figure 23. Drive Equivalent Circuit
The upper graph in Figure 22 represents Drain-to-Source Voltage (VDS) and Drain Current (ID) waveforms. The lower graph
details Gate-to-Source Voltage (VGS) vs. time with a constant
current charging the gate. The x-axis therefore is also representative of Gate Charge (QG). CISS = CGD + CGS, and it controls
t1, t2, and t4 timing. CGD receives the current from the gate
driver during t3 (as VDS is falling). Obtain the gate charge (QG)
parameters shown on the lower graph from the MOSFET data
sheets.
Output Capacitor Selection (LDO)
For stable operation, the minimum capacitance of 100µF with
ESR around 100mΩ is recommended. For other values, contact
the factory.
Power MOSFET Selection (PWM)
The FAN5069 is capable of driving N-Channel MOSFETs as circuit switch elements. For better performance, the MOSFET
selection should address the following key parameters:
Assuming switching losses are about the same for both the rising edge and falling edge, Q1's switching losses occur during
the shaded time when the MOSFET has voltage across it and
current through it.
■ The maximum drain to source voltage should be at least 25%
higher than the worst-case input voltage.
■ The MOSFETs chosen should have low QG, QGD, and QGS
These losses are given by (EQ. 9), (EQ. 11), and (EQ. 11):
■ The RDS_ON of the MOSFETs be as low as possible.
PUPPER = PSW + PCOND
In typical applications for a buck converter, the duty cycles are
lower than 20%. So, to optimize the selection of MOSFETs for
both the high-side and low-side, follow different selection criteria. Select the high-side MOSFET to minimize the switching
losses and the low-side MOSFET to minimize the conduction
losses due to the channel and the body diode losses. Note that
the gate drive losses also affect the temperature rise on the
controller.
FAN5069 Rev. 1.1.0
V DS × I L
P SW = ⎛ ---------------------- × 2 × t s⎞ F SW
⎝
⎠
2
⎛ V OUT⎞
2
P COND = ⎜ ---------------⎟ × I OUT
× R DS ( ON )
⎝ V IN ⎠
(EQ. 9)
(EQ. 10)
(EQ. 11)
Where:
PUPPER is the upper MOSFET's total losses, and PSW and
PCOND are the switching and conduction losses for a given
13
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FAN5069 PWM and LDO Controller Combo
For loss calculation, refer to Fairchild's Application Note AN6005 and the associated Excel spreadsheet.
Where IRipple is the ripple current.
The Switch node (SW) ringing is caused by fast switching transitions due to the energy stored in the parasitic elements . This
ringing on the SW node couples to other circuits around the
converter if they are not handled properly. To dampen this ringing, an R-C snubber is connected across the SW node and the
source of the low-side MOSFET.
The driver's impedance and CISS determine t2 while t3's period
is controlled by the driver's impedance and QGD. Since most of
tS occurs when VGS = VSP we can assume a constant current
for the driver to simplify the calculation of tS using the following
equation:
Q G ( SW )
Q G ( SW )
t s = ---------------------- ≈ ------------------------------------------------I Driver ⎛ V
CC – V SP ⎞
⎜ -------------------------------------------⎟
⎝ R Driver + R Gate⎠
R-C components for the snubber are selected as follows:
a) Measure the SW node ringing frequency (Fring) with a low
capacitance scope probe.
b) Connect a capacitor (CSNUB) from SW node to GND so that it
reduces this ringing by half.
c) Place a resistor (RSNUB) in series with this capacitor. RSNUB
is calculated using the following equation:
(EQ. 12)
Most MOSFET vendors specify QGD and QGS. QG(SW) can be
determined as:
2
R SNUB = ------------------------------------------------π × F ring × C SNUB
QG(SW) = QGD + QGS - QTH where QTH is the gate charge
required to get the MOSFET to its threshold (VTH).
d) Calculate the power dissipated in the snubber resistor as
shown in the following equation:
Note that for the high-side MOSFET, VDS equals VIN, which can
be as high as 20V in a typical portable application. Also include
the power delivered to the MOSFET's (PGATE) in calculating the
power dissipation required for the FAN5069.
2
P R ( SNUB ) = C SNUB × V IN ( MAX ) × F SW
(EQ. 17)
Where, VIN(MAX) is the maximum input voltage and FSW is the
converter switching frequency.
PGATE is determined by the following equation:
P Gate = Q G × V CC × F SW
(EQ. 16)
The snubber resistor chosen should be adequately de-rated to
handle the worst-case power dissipation. Do not use wire
wound resistors for RSNUB.
(EQ. 13)
where QG is the total gate charge to reach VCC.
Low-Side Losses
Q2, however, switches on or off with its parallel schottky diode
simultaneously conducting. Hence, the VDS ≈ 0.5V. Since PSW
is proportional to VDS, Q2's switching losses are negligible and
we can select Q2 based on RDS(ON) alone.
Conduction losses for Q2 are given by the following equation:
2
P COND = ( 1 – D ) × I OUT × R DS ( ON )
(EQ. 14)
where RDS(ON) is the RDS(ON) of the MOSFET at the highest
operating junction temperature and D=VOUT/VIN is the minimum
duty cycle for the converter.
Since DMIN < 20% for portable computers, (1-D) ≈ 1 produces a
conservative result, further simplifying the calculation.
The maximum power dissipation (PD(MAX)) is a function of the
maximum allowable die temperature of the low-side MOSFET,
the θJA, and the maximum allowable ambient temperature rise.
PD(MAX) is calculated using the following equation:
T J ( MAX ) – T A ( MAX )
P D ( MAX ) = ---------------------------------------------------θ JA
(EQ. 15)
θJA depends primarily on the amount of PCB area that is
devoted to heat sinking.
FAN5069 Rev. 1.1.0
14
www.fairchildsemi.com
FAN5069 PWM and LDO Controller Combo
Selection of MOSFET Snubber Circuit
MOSFET. RDS(ON) is at the maximum junction temperature (TJ).
tS is the switching period (rise or fall time) and equals t2+t3 (Figure 22.).
FAN5069 PWM and LDO Controller Combo
VIN
VIN
Current
Sense
Amplifier
RRAMP
Ramp
Generator
Summing
Σ
Q1
L
PWM
&
DRIVER
RDC
VOUT
C
Q2
Amplifier
RL
RES
C2
C1
R2
C3
RBIAS
R3
R1
Reference
Figure 24. Closed Loop System with Type 3 Network
Loop Compensation
R L = load resistance
Typically, the closed loop crossover frequency (Fcross) where the
overall gain is unity, should be selected to achieve optimal transient and steady state response to disturbances in line and load
conditions. It is recommended to keep Fcross, below 1/5th of the
switching frequency of the converter. Higher phase margin
tends to have a more stable system with more sluggish
response to load transients. Optimum phase margin is about
60°, a good compromise between steady state and transient
responses. A typical design should address variations over a
wide range of load conditions and over a large sample of
devices.
T s = Switching Period
V i = input voltage
F SW = switching frequency
Equations:
Effective current sense resistance = R i = 7 × R DSON
R
Ri
Current modulator DC gain = M i = ------L
FAN5069 has a high gain error amplifier around which the loop
is closed. Figure 24 shows a type 3 compensation network. For
type 2 compensation, R3 and C3 are not used. Since the
FAN5069 architecture employs summing current mode, type 2
compensation can be used for most applications. For type 2
compensation networks, refer to the following reference for further information:
(EQ. 18)
(EQ. 19)
Effective ramp amplitude =
V m = 2.34 × 10
■ Venable, H. Dean, "The K factor: A new mathematical tool for
stability analysis and synthesis", Proceedings of Powercon,
March 1983.
10
( V i – 0.8 ) × T s
× -----------------------------------R ramp
(EQ. 20)
Voltage modulator DC gain = M v = -------i
V
Vm
(EQ. 21)
M ×M
Mv + Mi
(EQ. 22)
v
i
Plant DC gain = M o = M v || M i = -------------------
For critical applications requiring wide loop bandwidth using
very low ESR output capacitors, use type 3 compensation.
πSampling gain natural frequency = ω n = ----Ts
(EQ. 23)
Type 3 Feedback Component Calculations
M
Mv
Use the following steps to calculate feedback components:
Notation:
C 0 = net output filter capacitance
G p ( s ) = net gain of plant = control-to-output transfer function
M ×R
ωn × Qz
v
-i ⎞
Effective inductance = L e = -------O- × ⎛⎝ L + ------------------⎠
(EQ. 24)
Mv × Ri × RL
R p = -------------------------------- = ( M v × R i ) || R L
Mv × Ri + RL
(EQ. 25)
L = inductor value
R DSON = on-state Drain-to Source resistance of Low-side MOSFET
R es = net ESR of the output filter capacitors
FAN5069 Rev. 1.1.0
15
www.fairchildsemi.com
K
R2 = --------------------------------------------------2 × π × F cross × C2
1
Plant zero frequency = fz = ----------------------------------------2 × π × C o × R es
(EQ. 26)
1
Plant 1st pole frequency = f p1 = ---------------------------------------------------------
(EQ. 27)
Le
2 × π × ⎛ C o × R p + ------⎞
⎝
R L⎠
Plant 2nd pole frequency = f p2
R
1
1
= ------------ × ⎛ -------------------- + ------p⎞
2 × π ⎝ Co × RL Le ⎠
R1
R3 = -----------------(K – 1)
The switching power converter layout needs careful attention
and is critical to achieving low losses and clean and stable operation. Below are specific recommendations for a good board
layout:
(EQ. 28)
■ Keep the high current traces and load connections as short
as possible.
(EQ. 29)
■ Use thick copper boards whenever possible to achieve higher
efficiency.
Plant gain (magnitude) response:
■ Keep the loop area between the SW node, low-side MOSFET, inductor and the output capacitor as small as possible.
f 2
1 + ⎛ ----⎞
⎝ f z⎠
G p (f) = 20 × log M 0 + 10 × log ------------------------------------------------------------------------------------------------------f 2
f 2
f 2
1 + ⎛⎝ ------⎞⎠ × 1 + ⎛⎝ ------⎞⎠ × 1 + ⎛⎝ ------⎞⎠
f p2
f p3
f p1
■ Route high dV/dt signals such as SW node away from the
error amplifier input/output pins. Keep components connected to these pins close to the pins.
(EQ. 30)
■ Place ceramic de-coupling capacitors very close to VCC pin.
(EQ. 31)
■ All input signals are referenced with respect to AGND pin.
Dedicate one layer of the PCB for a GND plane. Use at least
4 layers for the PCB.
Plant phase response:
–1 f
–1 f
–1 f
–1 f
∠G P (f) = tan ⎛ ----⎞ – tan ⎛ ------⎞ – tan ⎛ ------⎞ – – tan ⎛ ------⎞
⎝ f z⎠
⎝ f p1⎠
⎝ f p2⎠
⎝ f p3⎠
(EQ. 39)
Layout Considerations
2
ω ×L
2 × π × Rp
n
e
Plant 3rd pole frequency = f p3 = -------------------------
(EQ. 38)
■ Minimize GND loops in the layout to avoid EMI related
issues.
Choose R1, RBIAS to set the output voltage using EQ.5. Choose
the zero cross over frequency Fcross of the overall loop. Typically
Fcross should be less than 1/5th of Fsw. Choose the desired
phase margin. Typically this number should be between 60° to
90°.
■ Use wide traces for the lower gate drive to keep the drive
impedances low.
Calculate plant gain at Fcross using EQ.28 by substituting Fcross
in place of f. The gain that the amplifier needs to provide to get
the required cross over is given by
■ Use snubber circuits to minimize high frequency ringing at
the SW nodes.
1
G AMP = ---------------------------------G p (F cross )
■ Connect PGND directly to the lower MOSFET source pin.
■ Use wide land areas with appropriate thermal vias to effectively remove heat from the MOSFET’s.
■ Place the output capacitor for the LDO close to the source of
the LDO MOSFET.
(EQ. 32)
The phase boost required is calculated as given in (EQ. 33).
Phase Boost = M – P – 90°
(EQ. 33)
Where, M is the desired phase margin in degrees and P is the
modulator phase shift in degrees at the time of crossover.
The feedback component values are now calculated as given in
equations below:
2
⎧
⎫
Boost
K = ⎨ Tan ⎛⎝ -----------------⎞⎠ + 45 ⎬
4
⎩
⎭
(EQ. 34)
1
C1 = -------------------------------------------------------------------------2 × π × F cross × G AMP × R1
(EQ. 35)
C2 = C1 × ( K – 1 )
(EQ. 36)
1
C3 = ----------------------------------------------------------------2 × π × F cross × K × R3
(EQ. 37)
FAN5069 Rev. 1.1.0
16
www.fairchildsemi.com
FAN5069 PWM and LDO Controller Combo
Poles and Zeros of Plant Transfer Function:
+5V or +12V
Vcc
J1
R9
200
15
J7
16
R8
C4
0.1uF
J6
C17
+
VCC
3-24V
14
R(RAMP)
R6
1
5K
GLDO
HDRV
FBLDO
BOOT
R4
2
50K
GND
R5
3
243K
R(T)
10
4
SS
FDD6606
13
7
C9
FDD6606
PGND
EN
5
COMP
0.01uF
8
AGND
6
FB
820uF
J3
GND
Q3
1.8uH
Q4
C12
R2
R3
12.7k
825
C2
220pF
C13
+
C14
+
560uF 560uF 560uF
C16
3.3nF
C1
1500pF
J4
SW_Out
R11
2.2
12
0.1uF
TP2
820uF
L1
9
LDRV
VIN
C11 +
PWM OUT
C8
0.22uF
TP1
C5
+
11
SW
ILIM
C10
C6
Q2 0.1uF
R7 10K
560uF
J2
453K
FDD6296
Q1
FDD6530A
LDO
LDO_Out
U1
C7
0.22uF
PWM OUT
+ C15
0.1uF
J5
GND
C3
3300pF
R1
5.11K
R10
FAN5069
5.83K
Figure 25. Application Board Schematic
Bill of Materials
Part Description
Capacitor, 1500pF, 20%, 25V , 0603,X7R
Quantity
1
Designator
C1
Vendor
Panasonic
Vendor Part Number
PCC1774CT-ND
Capacitor, 220pF, 5%, 50V , 0603,NPO
1
C2
Panasonic
PCC221ACVCT-ND
Capacitor, 3300pF, 10%, 50V , 0603,X7R
1
C3
Panasonic
PCC1778CT-ND
Capacitor, 0.1uF, 10%, 25V , 0603,X7R
4
C4, C5, C6, C15
Panasonic
PCC2277CT-ND
Capacitor, 0.22uF, 20%, 25V , 0603,X7R
2
C7, C8
Panasonic
PCC1767CT-ND
Capacitor, 0.01uF, 10%, 50V , 0603,X7R
1
C9
Panasonic
PCC1784CT-ND
Capacitor, 820uF, 20%, 10X20, 25V ,20mOhm,1.96A
2
C10, C11
Nippon-Chemicon
KZH25VB820MHJ20
PSC2.5VB820MH08
Capacitor, 820uF, 20%, 8X8, 2.5V ,7mOhm,6.1A
1
C17
Nippon-Chemicon
Capacitor, 560uF, 20%, 8X11.5, 4V ,7mOhm,5.58A
3
C12, C13, C14,
Nippon-Chemicon
PSA4VB560MH11
Capacitor, 3300pF, 10%, 50V , 0603,X7R
1
C16
Panasonic
PCC332BNCT-ND
Connector Header 0.100 V ertical, Tin - 2 Pin
1
J1
Molex
W M6436-ND
Terminal Quickf it Male .052"Dia.187" Tab
6
J2 - J7
Keystone
1212K-ND
Inductor, 1.8uH, 20%, 26A mps Max, 3.24mOhm
1
L1
Inter-Technical
SC5018-1R8M
MOSFET N-CH, 32 mOhm, 20V , 21A , D-PA K, FSID: FDD6530A
1
Q1
Fairchild Semiconductor
FDD6530A
MOSFET N-CH, 8.8 mOhm, 30V , 50A , D-PA K, FSID: FDD6296
1
Q2
Fairchild Semiconductor
FDD6296
MOSFET N-CH, 6 mOhm, 30V , 75A , D-PA K, FSID: FDD6606
2
Q3, Q4
Fairchild Semiconductor
FDD6606
Resistor , 5.11K , 1% , 1/16W
1
R1
Panasonic
P5.11KHCT-ND
Resistor , 12.7K , 1% , 1/16W
1
R2
Panasonic
P12.7KHCT-ND
Resistor , 825 , 1% , 1/16W
1
R3
Panasonic
P825HCT-ND
Resistor , 49.9KK , 1% , 1/16W
1
R4
Panasonic
P49.9KHCT-ND
Resistor , 243K , 1% , 1/16W
1
R5
Panasonic
P243KHCT-ND
Resistor ,453K , 1% , 1/16W
1
R6
Panasonic
P453KHCT-ND
Resistor ,10K , 1% , 1/16W
1
R7
Panasonic
P10.0KHCT-ND
Resistor , 4.99K , 1% , 1/16W
1
R8
Panasonic
P4.99KHCT-ND
Resistor , 200 , 1% , 1/8W
1
R9
Panasonic
P200FCT-ND
Resistor , 5.90K , 1% , 1/16W
1
R10
Panasonic
P5.90KHCT-ND
Resistor , 2.2 , 1% , 1/8W
1
R11
Panasonic
P2.2ECT-ND
Connector Header 0.100 V ertical, Tin - 1 Pin
3
TP1,TP2, Vcc
Molex
W M6436-ND
IC, System Regulator, TSSOP16, FSID: FA N5069
1
U1
Fairchild Semiconductor
FAIRCHILD
FAN5069 Rev. 1.1.0
17
www.fairchildsemi.com
FAN5069 PWM and LDO Controller Combo
Application Board Schematic ( VIN = 3 to 24V; VOUT =1.5V @20A)
FAN5069 PWM and LDO Controller Combo
Typical Application Board Layout
Figure 26. Assembly Diagram
Figure 29. Mid Layer 2
Figure 27. Top Layer
Figure 30. Bottom Layer
Figure 28. Mid Layer 1
FAN5069 Rev. 1.1.0
18
www.fairchildsemi.com
16-Lead TSSOP
7.72 TYP
4.16 TYP.
DIMENSIONS METRIC ONLY
16
5.0 ± 0.1
-A-
(1.78 TYP)
0.42 TYP
0.65 TYP
LAND PATTERN RECOMMENDATION
8
6.4
GAGE PLANE
4.4 ± 0.1
-B-
0.25
3.2
0°−8°
1
8
PIN #1 IDENT.
0.2 C B A
ALL LEAD TIPS
SEATING PLANE
0.6 ± 0.1
DETAIL A
TYPICAL, SCALE: 40X
SEE DETAIL A
(0.90)
0.1 C
ALL LEAD TIPS
-C-
1.1 MAX TYP
0.65 TYP
0.10±0.05 TYP
(0.19−0.30 TYP)
(0.09−0.20 TYP)
0.13 M A B S C S
FAN5069 Rev. 1.1.0
19
www.fairchildsemi.com
FAN5069 PWM and LDO Controller Combo
Mechanical Dimensions
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not intended to be an exhaustive list of all such trademarks.
ACEx™
FACT Quiet Series™
ActiveArray™
FAST®
Bottomless™
FASTr™
CoolFET™
FPS™
CROSSVOLT™ FRFET™
DOME™
GlobalOptoisolator™
EcoSPARK™ GTO™
E2CMOSTM
HiSeC™
EnSignaTM
I2C™
FACT™
ImpliedDisconnect™
Across the board. Around the world.™
The Power Franchise™
Programmable Active Droop™
ISOPLANAR™
LittleFET™
MICROCOUPLER™
MicroFET™
MicroPak™
MICROWIRE™
MSX™
MSXPro™
OCX™
OCXPro™
OPTOLOGIC®
OPTOPLANAR™
PACMAN™
POP™
Power247™
PowerTrench®
QFET®
QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
RapidConnect™
SILENT SWITCHER®
SMART START™
SPM™
Stealth™
SuperFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic®
TINYOPTO™
TruTranslation™
UHC™
UltraFET®
VCX™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY
ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT
CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
2. A critical component is any component of a life
1. Life support devices or systems are devices or
support device or system whose failure to perform can
systems which, (a) are intended for surgical implant into
be reasonably expected to cause the failure of the life
the body, or (b) support or sustain life, or (c) whose
support device or system, or to affect its safety or
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. I7
FAN5069 Rev. 1.1.0
20
www.fairchildsemi.com
FAN5069 PWM and LDO Controller Combo
TRADEMARKS