Allegro A1386 5 v field-programmable linear hall effect sensor ic with 3 v supply functionality, analog output, and miniature package option Datasheet

A1386
5 V Field-Programmable Linear Hall Effect Sensor IC
with 3 V Supply Functionality, Analog Output, and Miniature Package Options
Features and Benefits
Description
• Low power consumption using 3 V supply
• Factory programmed sensitivity temperature coefficient
(0.13%/°C nominal)
• Programmability at end-of-line
• Ratiometric sensitivity, quiescent voltage output, and
clamps for interfacing with application DAC
• Temperature-stable quiescent voltage output and sensitivity
• Precise recoverability after temperature cycling
• Output voltage clamps provide short circuit diagnostic
capabilities
• Wide ambient temperature range: –40°C to 150°C
• Resistant to mechanical stress
• Miniature package options
The Allegro® A1386 programmable, linear, Hall effect sensor
IC is designed for low power, high accuracy, and small package
size applications. The accuracy of this device is enhanced via
programmability on the output pin for end-of-line optimization
without the added complexity and cost of a fully programmable
device.
The A1386 has two operating modes, normal and low power.
In normal operation mode the A1386 operates much like its
predecessors, the A1381, A1382, A1383, and A1384, as a highly
accurate, user-programmable linear sensor IC with a ratiometric
output. In low power mode, the device actually disengages some
internal components in order to reduce power consumption.
Although the accuracy of the device is substantially reduced
during low power operation, it remains effective as a detector
of magnetic regions (such as north and south poles on a rotating
ring magnet). This unique feature allows the device to be used
in systems that are put to sleep, during which time there may
be only 3 V available, or in applications that have start-up
conditions where the available supply voltage may drop below
4.5 V for a period of time.
This ratiometric Hall effect device provides a voltage output
that is proportional to the applied magnetic field over the entire
Packages
3-pin ultramini SIP
1.5 mm × 4 mm × 3 mm
(suffix UA)
Continued on the next page…
Approximate scale
Functional Block Diagram
V+
VCC
Amp
To all subcircuits
Filter
Dynamic Offset
Cancellation
CBYPASS
Chip Reference
Currents
Out
Hall Drive Circuit
Gain
Gain Temperature
Coefficient
Trim Control
GND
A1386-DS, Rev. 3
Offset
VOUT
5 V Field-Programmable Linear Hall Effect Sensor IC with 3 V Supply
Functionality Analog Output, and Miniature Package Options
A1386
Description (continued)
2.7 to 5.5 V supply operating region. Both the quiescent voltage
output and magnetic sensitivity are user adjustable. The quiescent
voltage output can be set to approximately 50% of the supply voltage,
and the sensitivity adjusted between 1.90 and 3.50 mV/G for VCC
= 5 V. The sensitivity temperature coefficient is programmed at the
factory, at 0.13%/°C nominal, to compensate for Neodymium-style
magnets. The features of this linear device make it ideal for the high
accuracy requirements of automotive and industrial applications.
Performance is guaranteed over an extended temperature range,
–40°C to 150°C.
Each device contains a BiCMOS monolithic circuit that integrates
a Hall element, temperature-compensating circuitry to reduce the
intrinsic sensitivity drift of the Hall element, a small-signal high-gain
amplifier, a clamped low-impedance output stage, and a proprietary
dynamic offset cancellation technique.
The A1386 device is provided in a 3-pin ultramini single-in-line
package (UA suffix), and a 3-pin surface mount SOT-23W package
(LH suffix). Both packages are lead (Pb) free, with 100% matte tin
leadframe plating.
Selection Guide
Part Number
Package
TA
(°C)
Surface mount
Through hole
–40 to 150
Packing*
A1386LLHLT-T
Tape and reel, 3000 pieces/reel
A1386LUA-T
Bulk bag, 500 pieces/bag
*Contact Allegro for additional packing options.
Absolute Maximum Ratings
Characteristic
Symbol
Notes
Rating
Units
Forward Supply Voltage
VCC
8
V
Reverse Supply Voltage
VRCC
–0.1
V
Forward Output Voltage
VOUT
28
V
Reverse Output Voltage
VROUT
–0.1
V
Output Source Current
IOUT(SOURCE)
VOUT to GND
8
mA
IOUT(SINK)
VCC to VOUT
2
mA
Output Sink Current
Operating Ambient Temperature
TA
–40 to 150
ºC
Storage Temperature
Tstg
–65 to 165
ºC
TJ(max)
165
ºC
Maximum Junction Temperature
Range L
Pin-out Diagrams
LH Package
UA Package
3
1
Terminal List Table
Number
2
1
2
3
LH
UA
1
1
3
2
Name
Description
VCC
Input power supply; use bypass capacitor to connect to ground
2
GND
Ground
3
VOUT
Output signal
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A1386
5 V Field-Programmable Linear Hall Effect Sensor IC with 3 V Supply
Functionality Analog Output, and Miniature Package Options
OPERATING CHARACTERISTICS, valid over full operating temperature range, TA; CBYPASS= 0.1 μF, unless otherwise specified
Characteristic
Min.
Typ.
Max.
Units1
VCC(NORM)
4.5
–
5.5
V
VCC(LOWPWR)
2.8
–
3.2
V
Symbol
Test Conditions
Electrical Characteristics
Supply Voltage
Supply Voltage Turn On Time
Operation Mode Threshold
Voltage2
tVCC
VTHRESH
Supply Zener Clamp Voltage
VZ
Supply Current
ICC
Power-On
Time2
Internal Bandwidth
Chopping
Frequency3
tPO
BWi
fC
–
–
10
ms
VCC(LOWPWR) → VCC(NORM)
–
4.1
–
V
VCC(NORM) → VCC(LOWPWR)
–
3.7
–
V
TA = 25°C, ICC = 11 mA
6
8.3
–
V
VCC = VCC(NORM) , RL(PULLDWN) = 10 kΩ
–
6.4
8
mA
VCC = VCC(LOWPWR) , RL(PULLDWN) = 10 kΩ
–
–
4
mA
VCC = VCC(NORM), TA = 25°C, CBYPASS = open,
CL (of test probe) = 4.7 nF
–
30
–
μs
VCC = VCC(LOWPWR), TA = 25°C, CBYPASS = open,
CL (of test probe) = 4.7 nF
–
50
–
μs
Small signal –3 dB, 100 G(p-p), magnetic input signal
–
20
–
kHz
TA = 25°C
–
200
–
kHz
VCC = 5 V, TA = 25°C, B = 750 G,
Sens = 3.3 mV/G, RL(PULLDWN) = 10 kΩ
4.39
4.5
4.58
V
VCC = 3 V, TA = 25°C, B = 750 G,
Sens = 3.3 mV/G, RL(PULLDWN) = 10 kΩ
2.62
2.7
2.78
V
VCC = 5 V, TA = 25°C, B = –750 G,
Sens = 3.3 mV/G, RL(PULLDWN) = 10 kΩ
0.39
0.5
0.58
V
VCC = 3 V, TA = 25°C, B = –750 G,
Sens = 3.3 mV/G, RL(PULLDWN) = 10 kΩ
0.19
0.3
0.37
V
VCC = VCC(NORM), TA = 25°C, CL = 4.7 nF,
Sens = 3.3 mV/G, no external filter
–
18
–
mV
VCC = VCC(LOWPWR), TA = 25°C, CL = 4.7 nF,
Sens = 1.75 mV/G, no external filter
–
18
–
mV
Output Characteristics
VCLP(HIGH)
VOUT Voltage
Clamp4
VCLP(LOW)
VOUT Noise (peak to peak)
VOUT DC Output Resistance
VOUT Load Capacitance
VOUT Load Resistance
VOUT Output Slew Rate
VN(p-p)
–
<1
–
Ω
CL
VOUT to GND
–
–
4.7
nF
RL(PULLDWN)
VOUT to GND
10
–
–
kΩ
VCC = VCC(NORM), CL = 4.7 nF
–
140
–
V/ms
VCC = VCC(LOWPWR), CL = 4.7 nF
–
50
–
V/ms
ROUT
SR
Continued on the next page...
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A1386
5 V Field-Programmable Linear Hall Effect Sensor IC with 3 V Supply
Functionality Analog Output, and Miniature Package Options
OPERATING CHARACTERISTICS (continued), valid over full operating temperature range, TA; CBYPASS= 0.1 μF, unless otherwise specified
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Units1
Pre-Programming Targets
Pre-Programming Quiescent
Voltage Output
VOUT(Q)PRE
Pre-Programming Sensitivity
SensPRE
VCC = 3 V, B = 0 G, TA = 25°C
1.34
–
1.53
V
VCC = 5 V, B = 0 G, TA = 25°C
–
2.5
–
V
VCC = 3 V, TA = 25°C
–
–
1.14
mV/G
VCC = 5 V, TA = 25°C
–
1.4
–
mV/G
2.4
–
2.6
V
–
5
–
bit
Quiescent Voltage Output Programming
Guaranteed Quiescent Voltage
Output Range4,5.6
VOUT(Q)
VCC = 5 V, B = 0 G, TA = 25°C
Quiescent Voltage Output
Programming Bits
Average Quiescent Voltage
Output Step Size7,8
StepVOUT(Q)
VCC = 5 V
12
16
18
mV
Quiescent Voltage Output
Programming Resolution9
ErrPGVOUT(Q)
VCC = 5 V
–
StepVOUT(Q)
× ±0.5
–
mV
–
3.3
mV/G
Sensitivity Programming
Guaranteed Sensitivity
Range 4,5,10
Sens
VCC = 5 V, TA = 25°C
1.9
–
6
–
bit
Average Sensitivity Step Size7,8
StepSENS
VCC = 5 V, TA = 25°C
30
40
50
μV/G
Sensitivity Programming
Resolution9
ErrPGSENS
VCC = 5 V, TA = 25°C
–
StepSENS
× ±0.5
–
mV/G
–
1
–
bit
–
0.13
–
%/°C
0.10
–
0.16
%/°C
VCC = VCC(NORM)
–
±1.5
–
%
VCC = VCC(LOWPWR)
–
±2
–
%
VCC = VCC(NORM)
–
±1.5
–
%
VCC = VCC(LOWPWR)
–
±2
–
%
VCC = VCC(NORM)
–
±1.5
–
%
VCC = VCC(LOWPWR)
–
±2.5
–
%
Sensitivity Programming Bits
Lock Bit Programming
Overall Programming Lock Bit
LOCK
Factory Programmed Sensitivity Temperature Coefficient
Factory Programmed Sensitivity
Temperature Coefficient Target
TCSENS(TGT)
Factory Programmed Sensitivity
Temperature Coefficient Range11
TCSENS
VCC = 5 V, TA = 150°C
Error Components
Linearity Sensitivity Error2
Symmetry Sensitivity Error2
LinERR
SymERR
Ratiometry Quiescent Voltage
Output Error2,12
RatERRVOUT(Q)
Ratiometry Sensitivity Error2,13
RatERRSENS
Ratiometry Clamp Error2,13
RatERRCLP
VCC = VCC(NORM)
–
±1.5
–
%
VCC = VCC(LOWPWR)
–
±2.5
–
%
VCC = VCC(NORM) , TA = 25°C
–
±1.5
–
%
VCC = VCC(LOWPWR) , TA = 25°C
–
±2.5
–
%
Continued on the next page...
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A1386
5 V Field-Programmable Linear Hall Effect Sensor IC with 3 V Supply
Functionality Analog Output, and Miniature Package Options
OPERATING CHARACTERISTICS (continued), valid over full operating temperature range, TA; CBYPASS= 0.1 μF, unless otherwise specified
Characteristic
Min.
Typ.
Max.
Units1
VCC = VCC(NORM), Sens = 3.3 mV/G, TA = 25°C to 150°C
–
–
±35
mV
VCC = VCC(LOWPWR), Sens = 1.75 mV/G, TA = 25°C to 150°C
–
±35
–
mV
VCC = VCC(NORM)
–
±3
–
%
VCC = VCC(LOWPWR)
–
±5
–
%
TA = 25°C; after temperature cycling
–
±2
–
%
Symbol
Test Conditions
Drift Characteristics
Quiescent Voltage Output Drift
Through Temperature Range2
∆VOUT(Q)
Maximum Sensitivity Drift
Through Temperature Range14,15
∆SensTC
Sensitivity Drift Due to Package
Hysteresis2,15
∆SensPKG
11G
(gauss) = 0.1 mT (millitesla).
Characteristic Definitions section.
3f varies up to approximately ± 20% over the full operating ambient temperature range, T , and process.
C
A
4Sens, V
OUT(Q), VCLP(LOW) , and VCLP(HIGH) scale with VCC due to ratiometry.
5For optimal device accuracy in the V
CC(NORM) operating range, the device should be programmed with VCC = 5 V.
6V
OUT(Q)(max) is the value available with all programming fuses blown (maximum programming code set). The VOUT(Q) range is the total range from
VOUT(Q)init up to and including VOUT(Q)(max). See Characteristic Definitions section.
7Step size is larger than required, to account for manufacturing spread. See Characteristic Definitions section.
8Non-ideal behavior in the programming DAC can cause the step size at each significant bit rollover code to be greater than twice the maximum
specified value of StepVOUT(Q) or StepSENS.
9Overall programming value accuracy. See Characteristic Definitions section.
10Sens(max) is the value available with all programming fuses blown (maximum programming code set). Sens range is the total range from Sens
init up
to and including Sens(max). See Characteristic Definitions section.
11Factory programmed at 150°C and calculated relative to 25°C.
12Percent change from actual value at V
CC = 3 V or VCC = 5 V, for a given temperature, over the guaranteed supply voltage operating range.
13Percent change from actual value at V
CC = 3 V or VCC = 5 V, with TA = 25°C, over the guaranteed supply voltage operating range.
14Sensitivity drift from expected value of V
OUT at TA , after programming TCSENS. See Characteristic Definitions section.
15Guaranteed by design only. Parameter is not tested in production flow.
2See
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
A1386
5 V Field-Programmable Linear Hall Effect Sensor IC with 3 V Supply
Functionality Analog Output, and Miniature Package Options
THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information
Characteristic
Symbol
RθJA
Package Thermal Resistance
Test Conditions*
Value Units
Package LH, 1-layer PCB with copper limited to solder pads
228
ºC/W
Package LH, 2-layer PCB with 0.463 in.2 of copper area each side
connected by thermal vias
110
ºC/W
Package UA, 1-layer PCB with copper limited to solder pads
165
ºC/W
*Additional thermal information available on Allegro website.
Power Derating Curve
6
Maximum Allowable VCC (V)
VCC(max)
5
1-layer PCB, Package LH
(RQJA = 228 ºC/W)
1-layer PCB, Package UA
(RQJA = 165 ºC/W)
2-layer PCB, Package LH
(RQJA = 110 ºC/W)
4
3
VCC(min)
2
1
0
20
40
60
80
100
120
140
160
180
Temperature (ºC)
Power Dissipation, PD (mW)
Power Dissipation versus Ambient Temperature
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
2l
(R aye
rP
QJ
C
A =
11 B, P
0 º ac
1-la
C/ ka
W
(R yer PC
) ge L
QJA =
B, P
H
165
ack
ºC/
a
W) ge U
A
1-lay
er P
(R
CB,
QJA =
228 Packag
ºC/W
e LH
)
20
40
60
80
100
120
Temperature (°C)
140
160
180
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
A1386
5 V Field-Programmable Linear Hall Effect Sensor IC with 3 V Supply
Functionality Analog Output, and Miniature Package Options
Characteristic Definitions
Supply Voltage Turn On Time To ensure that the internal compo-
nents of the A1386 device are initialized to their proper values,
the supply voltage, VCC, must be powered up within a specified
time interval. Supply Voltage Turn On Time, tVCC, is defined as
the time it takes for the supply voltage to transition from 10% to
90% of its steady state value.
Operating Mode Threshold The A1386 has two modes of
operation, Normal and Low Power. In Low Power mode, certain
components of the device are disengaged to limit the current consumption of the device. As a result, the overall device accuracy is
limited. In Normal mode, all components are fully functional.
The VCC supply level is used by the device to determine the mode
of operation. The threshold voltage, VTHRESH , is the VCC threshold voltage required to switch from Low Power operation to
Normal operation (VCC(LOWPWR) → VCC(NORM)) or from Normal
operation to Low Power operation (VCC(NORM) → VCC(LOWPWR)).
A region of hysteresis exists between the Normal VCC operational range and the Low Power VCC operational range, as shown
in figure 1. At the initial power up, the device remains in the
Low Power operating mode until reaching the VCC(LOWPWR) →
VCC(NORM) VTHRESH voltage.
Power-On Time When the supply is ramped to its operating volt-
age, the device requires a finite time to power its internal components before responding to an input magnetic field. Power-On
Time, tPO , is defined as: the time it takes for the output voltage
to settle within ±10% of its steady state value under an applied
magnetic field, after the power supply has reached its minimum
specified operating voltage, VCC(min), as shown in figure 2.
Quiescent Voltage Output In the quiescent state (no significant
magnetic field: B = 0 G), the output, VOUT(Q), has a constant
ratio to the supply voltage, VCC , throughout the entire operating
ranges of VCC and ambient temperature, TA.
Guaranteed Quiescent Voltage Output Range The quiescent
voltage output, VOUT(Q), can be programmed around its nominal
value of 2.5 V, within the guaranteed quiescent voltage range limits, VOUT(Q)(min) and VOUT(Q)(max). The available guaranteed
Initial power-up operating mode
V
VCC
VCC(typ.)
Normal
Switch to
Normal Mode
VCC(LOWPWR) m
VCC(NORM)
Low Power
Switch to
Low Power Mode
VCC(NORM) m
VCC(LOWPWR)
Operating Mode
VOUT
90% VOUT
VCC(min.)
tPO
t1
t2
t1= time at which power supply reaches
minimum specified operating voltage
t2= time at which output voltage settles
within ±10% of its steady state value
under an applied magnetic field
0
2.7
VTHRESH
+t
5.5
VCC (V)
Figure 1. Operating Mode relationship to VCC, with VCC shown over the
full operating range
Power-On Time
Figure 2. VCC and VOUT during power-on time interval
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
5 V Field-Programmable Linear Hall Effect Sensor IC with 3 V Supply
Functionality Analog Output, and Miniature Package Options
A1386
programming range for VOUT(Q) falls within the distributions of
the initial, VOUT(Q)init, and the maximum programming code for
setting VOUT(Q), as shown in figure 3.
Average Quiescent Voltage Output Step Size The average qui-
escent voltage output step size for a single device is determined
using the following calculation:
VOUT(Q)maxcode –VOUT(Q)init
.
StepVOUT(Q) =
(1)
2n–1
where:
n is the number of available programming bits in the trim range,
2n–1 is the value of the maximum programming code in the
range, and
VOUT(Q)maxcode is the quiescent voltage output at code 2n–1.
Quiescent Voltage Output Programming Resolution The
programming resolution for any device is half of its programming
step size. Therefore, the typical programming resolution will be:
ErrPGVOUT(Q)(typ) = 0.5 × StepVOUT(Q)(typ)
.
(2)
Quiescent Voltage Output Drift Through Temperature Range
Due to internal component tolerances and thermal considerations,
the quiescent voltage output, VOUT(Q), may drift from its nominal
value over the operating ambient temperature, TA. For purposes
of specification, the Quiescent Voltage Output Drift Through
Temperature Range, ∆VOUT(Q) (mV), is defined as:
∆VOUT(Q) = VOUT(Q)(TA) –VOUT(Q)(25°C)
.
(3)
VOUT(Q) should be calculated using the actual measured values
of VOUT(Q)(TA) and VOUT(Q)(25°C) , rather than programming target
values.
Sensitivity The presence of a south polarity magnetic field, per-
pendicular to the branded surface of the package face, increases
the output voltage from its quiescent value toward the supply
voltage rail. The amount of the output voltage increase is proportional to the magnitude of the magnetic field applied. Conversely,
the application of a north polarity field decreases the output
voltage from its quiescent value. This proportionality is specified
as the magnetic sensitivity, Sens (mV/G), of the device, and it is
defined as:
Sens =
VOUT(BPOS) – VOUT(BNEG)
BPOS – BNEG
(4)
,
where BPOS and BNEG are two magnetic fields with opposite
polarities.
Sensitivity Temperature Coefficient Device sensitivity changes
as temperature changes, with respect to its programmed sensitivity temperature coefficient, TCSENS. TCSENS is programmed at
150°C, and calculated relative to the nominal sensitivity programming temperature of 25°C. TCSENS (%/°C) is defined as:
⎛SensT2 – SensT1
⎞⎛ 1 ⎞
(5)
⎟⎟ ,
TCSens = ⎜⎜
100%⎟⎟ ⎜⎜
×
Sens
T2–T1
T1
⎝
⎠⎝
⎠
where T1 is the nominal Sens programming temperature of 25°C,
and T2 is the TCSENS programming temperature of 150°C. The
expected value of Sens over the full ambient temperature range,
SensEXPECTED(TA), is defined as:
SensEXPECTED(TA) = SensT1 [100% + TCSENS (TA –T1)]
. (6)
SensEXPECTED(TA) should be calculated using the actual measured
values of SensT1 and TCSENS rather than programming target
values.
Sensitivity Drift Through Temperature Range Second order
VOUT(Q)init(typ)
Guaranteed Output
Programming
Range, VOUT(Q)
Distribution for
VOUT(Q)init
Distribution for
Max Code VOUT(Q)
VOUT(Q)(min)
VOUT(Q)(max)
Figure 3. Relationship of the guaranteed quiescent output voltage and
overall VOUT(Q) values.
sensitivity temperature coefficient effects cause the magnetic sensitivity, Sens, to drift from its expected value over the operating
ambient temperature range, TA. For purposes of specification, the
sensitivity drift through temperature range, ∆SensTC, is defined as:
SensTA – SensEXPECTED(TA)
∆SensTC =
× 100% . (7)
SensEXPECTED(TA)
Sensitivity Drift Due to Package Hysteresis Package stress and
relaxation can cause the device sensitivity at TA = 25°C to change
during and after temperature cycling.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
A1386
5 V Field-Programmable Linear Hall Effect Sensor IC with 3 V Supply
Functionality Analog Output, and Miniature Package Options
For purposes of specification, the sensitivity drift due to package
hysteresis, ∆SensPKG, is defined as:
Sens(25°C)2 – Sens(25°C)1
∆SensPKG =
× 100%
Sens(25°C)1
,
(8)
where Sens(25°C)1 is the programmed value of sensitivity
at TA = 25°C, and Sens(25°C)2 is the value of sensitivity at
TA = 25°C, but after temperature cycling TA up to 150°C, down to
–40°C, and back to up 25°C.
Linearity Sensitivity Error The A1386 is designed to provide
a linear output in response to a ramping applied magnetic field.
Consider two magnetic fields, B1 and B2. Ideally, the sensitivity
of a device is the same for both fields, for a given supply voltage
and temperature. Linearity error is present when there is a difference between the sensitivities measured at B1 and B2.
Linearity Error is calculated separately for the positive
(LinERRPOS) and negative (LinERRNEG ) applied magnetic fields.
Linearity error (%) is measured and defined as:
⎛ SensBPOS2 ⎞
⎟⎟ × 100%
LinERRPOS = ⎜⎜1–
⎝ SensBPOS1 ⎠
,
⎛ SensBNEG2⎞
⎟⎟ × 100%
LinERRNEG = ⎜⎜1–
⎝ SensBNEG1⎠
,
(9)
|VOUT(Bx) – VOUT(Q)|
Bx
(10)
,
and BPOSx and BNEGx are positive and negative magnetic fields,
with respect to the quiescent voltage output such that
|BPOS2| > |BPOS1| and |BNEG2| > |BNEG1|. Then:
LinERR = max( LinERRPOS , LinERRNEG )
⎛ SensBPOS
SymERR = ⎜⎜1–
⎝ SensBNEG
⎞
⎟⎟ × 100%
⎠
,
(12)
where SensBx is as defined in equation 10, and BPOS and BNEG
are positive and negative magnetic fields such that |BPOS| = |BNEG|.
Ratiometry Error The A1386 device features a ratiometric
output. This means that the quiescent voltage output, VOUT(Q) ,
magnetic sensitivity, Sens, and clamp voltages, VCLP(HIGH) and
VCLP(LOW), are proportional to the supply voltage, VCC. In other
words, when the supply voltage increases or decreases by a
certain percentage, each characteristic also increases or decreases
by the same percentage. Error is the difference between the
measured change in the supply voltage relative to 5 V, and the
measured change in each characteristic.
The ratiometric error in quiescent voltage output, RatERRVOUT(Q)
(%), for a given supply voltage, VCC, is defined as:
⎛ VOUT(Q)(VCC) / VOUT(Q)(5V) ⎞
⎟⎟ × 100%
RatERRVOUT(Q) = ⎜⎜1–
VCC / 5 V
⎝
⎠
. (13)
The ratiometric error in magnetic sensitivity, RatERRSens (%), for
a given supply voltage, VCC, is defined as:
where:
SensBx =
Symmetry error, SymERR (%), is measured and defined as:
.
(11)
Symmetry Sensitivity Error The magnetic sensitivity of the
A1386 device is constant for any two applied magnetic fields of
equal magnitudes and opposite polarities.
⎛ Sens(VCC) / Sens(5V) ⎞
⎟⎟ × 100%
RatERRSens = ⎜⎜1–
VCC / 5 V
⎝
⎠
.
(14)
The ratiometric error in the clamp voltages, RatERRCLP (%), for a
given supply voltage, VCC, is defined as:
⎛ VCLP(VCC) / VCLP(5V) ⎞
⎟⎟ × 100%
RatERRCLP = ⎜⎜1–
VCC / 5 V
⎝
⎠
.
(15)
where VCLP is either VCLP(HIGH) or VCLP(LOW).
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
A1386
5 V Field-Programmable Linear Hall Effect Sensor IC with 3 V Supply
Functionality Analog Output, and Miniature Package Options
Typical Application Drawing
V+
VCC
VOUT
CL
CBYPASS
GND
Chopper Stabilization Technique
When using Hall-effect technology, a limiting factor for
switchpoint accuracy is the small signal voltage developed across
the Hall element. This voltage is disproportionally small relative
to the offset that can be produced at the output of the Hall element. This makes it difficult to process the signal while maintaining an accurate, reliable output over the specified operating
temperature and voltage ranges. Chopper stabilization is a unique
approach used to minimize Hall offset on the chip. The patented
Allegro technique, namely Dynamic Quadrature Offset Cancellation, removes key sources of the output drift induced by thermal
and mechanical stresses. This offset reduction technique is based
on a signal modulation-demodulation process. The undesired
offset signal is separated from the magnetic field-induced signal
in the frequency domain, through modulation. The subsequent
demodulation acts as a modulation process for the offset, causing
the magnetic field-induced signal to recover its original spectrum
at base band, while the DC offset becomes a high-frequency
signal. The magnetic-sourced signal then can pass through a
low-pass filter, while the modulated DC offset is suppressed. The
chopper stabilization technique uses a 200 kHz high frequency
clock. For the demodulation process, a sample and hold technique
is used, where the sampling is performed at twice the chopper frequency (400 kHz). This high-frequency operation allows
a greater sampling rate, which results in higher accuracy and
faster signal-processing capability. This approach desensitizes
the chip to the effects of thermal and mechanical stresses, and
produces devices that have extremely stable quiescent Hall output
voltages and Precise recoverability after temperature cycling.
This technique is made possible through the use of a BiCMOS
process, which allows the use of low-offset, low-noise amplifiers
in combination with high-density logic integration and sampleand-hold circuits.
Regulator
Clock/Logic
Amp
Sample and
Hold
Hall Element
Low-Pass
Filter
Chopper Stabilization Technique
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
5 V Field-Programmable Linear Hall Effect Sensor IC with 3 V Supply
Functionality Analog Output, and Miniature Package Options
A1386
Programming Guidelines
Overview
Definition of Terms
Programming is accomplished by sending a series of input voltage pulses serially through the VOUT pin of the device. A unique
combination of different voltage level pulses controls the internal
programming logic of the device to select a target programmable
parameter and change its value. There are two programming
pulses, referred to as a high voltage pulse, VPH, consisting of a
VP(LOW) –VP(HIGH) –VP(LOW) sequence and a mid voltage pulse,
VPM, consisting of a VP(LOW) –VP(MID) –VP(LOW) sequence.
Register. The section of the programming logic that controls the
choice of programmable modes and parameters.
The A1386 features Try mode, Blow mode, and Lock mode:
• In Try mode, the value of a single programmable parameter may
be set and measured. The parameter value is stored temporarily,
and resets after cycling the supply voltage. Note that other
parameters cannot be accessed simultaneously in this mode.
• In Blow mode, the value of a single programmable parameter
may be permanently set by blowing solid-state fuses internal to
the device. Additional parameters may be blown sequentially.
• In Lock mode, a device-level fuse is blown, blocking the further
programming of all parameters.
The programming sequence is designed to help prevent the
device from being programmed accidentally; for example, as a
result of noise on the supply line.
Although any programmable variable power supply can be used
to generate the pulse waveforms, Allegro highly recommends
using the Allegro Sensor Evaluation Kit, available on the Allegro
website On-line Store. The manual for that kit is available for
download free of charge, and provides additional information on
programming these devices.
Bit Field. The internal fuses unique to each register, represented
as a binary number. Incrementing the bit field of a particular
register causes its programmable parameter to change, based on
the internal programming logic.
Key. A series of VPM voltage pulses used to select a register, with
a value expressed as the decimal equivalent of the binary value.
The LSB of a register is denoted as key 1, or bit 0.
Code. The number used to identify the combination of fuses
activated in a bit field, expressed as the decimal equivalent of the
binary value. The LSB of a bit field is denoted as code 1, or bit 0.
Addressing. Incrementing the bit field code of a selected register
by serially applying a pulse train through the VOUT pin of the
device. Each parameter can be measured during the addressing
process, but the internal fuses must be blown before the programming code (and parameter value) becomes permanent.
Fuse Blowing. Applying a VPH voltage pulse of sufficient duration at the VP(HIGH) level to permanently set an addressed bit by
blowing a fuse internal to the device. Once a bit (fuse) has been
blown, it cannot be reset.
Blow Pulse. A VPH voltage pulse of sufficient duration at the
VP(HIGH) level to blow the addressed fuse.
Cycling the Supply. Powering-down, and then powering-up the
supply voltage. Cycling the supply is used to clear the programming settings in Try mode.
Programming Pulse Requirements, Protocol at TA = 25°C
Characteristic
Symbol
Notes
Min.
Typ.
-
-
5.5
V
14
15
16
V
26
27
28
V
Minimum supply current required to ensure proper fuse blowing. In addition, a minimum capacitance, CBLOW = 0.1 μF, must be connected between the VOUT and
GND pins during programming to provide the current necessary for fuse blowing.
300
-
-
mA
tOFF(HIGH)
Duration at VP(LOW) level following a VP(HIGH) level.
30
-
-
μs
tOFF(MID)
Duration at VP(LOW) level following a VP(MID) level.
5
-
-
μs
VP(LOW)
Programming Voltage
VP(MID)
Measured at the VOUT pin.
VP(HIGH)
Programming Current
Pulse Width
IP
Max. Units
tACTIVE(HIGH)
Duration of VP(HIGH) level for VPH pulses during key/code selection.
30
-
-
μs
tACTIVE(MID)
Duration of VP(MID) level for VPH pulses during key/code selection.
15
-
-
μs
Duration at VP(HIGH) level for fuse blowing.
30
-
-
μs
Pulse Rise Time
tBLOW
tPr
Rise time required for transitions from VP(LOW) to either VP(MID) or VP(HIGH).
1
-
100
μs
Pulse Fall Time
tPf
Fall time required for transitions from VP(HIGH) to either VP(MID) to VP(LOW).
1
-
100
μs
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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11
5 V Field-Programmable Linear Hall Effect Sensor IC with 3 V Supply
Functionality Analog Output, and Miniature Package Options
A1386
Programming Procedures
Parameter Selection
Each programmable parameter can be accessed through a specific
register. To select a register, a sequence of voltage pulses consisting of a VPH pulse, a series of VPM pulses, and a VPH pulse
(with no VCC supply interruptions) must be applied serially to
the VOUT pin. The number of VPM pulses is called the key, and
uniquely identifies each register. The pulse train used for selection of the first register, key 1, is shown in figure 4.
The A1386 has two registers that select among the three programmable parameters:
• Register 1:
Sensitivity, Sens
• Register 2:
Quiescent voltage output, VOUT(Q)
Overall device locking, LOCK
When addressing the bit field, the number of VPM pulses is represented by a decimal number called a code. Addressing activates
the corresponding fuse locations in the given bit field by incrementing the binary value of an internal DAC. The value of the bit
field (and code) increments by one with the falling edge of each
VPM pulse, up to the maximum possible code (see the Programming Logic table). As the value of the bit field code increases, the
value of the programmable parameter changes.
Measurements can be taken after each pulse to determine if the
desired result for the programmable parameter has been reached.
Cycling the supply voltage resets all the locations in the bit field
that have unblown fuses to their initial states.
Fuse Blowing
VP(HIGH)
VP(HIGH)
VP(MID)
VP(MID)
VP(LOW)
Code 2n – 1
V+
Code 2n – 2
V+
Code 2
After a programmable parameter has been selected, a VPH pulse
transitions the programming logic into the bit field addressing state. Applying a series of VPM pulses to the VOUT pin of
the device, as shown in figure 5, increments the bit field of the
selected parameter.
Code 1
Bit Field Addressing
After the required code is found for a given parameter, its value
can be set permanently by blowing individual fuses in the appropriate register bit field. Blowing is accomplished by applying
a VPH pulse, called a blow pulse, of sufficient duration at the
VP(HIGH) level to permanently set an addressed bit by blowing a
fuse internal to the device. Due to power requirements, the fuse
for each bit in the bit field must be blown individually. To accomplish this, the code representing the desired parameter value
VP(LOW)
tLOW
0
tACTIVE
Figure 4. Parameter selection pulse train. This shows the sequence for selecting the register corresponding to key 1, indicated by a single VPM pulse.
0
Figure 5. Bit field addressing pulse train. Addressing the bit field by
incrementing the code causes the programmable parameter value to
change. The number of bits available for a given programming code, n,
varies among parameters; for example, the bit field for VOUT(Q) has 6 bits
available, which allows 63 separate codes to be used.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
5 V Field-Programmable Linear Hall Effect Sensor IC with 3 V Supply
Functionality Analog Output, and Miniature Package Options
A1386
must be translated to a binary number. For example, as shown
in figure 6, decimal code 5 is equivalent to the binary number
101. Therefore bit 2 (code 4) must be addressed and blown, the
device power supply cycled, and then bit 0 (code 1) addressed
and blown. An appropriate sequence for blowing code 5 is shown
in figure 7. The order of blowing bits, however, is not important.
Blowing bit 0 first, and then bit 2 is acceptable.
Locking the Device
Note: After blowing, the programming is not reversible, even
after cycling the supply power. Although a register bit field fuse
cannot be reset after it is blown, additional bits within the same
register can be blown at any time until the device is locked. For
example, if bit 1 (binary 10) has been blown, it is still possible to
blow bit 0. The end result would be binary 11 (decimal code 3).
The additional guidelines in this section should be followed to
ensure the proper behavior of these devices:
Bit Field Selection
Address Code Format
(Decimal Equivalent)
Code 5
Code in Binary
(Binary)
1 0 1
Fuse Blowing
Target Bits
Bit 2
Fuse Blowing
Address Code Format
After the desired code for each parameter is programmed, the
device can be locked to prevent further programming of any
parameters.
Additional Guidelines
• A 0.1 μF blowing capacitor, CBLOW, must be mounted between
the VOUT pin and the GND pin during programming, to ensure
enough current is available to blow fuses.
• The CBLOW blowing capacitor must be replaced in the final
application with a suitable CL. (The maximum load capacitance
is 10 nF for proper operation.)
• The power supply used for programming must be capable of
delivering at least 26 V and 300 mA.
• Be careful to observe the tLOW delay time before powering
down the device after blowing each bit.
Bit 0
• The following programming order is recommended:
Code 4
Code 1
(Decimal Equivalents)
1. Sens
2. VOUT(Q)
3. LOCK (only after all other parameters have been programmed and validated, because this prevents any further
programming of the device)
Figure 6. Example of code 5 broken into its binary components, which are
code 4 and code 1.
V+
VP(HIGH)
VP(MID)
VP(LOW)
Register
Selection
(Key 1)
0
Addressing
(Code 4)
Register
Selection
(Key 1)
Blow
(Code 4 in
Key 1)
Blow
(Code 1 in
Key 1)
tBLOW
VCC = 0 V
VCC = 0 V
Addressing
(Code 1)
VCC = 0 V
Programming of Code 5 in Key 1
Figure 7. Example of programming pulses applied to the VOUT pin that
result in permanent parameter settings. In this example, the register
corresponding to key 1 is selected and code 5 is addressed and blown.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
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13
A1386
5 V Field-Programmable Linear Hall Effect Sensor IC with 3 V Supply
Functionality Analog Output, and Miniature Package Options
Programming Modes
Try Mode
Blow Mode
Try mode allows a single programmable parameter to be tested
without permanently setting its value. Multiple parameters cannot
be tested simultaneously in this mode. After powering the VCC
supply, select the desired parameter register and address its bit
field. When addressing the bit field, each VPM pulse increments
the value of the parameter register, up to the maximum possible
code (see Programming Logic table). The addressed parameter
value remains stored in the device even after the programming
drive voltage is removed from the VOUT pin, allowing the value
to be measured. Note that for accurate time measurements, the
blow capacitor, CBLOW, should be removed during output voltage
measurement.
After the required value of the programmable parameter is found
using Try mode, its corresponding code should be blown to make
its value permanent. To do this, select the required parameter
register, and address and blow each required bit separately (as
described in the Fuse Blowing section). The supply must be
cycled between blowing each bit of a given code. After a bit is
blown, cycling the supply will not reset its value.
It is not possible to decrement the value of the register without
resetting the parameter bit field. To reset the bit field, and thus the
value of the programmable parameter, cycle the supply (VCC) voltage.
Lock Mode
To lock the device, address the LOCK bit and apply a blow pulse
with CBLOW in place. After locking the device, no future programming of any parameter is possible.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
14
5 V Field-Programmable Linear Hall Effect Sensor IC with 3 V Supply
Functionality Analog Output, and Miniature Package Options
A1386
Programming State Machine
Power-Up
VPM
Initial
VPH
VPH
Parameter Selection
VPM
VPM
Sens
VPM
VOUT(Q),
LOCK
VPH
Bit Field Addressing
VPM
1
VPM
VPM
2
3
VPM
2n – 1
n = total
bits in
register
VPM
VPH
Fuse Blowing
VPM = VP(LOW) , VP(MID) , VP(LOW)
VPH = VP(LOW) , VP(HIGH) , VP(LOW)
User Power-Down
Required
Initial State After system power-up, the programming logic is
Bit Field Addressing State This state allows the selection of the
reset to a known state. This is referred to as the Initial state. All
the bit field locations that have intact fuses are set to logic 0.
While in the Initial state, any VPM pulses on the VOUT pin are
ignored. To enter the Parameter Selection state, apply one VPH
pulse on the VOUT pin.
individual bit fields to be programmed in the selected parameter
Parameter Selection State This state allows the selection of the
parameter register containing the bit fields to be programmed. To
select a parameter register, increment through the keys by applying VPM pulses on the VOUT pin. Register keys select among the
following programming parameters:
• 1 pulse - Sens
register (see Programming Logic table). To leave this state, either
cycle device power or blow the fuses for the selected code. Note
that merely addressing the bit field does not permanently set
the value of the selected programming parameter; fuses must be
blown to do so.
Fuse Blowing State To blow an addressed bit field, apply a
VPH pulse on the VOUT pin. Power to the device should then be
• 2 pulses - VOUT(Q) and LOCK
cycled before additional programming is attempted. Note: Each
To enter the Bit Field Addressing state, apply one VPH pulse on
the VOUT pin.
bit representing a decimal code must be blown individually (see
the Fuse Blowing section).
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115 Northeast Cutoff
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1.508.853.5000; www.allegromicro.com
15
5 V Field-Programmable Linear Hall Effect Sensor IC with 3 V Supply
Functionality Analog Output, and Miniature Package Options
A1386
Programming Logic Table
Programmable
Parameter
(Register Key)
Sens
(1)
VOUT(Q) , LOCK
(2)
Bit Field Address
Binary Format
[MSB → LSB]
Decimal Equivalent
Code
000000
0
Description
Initial value (Sensinit)
111111
63
Maximum value of sensitivity (Sens) in range
000000
0
Initial value (VOUT(Q)init)
011111
31
Maximum value of quiescent voltage output
(VOUT(Q)) in range; B = 0 G
100000
32
LOCK bit, enables permanent locking of all programming bit fields in the device
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
16
5 V Field-Programmable Linear Hall Effect Sensor IC with 3 V Supply
Functionality Analog Output, and Miniature Package Options
A1386
Package LH, 3 Pin; (SOT-23W)
+0.12
2.98 –0.08
1.49 D
3
+4°
4° –0°
A
+0.020
0.180–0.053
0.96 D
+0.10
2.90 –0.20
+0.19
1.91 –0.06
2.40
0.70
D
0.25 MIN
1.00
2
1
0.55 REF
0.25 BSC
0.95
Seating Plane
Gauge Plane
8X 10° REF
B
PCB Layout Reference View
Branded Face
1.00 ±0.13
+0.10
0.05 –0.05
0.95 BSC
0.40 ±0.10
For Reference Only; not for tooling use (reference dwg. 802840)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A
Active Area Depth, 0.28 mm REF
B
Reference land pattern layout
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
C
Branding scale and appearance at supplier discretion
D
Hall element, not to scale
NNT
1
C
Standard Branding Reference View
N = Last two digits of device part number
T = Temperature code
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
17
5 V Field-Programmable Linear Hall Effect Sensor IC with 3 V Supply
Functionality Analog Output, and Miniature Package Options
A1386
Package UA, 3-Pin SIP
+0.08
4.09 –0.05
45°
B
C
E
2.04
1.52 ±0.05
1.44 E
+0.08
3.02 –0.05
Mold Ejector
Pin Indent
2X10°
E
Branded
Face
45°
1
D Standard Branding Reference View
A
1.02
MAX
0.51
REF
= Supplier emblem
N = Last two digits of device part number
T = Temperature code
0.79 REF
1
2
3
+0.03
0.41 –0.06
14.99 ±0.25
+0.05
0.43 –0.07
NNT
For Reference Only; not for tooling use (reference DWG-9013)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A
Dambar removal protrusion (6X)
B
Gate and tie bar burr area
C
Active Area Depth, 0.50 mm REF
D
Branding scale and appearance at supplier discretion
E
Hall element, not to scale
1.27 NOM
Please note that there are changes to the existing UA package drawing pending.
Please contact the Allegro Marketing department for additional information.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
18
A1386
5 V Field-Programmable Linear Hall Effect Sensor IC with 3 V Supply
Functionality Analog Output, and Miniature Package Options
Copyright ©2009, Allegro MicroSystems, Inc.
The products described herein are manufactured under one or more of the following U.S. patents: 5,045,920; 5,264,783; 5,442,283; 5,389,889;
5,581,179; 5,517,112; 5,619,137; 5,621,319; 5,650,719; 5,686,894; 5,694,038; 5,729,130; 5,917,320; and other patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, Inc.
115 Northeast Cutoff
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1.508.853.5000; www.allegromicro.com
19