Holtek HT95L200 Cid type phone 8-bit mcu Datasheet

HT95CXXX
CID Type Phone 8-Bit MCU
Features
· Provide MASK type and OTP type version
· Programmable frequency divider (PFD)
· Operating voltage range:
- FSK: 3.0V~5.5V
- Others: 2.4V~5.5V
· Dual system clock: 32768Hz, 3.58MHz
· Program ROM
- HT95C400/40P: 16K´16 bits
- HT95C300/30P: 8K´16 bits
· Up to 1.117ms instruction cycle with 3.58MHz system
· Four operating modes: Idle mode, Sleep mode,
Green mode and Normal mode
clock
· All instructions in one or two machine cycles
- HT95C200/20P: 8K´16 bits
· Built-in 3.58MHz DTMF Generator
· Data RAM
- HT95C400/40P: 2880´8 bits
- HT95C300/30P: 2112´8 bits
· Built-in FSK decoder:
- Supports Bell 202 and V.23
- Supports ring and line reversal detection
- HT95C200/20P: 1152´8 bits
· Built-in dialer I/O
· Bidirectional I/O lines
- HT95C400/40P: 40~28 I/O lines
- HT95C300/30P: 28~16 I/O lines
- HT95C200/20P: 28~20 I/O lines
· Built-in low battery detector
· LCD driver
- LCD contrast can be adjusted by software or exter-
nal resistor
· 16-bit table read instructions
- Support two LCD frame frequency 64Hz, 128Hz
- Support 16 or 8 common driver pins
- Some segments or commons can option to
· Subroutine nesting
- HT95C400/40P: 12 levels
- HT95C300/30P: 8 levels
- HT95C200/20P: 8 levels
bidirectional I/O lines
- HT95C400/40P: 48 seg.´16 com.
- HT95C300/30P: 48 seg.´16 com.
- HT95C200/20P: 24 seg.´16 com.
· Timer
- Two 16-bit programmable Timer/Event Counter
- Real time clock (RTC)
- Watchdog Timer (WDT)
· 128-pin QFP package
Applications
· Deluxe Feature Phone
· Fax and answering machines
· Caller ID Phone
· Other communication system
· Cordless Phone
General Description
tion. It can also operate with high speed system clock
rate of 3.58MHz in normal mode for high performance
operation. To ensure smooth dialer function and to
avoid MCU shut-down in extreme low voltage situation,
the dialer I/O circuit is built-in to generate hardware dialer signals such as on-hook, hold-line and hand-free.
Built-in real time clock and programmable frequency divider are provided for additional fancy features in product developments. The device is best suited for feature
phone products that comply with versatile dialer specification requirements of different areas or countries.
The HT95CXXX family MCU are 8-bit high performance
RISC-like microcontrollers with built-in DTMF generator,
FSK decoder and dialer I/O which provide MCU dialer
implementation or system control features for telecom
product applications. The phone controller has a built-in
program ROM, data RAM, LCD driver and I/O lines for
high end products design. In addition, for power management purpose, it has a built-in frequency up conversion circuit (32768Hz to 3.58MHz) which provides dual
system clock and four types of operation modes. For example, it can operate with low speed system clock rate
of 32768Hz in green mode with little power consump-
Rev. 1.50
1
May 26, 2005
HT95CXXX
Selection Table
Operating Program
Data
Normal Dialer
Voltage
Memory Memory
I/O
I/O
Part No.
LCD
Timer
Stack
External
Interrupt
DTMF
Generator
FSK
Receiver
Package
HT95A100
HT95A10P
2.4V~5.5V
4K´16
384´8
20
6
¾
16-bit´2
4
3
Ö
¾
28SOP
HT95A200
HT95A20P
2.4V~5.5V
4K´16
1152´8
28
8
¾
16-bit´2
8
4
Ö
¾
48SSOP
HT95A300
HT95A30P
2.4V~5.5V
8K´16
2112´8
28
8
¾
16-bit´2
8
4
Ö
¾
48SSOP
HT95A400
HT95A40P
2.4V~5.5V
16K´16
2880´8
44
8
¾
16-bit´2
12
4
Ö
¾
64QFP
HT95L000
HT95L00P
2.4V~5.5V
4K´16
384´8
14~18
6
12´8~16´8
16-bit´2
4
3
Ö
¾
56SSOP
HT95L100
HT95L10P
2.4V~5.5V
4K´16
1152´8
16~20
8
16´8~20´8
16-bit´2
8
4
Ö
¾
64QFP
HT95L200
HT95L20P
2.4V~5.5V
8K´16
1152´8
20~28
8
24´8~24´16
16-bit´2
8
4
Ö
¾
100QFP
HT95L300
HT95L30P
2.4V~5.5V
8K´16
2112´8
16~28
8
36´16~48´16
16-bit´2
8
4
Ö
¾
100QFP
HT95L400
HT95L40P
2.4V~5.5V
16K´16
2880´8
28~40
8
36´16~48´16
16-bit´2
12
4
Ö
¾
128QFP
HT95C200
HT95C20P
2.4V~5.5V
8K´16
1152´8
20~28
8
24´8~24´16
16-bit´2
8
4
Ö
Ö
128QFP
HT95C300
HT95C30P
2.4V~5.5V
8K´16
2112´8
16~28
8
36´16~48´16
16-bit´2
8
4
Ö
Ö
128QFP
HT95C400
HT95C40P
2.4V~5.5V
16K´16
2880´8
28~40
8
36´16~48´16
16-bit´2
12
4
Ö
Ö
128QFP
Note: Part numbers suffixed with ²P² are OTP devices, all others are mask version devices.
Block Diagram (HT95C400/40P)
R E S
S T A C K 0
S T A C K 1
S T A C K 2
P o w e r D o w n
D e te c to r &
R e s e t C ir c u it
P ro g ra m
C o u n te r
P ro g ra m
R O M
S T A C K 9
S T A C K 1 0
S T A C K 1 1
M P 0
M P 1
M
A L U
H F I
H F O
H D I
H D O
H K S
P O
D N P O
X M U T E
V
V D
V
V S
D D
D 2
S S
S 2
O S C C ir c u it
A C C
U
D A T A
M e m o ry
X
S T A T U S
S h ifte r
3 2 7 6 8 H z
W D T O S C
S y s te m C lo c k /4
M
W D T S
U
X
U
X
3 2 7 6 8 H z
M
W D T P r e s c a le r
T M R 0
U
X
S y s te m
c lo c k /4
P A
P A C
P A 0 ~ P A 7
P B
P B C
P B 0 ~ P B 7
P D
P D C
P D 0 ~ P D 7
P E
P E C
P E 0 ~ P E 3
P F
P F C
P F 0 ~ P F 7
P G
P G C
P G 0 ~ P G 3
D T M F
G e n e ra to r
F S K
D e c o d e r
P o w e r
S u p p ly
D T M F
3 .5 8 M H z
D ia le r I/O
L o w
B a tte ry
D e te c to r
L B IN
Rev. 1.50
R T C
IN T /T M R 1
M
T M R 1
T M R 1 C
IN T C 0
IN T C 1
M U X
In s tr u c tio n
D e c o d e r
X 1
X 2
X C
In te rru p t
C ir c u it
T M R 0
T M R 0 C
In s tr u c tio n
R e g is te r
T im in g
G e n e ra to r
3 2 7 6 8 H z
3 2 7 6 8 H z
o r 3 .5 8 M H z /4
L C D D r iv e r
P F D
C O M 0 ~ C O M 1 5 S E G 0 ~ S E G 4 7
2
T IP
R IN G
R D E T 1
R T IM E
M U S IC
V L C D
May 26, 2005
HT95CXXX
Pin Assignment
HT95C400/40P
S E G 2
S E G 1
S E G 0
C O M 1 5
C O M 1 4
C O M 1 3
C O M 1 2
C O M 1 1
C O M 1 0
C O M 9
C O M 8
C O M 7
C O M 6
C O M 5
C O M 4
C O M 3
C O M 2
C O M 1
C O M 0
P F 7
V D D 2
R T IM E
R D E T 1
R IN G
T IP
V S S 2
P F 6
P F 5
P F 4
P F 3
P F 2
P F 1
P F 0
P A 7
P A 6
P A 5
P A 4
P A 3
P A 2
P A 1
P A 0
P B 7
P B 6
P B 5
P B 4
P B 3
P B 2
P B 1
P B 0
X M U T E
D N P O
P O
H K S
H D O
H D I
H F O
H F I
V S S
V D D
IN T /T M R 1
P G 3
P G 2
P G 1
P G 0
1
1 2 8 1 2 7 1 2 6 1 2 5 1 2 4 1 2 3 1 2 2 1 2 1 1 2 0 1 1 9 1 1 8 1 1 7 1 1 6 1 1 5 1 1 4 1 1 3 1 1 2 1 1 1 1 1 0 1 0 9 1 0 8 1 0 7 1 0 6 1 0 5 1 0 4 1 0 3
1 0 2
2
1 0 1
3
1 0 0
4
9 9
5
9 8
6
9 7
7
9 6
8
9 5
9
9 4
1 0
9 3
1 1
9 2
1 2
9 1
1 3
9 0
1 4
8 9
1 5
8 8
1 6
8 7
1 7
8 6
1 8
8 5
H T 9 5 C 4 0 0 /4 0 P
1 2 8 Q F P -A
1 9
2 0
8 4
8 3
2 1
8 2
2 2
8 1
2 3
8 0
2 4
7 9
2 5
7 8
2 6
7 7
2 7
7 6
2 8
7 5
2 9
7 4
3 0
7 3
3 1
7 2
3 2
7 1
3 3
7 0
3 4
6 9
3 5
6 8
3 6
6 7
6 6
3 7
3 8
3 9
4 0 4 1
4 2
4 3
4 4
4 5
4 6
4 7 4 8
4 9
5 0
5 1
5 2
5 3
5 4
5 5
5 6
5 7 5 8
5 9
6 0
6 1
6 2
6 3 6 4
6 5
N C
N C
N C
N C
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
N C
N C
N C
N C
G 3
G 4
G 5
G 6
G 7
G 8
G 9
G 1
G 1
G 1
G 1
G 1
G 1
G 1
G 1
G 1
G 1
G 2
G 2
G 2
G 2
G 2
G 2
G 2
G 2
G 2
G 2
G 3
G 3
G 3
2
1
0
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
N C
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
V L C
M U S
R E S
T M R
D T M
L B IN
X C
X 1
X 2
N C
D
IC
3 3
3 4
3 5
3 6
3 7
3 8
3 9
4 0
4 1
4 2
4 3
4 4
4 5
4 6
4 7
0
F
/P
/P
/P
/P
/P
/P
/P
/P
/P
/P
/P
/P
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
E 0
E 1
E 2
E 3
Rev. 1.50
3
May 26, 2005
HT95CXXX
HT95C300/30P
S E G 2
S E G 1
S E G 0
C O M 1 5
C O M 1 4
C O M 1 3
C O M 1 2
C O M 1 1
C O M 1 0
C O M 9
C O M 8
C O M 7
C O M 6
C O M 5
C O M 4
C O M 3
C O M 2
C O M 1
C O M 0
N C
V D D 2
R T IM E
R D E T 1
R IN G
T IP
V S S 2
1
1 2 8 1 2 7 1 2 6 1 2 5 1 2 4 1 2 3 1 2 2 1 2 1 1 2 0 1 1 9 1 1 8 1 1 7 1 1 6 1 1 5 1 1 4 1 1 3 1 1 2 1 1 1 1 1 0 1 0 9 1 0 8 1 0 7 1 0 6 1 0 5 1 0 4 1 0 3
1 0 2
2
1 0 1
3
1 0 0
4
9 9
5
9 8
6
9 7
7
9 6
8
9 5
9
9 4
1 0
9 3
1 1
9 2
1 2
9 1
1 3
9 0
1 4
8 9
1 5
8 8
1 6
8 7
1 7
8 6
N C
N C
N C
N C
N C
N C
N C
P A 7
P A 6
P A 5
P A 4
P A 3
P A 2
P A 1
P A 0
P B 7
P B 6
P B 5
P B 4
P B 3
P B 2
P B 1
P B 0
X M U T E
D N P O
P O
H K S
H D O
H D I
H F O
H F I
V S S
V D D
IN T /T M R 1
N C
N C
N C
N C
1 8
8 5
H T 9 5 C 3 0 0 /3 0 P
1 2 8 Q F P -A
1 9
2 0
8 4
8 3
2 1
8 2
2 2
8 1
2 3
8 0
2 4
7 9
2 5
7 8
2 6
7 7
2 7
7 6
2 8
7 5
2 9
7 4
3 0
7 3
3 1
7 2
3 2
7 1
3 3
7 0
3 4
6 9
3 5
6 8
3 6
6 7
3 7
6 6
3 8
3 9
4 0 4 1
4 2
4 3
4 4
4 5
4 6
4 7 4 8
4 9
5 0
5 1
5 2
5 3
5 4
5 5
5 6
5 7 5 8
5 9
6 0
6 1
6 2
6 3 6 4
6 5
N C
N C
N C
N C
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
N C
N C
N C
N C
G 3
G 4
G 5
G 6
G 7
G 8
G 9
G 1
G 1
G 1
G 1
G 1
G 1
G 1
G 1
G 1
G 1
G 2
G 2
G 2
G 2
G 2
G 2
G 2
G 2
G 2
G 2
G 3
G 3
G 3
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
0
1
2
N C
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
V L C
M U S
R E S
T M R
D T M
L B IN
X C
X 1
X 2
N C
D
IC
3 3
3 4
3 5
3 6
3 7
3 8
3 9
4 0
4 1
4 2
4 3
4 4
4 5
4 6
4 7
0
F
/P
/P
/P
/P
/P
/P
/P
/P
/P
/P
/P
/P
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
E 0
E 1
E 2
E 3
Rev. 1.50
4
May 26, 2005
HT95CXXX
HT95C200/20P
C O M
C O M
C O M
C O M
C O M
C O M
C O M
C O M
N C
N C
C O M 9
C O M 8
7 /P D 7
6 /P D 6
5 /P D 5
4 /P D 4
3 /P D 3
2 /P D 2
1 /P D 1
0 /P D 0
N C
N C
N C
N C
N C
N C
N C
N C
V D D 2
R T IM E
R D E T 1
R IN G
T IP
V S S 2
1
1 2 8 1 2 7 1 2 6 1 2 5 1 2 4 1 2 3 1 2 2 1 2 1 1 2 0 1 1 9 1 1 8 1 1 7 1 1 6 1 1 5 1 1 4 1 1 3 1 1 2 1 1 1 1 1 0 1 0 9 1 0 8 1 0 7 1 0 6 1 0 5 1 0 4 1 0 3
1 0 2
2
1 0 1
3
1 0 0
4
9 9
5
9 8
6
9 7
7
9 6
8
9 5
9
9 4
1 0
9 3
1 1
9 2
1 2
9 1
1 3
9 0
1 4
8 9
1 5
8 8
1 6
8 7
1 7
8 6
N C
N C
N C
N C
N C
N C
N C
P A 7
P A 6
P A 5
P A 4
P A 3
P A 2
P A 1
P A 0
P B 7
P B 6
P B 5
P B 4
P B 3
P B 2
P B 1
P B 0
X M U T E
D N P O
P O
H K S
H D O
H D I
H F O
H F I
V S S
V D D
IN T /T M R 1
N C
N C
N C
N C
1 8
8 5
H T 9 5 C 2 0 0 /2 0 P
1 2 8 Q F P -A
1 9
2 0
8 4
8 3
2 1
8 2
2 2
8 1
2 3
8 0
2 4
7 9
2 5
7 8
2 6
7 7
2 7
7 6
2 8
7 5
2 9
7 4
3 0
7 3
3 1
7 2
3 2
7 1
3 3
7 0
3 4
6 9
3 5
6 8
3 6
6 7
6 6
3 7
3 8
3 9
4 0 4 1
4 2
4 3
4 4
4 5
4 6
4 7 4 8
4 9
5 0
5 1
5 2
5 3
5 4
5 5
5 6
5 7 5 8
6 0
5 9
6 1
6 2
6 3 6 4
6 5
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
C O M
C O M
C O M
C O M
C O M
C O M
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
N C
N C
N C
N C
1 0
1 1
1 2
1 3
1 4
1 5
0
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
N C
N C
N C
N C
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
P E 0
P E 1
P E 2
P E 3
V L C
M U S
R E S
T M R
D T M
L B IN
X C
X 1
X 2
N C
D
1 6
1 7
1 8
1 9
2 0
2 1
2 2
IC
2 3
0
F
Pin Description
Pin Name
I/O
Description
CPU
VDD
¾
VDD2
VSS
Positive power supply
Positive power supply for FSK decoder
¾
VSS2
Negative power supply, ground
Negative power supply for FSK decoder, ground
X1
I
X2
O
A 32768Hz crystal (or resonator) should be connected to this pin and X1.
XC
I
External low pass filter used for frequency up conversion circuit.
RES
I
Schmitt trigger reset input, active low.
INT/TMR1
I
Schmitt trigger input for external interrupt or Timer/Event Counter 1.
No internal pull-high resistor.
For INT: Edge trigger activated on a falling edge.
For TMR1: Activated on falling or rising transition edge, selected by software.
TMR0
I
Schmitt trigger input for Timer/Event Counter 0.
No internal pull-high resistor.
Activated on falling or rising transition edge, selected by software.
Rev. 1.50
A 32768Hz crystal (or resonator) should be connected to this pin and X2.
5
May 26, 2005
HT95CXXX
Pin Name
I/O
Description
SEG47~SEG0
O
or
I/O
LCD panel segment outputs.
Some segment outputs can be optioned to Bidirectional input/output ports by software.
(See the ²LCD Driver² function)
COM15~COM0
O
or
I/O
LCD panel common outputs.
Some common outputs can be optioned to Bidirectional input/output ports by software.
(See the ²LCD Driver² function)
LCD Driver
VLCD
I
LCD driver power source.
Normal I/O
PA7~PA0
I/O
Bidirectional input/output ports.
Schmitt trigger input and CMOS output.
See mask option table for pull-high and wake-up function
PB7~PB0
I/O
Bidirectional input/output ports.
Schmitt trigger input and CMOS output.
See mask option table for pull-high function
I/O
Bidirectional input/output ports.
Schmitt trigger input and CMOS output.
See mask option table for pull-high function
Port D could be optioned to LCD signal output, see the ²Input/Output Ports² function
PE3~PE0
I/O
Bidirectional input/output ports.
Schmitt trigger input and CMOS output.
See mask option table for pull-high function
Port E could be optioned to LCD signal output, see the ²Input/Output Ports² function
PF7~PF0
I/O
Bidirectional input/output ports.
Schmitt trigger input and CMOS output.
See mask option table for pull-high function
PG3~PG0
I/O
Bidirectional input/output ports.
Schmitt trigger input and CMOS output.
See mask option table for pull-high function
PD7~PD0
Dialer I/O (See the ²Dialer I/O function²)
Schmitt trigger input structure. An external RC network is recommended for input
debouncing.
This pin is pulled low with internal resistance of 200kW typ.
HFI
I
HFO
O
CMOS output structure.
HDI
I
Schmitt trigger input structure. An external RC network is recommended for input
debouncing.
This pin is pulled high with internal resistance of 200kW typ.
HDO
O
CMOS output structure.
HKS
I
This pin detects the status of the hook-switch and its combination with HFI/HDI can control the PO pin output to make or break the line.
PO
O
CMOS output structure controlled by HKS and HFI/HDI pins and which determines
whether the dialer connects or disconnects the telephone line.
DNPO
O
NMOS output structure.
XMUTE
O
NMOS output structure. Usually, XMUTE is used to mute the speech circuit when transmitting the dialer signal.
Rev. 1.50
6
May 26, 2005
HT95CXXX
Pin Name
I/O
Description
DTMF
O
This pin outputs dual tone signals to dial out the phone number. The load resistor should
not be less than 5kW.
MUSIC
O
This pin outputs the single tone that is generated by the PFD generator.
TIP
I
Input pin connected to the tip side of the twisted pair wires. It is internally biased to 1/2
VDD when the device is in power-up mode. This pin must be DC isolated from the line.
RING
I
Input pin connected to the ring side of the twisted pair wires. It is internally biased to 1/2
VDD when the device is in power-up mode. This pin must be DC isolated from the line.
RDET1
I
Peripherals
RTIME
LBIN
I/O
I
This pin detects ring energy on the line through an attenuating network.
Schmitt trigger input and NMOS output pin which functions with RDET1 pin to make an
RC network that performs ring detection function.
This pin detects battery low through external R1/R2 to determine threshold voltage.
Absolute Maximum Ratings
Supply Voltage ..........................VSS-0.3V to VSS+5.5V
Storage Temperature ...........................-50°C to 125°C
Input Voltage .............................. VSS-0.3 to VDD+0.3V
Operating Temperature ..........................-20°C to 70°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Electrical Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
CPU
IIDL
Idle Mode Current
5V
32768Hz off, 3.58MHz off,
CPU off, LCD off, WDT off,
no load
¾
¾
2
mA
ISLP
Sleep Mode Current
5V
32768Hz on, 3.58MHz off,
CPU off, LCD off, WDT off,
no load
¾
17
30
mA
IGRN
Green Mode Current
5V
32768Hz on, 3.58MHz off,
CPU on, LCD off, WDT off,
no load
¾
28
50
mA
32768Hz on, 3.58MHz on,
CPU on, LCD on, WDT on,
DTMF generator off,
FSK decoder off, no load
¾
1.8
3
mA
INOR
Normal Mode Current
5V
VIL
I/O Port Input Low Voltage
5V
¾
0
¾
1
V
VIH
I/O Port Input High Voltage
5V
¾
4
¾
5
V
IOL
I/O Port Sink Current
5V
¾
4
6
¾
mA
IOH
I/O Port Source Current
5V
¾
-2
-3
¾
mA
RPH
Pull-high Resistor
5V
¾
10
30
¾
kW
VLBIN
Low Battery Detection
Reference Voltage
5V
¾
1.05
1.15
1.25
V
Rev. 1.50
7
May 26, 2005
HT95CXXX
Symbol
Parameter
Test Conditions
VDD
Conditions
¾
Min.
Typ.
Max.
Unit
¾
3
5
V
¾
¾
100
mA
LCD Driver
VLCD
LCD Panel Power Supply
¾
ILCD
LCD Operation Current
¾
VLCD=5V, 32768Hz, no load
Dialer I/O
IXMO
XMUTE Leakage Current
2.5V XMUTE pin=2.5V
¾
¾
1
mA
IOLXM
XMUTE Sink Current
2.5V XMUTE pin=0.5V
1
¾
¾
mA
IHKS
HKS Input Current
2.5V HKS pin=2.5V
¾
¾
0.1
mA
¾
kW
RHFI
HFI Pull-low Resistance
2.5V VHFI=2.5V
¾
200
RHDI
HDI Pull-high Resistance
2.5V VHDI=0V
¾
200
¾
kW
IOH2
HFO Source Current
2.5V VOH=2V
-1
¾
¾
mA
IOL2
HFO Sink Current
2.5V VOL=0.5V
1
¾
¾
mA
IOH3
HDO Source Current
2.5V VOH=2V
-1
¾
¾
mA
IOL3
HDO Sink Current
2.5V VOL=0.5V
1
¾
¾
mA
IOH4
PO Source Current
2.5V VOH=2V
-1
¾
¾
mA
IOL4
PO Sink Current
2.5V VOL=0.5V
1
¾
¾
mA
IOL5
DNPO Sink Current
2.5V VOL=0.5V
1
¾
¾
mA
0.45VDD
¾
0.7VDD
V
DTMF Generator
VTDC
DTMF Output DC Level
¾
¾
VTOL
DTMF Sink Current
¾
VDTMF=0.5V
0.1
¾
¾
mA
VTAC
DTMF Output AC Level
¾
Row group, RL=5kW
120
155
180
mVrms
RL
DTMF Output Load
¾
THD£-23dB
5
¾
¾
kW
ACR
Column Pre-emphasis
¾
Row group=0dB
1
2
3
dB
THD
Tone Signal Distortion
¾
RL=5kW
¾
-30
-23
dB
FSK Decoder
S/N
tSUPD
Rev. 1.50
Input Sensitivity: TIP, RING
¾
¾
-40
-45
¾
dBm
Transmission Rate
5V
¾
1188
1200
1212
baud
Signal to Noise Ratio
¾
¾
¾
20
¾
dB
Band-pass Filter
Frequency Response
Relative to 1700Hz at 0dBm
£60Hz
550Hz
2700Hz
³3300Hz
¾
¾
¾
¾
¾
¾
-64
-4
-3
-34
¾
¾
¾
¾
dB
Carrier Detect Sensitivity
¾
¾
¾
-48
¾
dBm
Power Up to FSK Signal Set
Up Time
¾
¾
15
¾
¾
ms
8
May 26, 2005
HT95CXXX
Functional Description
to fetch an instruction code, the contents of the program
counter are incremented by 1. The program counter
then points to the memory word containing the next instruction code.
Execution Flow
The system clock for the telephone controller is derived
from a 32768Hz crystal oscillator. A built-in frequency up
conversion circuit provides dual system clock, namely;
32768Hz and 3.58MHz. The system clock is internally
divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way
that a fetch takes an instruction cycle while decoding
and execution takes the next instruction cycle. The
pipelining scheme causes each instruction to be effectively executed in a instruction cycle. If an instruction
changes the program counter, two instruction cycles are
required to complete the instruction.
When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from
subroutine, the program counter manipulates the program transfer by loading the address corresponding to
each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is
discarded and a dummy cycle replaces it to get the
proper instruction. Otherwise proceed to the next instruction.
Program Counter - PC
The program counter lower order byte register
(PCL:06H) is a readable and write-able register. Moving
data into the PCL performs a short jump. The destination will be within 256 locations. When a control transfer
takes place, an additional dummy cycle is required.
The program counter (PC) controls the sequence in
which the instructions stored in the program ROM are
executed and its contents specify a full range of program memory. After accessing a program memory word
S y s te m
C lo c k
T 1
T 2
T 3
T 4
T 1
T 2
P C
P C
T 3
T 4
T 1
T 2
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
T 3
T 4
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Program Counter
Mode
*13
*12
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
External interrupt
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter 0 overflow
0
0
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter 1 overflow
0
0
0
0
0
0
0
0
0
0
1
1
0
0
Peripheral interrupt
0
0
0
0
0
0
0
0
0
1
0
0
0
0
RTC interrupt
0
0
0
0
0
0
0
0
0
1
0
1
0
0
Dialer I/O interrupt
0
0
0
0
0
0
0
0
0
1
1
0
0
0
@2
@1
@0
Skip
Program Counter+2 (within current bank)
Loading PCL
*13
*12
*11
*10
*9
*8
@7
@6
@5
@4
@3
Jump, call branch
BP.5 #12 #11 #10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from subroutine
S13 S12 S11 S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Note: *13~*0: Program counter bits
Program ROM Address
S13~S0: Stack register bits
#12~#0: Instruction code bits
@[email protected]: PCL bits
Available bits of program counter for HT95C400/40P: Bit 13~Bit 0
Available bits of program counter for HT95C300/30P: Bit 12~Bit 0
Available bits of program counter for HT95C200/20P: Bit 12~Bit 0
Rev. 1.50
9
May 26, 2005
HT95CXXX
· Location 0000H (Bank0)
Program Memory - ROM
The program memory is used to store the program instructions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
8K´16 bits´2 banks (HT95C400/40P) or 8K´16 bits
(HT95C300/30P, HT95C200/20P) addressed by the
program counter and table pointer.
This area is reserved for the initialization program. After chip power-on reset or external reset or WDT
time-out reset, the program always begins execution
at location 0000H.
· Location 0004H (Bank0)
This area is reserved for the external interrupt service
program. If the INT/TMR1 input pin is activated, the
external interrupt is enabled and the stack is not full,
the program begins execution at location 0004H.
For the HT95C400/40P, the program memory is divided
into 2 banks, each bank having a ROM Size 8K´16 bits.
To move from the present ROM bank to a different ROM
bank, the higher 1 bits of the ROM address are set by
the BP (Bank Pointer), while the remaining 13 bits of the
PC are set in the usual way by executing the appropriate
jump or call instruction. As the 14 address bits are
latched during the execution of a call or jump instruction,
the correct value of the BP must first be setup before a
jump or call is executed. When either a software or hardware interrupt is received, note that no matter which
ROM bank the program is in, the program will always
jump to the appropriate interrupt service address in
Bank 0. The original 14 bits address will be stored on the
stack and restored when the relevant RET/RETI instruction is executed, automatically returning the program to
the original ROM bank. This eliminates the need for programmers to manage the BP when interrupts occur.
Certain locations in the program memory are reserved
for special usage:
0 0 0 H
0 0 C H
This area is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results
from a Timer/Event Counter 0 overflow, the
Timer/Event Counter 0 interrupt is enabled and the
stack is not full, the program begins execution at location 0008H.
· Location 000CH (Bank0)
This location is reserved for the Timer/Event Counter
1 interrupt service program. If a timer interrupt results
from a Timer/Event Counter 1 overflow, the
Timer/Event Counter 1 interrupt is enabled and the
stack is not full, the program begins execution at location 000CH.
· Location 0010H (Bank0)
This location is reserved for the peripherals interrupt
service program. When the FSK decoder detects a
ringer or line reversal or FSK carrier signal or FSK
packet data, the FSK interrupt is generated. If these
interrupts occurred, the peripheral interrupt is enabled and the stack is not full, the program begins execution at location 0010H. The programmer could
distinguish from these interrupts from the FSKS register.
D e v ic e in itia liz a tio n p r o g r a m
0 0 4 H
0 0 8 H
· Location 0008H (Bank0)
E x te r n a l in te r r u p t s u b r o u tin e
T im e r /e v e n t c o u n te r 0 in te r r u p t s u b r o u tin e
T im e r /e v e n t c o u n te r 1 in te r r u p t s u b r o u tin e
0 1 0 H
0 1 4 H
0 1 8 H
n 0 0 H
P e r ip h e r a l in te r r u p t s u b r o u tin e
R T C in te r r u p t s u b r o u tin e
D ia le r I/O
in te r r u p t s u b r o u tin e
· Location 0014H (Bank0)
P ro g ra m
R O M
This location is reserved for real time clock (RTC) interrupt service program. When RTC generator is enabled and time-out occurs, the RTC interrupt is
enabled and the stack is not full, the program begins
execution at location 0014H.
L o o k - u p ta b le ( 2 5 6 w o r d s )
n F F H
· Location 0018H (Bank0)
This location is reserved for the HKS pin edge transition or HDI pin falling edge transition or HFI pin rising
edge transition. If this condition occurs, the dialer I/O
interrupt is enabled and the stack is not full, the program begins execution at location 18H.
L o o k - u p ta b le ( 2 5 6 w o r d s )
1 6 b its
N o te : T h e L a s t p a g e fo r H T 9 5 C 4 0 0 /4 0 P is 3 F 0 0 H ~ 3 F F F H
T h e L a s t p a g e fo r H T 9 5 C 3 0 0 /3 0 P is 1 F 0 0 H ~ 1 F F F H
T h e L a s t p a g e fo r H T 9 5 C 2 0 0 /2 0 P is 1 F 0 0 H ~ 1 F F F H
Program Memory
Rev. 1.50
10
May 26, 2005
HT95CXXX
neither readable nor writable. The activated level is indexed by the stack pointer (SP) and is neither readable
nor writable. At a subroutine call or interrupt acknowledge signal, the contents of the program counter are
pushed onto the stack. At the end of a subroutine or an
interrupt routine, signaled by a return instruction (RET or
RETI), the program counter is restored to its previous
value from the stack. After a chip reset, the SP will point
to the top of the stack. If the stack is full and an interrupt
takes place, the interrupt request flag will be recorded
but the acknowledge signal will be inhibited even if this
interrupt is enabled. When the stack pointer is
decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the
programmer to use the structure more easily. If the stack
is full and a ²CALL² is subsequently executed, stack
overflow occurs and the first entry will be lost (only the
most recent 12 or 8, depending on various MCU type,
returned addresses are stored).
Table Location
Any location in the ROM space can be used as look-up
tables. The instructions ²TABRDC [m]² (the current
page, one page=256 words) and ²TABRDL [m]² (the last
page) transfer the contents of the lower-order byte to the
specified data memory, and the higher-order byte to
TBLH (08H). For the HT95C400/40P, the instruction
²TABRDC [m]² is used for any page of any bank. Only
the destination of the lower-order byte in the table is
well-defined, and the higher-order byte of the table word
is transferred to TBLH. The table pointer (TBLP) or
(TBHP, TBLP for the HT95C400/40P) is a read/write
register (07H) or (1FH, 07H for the HT95C400/40P),
which indicates the table location. Before accessing the
table, the location must be placed in the (TBLP) or
(TBHP, TBLP for the HT95C400/40P). The TBLH is read
only and cannot be restored. If the main routine and the
ISR (Interrupt Service Routine) both employ the table
read instruction, the contents of the TBLH in the main
routine are likely to be changed by the table read instruction used in the ISR. Errors will then occur. Hence,
simultaneously using the table read instruction in the
main routine and the ISR should be avoided. However, if
the table read instruction has to be applied in both the
main routine and the ISR, the interrupt should be disabled prior to the table read instruction. It will not be enabled until the TBLH has been backed-up. All table
related instructions require two cycles to complete the
operation. These areas may function as normal program memory depending on the requirements.
Data Memory
The data memory is divided into four functional groups:
special function registers, embedded control register,
LCD display memory and general purpose memory.
Most are read/write, but some are read only.
The special function registers are located from 00H to
1FH. The embedded control registers are located in the
memory areas from 20H to 3FH. The remaining spaces
which are not specified in the following table before the
40H are reserved for future expanded usage and reading these locations will get ²00H². The general purpose
data memory is divided into 15 banks (HT95C400/40P),
11 banks (HT95C300/30P) or 6 banks (HT95C200/
20P). The banks in the RAM are all addressed from 40H
to 0FFH and they are selected by setting the value of the
bank pointer (BP).
Stack Register
This is a special part of the memory which is used to
save the contents of the program counter only. The
stack is organized into 12 levels (HT95C400/40P) or 8
levels (HT95C300/30P, HT95C200/20P) and is neither
part of the data nor part of the program space, and is
HT95C400/40P
Instruction(s)
Table Location
*13
*12
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
#5
#4
#3
#2
#1
#0
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
HT95C300/30P, HT95C200/20P
Instruction(s)
Table Location
*12
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P12
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Note: *13~*0: Table location bits
#7~#0: TBHP register bit7~bit0
@[email protected]: TBLP register bit7~bit0
Rev. 1.50
P12~P8: Current program counter bits
11
May 26, 2005
HT95CXXX
The LCD display memory is located at bank 1BH. They
can be read and written to by the indirect addressing
mode using memory pointer 1 (MP1). To turn the display
On or Off, a ²1² or ²0² is written to the corresponding bit
of the memory area.
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the
data memory can be set and reset by ²SET [m].i² and
²CLR [m].i². They are also indirectly accessible through
memory pointer registers (MP0 or MP1). The
bank1~bank14 and bank27 are only indirectly accessible through memory pointer 1 register (MP1).
Special Register, Embedded Control Register, LCD Display Memory and General Purpose RAM
BP
Address
(RAM Bank)
Function
Description
Supported for HT95CXXX
400/P
300/P
200/P
Special Function Register
00H
00H
IAR0
Indirect addressing register 0
Ö
Ö
Ö
00H
01H
MP0
Memory pointer register 0
Ö
Ö
Ö
00H
02H
IAR1
Indirect addressing register 1
Ö
Ö
Ö
00H
03H
MP1
Memory pointer register 1
Ö
Ö
Ö
00H
04H
BP
Bank Pointer register
Ö
Ö
Ö
00H
05H
ACC
Accumulator
Ö
Ö
Ö
00H
06H
PCL
Program counter lower-order byte register
Ö
Ö
Ö
00H
07H
TBLP
Table pointer
Ö
Ö
Ö
00H
08H
TBLH
Table higher-order byte register
Ö
Ö
Ö
00H
09H
WDTS
Watchdog Timer option setting register
Ö
Ö
Ö
00H
0AH
STATUS
Status register
Ö
Ö
Ö
00H
0BH
INTC0
Interrupt control register 0
Ö
Ö
Ö
00H
0CH
TMR0H
Timer/Event Counter 0 high-order byte
register
Ö
Ö
Ö
00H
0DH
TMR0L
Timer/Event Counter 0 low-order byte
register
Ö
Ö
Ö
00H
0EH
TMR0C
Timer/Event Counter 0 control register
Ö
Ö
Ö
00H
0FH
TMR1H
Timer/Event Counter 1 high-order byte
register
Ö
Ö
Ö
00H
10H
TMR1L
Timer/Event Counter 1 low-order byte
register
Ö
Ö
Ö
00H
11H
TMR1C
Timer/Event Counter 1 control register
Ö
Ö
Ö
00H
12H
PA
Port A data register
Ö
Ö
Ö
00H
13H
PAC
Port A control register
Ö
Ö
Ö
00H
14H
PB
Port B data register
Ö
Ö
Ö
00H
15H
PBC
Port B control register
Ö
Ö
Ö
00H
16H
DIALERIO
Dialer I/O register
Ö
Ö
Ö
00H
18H
PD
Port D data register
Ö
Ö
Ö
00H
19H
PDC
Port D control register
Ö
Ö
Ö
00H
1AH
PE
Port E data register
Ö
Ö
Ö
00H
1BH
PEC
Port E control register
Ö
Ö
Ö
00H
1EH
INTC1
Interrupt control register 1
Ö
Ö
Ö
00H
1FH
TBHP
Table high-order byte pointer
Ö
¾
¾
Rev. 1.50
12
May 26, 2005
HT95CXXX
BP
Address
(RAM Bank)
Function
Description
Supported for HT95CXXX
400/P
300/P
200/P
Embedded Control Register
00H
20H
DTMFC
DTMF generator control register
Ö
Ö
Ö
00H
21H
DTMFD
DTMF generator data register
Ö
Ö
Ö
00H
22H
LINE
Line control register
Ö
Ö
Ö
00H
24H
RTCC
Real time clock control register
Ö
Ö
Ö
00H
26H
MODE
Operation mode control register
Ö
Ö
Ö
00H
28H
LCDIO
LCD segment and I/O option register
Ö
Ö
¾
00H
29H
FSKC
FSK decoder control register
Ö
Ö
Ö
00H
2AH
FSKS
FSK decoder status register
Ö
Ö
Ö
00H
2BH
FSKD
FSK packet data register
Ö
Ö
Ö
00H
2DH
LCDC
LCD driver control register
Ö
Ö
Ö
00H
2EH
PFDC
PFD control register
Ö
Ö
Ö
00H
2FH
PFDD
PFD data register
Ö
Ö
Ö
00H
34H
PF
Port F data register
Ö
¾
¾
00H
35H
PFC
Port F control register
Ö
¾
¾
00H
36H
PG
Port G data register
Ö
¾
¾
00H
37H
PGC
Port G control register
Ö
¾
¾
General Purpose RAM
00H
40H~FFH BANK0 RAM General purpose RAM space
Ö
Ö
Ö
01H
40H~FFH BANK1 RAM General purpose RAM space
Ö
Ö
Ö
02H
40H~FFH BANK2 RAM General purpose RAM space
Ö
Ö
Ö
03H
40H~FFH BANK3 RAM General purpose RAM space
Ö
Ö
Ö
04H
40H~FFH BANK4 RAM General purpose RAM space
Ö
Ö
Ö
05H
40H~FFH BANK5 RAM General purpose RAM space
Ö
Ö
Ö
06H
40H~FFH BANK6 RAM General purpose RAM space
Ö
Ö
¾
07H
40H~FFH BANK7 RAM General purpose RAM space
Ö
Ö
¾
08H
40H~FFH BANK8 RAM General purpose RAM space
Ö
Ö
¾
09H
40H~FFH BANK9 RAM General purpose RAM space
Ö
Ö
¾
0AH
40H~FFH BANK10 RAM General purpose RAM space
Ö
Ö
¾
0BH
40H~FFH BANK11 RAM General purpose RAM space
Ö
¾
¾
0CH
40H~FFH BANK12 RAM General purpose RAM space
Ö
¾
¾
0DH
40H~FFH BANK13 RAM General purpose RAM space
Ö
¾
¾
0EH
40H~FFH BANK14 RAM General purpose RAM space
Ö
¾
¾
LCD RAM Display Memory
1BH
Rev. 1.50
40H~9FH
LCD RAM
LCD RAM mapping space for COM0~COM15 (see ²LCD Driver² function)
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May 26, 2005
HT95CXXX
Indirect Addressing Register
also records the status information and controls the operation sequence.
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write operation of [00H] and [02H] will access the memory
pointed to by MP0 and MP1, respectively. Reading location [00H] or [02H] indirectly returns the result 00H,
while writing it leads to no operation. MP0 is indirectly
addressable in bank0, but MP1 is available for all banks
by switch BP [04H]. If BP is unequal to 00H, the indirect
addressing mode to read/write operation from 00H~3FH
will return the result as same as the value of bank0.
Except for the TO and PDF flags, bits in the status register can be altered by instructions, similar to the other
registers. Data written into the status register will not
change the TO or PDF flag. Operations related to the
status register may yield different results from those intended. The TO flag can be affected only by system
power-up, a WDT time-out or executing the ²CLR WDT²
or ²HALT² instruction. The PDF flag can be affected only
by executing the ²HALT² or ²CLR WDT² instruction or
during a system power-up.
The memory pointer registers MP0 and MP1 are 8-bits
registers, and the bank pointer register BP is 6-bits register for the HT95C400/40P or 5-bits for the other devices in the series.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
On entering the interrupt sequence or executing the
subroutine call, the status register will not be automatically pushed onto the stack.
Accumulator
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can operate with immediate data. All data movement
between two data memory locations must pass through
the accumulator.
If the contents of the status are important and if the subroutine can corrupt the status register, precautions must
be taken to save it.
Interrupt
Arithmetic and Logic Unit - ALU
The telephone controller provides an external interrupt,
internal timer/event counter interrupt, a peripheral interrupt, an internal real time clock interrupt and internal dialer I/O interrupt. The Interrupt Control Registers 0 and
Interrupt Control Register 1 both contains the interrupt
control bits that set the enable/disable and the interrupt
request flags.
This circuit performs 8-bit arithmetic and logic operations and provides the following functions:
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by hardware clearing the EMI
bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only the interrupt request flag is recorded. If a
certain interrupt requires servicing within the service
routine, the EMI bit and the corresponding bit of the
INTC0 (INTC1) may be set to allow interrupt nesting.
· Branch decision (SZ, SNZ, SIZ, SDZ, etc.)
The ALU not only saves the results of a data operation
but also changes the status register.
Status Register - STATUS
This status register contains the carry flag (C), auxiliary
carry flag (AC), zero flag (Z), overflow flag (OV), power
down flag (PDF), and watchdog time-out flag (TO). It
Bit No.
Label
Function
0
C
C is set if the operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. Also it is affected by a rotate
through carry instruction.
1
AC
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
3
OV
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared when either a system power-up or executing the ²CLR WDT² instruction. PDF
is set by executing the ²HALT² instruction.
5
TO
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is
set by a WDT time-out.
6, 7
¾
Unused bit, read as ²0²
Z is set if the result of an arithmetic or logic operation is 0; otherwise Z is cleared.
STATUS (0AH) Register
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May 26, 2005
HT95CXXX
The Timer/Event Counter 1 interrupt is generated by a
timeout overflow and the interrupt request flag T1F will
be set. When the Timer/Event Counter 1 interrupt is enabled, the stack is not full and the T1F bit is set, a subroutine call to location 0CH will occur. The interrupt
request flag T1F and EMI bits will be cleared to disable
further interrupts.
If the stack is full, any other interrupt request will not be
acknowledged, even if the related interrupt is enabled,
until the stack pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full.
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified location in the program memory. Only the program counter is pushed onto
the stack. If the contents of the register or status register
(STATUS) are altered by the interrupt service program
which corrupts the desired control sequence, the contents should be saved in advance.
The peripheral interrupt is activated when the FSK decoder detect the ring signal or line reversal or FSK carrier signal or FSK packet data. When these interrupts
occurred, the interrupt request flag PERF will be set.
When the peripheral interrupt is enabled, the stack is not
full and the PERF is set, a subroutine call to location
10H will occur. The interrupt request flag PERF and EMI
bits will be cleared to disable other interrupts.
External interrupt is triggered by a high to low transition
of the INT/TMR1 pin and the interrupt request flag EIF
will be set. When the external interrupt is enabled, the
stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag EIF and EMI bits will be cleared to disable
other interrupts.
The real time clock interrupt is generated by a 1Hz RTC
generator. When the RTC time-out occurs, the interrupt
request flag RTCF will be set. When the RTC interrupt is
enabled, the stack is not full and the RTCF is set, a subroutine call to location 14H will occur. The interrupt request flag RTCF and EMI bits will be cleared to disable
other interrupts.
The Timer/Event Counter 0 interrupt is generated by a
timeout overflow and the interrupt request flag T0F will
be set. When the Timer/Event Counter 0 interrupt is enabled, the stack is not full and the T0F bit is set, a subroutine call to location 08H will occur. The interrupt
request flag T0F and EMI bits will be cleared to disable
further interrupts.
Bit No.
The dialer I/O interrupt is triggered by any edge transition onto HKS pin or a falling edge transition onto HDI
pin or a rising edge transition onto HFI pin, the interrupt
request flag DRF will be set. When the dialer I/O interrupt is enabled, the stack is not full and the DRF is set, a
subroutine call to location 18H will occur. The interrupt
request flag DRF and EMI bits will be cleared to disable
other interrupts.
Label
R/W
0
EMI
RW
Controls the master (global) interrupt (1=enabled; 0=disabled)
Function
1
EEI
RW
Controls the external interrupt (1=enabled; 0=disabled)
2
ET0I
RW
Controls the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled)
3
ET1I
RW
Controls the Timer/Event Counter1 interrupt (1=enabled; 0=disabled)
4
EIF
RW
External interrupt request flag (1=active; 0=inactive)
5
T0F
RW
Timer/Event Counter 0 request flag (1=active; 0=inactive)
6
T1F
RW
Timer/Event Counter1 request flag (1=active; 0=inactive)
7
¾
RO
Unused bit, read as ²0²
INTC0 (0BH) Register
Bit No.
Label
R/W
0
EPERI
RW
Control the peripheral interrupt (1=enable; 0=disable)
Function
1
ERTCI
RW
Control the real time clock interrupt (1=enable; 0=disable)
2
EDRI
RW
Control the dialer I/O interrupt (1=enable; 0=disable)
3
¾
RO
Unused bit, read as ²0²
4
PERF
RW
Peripheral interrupt request flag (1=active; 0=inactive)
5
RTCF
RW
Internal real time clock interrupt request flag (1=active; 0=inactive)
6
DRF
RW
Internal dialer I/O interrupt request flag (1=active: 0=inactive)
7
¾
RO
Unused bit, read as ²0²
INTC1 (1EH) Register
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May 26, 2005
HT95CXXX
Note: 1. If the dialer status is on-hook and hold-line,
the falling edge transition onto HDI pin will not
generate the dialer I/O interrupt.
The WDT OSC is a free running on-chip RC oscillator,
and no external components are required. Even if the
system enters the Idle mode (the system clock is
stopped), the WDT OSC still works within a period of
78ms normally. When the WDT is disabled or the WDT
source is not this RC oscillator, the WDT OSC will be
disabled.
2. The dialer I/O interrupt will be disabled when
the operation mode is in Idle mode.
During the execution of an interrupt subroutine, other interrupt acknowledge signals are held until the RETI instruction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, ²RET² or ²RETI²
may be invoked. RETI will set the EMI bit to enable an
interrupt service, but RET will not.
X 1
X 2
X C
3 n F
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Interrupt Source
Priority
1
04H
Timer/Event Counter 0 interrupt
2
08H
Timer/Event Counter 1 interrupt
3
0CH
Peripheral interrupt
4
10H
Real time clock interrupt
5
14H
Dialer I/O interrupt
6
18H
Watchdog Timer - WDT
The WDT clock source is implemented by a WDT OSC
or external 32768Hz or an instruction clock (system
clock divided by 4), determined by the mask option. This
timer is designed to prevent a software malfunction or
sequence from jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by mask option. If the Watchdog Timer is disabled,
all the executions related to the WDT result in no operation.
If the device operates in a noisy environment, using the
on-chip WDT OSC or 32768Hz crystal oscillator is
strongly recommended.
Priority of the Interrupt
EMI, EEI, ET0I, ET1I, EPERI, ERTCI and EDRI are
used to control the enabling/disabling of interrupts.
These bits prevent the requested interrupt from being
serviced. Once the interrupt request flags (EIF, T0F,
T1F, PERF, RTCF, DRF) are set by hardware or software, they will remain in the INTC0 or INTC1 registers
until the interrupts are serviced or cleared by a software
instruction.
When the WDT clock source is selected, it will be first divided by 512 (9-stage) to get the nominal time-out period. By invoking the WDT prescaler, longer time-out
periods can be realized. Writing data to WS2, WS1,
WS0 can give different time-out periods.
The WDT OSC period is 78ms. This time-out period may
vary with temperature, VDD and process variations. The
WDT OSC always works for any operation mode.
It is recommended that a program should not use the
²CALL subroutine² within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only
one stack is left and enabling the interrupt is not well
controlled, the original control sequence will be damaged once the ²CALL² operates in the interrupt subroutine.
If the instruction clock is selected as the WDT clock
source, the WDT operates in the same manner except in
the Sleep mode or Idle mode. In these two modes, the
WDT stops counting and lose its protecting purpose. In
this situation the logic can only be re-started by external
logic.
If the WDT clock source is the 32768Hz, the WDT also
operates in the same manner except in the Idle mode.
Oscillator Configuration
There are two oscillator circuits in the controller, the external 32768Hz crystal oscillator and internal WDT
OSC.
3 2 7 6 8 H z
W D T O S C
S y s te m
The 32768Hz crystal oscillator and frequency-up conversion circuit (32768Hz to 3.58MHz) are designed for
dual system clock source. It is necessary for frequency
conversion circuit to add external RC components to
make up the low pass filter that stabilize the output frequency 3.58MHz (see the oscillator circuit).
Rev. 1.50
5 0 n F
System Oscillator Circuit
Vector
External interrupt
1 5 k W
C lo c k /4
M a s k
O p tio n
S e le c t
W D T P r e s c a le r
9 - b it C o u n te r
W S 0 ~ W S 2
7 - b it C o u n te r
8 -to -1 M U X
W D T T im e - o u t
Watchdog Timer
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May 26, 2005
HT95CXXX
Bit No.
Label
R/W
Function
0
1
2
WS0
WS1
WS2
RW
Watchdog Timer division ratio selection bits
Bit 2, 1, 0=000, Division ratio=1:1
Bit 2, 1, 0=001, Division ratio=1:2
Bit 2, 1, 0=010, Division ratio=1:4
Bit 2, 1, 0=011, Division ratio=1:8
Bit 2, 1, 0=100, Division ratio=1:16
Bit 2, 1, 0=101, Division ratio=1:32
Bit 2, 1, 0=110, Division ratio=1:64
Bit 2, 1, 0=111, Division ratio=1:128
7~3
¾
RW
Unused bit. These bits are read/write-able.
WDTS (09H) Register
²CLR WDT1² and ²CLR WDT2² are chosen (i.e. Two
clear instructions), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset
the chip as a result of time-out.
When in the Idle mode, the 32768Hz stops, the WDT
stops counting and lose its protecting purpose. In this
situation the logic can only be re-started by external
logic.
The high nibble and bit3 of the WDTS are reserved for
user defined flags, which can be used to indicate some
specified status.
Controller Operation Mode
Holtek¢s telephone controllers support two system clock
and four operation modes. The system clock could be
32768Hz or 3.58MHz and operation mode could be Normal, Green, Sleep or Idle mode. These are all selected
by the software.
The WDT time-out under Normal mode or Green mode
will initialize ²chip reset² and set the status bit ²TO². But
in the Sleep mode or Idle mode, the time-out will initialize a ²warm reset² and only the program counter and
stack pointer are reset to 0. To clear the WDT contents
(including the WDT prescaler), three methods are
adopted; external reset (a low level to RES pin), software instruction and a ²HALT² instruction.
The following conditions will force the operation mode to
change to Green mode:
· Any reset condition from any operation mode
· Any interrupt from Sleep mode or Idle mode
· Port A wake-up from Sleep mode or Idle mode
The software instruction include ²CLR WDT² and the
other set ²CLR WDT1² and ²CLR WDT2². Of these two
types of instruction, only one can be active depending
on the mask option ²WDT instr². If the ²CLR WDT² is selected (i.e. One clear instruction), any execution of the
CLR WDT instruction will clear the WDT. In the case that
How to change the Operation Mode
· Normal mode to Green mode:
Clear MODE1 to 0, then operation mode is changed to
Green mode but the UPEN status is not changed.
However, UPEN can be cleared by software.
Bit No.
Label
R/W
Function
4~0
¾
RO
Unused bit, read as ²0²
5
UPEN
RW
1: Enable frequency up conversion function to generate 3.58MHz
0: Disable frequency up conversion function to generate 3.58MHz
6
MODE0
RW
1: Disable 32768Hz oscillator while the HALT instruction is executed
(Idle mode)
0: Enable 32768Hz oscillator while the HALT instruction is executed
(Sleep mode)
7
MODE1
RW
1: Select 3.58MHz as CPU system clock
0: Select 32768Hz as CPU system clock
MODE (26H) Register
Operation Mode Description
HALT
Instruction
MODE1
MODE0
UPEN
Operation
Mode
32768Hz
Not execute
1
X
1
Normal
ON
ON
3.58MHz
Not execute
0
X
0
Green
ON
OFF
32768Hz
Be executed
0
0
0
Sleep
ON
OFF
HALT
Be executed
0
1
0
Idle
OFF
OFF
HALT
3.58MHz
System
Clock
Note: ²X² means don¢t care
Rev. 1.50
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May 26, 2005
HT95CXXX
· Normal mode or Green mode to Sleep mode:
resume to Green mode. In other words, a dummy period
is inserted after a wake-up. If the wake-up results from
an interrupt acknowledge signal, the actual interrupt
subroutine execution will be delayed by one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately after the dummy
period is finished.
Step 1: Clear MODE0 to 0
Step 2: Clear MODE1 to 0
Step 3: Clear UPEN to 0
Step 4: Execute HALT instruction
After Step 4, operation mode is changed to Sleep
mode.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the Sleep mode
or Idle mode.
· Normal mode or Green mode to Idle mode:
Step 1: Set MODE0 to 1
Step 2: Clear MODE1 to 0
Step 3: Clear UPEN to 0
Step 4: Execute HALT instruction
After Step 4, operation mode is changed to Idle mode.
The Sleep mode or Idle mode is initialized by the HALT
instruction and results in the following.
· The system clock will be turned off.
· Green mode to Normal mode:
· The WDT function will be disabled if the WDT clock
source is the instruction clock.
Step 1: Set UPEN to 1
Step 2: Software delay 20ms
Step 3: Set MODE1 to 1
After Step 3, operation mode is changed to Normal
mode.
· The WDT function will be disabled if the WDT clock
source is the 32768Hz in Idle mode.
· The WDT will still function if the WDT clock source is
the WDT OSC.
· If the WDT function is still enabled, the WDT counter
· Sleep mode or Idle mode to Green mode:
and WDT prescaler will be cleared and recounted
again.
· The contents of the on chip RAM and registers remain
unchanged.
Method 1: Any reset condition occurred
Method 2: Any interrupt is active
Method 3: Port A wake-up
Note
The Timer0, Timer1, RTC and dialer I/O interrupt
function will not work at the Idle mode because
the 32768Hz crystal is stopped.
· All the I/O ports maintain their original status.
· The flag PDF is set and the flag TO is cleared by hard-
ware.
The reset conditions include power on reset, external reset, WDT time-out reset. By examining the processor
status flag, PDF and TO, the program can distinguish
between different ²reset conditions². Refer to the Reset
function for detailed description.
Reset
There are three ways in which a reset can occur.
· Power on reset.
· A low pulse onto RES pin.
The port A wake-up and interrupt can be considered as
a continuation of normal execution. Each bit in port A
can be independently selected to wake-up the device by
mask option. Awakening from Port A stimulus, the program will resume execution of the next instruction.
· WDT time-out.
After these reset conditions, the Program Counter and
Stack Pointer will be cleared to 0.
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the system is reset or awakes from the Sleep or Idle operation
mode.
Any valid interrupts from Sleep mode or Idle mode may
cause two sequences. One is if the related interrupt is
disabled or the interrupt is enabled but the stack is full,
the program will resume execution at the next instruction. The other is if the interrupt is enabled and the stack
is not full, the regular interrupt response takes place. It is
necessary to mention that if an interrupt request flag is
set to ²1² before entering the Sleep mode or Idle mode,
the wake-up function of the related interrupt will be disabled.
V
1 0 0 k W
R E S
0 .1 m F
Once a Sleep mode or Idle mode wake-up event occurs,
it will take SST delay time (1024 system clock period) to
Rev. 1.50
D D
Reset Circuit
18
May 26, 2005
HT95CXXX
By examining the processor status flags PDF and TO,
the software program can distinguish between the different ²chip resets².
TO
PDF
The functional units chip reset status are shown below:
Reset Condition
0
0
Power on reset
u
u
External reset during Normal mode or
Green mode
0
1
External reset during Sleep mode or
Idle mode
1
u
WDT time-out during Normal mode or
Green mode
1
1
WDT time-out during Sleep mode or
Idle mode
Program Counter
000H
Interrupt
Disabled
Prescaler
Cleared
WDT
Cleared
After a master reset,
WDT begins counting.
(If WDT function is enabled
by mask option)
Timer/Event Counter 0/1 Off
Input/output Port
Input mode
Stack Pointer
Points to the top of the stack
Note: ²u² means ²unchanged²
H A L T
W D T
E x te rn a l
W a rm
W D T T im e - o u t
R e s e t
V D D
R E S
C o ld R e s e t
R E S
S S T
1 0 - b it R ip p le
C o u n te r
S Y S C L K
S y s te m
tS
S T
S S T T im e - o u t
C h ip
R e s e t
Reset Timing Chart
R e s e t
Reset Configuration
When the reset conditions occurred, some registers may be changed or unchanged. (HT95C400/40P)
Reset Conditions
Register
Addr.
IAR0
Power On
RES Pin
RES Pin
(Sleep/Idle)
WDT
WDT
(Sleep/Idle)
00H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP0
01H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
IAR1
02H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
03H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
BP
04H
---0 0000
---0 0000
---0 0000
---0 0000
---u uuuu
ACC
05H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
PCL
06H
0000H
0000H
0000H
0000H
0000H
TBLP
07H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
08H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
WDTS
09H
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
STATUS
0AH
--00 xxxx
--uu uuuu
--01 uuuu
--1u uuuu
--11 uuuu
INTC0
0BH
-000 0000
-000 0000
-000 0000
-000 0000
uuuu uuuu
TMR0H
0CH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0L
0DH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0C
0EH
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
TMR1H
0FH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR1L
10H
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR1C
11H
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
Rev. 1.50
19
May 26, 2005
HT95CXXX
Reset Conditions
Register
Addr.
PA
Power On
RES Pin
RES Pin
(Sleep/Idle)
WDT
WDT
(Sleep/Idle)
12H
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
13H
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
14H
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
15H
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
DialerIO
16H
111x xxxx
111x xxxx
111x xxxx
111x xxxx
uuuu uuuu
PD
18H
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PDC
19H
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PE
1AH
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
PEC
1BH
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
INTC1
1EH
-000 -000
-000 -000
-000 -000
-000 -000
-uuu -uuu
TBHP
1FH
--xx xxx
--uu uuuu
--uu uuuu
--uu uuuu
--uu uuuu
DTMFC
20H
---- -0-1
---- -0-1
---- -0-1
---- -0-1
---- -u-u
DTMFD
21H
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
LINE
22H
0--- ----
u--- ----
u--- ----
u--- ----
u--- ----
RTCC
24H
0-0- ----
u-u- ----
u-u- ----
u-u- ----
u-u- ----
MODE
26H
000- ----
00u- ----
000- ----
00u- ----
000- ----
LCDIO
28H
000- ----
uuu- ----
uuu- ----
uuu- ----
uuu- ----
FSKC
29H
--11 11-1
--11 11-1
--11 11-1
--11 11-1
--uu uu-u
FSKS
2AH
-x0- 1100
-x0- 1100
-x0- 1100
-x0- 1100
-xu- uuuu
FSKD
2BH
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
LCDC
2DH
0000 -000
uuuu -uuu
uuuu -uuu
uuuu -uuu
uuuu -uuu
PFDC
2EH
0000 ----
0000 ----
0000 ----
0000 ----
uuuu ----
PFDD
2FH
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PF
34H
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PFC
35H
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PG
36H
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
PGC
37H
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
x
u
u
u
u
RAM (Data & LCD)
Note: ²u² means ²unchanged²
²x² means ²unknown²
²-² means ²unused²
intervals or pulse width, or generate an accurate time
base.
Timer/Event Counter
Two timer/event counters (TMR0, TMR1) are implemented in the telephone controller series. The
Timer/Event Counter 0 and Timer/Event Counter 1 contain 16-bits programmable count-up counter and the
clock may come from an external or internal source. For
TMR0, the internal source is the instruction clock (system clock/4). For TMR1, the internal source is 32768Hz.
There are 3 registers related to the Timer/Event Counter
0; TMR0H, TMR0L and TMR0C. Writing TMR0L only
writes the data into a low byte buffer, but writing TMR0H
simultaneously writes the data along with the contents
of the low byte buffer into the Timer/Event Counter 0
preload register (16-bit). The Timer/Event Counter 0
preload register is changed by writing TMR0H operations. Writing TMR0L will keep the Timer/Event Counter
0 preload register unchanged.
Using the 32768Hz clock or instruction clock, there is
only one reference time-base. The external clock input
allows the user to count external events, measure time
Rev. 1.50
20
May 26, 2005
HT95CXXX
Reading TMR0H latches the TMR0L into the low byte
buffer to avoid a false timing problem. Reading TMR0L
returns the contents of the low byte buffer. In other
words, the low byte of the Timer/Event Counter 0 can
not be read directly. It must read the TMR0H first to
make the low byte contents of Timer/Event Counter 0 be
latched into the buffer.
Timer/Event Counter 0 and is defined by TMR1C. The
timer/event counter control registers define the operating mode, counting enable or disable and active edge.
The T0M0/T1M0, T0M1/T1M1 bits define the operating
mode. The event count mode is used to count external
events, which means the clock source comes from an
external (TMR0 or INT/TMR1) pin. The timer mode functions as a normal timer with the clock source coming
from instruction clock (TMR0) or 32768Hz (TMR1). The
pulse width measurement mode can be used to count
the high or low level duration of the external signal
(TMR0 or INT/TMR1). The counting is based on the
32768Hz clock for TMR1 or instruction clock for TMR0.
There are 3 registers related to the Timer/Event Counter
1; TMR1H, TMR1L and TMR1C. The Timer/Event
Counter 1 operates in the same manner as the
Timer/Event Counter 0.
The TMR0C is the Timer/Event Counter 0 control register, which defines the Timer/Event Counter 0 options.
The Timer/Event Counter 1 has the same options as the
T im e r 0 : In s tr u c tio n c lo c k ( s y s te m
T im e r 1 : 3 2 7 6 8 H z
IN T /T M R 1
T M R 0
c lo c k /4 )
D a ta B u s
T 0 M 1 /T 1 M 1
T 0 M 0 /T 1 M 0
T im e r /E v e n t C o u n te r 0 /1
P r e lo a d R e g is te r
T 0 E /T 1 E
T 0 M 1 /T 1 M 1
T 0 M 0 /T 1 M 0
T 0 O N /T 1 O N
T im e r /e v e n t
C o u n te r 0 /1
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
L o w
R e lo a d
O v e r flo w
to In te rru p t
B y te B u ffe r
Timer/Event Counter 0/1
Bit No.
Label
R/W
Function
0~2
¾
RO
Unused bit, read as ²0²
3
T0E/T1E
RW
To define the TMR0/TMR1 active edge of timer
For event count or Timer mode
(0=active on low to high; 1=active on high to low)
For pulse width measurement mode
(0=measures low pulse width; 1=measures high pulse width)
4
T0ON/T1ON
RW
To enable/disable timer counting (0=disabled; 1=enabled)
5
¾
RO
Unused bit, read as ²0²
RW
To define the operating mode
Bit 7, 6=01, Event count mode (external clock)
Bit 7, 6=10, Timer mode
Bit 7, 6=11, Pulse width measurement mode
Bit 7, 6=00, Unused
6
7
T0M0/T1M0
T0M1/T1M1
TMR0C (0EH)/TMR1C (11H) Register
Register
Bit No.
R/W
Function
TMR0H (0CH)
0~7
RW
Timer/Event Counter 0 higher-order byte register
TMR0L (0DH)
0~7
RW
Timer/Event Counter 0 lower-order byte register
TMR1H (0FH)
0~7
RW
Timer/Event Counter 1 higher-order byte register
TMR1L (10H)
0~7
RW
Timer/Event Counter 1 lower-order byte register
Rev. 1.50
21
May 26, 2005
HT95CXXX
Input/Output Ports
In the event count or timer mode, once the timer/event
counter starts counting, it will count from the current
contents in the timer/event counter to FFFFH. If an overflow occurs, the counter is reloaded from the timer/event
counter preload register and generates the corresponding interrupt request flag (T0F/T1F) at the same time.
There is a maximum of 40 bidirectional input/output
lines in the HT95CXXX family MCU, labeled as PA, PB,
PD, PE, PF and PG. All of these I/O ports can be used
for input and output operations. For input operation,
these ports are non-latching, that is, the inputs must be
ready at the T2 rising edge of instruction “MOV A,[m]”
(m=12H, 14H, 18H, 1AH, 34H or 36H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten.
I n p u lse w i dt h m e a s ur e m e n t m ode w i t h t h e
T0ON/T1ON and T0E/T1E bits equal to 1, once the
TMR0/TMR1 pin has received a transient from low to
high (or high to low; if the T0E/T1E bit is 0) it will start
counting until the TMR0/TMR1 pin returns to the original
level and resets the T0ON/T1ON. The measured result
will remain in the timer/event counter even if the activated transient occurs again. In other words, only 1 cycle measurement can be done. Until setting the
T0ON/T1ON, the cycle measurement will function again
as long as it receives further transient pulse. Note that,
in this operating mode, the timer/event counter starts
counting not according to the logic level but according to
the transient edges. In the case of counter overflows,
the counter is reloaded from the timer/event counter
preload register and continue to measure the width and
issues the interrupt request just like the other two
modes.
Each I/O line has its own control register (PAC, PBC,
PDC, PEC, PFC, PGC) to control the input/output configuration. With this control register, CMOS output or
Schmitt trigger input can be reconfigured dynamically
under software control. To make one I/O line to function
as an input line, the corresponding latch of the control
register must be written with a ²1². The pull-high resistance shows itself automatically if the pull-high option is
selected. The input source also depends on the control
register. If the control register bit is ²1², the input will
read the pad state. If the control register bit is ²0², the
contents of the latches will move to the internal bus. The
latter is possible in the ²read-modify-write² instruction.
For output function, CMOS is the only configuration.
Each bit of these input/output latches can be set or
cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H,
18H, 1AH, 34H or 36H) instructions.
To enable the counting operation, the timer on bit
(T0ON/T1ON) should be set to 1. In the pulse width
measurement mode, the T0ON/T1ON will be cleared
automatically after the measurement cycle is completed. But in the other two modes the T0ON/T1ON can
only be reset by instruction. The overflow of the
timer/event counter is one of the wake-up sources. No
matter what the operation mode is, writing a 0 to
ET0I/ET1I can disable the corresponding interrupt service.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability of waking-up the
device. They are selected by mask option per bit.
In the case of timer/event counter off condition, writing
data to the timer/event counter preload register also reloads that data to the timer/event counter. But if the
timer/event counter is turned on, data written to the
timer/event counter is reserved only in the timer/event
counter preload register. The timer/event counter will go
on operating until an overflow occurs.
There is a pull-high option available for all I/O lines.
Once the pull-high option of an I/O line is selected, the
I/O lines have pull-high resistor. Otherwise, the pull-high
resistor is absent. It should be noted that a non-pull-high
I/O line operating in input mode may cause a floating
state.
I/O port pull-high, wake-up function are selected by mask option
I/O Port
Output
Input
Supported for HT95CXXX
Pull-high Resistor Wake-up Function
400/40P
300/30P
200/20P
PA7~PA0
CMOS
Selected per bit
Selected per bit
Ö
Ö
Ö
PB7~PB0
CMOS
Selected per bit
¾
Ö
Ö
Ö
PD7~PD0
CMOS
Selected per nibble
¾
Ö
Ö
Ö
PE3~PE0
CMOS
Selected per nibble
¾
Ö
Ö
Ö
PF7~PF0
CMOS
Selected per nibble
¾
Ö
¾
¾
PG3~PG0
CMOS
Selected per nibble
¾
Ö
¾
¾
Note: ²¾² means unavailable
Rev. 1.50
22
May 26, 2005
HT95CXXX
V
C o n tr o l B it
D a ta B u s
P U
Q
D
C K
W r ite C o n tr o l R e g is te r
D D
Q B
S
C h ip R e s e t
A ll I/O
R e a d C o n tr o l R e g is te r
P in s
D a ta B it
Q
D
C K
W r ite D a ta R e g is te r
Q B
S
M
R e a d D a ta R e g is te r
S y s te m W a k e -u p
( P A o n ly )
U
X
P A W a k e - u p O p tio n 0 ~ 7
Input/Output Ports
Some input/output pins can be optioned to LCD outputs by software.
Bit No.
Label
R/W
5
SPE0
RW
7
6
1
SPD1
SPD0
VBIAS
Value
400/40P
300/30P
200/20P
0
SEG47~SEG44
¾
1
PE3~PE0
¾
0
SEG43~SEG40
¾
1
PD7~PD4
¾
0
SEG39~SEG36
¾
1
PD3~PD0
¾
0
COM7~COM0
COM7~COM0
1
COM7~COM0 are unavailable
PD7~PD0
RW
RW
RW
LCDIO (28H) Register
Bit No.
Label
R/W
1
VBIAS
RW
Value
400/40P
300/30P
200/20P
0
COM7~COM0
COM7~COM0
1
COM7~COM0 are unavailable
PD7~PD0
LCDC (2DH) Register
abled. These interrupts will cause a peripheral interrupt
if the peripheral interrupt is enabled.When the peripheral interrupt occurs, the interrupt request flag PERF will
be set and a subroutine call to location 10H will occur.
Returning from the interrupt subroutine, the interrupt
flag RDETF, CDETF or FSKF will not be cleared by
hardware, the user should clear it by software. If interrupt flag RDETF is not cleared, next ring detect interrupt
will be inhibited, other interrupt flags CDETF, FSKF
have the same behavior. The power down mode
(F_PWDN=1) will terminate all the FSK decoder function, however, the registers FSKC, FSKS and FSKD are
accessible at this power down mode.
When the PD0~PD7 or the PE0~PE3 are not selected,
the I/O port control register PDC(19H), PEC(1BH) could
be readable/writable and be used as a general user
RAM, but this function is not available for register PD
(18H) and PE (1AH).
FSK Decoder
The FSK decoder supports three interrupt sources to
the peripheral interrupt vector. There are ring detect or
line reversal detect, FSK carrier detect and FSK packet
data. Write 0 to the control flag, RMSK, CMSK and
FMSK will enable these interrupt. When any of these interrupt occurs, its interrupt flag (RDETF, CDETF, FSKF)
will be set to 1 by hardware even if the interrupt is dis-
Rev. 1.50
23
May 26, 2005
HT95CXXX
Bit No.
Label
R/W
Function
0
F_PWDN
RW
FSK decoder power down
1: FSK decoder is at power down mode
0: FSK decoder is at operation mode
1
¾
RO
Unused bit, read as ²0²
2
FMSK
RW
FSK packet data interrupt mask
1: Disable FSK packet data interrupt
0: Enable FSK packet data interrupt
3
RMSK
RW
Ring or line reversal detect interrupt mask
1: Disable ring or line reversal detect interrupt
0: Enable ring or line reversal detect interrupt
4
CMSK
RW
Carrier detect interrupt mask
1: Disable carrier detect interrupt
0: Enable carrier detect interrupt
5
FSKSEL
RW
Select FSK packet data source
1: FSK packet data source is DOUTC
0: FSK packet data source is DOUT
6, 7
¾
RO
Unused bit, read as ²0²
FSKC (29H) Register
Bit No.
0
Label
RDETF
R/W
Function
RW
Ring or line reversal detect interrupt flag
1: Ring or line reversal detected
0: No ring or line reversal detected
This flag is set by hardware and cleared by software.
1
CDETF
RW
FSK carrier detect interrupt flag
1: An FSK carrier signal is detected
0: No valid FSK carrier signal is detected
This flag is set by hardware and cleared by software.
2
DOUT
RO
This flag presents the FSK decoder output when the decoder is at operation
mode. This data stream includes the alternate 1 and 0 pattern, the marking and
the data.
3
DOUTC
RO
This flag present the FSK decoder output like as the DOUT flag but does not include the alternate 1 and 0 pattern.
4
¾
RO
Unused bit, read as ²0²
5
FSKF
RW
FSK packet data interrupt flag
1: FSK packet data is ready
0: FSK packet data is not ready
This flag is set by hardware and cleared by software.
6
RINGF
RO
This flag presents the ring coming signal. Refer to the following figure.
7
¾
RO
Unused bit, read as ²0²
FSKS (2AH) Register
Bit No.
Label
R/W
7~0
¾
RO
Function
FSK packet data register
FSKD (2BH) Register
Rev. 1.50
24
May 26, 2005
HT95CXXX
Ring or Line Reversal Detect
The flag DOUT presents the output of the decoder when
the decoder is at operation mode. This data stream includes the alternate 1 and 0 pattern, the marking and
the data.
When no signal is present on the telephone line, RDET1
will be at GND and RTIME is pulled to VDD by R1. If a
line reversal occurs, the RDET1 pin will become high.
This causes RTIME and internal signal R_DET to be
pulled low. The C1 and R1 ensure that the R_DET signal
is low during such a time, so that processor can detect it.
The flag DOUTC presents the output of the decoder
when the decoder is at operation mode. This data
stream is like the DOUT flag but does not include the alternate 1 and 0 pattern.
When a ring occurs on the line, internal signal R_DET is
permanently low, indicating the envelope of the ring. If
the frequency of the ring must be measured, C1 may be
removed, RTIME and R_DET inverter follow RDET1.
If the FSK data is not detected, the DOUT and DOUTC
are held high.
Beside the serial data, the decoder also provides FSK
packet data. When decoder receives an FSK signal, it
will packet 10 bits data to 8 bits data, the first and 10th
bits will be discarded. When the 8-bit packet data is
valid, it will be stored in the FSK data register FSKD, the
FSK packet data interrupt flag FSKF will be set to 1. This
may cause a peripheral interrupt if FMSK is 0 and the
peripheral interrupt is enabled. The FSK packet source
could be DOUT or DOUTC, selected by FSKSEL. Note
that the start bit of the 10 packet bit should be 0, so the
MARK signal (one of the FSK data signals) will not be
packeted.
The flag RDETF will go high when the R_DET signal falling edge is detected. This may cause a peripheral interrupt if RMSK is 0 and the peripheral interrupt is enabled
(EPERI=1).
FSK Data Output
The FSK decoder will decode the FSK signal on the TIP
and RING line and produce two kinds of data formats,
the serial data and the 8-bit packet data. It also provides
the FSK carrier detection signal.
To enable the FSK decoder, the F_PWDN should be
written as 0. Once the FSK carrier signal is detected, the
flag CDETF will be set to 1. This may cause a peripheral
interrupt if CMSK is 0 and the peripheral interrupt is enabled.
To detect the carrier signal or decode the serial data or
packet 10-bit data to 8-bit data, the operation mode of
the controller must be selected in Normal mode (processor running with 3.58MHz). When the operation mode is
Green or Sleep, FSK decoder will decode the wrong signal. However, when the operation mode is Green or
Sleep mode and the FSK decoder is at power down
mode (F_PWDN=1), the ring and line reversal detect is
still functional.
The serial FSK data is present in two formats: RAW data
and COOK data, and could be monitored by the flag
DOUT, DOUTC, respectively.
R IN G F
T IP
R IN G
L in e
P r o te c tio n
N e tw o rk
C 1
2 S
R in g S ig n a l
R D E T F
F _ P W D N
C L O C K
R T IM E
0 .5 S
R 1
V
D D
0 .5 S
0 1 0 1 0 1 ...
F S K D A T A
1 1 1 1 1 ...
C le a r e d b y S o ftw a r e
tS
S o ftw a re C o n tro l
U P D
3 .5 8 M H z
R a w D A T A
D O U T
D O U T C
F S K D a ta
R _ D E T
R D E T 1
C o o k e d D A T A
* 5 5 ......
S y n c S ig n a l
8 - b it P a c k e te d F S K D A T A
M a r k S ig n a l
D A T A S ig n a l
Note: ²*² If the flag FSKSEL=1, the sync signal data will not be packeted.
Rev. 1.50
25
May 26, 2005
HT95CXXX
DTMF Generator
The DTMF (Dual Tone Multiple-Frequency) signal generator is implemented in the telephone controller. It can generate
16 dual tones and 8 single tones from the DTMF pin. This generator also supports power down, tone on/off function.
The DTMF generator clock source is 3.58MHz, before using this function, the system operation mode must be at Normal mode.
The power down mode (D_PWDN=1) will terminate all the DTMF generator function, however, the registers DTMFC
and DTMFD are accessible at this power down mode. The duration of DTMF output should be handled by the software.
DTMFD register value could be changed as desired, the DTMF pin will output the new dual-tone simultaneously.
Bit No.
Label
R/W
Function
0
D_PWDN
1
¾
RO
Unused bit, read as ²0²
2
TONE
RW
Tone output enable
1: DTMF signal output is enabled.
0: DTMF signal output is disabled.
3
¾
RW
Reserved, inhibit using.
4
¾
RW
Reserved, inhibit using.
5
¾
RO
Unused bit, read as ²0²
6
¾
RW
Reserved, inhibit using.
7
¾
RO
Unused bit, read as ²0²
DTMF generator power down
1: DTMF generator is at power down mode.
0: DTMF generator is at operation mode.
DTMFC (20H) Register
Note: Bit3, 4, 6 of DTMFC are reserved, always keep the initial value.
Bit No.
Label
R/W
3~0
TC4~TC1
RW
To set high group frequency
Function
7~4
TR4~TR1
RW
To set low group frequency
DTMFD (21H) Register
Note: Bit3, 4, 6 of DTMFC are reserved, always keep the initial value.
The DTMF pin output is controlled by the combination of the D_PWDN, TONE, TR~TC value.
Control Register Bits
DTMF Pin Output Status
D_PWDN
TONE
TR4~TR1/TC4~TC1
1
x
x
0
0
0
x
1/2 VDD
0
1
0
1/2 VDD
0
1
Any valid value
16 dual tones or 8 signal tones, bias with 1/2 VDD
D _ P D W N = 0
D _ P D W N = 1
1 /2 V D D
T O N E = 1
T O N E = 0
T O N E = 1
T O N E = 0
T O N E = 1
T O N E = 0
A ll th e tim in g o f th e T O N E = 1 a n d T O N E = 0 a r e d e te r m in e d b y s o ftw a r e
DTMF Output
Rev. 1.50
26
May 26, 2005
HT95CXXX
Tone frequency
Output Frequency (Hz)
% Error
Specified
Actual
697
699
+0.29%
770
766
-0.52%
852
847
-0.59%
941
948
+0.74%
1209
1215
+0.50%
1336
1332
-0.30%
1477
1472
-0.34%
% Error does not contain the crystal frequency shift
DTMF frequency selection table: register DTMFD[21H]
Low Group
High Group
DTMF Output
TR4
TR3
TR2
TR1
TC4
TC3
TC2
TC1
Low
High
DTMF
Code
0
0
0
1
0
0
0
1
697
1209
1
0
0
0
1
0
0
1
0
697
1336
2
0
0
0
1
0
1
0
0
697
1477
3
0
0
0
1
1
0
0
0
697
1633
A
0
0
1
0
0
0
0
1
770
1209
4
0
0
1
0
0
0
1
0
770
1336
5
0
0
1
0
0
1
0
0
770
1477
6
0
0
1
0
1
0
0
0
770
1633
B
0
1
0
0
0
0
0
1
852
1209
7
0
1
0
0
0
0
1
0
852
1336
8
0
1
0
0
0
1
0
0
852
1477
9
0
1
0
0
1
0
0
0
852
1633
C
1
0
0
0
0
0
0
1
941
1209
*
1
0
0
0
0
0
1
0
941
1336
0
1
0
0
0
0
1
0
0
941
1477
#
1
0
0
0
1
0
0
0
941
1633
D
Single tone for testing only
0
0
0
1
0
0
0
0
697
0
0
1
0
0
0
0
0
770
0
1
0
0
0
0
0
0
852
1
0
0
0
0
0
0
0
941
0
0
0
0
0
0
0
1
1209
0
0
0
0
0
0
1
0
1336
0
0
0
0
0
1
0
0
1477
0
0
0
0
1
0
0
0
1633
Writing other values to TR4~TR1, TC4~TC1 may generate an unpredictable tone.
Rev. 1.50
27
May 26, 2005
HT95CXXX
Dialer I/O Function
A special dialer I/O circuit is built into the telephone controller for dialing application. These specially designed I/O cells
allows the controller to work under a low voltage condition that usually happens when the subscriber¢s loop is long.
Dialer I/O pin function:
Name
I/O
Description
XMUTE
NMOS Output
XMUTE pin output is controlled by software. This is an NMOS open drain structure pulled to VSS during dialing signal transmission. Otherwise, it is an open
circuit. XMUTE is used to mute the speech circuit when transmitting the dialer
signal.
DNPO
NMOS Output
DNPO pin is an NMOS output, usually by means of software to make/break the
line.
This pin is only controlled by software.
PO
CMOS Output
This pin is controlled by the HKS, HFI and HDI pins.
When PO pin is high, the telephone line is make.
When PO pin is low, the telephone line is break.
HKS
Schmitt Trigger Input
This pin controls the PO pin directly.
This pin is used to monitor the status of the hook-switch and its combination
with HFI/HDI can control the PO pin output to make or break the line.
A rising edge to HKS pin will cause the dialer I/O to be on-hook status and generate an interrupt, its vector is 18H.
A falling edge to HKS pin will cause the dialer I/O to be off-hook status and clear
HFO and HDO flags to 0. This falling edge will also generate an interrupt, its
vector is 18H.
HDO
CMOS Output
This pin is controlled directly by HDI, HKS and HFI pin.
When HDO pin is high, the hold-line function is enabled and PO outputs a high
signal to make the line.
HDI
Schmitt Trigger Input
A low pulse to HDI pin (hold-line function request) will clear HFO to 0 and toggle
HDO and generates an interrupt, its vector is 18H.
This pin controls the HFO and HDO pins directly.
This pin is functional only when the line is made, that is, off-hook or hand-free
(PO output high signal).
HFO
CMOS Output
This pin is controlled directly by HFI, HDI and HKS pins.
When HFO pin is high, the hand-free function is enabled and PO outputs a high
signal to make the line.
HFI
Schmitt Trigger Input
A high pulse to HFI pin (hand-free function request) will clear HDO to 0 and toggle HFO and generates an interrupt, its vector is 18H.
This pin controls the PO, HFO and HDO pins directly.
The following are the recommended circuit for HFI and HDI pins.
V
D D
V
1 0 k W
H D I P in
H F I P in
0 .1 m F
Rev. 1.50
In te r n a l P u ll- lo w
2 0 0 k W
1 0 k W
28
D D
In te r n a l P u ll- h ig h 2 0 0 k W
0 .1 m F
May 26, 2005
HT95CXXX
Phone controller also supports the dialer I/O flag to monitor the dialer status.
Bit No.
Label
R/W
Function
0
HFI
RO
1: The HFI pin level is 1.
0: The HFI pin level is 0.
1
HFO
RO
1: The HFO pin level is 1.
0: The HFO pin level is 0.
2
HDI
RO
1: The HDI pin level is 1.
0: The HDI pin level is 0.
3
HDO
RO
1: The HDO pin level is 1.
0: The HDO pin level is 0.
4
HKS
RO
1: The HKS pin level is 1.
0: The HKS pin level is 0.
5
SPO
RW
1: The PO pin is controlled by the combination of the HKS, HFI and HDI pin.
0: The PO pin level is set to 0 by software.
6
SDNPO
RW
1: The DNPO pin level is set to floating by software.
0: The DNPO pin level is set to 0 by software.
7
XMUTE
RW
1: The XMUTE pin is set to floating by software.
0: The XMUTE pin is set to 0 by software.
DIALERIO (16H) Register
The SPO flag is special designed to control the PO. When the flag SPO is set to 1, the PO pin is controlled by the combination of the HKS pin, HFI pin and HDI pin. The PO pin will always be 0 if the flag SPO=0.
The relation between the Dialer I/O function (SPO=1)
Dialer I/O Pin (Flag) Status
Dialer Function
Result
HKS
HFO
HDO
PO
DNPO
Telephone Line
On-hook
1
0
0
0
floating
break
On-hook & Hand-free
1
1
0
1
floating
make
On-hook & Hold-line
1
0
1
1
floating
make
Off-hook
0
0
0
1
floating
make
Off-hook & Hand-free
0
1
0
1
floating
make
Off-hook & Hold-line
0
0
1
1
floating
make
The following describes the dialer I/O function status machine figure (Available on Normal mode, Green mode or Sleep
mode):
Off-hook: A falling edge to HKS pin
On-hook: A rising edge to HKS pin
H D I
HFI: A high pulse to HFI pin (Hand-free request is generated.)
O n -h o o k
HDI: A low pulse to HDI pin (Hold-line request is generated.)
H F I
O ff-h o o k
H a n d -fre e
O n -h o o k
O ff-h o o k
O n -h o o k
O ff-h o o k
O n -h o o k
H a n d -fre e
H F I
H F I
H D I
H F I
H D I
O ff-h o o k
H D I
O ff-h o o k
H o ld - lin e
H D I
O ff-h o o k
O n -h o o k
O n -h o o k
H o ld - lin e
Note: 1. If the dialer status is on-hook and hold-line, the falling edge transition onto HDI pin will not generate the dialer
I/O interrupt.
2. Dialer I/O function is not available in Idle mode
Rev. 1.50
29
May 26, 2005
HT95CXXX
Line Control Function
Bit No.
Label
R/W
Function
6~0
¾
RO
Unused bit, read as ²0²
7
LINEC
RW
1: Enable the line control function
0: Disable the line control function
LINE (22H) Register
The line control function is enabled by the flag LINEC
Conditions
LINEC
Operation Mode
Source to Enable
Line Control Function
1
Normal or Green mode
RTC time out interrupt
1
Sleep mode
Port A wake-up
RTC time out interrupt
1
Idle mode
Port A wake-up
When the line control source is activated, the PO pin will be set to high signal. Clearing LINEC to 0 will terminate the line
control function and drive PO pin outputs low signal.
R T C
In te rru p t
P o r t A W a k e - u p F u n c tio n
L in e C o n tr o l
C ir c u it
P O
= 1
L IN E C = 1
RTC Function
Bit No.
Label
R/W
Function
6, 4~0
¾
RO
Unused bit, read as ²0²
5
RTCEN
RW
1: Enable RTC function
0: Disable RTC function
7
RTCTO
RW
1: RTC time-out occurs
0: RTC time-out not occurs
RTCC (24H) Register
The real time clock (RTC) is used to supply a regular internal interrupt. Its time-out period is 1000ms. If the RTC
time-out occurs, the interrupt request flag RTCF and the
RTCTO flag will be set to 1. The interrupt vector for the
RTC is 14H. When the interrupt subroutine is serviced,
the interrupt request flag (RTCF) will be cleared to 0, but
the flag RTCTO remain in its original value. If the
RTCTO flag is not cleared, next RTC time-out interrupt
will occur.
V
R
1 .1 5 V R e fe r e n c e V o lta g e
1
R
2
L B F G
L B IN
L B E N
The battery low threshold is determined by external R1
and R2 resistors.
Low Battery Detection
The phone controller provides a circuit that detects the
LBIN pin voltage level. To enable this detection function, the LBEN should be written as 1. Once this function
is enabled, the detection circuit needs 50ms to be stable.
After that, the user could read the result from LBFG. The
low battery detect function will consume power. For
power saving, write 0 to LBEN if the low battery detection function is unnecessary.
Rev. 1.50
D E T
1.15=
VDETxR2
1.15x(R1+ R2)
® VDET=
R1+ R2
R2
If we want to detect VDET=2.4V
then 2.4V=
30
1.15x(R1+ R2)
® R1=1.087R2
R2
May 26, 2005
HT95CXXX
LCD Driver
Segment/Common to I/O Selection
The LCD driver can directly drive an LCD panel with 1/8
duty and 1/4 bias or with 1/16 duty and 1/5 bias, this
function is selected by the flag VBIAS. The frame of this
LCD driver may select a 64Hz or 128Hz by flag FRAME.
For the flexible purpose, some of the LCD COMMON
and SEGMENT pins are shared with the input/output
port.
Both of the HT95C400/40P and HT95C300/30P provide
12 pins to be selected to SEGMENT output pins or I/O
pins. HT95C200/20P provides 8 pins to be selected for
COMMON output pins or I/O pins.
LCD driver uses the voltage of the VLCD pin as the
power source. To adjust the view angle, the programmer
can select the real LCD power by the flags VCON0 and
VCON1. The flag LCDON is used to turn On/Off the LCD
display. Note that the VLCD voltage must equal or be
less than VDD.
Bit No.
0
Label
FRAME
All of the HT95C400/40P, HT95C300/30P and
HT95C200/20P provide the LCD COMMON output pins
for 8 COMMON or 16 COMMON. The description of the
relation between segment pins, common pins and I/O
pins are shown on the below.
R/W
Function
RW
LCD frame selection
0: LCD frame is 64Hz
1: LCD frame is 128Hz
1
VBIAS
RW
LCD BIAS selection
0: select 1/16 duty and 1/5 bias, COM15~COM0 are available
1: select 1/8 duty and 1/4 bias, only COM15~COM8 are available
When the 8 COM is selected
HT95C400/40P: COM7~COM0 will be optioned to unused pins
HT95C300/30P: COM7~COM0 will be optioned to unused pins
HT95C200/20P: COM7~COM0 are disabled, PD7~PD0 are available
2
LBEN
RW
Low battery detection switch
0: disable the low battery detection
1: enable the low battery detection
3
¾
RO
Unused bit, read as ²0²
4
LBFG
RO
Low battery detection flag
1: LBIN pin voltage is less than 1.15V
0: LBIN pin voltage is not less than 1.15V
5
6
VCON0
VCON1
RW
LCD contrast adjusting
Bit6,5=00: LCD voltage supply is 0.66´VLCD
Bit6,5=10: LCD voltage supply is 0.82´VLCD
Bit6,5=01: LCD voltage supply is 0.93´VLCD
Bit6,5=11: LCD voltage supply is 1.00´VLCD
7
LCDON
RW
1: Turn on the LCD display
0: Turn off the LCD display
LCDC (2DH) Register
Bit No.
Label
R/W
Function
0~4
¾
RO
Unused bit, read as ²0²
5
SPE0
RW
Supported for HT95C400/40P, HT95C300/30P
Bit value is 0:
HT95C400/40P: SEG47~SEG44 output are available
HT95C300/30P: SEG47~SEG44 output are available
Bit value is 1:
HT95C400/40P: PE3~PE0 output are available
HT95C300/30P: PE3~PE0 output are available
6
SPD0
RW
Supported for HT95C400/40P, HT95C300/30P
Bit value is 0: SEG39~SEG36 output are available
Bit value is 1: PD3~PD0 output are available
7
SPD1
RW
Supported for HT95C400/40P, HT95C300/30P
Bit value is 0: SEG43~SEG40 output are available
Bit value is 1: PD7~PD4 output are available
LCDIO (28H) Register
Rev. 1.50
31
May 26, 2005
HT95CXXX
LCD Display Memory
The phone controller provides an area on embedded data memory for LCD display. The LCD display memory are located at bank 1BH and can be read and written to, only by indirect addressing mode using MP1. When data is written
into the display data area it is automatically read by the LCD driver which then generates the corresponding LCD driving signals, to turn the display On or Off, a ²1² or ²0² is written to the corresponding bit of the display memory, respectively. All of the LCD display memories are with random values after the power on reset and unchanged after other reset
conditions.
COM7 to COM0 for HT95C400/40P, HT95C300/30P
Address
Register Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
40H
SEG0
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
41H
SEG1
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
¾
¾
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
6EH
SEG46
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
6FH
SEG47
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
Address
Register Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
70H
SEG0
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
71H
SEG1
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
¾
¾
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
9EH
SEG46
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
9FH
SEG47
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM15 to COM8 for HT95C400/40P, HT95C300/30P
Note: When VBIAS bit set to 1 for 8 COM operation (48´8), the LCD RAM only map to (70H~9FH).
COM7 to COM0 for HT95C200/20P
Address
Register Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
40H
SEG0
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
41H
SEG1
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
¾
¾
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
56H
SEG22
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
57H
SEG23
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
COM15 to COM8 for HT95C200/20P
Address
Register Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
70H
SEG0
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
71H
SEG1
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
¾
¾
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
86H
SEG22
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
87H
SEG23
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
Note: When VBIAS bit is set to 1 for 8 COM operation (24´8), the LCD RAM only map to (70H~87H).
Rev. 1.50
32
May 26, 2005
HT95CXXX
PFD Generator
Bit No.
Label
R/W
Function
3~0
¾
RO
Unused bit, read as ²0²
4
PFDEN
RW
1: Enable PFD output
0: Disable PFD output, the MUSIC pin output low level.
5
6
PRES0
PRES1
RW
Bit6, 5=00: Prescaler output= PFD frequency source/1
Bit6, 5=01: Prescaler output= PFD frequency source/2
Bit6, 5=10: Prescaler output= PFD frequency source/4
Bit6, 5=11: Prescaler output= PFD frequency source/8
7
FPFD
RW
1: The PFD frequency source is 3.58MHz/4
0: The PFD frequency source is 32768Hz
PFDC (2EH) Register
Bit No.
Label
R/W
7~0
¾
RW
Function
PFD data register
PFDD (2FH) Register
The PFD (programmable frequency divider) is implemented in the phone controller. It is composed of two portions: a
prescaler and a general counter.
The prescaler is controlled by the register bits, PRES0 and PRES1. The general counter is programmed by an 8-bit
register PFDD.
The source for this generator can be selected from 3.58MHz/4 or 32768Hz. To enable the PFD output, write 1 to the
PFDEN bit.
The PFDD is inhibited to write while the PFD is disabled. To modify the PFDD contents, the PFD must be enabled.
When the generator is disabled, the PFDD is cleared by hardware.
3 2 7 6 8 H z
3 .5 8 M H z /4
P r e s c a le r
Rev. 1.50
P F D D
P F D
O u tp u t
M U S IC
C le a r
P R E S 1 , P R E S 0
PFD output frequency=
P r e s c a le r
O u tp u t
P F D E N
P F D E N
Prescaler output
, where N=the value of the PFDD
2x(N + 1)
33
May 26, 2005
HT95CXXX
Application Circuits
2 2 M W
1 0 0 k W
O ff-h o o k
T ip
O n -h o o k
A 9 2
R in g
3 .3 k W
3 3 0 k W
2 2 0 k W
3 3 k W
1 0 m F
1 N 4 1 4 8
2 .2 k W
1 N 4 1 4 8
1 m F
4 7 k W
H a n d fre e
0 .0 2 m F
1 .5 k W
1 5 0 W
1 N 4 1 4 8
2 2 0 k W
1 0 0 k W
A 4 2
1 N 4 1 4 8
1 0 0 k W
2 2 0 k W
1 m F
B a tte ry
1 .5 ´ 3
= 4 .5 V
1 0 k W
2 7 0 k W
V
D D
S p e e c h
N e tw o rk
5 .1 V
1 0 0 k W
0 .1 m F
0 .1 m F
1 0 0 m F
V
D D
H F I
P O
H D O
H D I
V D D
H K S
H F O
0 .1 m F
D T M F X M U T E
I/O
M U S IC
V
0 .0 1 m F
2 0 0 k W
1 0 0 k W
T IP
T ip
D D
V L C D
R E S
0 .1 m F
0 .2 m F
4 7 0 k W
R in g
R D E T 1
0 .2 m F
0 .0 1 m F
3 3 k W
2 0 0 k W
R IN G
V
V
D D
V
D D
V D D 2
H T 9 5 C X X X
D D
2 7 0 k W
R T IM E
0 .2 m F
M E M O R Y
S T O R E
A M
D IA L IN G
H O L D
P M
A B R
M O N
T U E
W E D
T H R
L B IN
F R I
S A T
S U N
C O M M O N
S E G M E N T
L C D P a n n e l
I/O
I/O
X 1
X 2
X C
V S S
V S S 2
1 5 k W
1
2
3
K e y 1
K e y 5
K e y 9
4
5
6
K e y 2
K e y 6
K e y 1 0
7
8
9
K e y 3
K e y 7
K e y 1 1
* /T
0
#
K e y 4
K e y 8
K e y 1 2
3 2 7 6 8 H z
3 n F
5 0 n F
K e y M a tr ix
Note: Some floating input pins (INT/TMR1, TMR0, etc.) are not shown in this circuit.
Rev. 1.50
34
May 26, 2005
HT95CXXX
Instruction Set Summary
Description
Instruction
Cycle
Flag
Affected
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to data memory with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1
1
1(1)
1
1
1(1)
1
1(1)
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
1
1(1)
Z
Z
Z
Z
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1
1(1)
1
1(1)
1
1(1)
1
1(1)
None
None
C
C
None
None
C
C
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Mnemonic
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Rev. 1.50
35
May 26, 2005
HT95CXXX
Instruction
Cycle
Flag
Affected
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
None
TO,PDF
Mnemonic
Description
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note: x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
:
(4)
and (2)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
²CLR WDT1² or ²CLR WDT2² instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
Rev. 1.50
36
May 26, 2005
HT95CXXX
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
Rev. 1.50
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
37
May 26, 2005
HT95CXXX
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ PC+1
PC ¬ addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
The contents of the specified data memory are cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
Rev. 1.50
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
38
May 26, 2005
HT95CXXX
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
0
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
Rev. 1.50
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
39
May 26, 2005
HT95CXXX
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory is decremented by 1.
Operation
[m] ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
Rev. 1.50
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
40
May 26, 2005
HT95CXXX
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation
PC ¬ PC+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
1
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Data in the specified data memory is incremented by 1
Operation
[m] ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
PC ¬addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV A,[m]
Move data memory to the accumulator
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
Rev. 1.50
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
41
May 26, 2005
HT95CXXX
MOV A,x
Move immediate data to the accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
PC ¬ PC+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
Rev. 1.50
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
42
May 26, 2005
HT95CXXX
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a 2-cycle instruction.
Operation
PC ¬ Stack
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data.
Operation
PC ¬ Stack
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
PC ¬ Stack
EMI ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
Rev. 1.50
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
43
May 26, 2005
HT95CXXX
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
Rev. 1.50
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
44
May 26, 2005
HT95CXXX
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
Rev. 1.50
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
45
May 26, 2005
HT95CXXX
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Bit i of the specified data memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
Rev. 1.50
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
46
May 26, 2005
HT95CXXX
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
Rev. 1.50
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
47
May 26, 2005
HT95CXXX
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
Rev. 1.50
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
48
May 26, 2005
HT95CXXX
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Rev. 1.50
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
49
May 26, 2005
HT95CXXX
Package Information
128-pin QFP (14´20) Outline Dimensions
C
H
D
1 0 2
G
6 5
I
6 4
1 0 3
F
A
B
E
1 2 8
3 9
a
K
J
3 8
1
Symbol
Rev. 1.50
Dimensions in mm
Min.
Nom.
Max.
A
17.00
¾
17.50
B
13.90
¾
14.10
C
23.00
¾
23.50
D
19.90
¾
20.10
E
¾
0.50
¾
F
¾
0.20
¾
G
2.50
¾
3.10
H
¾
¾
3.40
I
¾
0.10
¾
J
0.65
¾
0.95
K
0.10
¾
0.20
a
0°
¾
7°
50
May 26, 2005
HT95CXXX
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shanghai Sales Office)
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 021-6485-5560
Fax: 021-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor Inc. (Shenzhen Sales Office)
43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031
Tel: 0755-8346-5589
Fax: 0755-8346-5590
ISDN: 0755-8346-5591
Holtek Semiconductor Inc. (Beijing Sales Office)
Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 010-6641-0030, 6641-7751, 6641-7752
Fax: 010-6641-0125
Holmate Semiconductor, Inc. (North America Sales Office)
46712 Fremont Blvd., Fremont, CA 94538
Tel: 510-252-9880
Fax: 510-252-9885
http://www.holmate.com
Copyright Ó 2005 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.50
51
May 26, 2005
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