LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C www.ti.com SNOSAW2P – SEPTEMBER 2006 – REVISED MARCH 2013 LM5100A/B/C LM5101A/B/C 3A, 2A and 1A High Voltage High-Side and Low-Side Gate Drivers Check for Samples: LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C FEATURES DESCRIPTION • The LM5100A/B/C and LM5101A/B/C High Voltage Gate Drivers are designed to drive both the high-side and the low-side N-Channel MOSFETs in a synchronous buck or a half-bridge configuration. The floating high-side driver is capable of operating with supply voltages up to 100V. The “A” versions provide a full 3A of gate drive while the “B” and “C” versions provide 2A and 1A respectively. The outputs are independently controlled with CMOS input thresholds (LM5100A/B/C) or TTL input thresholds (LM5101A/B/C). An integrated high voltage diode is provided to charge the high-side gate drive bootstrap capacitor. A robust level shifter operates at high speed while consuming low power and providing clean level transitions from the control logic to the high-side gate driver. Under-voltage lockout is provided on both the low-side and the high-side power rails. These devices are available in the standard SOIC-8 pin, SO PowerPad-8 pin and the WSON-10 pin packages. The LM5100C and LM5101C are also available in MSOP-PowerPad-8 package. The LM5101A is also available in WSON-8 pin package. 1 2 • • • • • • • • Drives Both a High-side and Low-side NChannel MOSFETs Independent High and Low Driver Logic Inputs Bootstrap Supply Voltage up to 118V DC Fast Propagation Times (25 ns Typical) Drives 1000 pF Load with 8 ns Rise and Fall Times Excellent Propagation Delay Matching (3 ns typical) Supply Rail Under-voltage Lockout Low Power Consumption Pin Compatible with HIP2100/HIP2101 TYPICAL APPLICATIONS • • • • • Current Fed Push-pull Converters Half and Full Bridge Power Converters Synchronous Buck Converters Two Switch Forward Power Converters Forward with Active Clamp Converters Package • • • • • SOIC-8 SO PowerPad-8 WSON-8 (4 mm x 4 mm) WSON-10 (4 mm x 4 mm) MSOP-PowerPad-8 Simplified Block Diagram HB HO UVLO LEVEL SHIFT DRIVER HS HI VDD UVLO LI LO DRIVER VSS 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2013, Texas Instruments Incorporated LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C SNOSAW2P – SEPTEMBER 2006 – REVISED MARCH 2013 www.ti.com Table 1. Input/Output Options Part Number Input Thresholds Peak Output Current LM5100A CMOS 3A LM5101A TTL 3A LM5100B CMOS 2A LM5101B TTL 2A LM5100C CMOS 1A LM5101C TTL 1A Connection Diagrams VDD 1 HB 2 8 LO 7 VSS VDD 1 HB 2 SOIC-8 8 LO 7 VSS WSON-8 HO 3 6 LI HS 4 5 HI VDD 1 8 LO HB 2 7 VSS HO 3 6 LI HS 4 5 HI VDD 1 10 LO HB 2 9 VSS HO 3 8 LI HS 4 7 HI NC 5 6 NC SO PowerPad-8 HO 3 6 LI HS 4 5 HI WSON-10 Exposed Pad Connect to VSS VDD LO HB MSOPPowerPad-8 HO VSS LI HI HS PIN DESCRIPTIONS (1) Pin # SOIC-8 SO Power Pad-8 WSON8 (1) WSON10 (1) MSOPPowerPad -8 (1) Name 1 1 1 1 1 VDD 2 2 2 2 2 3 3 3 3 3 (1) 2 Description Application Information Positive gate drive supply Locally decouple to VSS using low ESR/ESL capacitor located as close to the IC as possible. HB High-side gate driver bootstrap rail Connect the positive terminal of the bootstrap capacitor to HB and the negative terminal to HS. The bootstrap capacitor should be placed as close to the IC as possible. HO High-side gate driver output Connect to the gate of high-side MOSFET with a short, low inductance path. Note: For WSON-8, WSON-10 and MSOP-PowerPad-8 package, it is recommended that the exposed pad on the bottom of the package is soldered to ground plane on the PC board, and that ground plane should extend out from beneath the IC to help dissipate heat. For WSON-10 package, pins 5 and 6 have no connection. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C www.ti.com SNOSAW2P – SEPTEMBER 2006 – REVISED MARCH 2013 PIN DESCRIPTIONS(1) (continued) Pin # SO Power Pad-8 SOIC-8 4 WSON8 (1) 4 5 4 5 WSON10 (1) MSOPPowerPad -8 (1) 4 5 4 7 5 Name Description Application Information HS High-side MOSFET source connection Connect to the bootstrap capacitor negative terminal and the source of the high-side MOSFET. HI High-side driver control input The LM5100A/B/C inputs have CMOS type thresholds. The LM5101A/B/C inputs have TTL type thresholds. Unused inputs should be tied to ground and not left open. The LM5100A/B/C inputs have CMOS type thresholds. The LM5101A/B/C inputs have TTL type thresholds. Unused inputs should be tied to ground and not left open. 6 6 6 8 6 LI Low-side driver control input 7 7 7 9 7 VSS Ground return All signals are referenced to this ground. 8 8 8 10 8 LO Low-side gate driver output Connect to the gate of the low-side MOSFET with a short, low inductance path. EP EP EP EP EP (WSON and SO PowerPad and MSOPPowerPad packages) Solder to the ground plane under the IC to aid in heat dissipation. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) −0.3V to +18V VDD to VSS −0.3V to +18V HB to HS LI or HI Input −0.3V to VDD +0.3V LO Output −0.3V to VDD +0.3V VHS −0.3V to VHB +0.3V HO Output HS to VSS (3) −5V to +100V HB to VSS 118V Junction Temperature +150°C −55°C to +150°C Storage Temperature Range ESD Rating HBM (1) (2) (3) (4) (4) 2 kV Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test conditions, see the Electrical Characteristics Electrical Characteristics tables. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS node will generally not exceed -1V. However, in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently. If negative transients occur, the HS voltage must never be more negative than VDD-15V. For example if VDD = 10V, the negative transients at HS must not exceed -5V. The Human Body Model (HBM) is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. 2 kV for all pins except Pin 2, Pin 3 and Pin 4 which are rated at 1000V for HBM. Machine Model (MM) ratings are : 100V(MM) for Options B and C; 50V(MM) for Option A. Recommended Operating Conditions VDD +9V to +14V HS −1V to 100V HB VHS +8V to VHS +14V HS Slew Rate < 50 V/ns −40°C to +125°C Junction Temperature Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 3 LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C SNOSAW2P – SEPTEMBER 2006 – REVISED MARCH 2013 www.ti.com Electrical Characteristics Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO (1). Symbol Parameter Conditions Min Typ Max Units SUPPLY CURRENTS IDD VDD Quiescent Current, LM5100A/B/C LI = HI = 0V 0.1 0.2 VDD Quiescent Current, LM5101A/B/C LI = HI = 0V 0.25 0.4 IDDO VDD Operating Current f = 500 kHz 2.0 3 mA IHB Total HB Quiescent Current LI = HI = 0V 0.06 0.2 mA IHBO Total HB Operating Current f = 500 kHz 1.6 3 mA IHBS HB to VSS Current, Quiescent HS = HB = 100V 0.1 10 IHBSO HB to VSS Current, Operating f = 500 kHz 0.4 mA µA mA INPUT PINS VIL Input Voltage Threshold LM5100A/B/C Rising Edge 4.5 5.4 6.3 1.8 2.3 V VIL Input Voltage Threshold LM5101A/B/C Rising Edge 1.3 VIHYS Input Voltage Hysteresis LM5100A/B/C 500 mV VIHYS Input Voltage Hysteresis LM5101A/B/C 50 mV RI Input Pulldown Resistance V 100 200 400 kΩ 6.0 6.9 7.4 V UNDER VOLTAGE PROTECTION VDDR VDD Rising Threshold VDDH VDD Threshold Hysteresis VHBR HB Rising Threshold VHBH HB Threshold Hysteresis 0.5 5.7 6.6 V 7.1 0.4 V V BOOT STRAP DIODE VDL Low-Current Forward Voltage IVDD-HB = 100 µA 0.52 0.85 VDH High-Current Forward Voltage IVDD-HB = 100 mA 0.8 1 V V RD Dynamic Resistance LM5100A/B/C, LM5101A/B/C IVDD-HB = 100 mA 1.0 1.65 Ω 0.12 0.25 0.16 0.4 0.28 0.65 0.24 0.45 0.28 0.60 0.60 1.10 LO & HO GATE DRIVER VOL Low-Level Output Voltage LM5100A/LM5101A IHO = ILO = 100 mA Low-Level Output Voltage LM5100B/LM5101B Low-Level Output Voltage LM5100C/LM5101C VOH High-Level Output Voltage LM5100A/LM5101A High-Level Output Voltage LM5100B/LM5101B High-Level Output Voltage LM5100C/LM5101C IOHL IOLL (1) 4 Peak Pullup Current LM5100A/LM5101A IHO = ILO = 100 mA VOH = VDD– LO or VOH = HB - HO HO, LO = 0V V 3 Peak Pullup Current LM5100B/LM5101B 2 Peak Pullup Current LM5100C/LM5101C 1 Peak Pulldown Current LM5100A/LM5101A V HO, LO = 12V A 3 Peak Pulldown Current LM5100B/LM5101B 2 Peak Pulldown Current LM5100C/LM5101C 1 A Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL). Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C www.ti.com SNOSAW2P – SEPTEMBER 2006 – REVISED MARCH 2013 Electrical Characteristics (continued) Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO (1). Symbol Parameter Conditions Min Typ Max Units THERMAL RESISTANCE SOIC-8 170 WSON-8 (3) θJA (2) Junction to Ambient WSON-10 40 (3) 40 SO PowerPad-8 MSOP-PowerPad-8 (2) (3) °C/W 40 (3) 80 The θJA is not a given constant for the package and depends on the printed circuit board design and the operating environment. 4 layer board with Cu finished thickness 1.5/1/1/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm ground and power planes embedded in PCB. See Application Note AN-1187. Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 5 LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C SNOSAW2P – SEPTEMBER 2006 – REVISED MARCH 2013 www.ti.com Switching Characteristics Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO (1). Symbol tLPHL Parameter Typ Max 20 45 22 56 20 45 26 56 20 45 22 56 20 45 LO Turn-On Propagation Delay LM5101A/B/C 26 56 Delay Matching: LO on & HO off LM5100A/B/C 1 10 Delay Matching: LO on & HO off LM5101A/B/C 4 10 Delay Matching: LO off & HO on LM5100A/B/C 1 10 Delay Matching: LO on & HO off LM5101A/B/C 4 10 LO Turn-Off Propagation Delay LM5100A/B/C Conditions LI Falling to LO Falling LO Turn-On Propagation Delay LM5100A/B/C LI Rising to LO Rising ns LO Turn-On Propagation Delay LM5101A/B/C tHPHL HO Turn-Off Propagation Delay LM5100A/B/C HI Falling to HO Falling ns HO Turn-Off Propagation Delay LM5101A/B/C tHPLH tMON tMOFF LO Turn-On Propagation Delay LM5100A/B/C HI Rising to HO Rising ns Either Output Rise/Fall Time CL = 1000 pF tR Output Rise Time (3V to 9V) LM5100A/LM5101A CL = 0.1 µF 8 ns 430 ns Output Rise Time (3V to 9V) LM5100B/LM5101B 570 Output Rise Time (3V to 9V) LM5100C/LM5101C 990 Output Fall Time (3V to 9V) LM5100A/LM5101A ns ns tRC, tFC tF Units ns LO Turn-Off Propagation Delay LM5101A/B/C tLPLH Min CL = 0.1 µF 260 Output Fall Time (3V to 9V) LM5100B/LM5101B 430 Output Fall Time (3V to 9V) LM5100C/LM5101C 715 tPW Minimum Input Pulse Width that Changes the Output 50 ns tBS Bootstrap Diode Reverse Recovery Time 37 ns (1) 6 IF = 100 mA, IR = 100 mA ns Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL). Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C www.ti.com SNOSAW2P – SEPTEMBER 2006 – REVISED MARCH 2013 Typical Performance Characteristics Peak Sourcing Current vs VDD Peak Sinking Current vs VDD 5.0 5.0 4.5 4.5 4.0 4.0 LM5100A/LM5101A 3.5 CURRENT (A) CURRENT (A) 3.5 3.0 2.5 2.0 LM5100B/LM5101B 1.5 1.0 2.5 2.0 LM5100B/LM5101B 1.5 1.0 LM5100C/LM5101C 0.5 0.0 LM5100A/LM5101A 3.0 7 8 9 10 11 12 13 14 LM5100C/LM5101C 0.5 0.0 15 7 8 9 10 11 12 Figure 1. Figure 2. Sink Current vs Output Voltage Source Current vs Output Voltage 3.5 14 15 3.5 VDD = 12V VDD = 12V 3.0 3.0 LM5100A/LM5101A LM5100A/LM5101A 2.5 CURRENT (A) 2.5 CURRENT (A) 13 VDD (V) VDD (V) 2.0 LM5100B/LM5101B 1.5 1.0 2.0 LM5100B/LM5101B 1.5 1.0 LM5100C/LM5101C 0.5 0.0 LM5100C/LM5101C 0.5 0 2 4 6 8 10 0.0 12 0 OUTPUT VOLTAGE (V) 2 4 8 10 6 OUTPUT VOLTAGE (V) Figure 3. Figure 4. LM5100A/B/C IDD vs Frequency LM5101A/B/C IDD vs Frequency 100000 100000 VDD = 12V VDD = 12V CL = 4400 pF CL = 4400 pF CURRENT (PA) CURRENT (PA) 10000 CL = 1000 pF 1000 100 10 0.1 12 10000 CL = 1000 pF 1000 CL = 0 pF 1 10 100 FREQUENCY (kHz) Figure 5. Copyright © 2006–2013, Texas Instruments Incorporated CL = 0 pF 1000 100 0.1 1 10 100 1000 FREQUENCY (kHz) Figure 6. Submit Documentation Feedback Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 7 LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C SNOSAW2P – SEPTEMBER 2006 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Operating Current vs Temperature IHB vs Frequency 2.3 100000 2.1 HB = 12V, HS = 0V IDDO (LM5101A/B/C) CL = 4400 pF 10000 IDDO (LM5100A/B/C) 1.7 CURRENT (PA) CURRENT (mA) 1.9 IHBO 1.5 1.3 CL = 1000 pF 1000 CL = 0 pF 100 1.1 0.9 0.7 -50 -25 0 25 50 75 10 0.1 100 125 150 1 10 100 1000 o TEMPERATURE ( C) FREQUENCY (kHz) Figure 7. Figure 8. Quiescent Current vs Supply Voltage Quiescent Current vs Temperature 350 400 300 350 IDD (LM5101A/B/C) IDD (LM5101A/B/C) 250 CURRENT (PA) CURRENT (PA) 300 250 200 IDD (LM5100A/B/C) 150 200 150 IDD (LM5100A/B/C) 100 100 0 50 IHB 50 8 9 10 11 12 13 14 15 IHB 0 -50 -25 16 0 25 50 75 100 125 150 TEMPERATURE (°C) VDD, VHB (V) Figure 9. Figure 10. Undervoltage Rising Thresholds vs Temperature Undervoltage Threshold Hysteresis vs Temperature 0.60 7.30 7.20 0.55 VDDH 7.00 VDDR HYSTERESIS (V) THRESHOLD (V) 7.10 6.90 6.80 6.70 6.60 0.50 0.45 VHBH 0.40 VHBR 6.50 0.35 6.40 6.30 -50 -25 8 0 25 50 75 100 125 150 0.30 -50 -25 0_ 25 50_ 75_100_125_150_ TEMPERATURE (°C) TEMPERATURE (oC) Figure 11. Figure 12. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C www.ti.com SNOSAW2P – SEPTEMBER 2006 – REVISED MARCH 2013 Typical Performance Characteristics (continued) LM5100A/B/C Input Threshold vs Temperature Bootstrap Diode Forward Voltage 50 1.00E-01 THRESHOLD VOLTAGE (%VDD) T = 150°C 1.00E-02 ID (A) 1.00E-03 T = 25°C 1.00E-04 T = -40°C 1.00E-05 1.00E-06 0.2 0.3 0.4 0.5 0.6 0.7 0.8 49 48 Rising 47 46 45 44 Falling 43 42 41 40 -50 -25 0.9 25 50 75 100 125 150 TEMPERATURE (°C) VD (V) Figure 13. Figure 14. LM5101A/B/C Input Threshold vs Temperature LM5100A/B/C Input Threshold vs VDD 50 1.92 1.90 THRESHOLD VOLTAGE (%VDD) 1.91 THRESHOLD VOLTAGE (V) 0 Rising 1.89 1.88 1.87 1.86 Falling 1.85 1.84 1.83 1.82 1.81 1.80 -50 -25 49 48 46 45 44 43 25 50 Falling 42 41 40 0 Rising 47 75 100 125 150 8 9 10 11 12 13 14 15 16 VDD (V) TEMPERATURE (°C) Figure 15. Figure 16. LM5101A/B/C Input Threshold vs VDD LM5100A/B/C Propagation Delay vs Temperature 1.92 35 1.90 Rising 1.89 30 1.88 DELAY (ns) THRESHOLD VOLTAGE (V) 1.91 1.87 1.86 1.85 Falling 1.84 25 T_PLH 20 1.83 1.82 T_PHL 1.81 1.80 8 9 10 11 12 13 14 VDD (V) Figure 17. Copyright © 2006–2013, Texas Instruments Incorporated 15 16 15 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (°C) Figure 18. Submit Documentation Feedback Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 9 LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C SNOSAW2P – SEPTEMBER 2006 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) LM5101A/B/C Propagation Delay vs Temperature LO & HO Gate Drive - High Level Output Voltage vs Temperature 1.0 40 VDD = 12V 0.9 0.8 35 LM5100C/LM5101C 30 VOH (V) DELAY (ns) 0.7 T_PLH 25 0.6 0.5 LM5100B/LM5101B 0.4 0.3 T_PHL 0.2 20 LM5100A/LM5101A 0.1 15 -50 -25 0 25 50 0.0 -50 -25 75 100 125 150 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) Figure 19. Figure 20. LO & HO Gate Drive - Low Level Output Voltage vs Temperature LO & HO Gate Drive - Output High Voltage vs VDD 0.50 0.8 VDD = 12V IOUT = -100 mA 0.45 0.7 0.40 0.6 LM5100C/LM5101C 0.30 0.25 VOH (V) VOL (V) 0.35 LM5100B/LM5101B 0.20 0.15 0.5 0.4 0.3 0.10 LM5100B/LM5101B LM5100A/LM5101A 0.2 0.05 0.00 -50 -25 LM5100C/LM5101C LM5100A/LM5101A 0 25 50 0.1 75 100 125 150 7 8 9 10 11 12 TEMPERATURE (°C) VDD (V) Figure 21. Figure 22. 13 14 15 LO & HO Gate Drive - Output Low Voltage vs VDD 0.35 IOUT = 100 mA VOL (V) 0.30 LM5100C/LM5101C 0.25 0.20 LM5100B/LM5101B 0.15 LM5100A/LM5101A 0.10 7 8 9 10 11 12 13 14 15 VDD (V) Figure 23. 10 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C www.ti.com SNOSAW2P – SEPTEMBER 2006 – REVISED MARCH 2013 TIMING DIAGRAM LI LI HI tHPLH tLPLH HI tHPHL tLPHL LO LO HO HO tMON tMOFF Figure 24. Layout Considerations The optimum performance of high and low-side gate drivers cannot be achieved without taking due considerations during circuit board layout. Following points are emphasized. 1. Low ESR / ESL capacitors must be connected close to the IC, between VDD and VSS pins and between the HB and HS pins to support the high peak currents being drawn from VDD during turn-on of the external MOSFET. 2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be connected between MOSFET drain and ground (VSS). 3. In order to avoid large negative transients on the switch node (HS pin), the parasitic inductances in the source of top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier) must be minimized. 4. Grounding Considerations: – a) The first priority in designing grounding connections is to confine the high peak currents that charge and discharge the MOSFET gate into a minimal physical area. This will decrease the loop inductance and minimize noise issues on the gate terminal of the MOSFET. The MOSFETs should be placed as close as possible to the gate driver. – b) The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground referenced bypass capacitor and low-side MOSFET body diode. The bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor. The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation. A recommended layout pattern for the driver is shown in the following figure. If possible a single layer placement is preferred. Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 11 LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C SNOSAW2P – SEPTEMBER 2006 – REVISED MARCH 2013 www.ti.com Recommended Layout for Driver IC and Passives VDD LO HB VSS SO PowerPAD-8 LI HS HI To Hi-Side FET D Multi Layer Option LO N G HO HS HO Single Layer Option HO To Low-Side FET Power Dissipation Considerations The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate driver losses are related to the switching frequency (f), output load capacitance on LO and HO (CL), and supply voltage (VDD) and can be roughly calculated as: PDGATES = 2 • f • CL • VDD2 (1) There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and HO outputs. The following plot shows the measured gate driver power dissipation versus frequency and load capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the power losses driving the output loads and agrees well with the above equation.Equation 1 This plot can be used to approximate the power losses due to the gate drivers. 1.000 CL = 4400 pF POWER (W) 0.100 CL = 1000 pF 0.010 CL = 0 pF 0.001 0.1 1.0 10.0 100.0 1000.0 SWITCHING FREQUENCY (kHz) Figure 25. Gate Driver Power Dissipation (LO + HO) VDD = 12V, Neglecting Diode Losses 12 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C www.ti.com SNOSAW2P – SEPTEMBER 2006 – REVISED MARCH 2013 The bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Since each of these events happens once per cycle, the diode power loss is proportional to frequency. Larger capacitive loads require more energy to recharge the bootstrap capacitor resulting in more losses. Higher input voltages (VIN) to the half bridge result in higher reverse recovery losses. The following plot was generated based on calculations and lab measurements of the diode recovery time and current under several operating conditions. This can be useful for approximating the diode power dissipation. The total IC power dissipation can be estimated from the previous plots by summing the gate drive losses with the bootstrap diode losses for the intended application. 0.100 POWER (W) CL = 4400 pF CL = 0 pF 0.010 0.001 1 10 100 1000 SWITCHING FREQUENCY (kHz) Figure 26. Diode Power Dissipation VIN = 50V Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C 13 LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C SNOSAW2P – SEPTEMBER 2006 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision O (March 2013) to Revision P • 14 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 13 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LM5100A LM5100B LM5100C LM5101A LM5101B LM5101C PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) LM5100AM ACTIVE SOIC D 8 95 TBD Call TI Call TI -40 to 125 L5100 AM LM5100AM/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5100 AM LM5100AMR/NOPB ACTIVE SO PowerPAD DDA 8 95 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR L5100 AMR LM5100AMRX/NOPB ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS & no Sb/Br) SN Level-3-260C-168 HR L5100 AMR LM5100AMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5100 AM LM5100ASD ACTIVE WSON DPR 10 1000 TBD Call TI Call TI -40 to 125 5100ASD LM5100ASD/NOPB ACTIVE WSON DPR 10 1000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 5100ASD LM5100ASDX ACTIVE WSON DPR 10 4500 TBD Call TI Call TI -40 to 125 5100ASD LM5100ASDX/NOPB ACTIVE WSON DPR 10 4500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 5100ASD LM5100BMA ACTIVE SOIC D 8 95 TBD Call TI Call TI -40 to 125 L5100 BMA LM5100BMA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5100 BMA LM5100BMAX ACTIVE SOIC D 8 2500 TBD Call TI Call TI -40 to 125 L5100 BMA LM5100BMAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5100 BMA LM5100BSD ACTIVE WSON DPR 10 1000 TBD Call TI Call TI -40 to 125 5100BSD LM5100BSD/NOPB ACTIVE WSON DPR 10 1000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 5100BSD LM5100BSDX ACTIVE WSON DPR 10 4500 TBD Call TI Call TI -40 to 125 5100BSD LM5100BSDX/NOPB ACTIVE WSON DPR 10 4500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 5100BSD LM5100CMA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5100 CMA Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) LM5100CMAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5100 CMA LM5100CMY/NOPB ACTIVE MSOPPowerPAD DGN 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM SXCB LM5100CMYE/NOPB ACTIVE MSOPPowerPAD DGN 8 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM SXCB LM5100CMYX/NOPB ACTIVE MSOPPowerPAD DGN 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM SXCB LM5100CSD/NOPB ACTIVE WSON DPR 10 1000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 5100CSD LM5100CSDX/NOPB ACTIVE WSON DPR 10 4500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 5100CSD LM5101AM ACTIVE SOIC D 8 95 TBD Call TI Call TI -40 to 125 L5101 AM LM5101AM/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5101 AM LM5101AMR/NOPB ACTIVE SO PowerPAD DDA 8 95 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR L5101 AMR LM5101AMRX/NOPB ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR L5101 AMR LM5101AMX ACTIVE SOIC D 8 2500 TBD Call TI Call TI -40 to 125 L5101 AM LM5101AMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5101 AM LM5101ASD ACTIVE WSON DPR 10 1000 TBD Call TI Call TI -40 to 125 5101ASD LM5101ASD-1/NOPB ACTIVE WSON NGT 8 1000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM LM5101ASD/NOPB ACTIVE WSON DPR 10 1000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 5101ASD LM5101ASDX ACTIVE WSON DPR 10 4500 TBD Call TI Call TI -40 to 125 5101ASD LM5101ASDX-1/NOPB ACTIVE WSON NGT 8 4500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM LM5101ASDX/NOPB ACTIVE WSON DPR 10 4500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM Addendum-Page 2 5101A-1 5101A-1 -40 to 125 5101ASD Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) LM5101BMA ACTIVE SOIC D 8 95 TBD Call TI Call TI -40 to 125 L5101 BMA LM5101BMA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5101 BMA LM5101BMAX ACTIVE SOIC D 8 2500 TBD Call TI Call TI -40 to 125 L5101 BMA LM5101BMAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5101 BMA LM5101BSD ACTIVE WSON DPR 10 1000 TBD Call TI Call TI -40 to 125 5101BSD LM5101BSD/NOPB ACTIVE WSON DPR 10 1000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 5101BSD LM5101BSDX ACTIVE WSON DPR 10 4500 TBD Call TI Call TI -40 to 125 5101BSD LM5101BSDX/NOPB ACTIVE WSON DPR 10 4500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 5101BSD LM5101CMA ACTIVE SOIC D 8 95 TBD Call TI Call TI -40 to 125 L5101 CMA LM5101CMA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5101 CMA LM5101CMAX ACTIVE SOIC D 8 2500 TBD Call TI Call TI -40 to 125 L5101 CMA LM5101CMAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5101 CMA LM5101CMY/NOPB ACTIVE MSOPPowerPAD DGN 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM SXDB LM5101CMYE/NOPB ACTIVE MSOPPowerPAD DGN 8 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM SXDB LM5101CMYX/NOPB ACTIVE MSOPPowerPAD DGN 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM SXDB LM5101CSD ACTIVE WSON DPR 10 1000 TBD Call TI Call TI -40 to 125 5101CSD LM5101CSD/NOPB ACTIVE WSON DPR 10 1000 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 5101CSD LM5101CSDX ACTIVE WSON DPR 10 4500 TBD Call TI Call TI -40 to 125 5101CSD Addendum-Page 3 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 11-Apr-2013 Status (1) LM5101CSDX/NOPB ACTIVE Package Type Package Pins Package Drawing Qty WSON DPR 10 4500 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) SN Level-1-260C-UNLIM (4) -40 to 125 5101CSD (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 4 Samples PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device LM5100AMRX/NOPB Package Package Pins Type Drawing SO Power PAD DDA SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM5100AMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM5100ASD WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5100ASD/NOPB WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5100ASDX WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5100ASDX/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5100BMAX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM5100BMAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM5100BSD WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5100BSD/NOPB WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5100BSDX WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5100BSDX/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5100CMAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM5100CMY/NOPB MSOPPower PAD DGN 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5100CMYE/NOPB MSOP- DGN 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant Power PAD LM5100CMYX/NOPB MSOPPower PAD DGN 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5100CSD/NOPB WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5100CSDX/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5101AMRX/NOPB SO Power PAD DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM5101AMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM5101AMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM5101ASD WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5101ASD-1/NOPB WSON NGT 8 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5101ASD/NOPB WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5101ASDX WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5101ASDX-1/NOPB WSON NGT 8 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5101ASDX/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5101BMAX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM5101BMAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM5101BSD WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5101BSD/NOPB WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5101BSDX WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5101BSDX/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5101CMAX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM5101CMAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM5101CMY/NOPB MSOPPower PAD DGN 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5101CMYE/NOPB MSOPPower PAD DGN 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5101CMYX/NOPB MSOPPower PAD DGN 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5101CSD WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5101CSD/NOPB WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5101CSDX WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5101CSDX/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5100AMRX/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0 LM5100AMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM5100ASD WSON DPR 10 1000 210.0 185.0 35.0 LM5100ASD/NOPB WSON DPR 10 1000 210.0 185.0 35.0 LM5100ASDX WSON DPR 10 4500 367.0 367.0 35.0 LM5100ASDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0 LM5100BMAX SOIC D 8 2500 367.0 367.0 35.0 LM5100BMAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM5100BSD WSON DPR 10 1000 210.0 185.0 35.0 LM5100BSD/NOPB WSON DPR 10 1000 210.0 185.0 35.0 LM5100BSDX WSON DPR 10 4500 367.0 367.0 35.0 LM5100BSDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0 LM5100CMAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM5100CMY/NOPB MSOP-PowerPAD DGN 8 1000 210.0 185.0 35.0 LM5100CMYE/NOPB MSOP-PowerPAD DGN 8 250 210.0 185.0 35.0 LM5100CMYX/NOPB MSOP-PowerPAD DGN 8 3500 367.0 367.0 35.0 LM5100CSD/NOPB WSON DPR 10 1000 210.0 185.0 35.0 LM5100CSDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0 LM5101AMRX/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0 LM5101AMX SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5101AMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM5101ASD WSON DPR 10 1000 210.0 185.0 35.0 LM5101ASD-1/NOPB WSON NGT 8 1000 210.0 185.0 35.0 LM5101ASD/NOPB WSON DPR 10 1000 210.0 185.0 35.0 LM5101ASDX WSON DPR 10 4500 367.0 367.0 35.0 LM5101ASDX-1/NOPB WSON NGT 8 4500 367.0 367.0 35.0 LM5101ASDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0 LM5101BMAX SOIC D 8 2500 367.0 367.0 35.0 LM5101BMAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM5101BSD WSON DPR 10 1000 210.0 185.0 35.0 LM5101BSD/NOPB WSON DPR 10 1000 210.0 185.0 35.0 LM5101BSDX WSON DPR 10 4500 367.0 367.0 35.0 LM5101BSDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0 LM5101CMAX SOIC D 8 2500 367.0 367.0 35.0 LM5101CMAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM5101CMY/NOPB MSOP-PowerPAD DGN 8 1000 210.0 185.0 35.0 LM5101CMYE/NOPB MSOP-PowerPAD DGN 8 250 210.0 185.0 35.0 LM5101CMYX/NOPB MSOP-PowerPAD DGN 8 3500 367.0 367.0 35.0 LM5101CSD WSON DPR 10 1000 210.0 185.0 35.0 LM5101CSD/NOPB WSON DPR 10 1000 210.0 185.0 35.0 LM5101CSDX WSON DPR 10 4500 367.0 367.0 35.0 LM5101CSDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0 Pack Materials-Page 4 MECHANICAL DATA DGN0008A MUY08A (Rev A) BOTTOM VIEW www.ti.com MECHANICAL DATA DDA0008B MRA08B (Rev B) www.ti.com MECHANICAL DATA NGT0008A SDC08A (Rev A) www.ti.com MECHANICAL DATA DPR0010A SDC10A (Rev A) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to 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