Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MPC5634M
Rev. 8, Feb 2011
MPC5634M
144 LQFP
20 x 20 mm
MPC5634M Microcontroller
Data Sheet
• Operating Parameters
– Fully static operation, 0 MHz – 80 MHz (plus 2%
frequency modulation - 82 MHz)
– –40 C to 150 C junction temperature operating range
– Low power design
– Less than 400 mW power dissipation (nominal)
– Designed for dynamic power management of core
and peripherals
– Software controlled clock gating of peripherals
– Low power stop mode, with all clocks stopped
– Fabricated in 90 nm process
– 1.2 V internal logic
– Single power supply with 5.0 V 5% (4.5 V to
5.25 V) with internal regulator to provide 3.3 V and
1.2 V for the core
– Input and output pins with 5.0 V 5% (4.5 V to
5.25 V) range
– 35%/65% VDDE CMOS switch levels (with
hysteresis)
– Selectable hysteresis
– Selectable slew rate control
– Nexus pins powered by 3.3 V supply
– Designed with EMI reduction techniques
– Phase-locked loop
– Frequency modulation of system clock frequency
– On-chip bypass capacitance
– Selectable slew rate and drive strength
• High performance e200z335 core processor
– 32-bit Power Architecture Book E programmer’s model
– Variable Length Encoding Enhancements
– Allows Power Architecture instruction set to be
optionally encoded in a mixed 16 and 32-bit
instructions
– Results in smaller code size
176 LQFP
24 x 24 mm
100 LQFP
14 x 14 mm
208 MAPBGA
17 x 17 mm
– Single issue, 32-bit Power Architecture Book E
compliant CPU
– In-order execution and retirement
– Precise exception handling
– Branch processing unit
– Dedicated branch address calculation adder
– Branch acceleration using Branch Lookahead
Instruction Buffer
– Load/store unit
– One-cycle load latency
– Fully pipelined
– Big and Little Endian support
– Misaligned access support
– Zero load-to-use pipeline bubbles
– Thirty-two 64-bit general purpose registers (GPRs)
– Memory management unit (MMU) with 16-entry
fully-associative translation look-aside buffer (TLB)
– Separate instruction bus and load/store bus
– Vectored interrupt support
– Interrupt latency < 120 ns @ 80 MHz (measured from
interrupt request to execution of first instruction of
interrupt exception handler)
– Non-maskable interrupt (NMI) input for handling
external events that must produce an immediate
response, e.g., power down detection. On this device, the
NMI input is connected to the Critical Interrupt Input.
(May not be recoverable)
– Critical Interrupt input. For external interrupt sources
that are higher priority than provided by the Interrupt
Controller. (Always recoverable)
– New ‘Wait for Interrupt’ instruction, to be used with new
low power modes
– Reservation instructions for implementing
read-modify-write accesses
– Signal processing extension (SPE) APU
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2008, 2010–2011. All rights reserved.
Table of Contents
1
2
3
4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.1 Document overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.1 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2 MPC5634M features . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.3 MPC5634M feature details . . . . . . . . . . . . . . . . . . . . . .19
2.3.1 e200z335 core . . . . . . . . . . . . . . . . . . . . . . . . . .19
2.3.2 Crossbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.3.3 eDMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.3.4 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . .21
2.3.5 FMPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.3.6 Calibration EBI. . . . . . . . . . . . . . . . . . . . . . . . . .22
2.3.7 SIU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.3.8 ECSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2.3.9 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2.3.10 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.3.11 BAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.3.12 eMIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.3.13 eTPU2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.3.14 eQADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.3.15 DSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.3.16 eSCI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
2.3.17 FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.3.18 System timers . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.3.19 Software Watchdog Timer (SWT) . . . . . . . . . . .33
2.3.20 Debug features . . . . . . . . . . . . . . . . . . . . . . . . .34
2.4 MPC5634M series architecture. . . . . . . . . . . . . . . . . . .36
2.4.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . .36
2.4.2 Block summary . . . . . . . . . . . . . . . . . . . . . . . . .36
Pinout and signal description . . . . . . . . . . . . . . . . . . . . . . . . .38
3.1 144 LQFP pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
3.2 176 LQFP pinout (MPC5634M) . . . . . . . . . . . . . . . . . .39
3.3 176 LQFP pinout (MPC5633M) . . . . . . . . . . . . . . . . . .41
3.4 208 MAPBGA ballmap (MPC5634M) . . . . . . . . . . . . . .42
3.5 208 MAPBGA ballmap (MPC5633M only) . . . . . . . . . .43
3.6 Signal summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
3.7 Signal details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
4.1
4.2
4.3
5
6
7
Parameter classification. . . . . . . . . . . . . . . . . . . . . . . . 65
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 67
4.3.1 General notes for specifications at maximum
junction temperature. . . . . . . . . . . . . . . . . . . . . 69
4.4 Electromagnetic Interference (EMI) characteristics . . . 72
4.5 Electromagnetic static discharge (ESD) characteristics72
4.6 Power Management Control (PMC) and Power On Reset
(POR) electrical specifications. . . . . . . . . . . . . . . . . . . 73
4.6.1 Regulator example . . . . . . . . . . . . . . . . . . . . . . 77
4.6.2 Recommended power transistors. . . . . . . . . . . 77
4.7 Power up/down sequencing. . . . . . . . . . . . . . . . . . . . . 78
4.8 DC electrical specifications . . . . . . . . . . . . . . . . . . . . . 79
4.9 I/O Pad current specifications . . . . . . . . . . . . . . . . . . . 86
4.9.1 I/O pad VRC33 current specifications . . . . . . . 87
4.9.2 LVDS pad specifications. . . . . . . . . . . . . . . . . . 88
4.10 Oscillator and PLLMRFM electrical characteristics . . . 89
4.11 Temperature sensor electrical characteristics . . . . . . . 91
4.12 eQADC electrical characteristics . . . . . . . . . . . . . . . . . 91
4.13 Platform flash controller electrical characteristics . . . . 94
4.14 Flash memory electrical characteristics . . . . . . . . . . . 94
4.15 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.15.1 Pad AC specifications. . . . . . . . . . . . . . . . . . . . 96
4.16 AC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.16.1 IEEE 1149.1 interface timing . . . . . . . . . . . . . . 99
4.16.2 Nexus timing. . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.16.3 Calibration bus interface timing . . . . . . . . . . . 105
4.16.4 eMIOS timing . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.16.5 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.16.6 eQADC SSI timing . . . . . . . . . . . . . . . . . . . . . 114
Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
5.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . 115
5.1.1 144 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
5.1.2 176 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.1.3 208 MAPBGA. . . . . . . . . . . . . . . . . . . . . . . . . 122
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . 126
MPC5634M Microcontroller Data Sheet, Rev. 8
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– Operating on all 32 GPRs that are all extended to 64 bits wide
– Provides a full compliment of vector and scalar integer and floating point arithmetic operations (including
integer vector MAC and MUL operations) (SIMD)
– Provides rich array of extended 64-bit loads and stores to/from extended GPRs
– Fully code compatible with e200z6 core
— Floating point
– IEEE 754 compatible with software wrapper
– Scalar single precision in hardware, double precision with software library
– Conversion instructions between single precision floating point and fixed point
– Fully code compatible with e200z6 core
— Long cycle time instructions, except for guarded loads, do not increase interrupt latency
— Extensive system development support through Nexus debug port
Advanced microcontroller bus architecture (AMBA) crossbar switch (XBAR)
— Three master ports, four slave ports
– Masters: CPU Instruction bus; CPU Load/store bus (Nexus); eDMA
– Slave: Flash; SRAM; Peripheral Bridge; calibration EBI
— 32-bit internal address bus, 64-bit internal data bus
Enhanced direct memory access (eDMA) controller
— 32 channels support independent 8-bit, 16-bit, or 32-bit single value or block transfers
— Supports variable sized queues and circular queues
— Source and destination address registers are independently configured to post-increment or remain constant
— Each transfer is initiated by a peripheral, CPU, or eDMA channel request
— Each eDMA channel can optionally send an interrupt request to the CPU on completion of a single value or block
transfer
Interrupt controller (INTC)
— 191 peripheral interrupt request sources
— 8 software settable interrupt request sources
— 9-bit vector
– Unique vector for each interrupt request source
– Provided by hardware connection to processor or read from register
— Each interrupt source can be programmed to one of 16 priorities
— Preemption
– Preemptive prioritized interrupt requests to processor
– ISR at a higher priority preempts ISRs or tasks at lower priorities
– Automatic pushing or popping of preempted priority to or from a LIFO
– Ability to modify the ISR or task priority. Modifying the priority can be used to implement the Priority Ceiling
Protocol for accessing shared resources.
— Low latency—three clocks from receipt of interrupt request from peripheral to interrupt request to processor
Frequency Modulating Phase-locked loop (FMPLL)
— Reference clock pre-divider (PREDIV) for finer frequency synthesis resolution
— Reduced frequency divider (RFD) for reducing the FMPLL output clock frequency without forcing the FMPLL
to re-lock
— System clock divider (SYSDIV) for reducing the system clock frequency in normal or bypass mode
— Input clock frequency range from 4 MHz to 20 MHz before the pre-divider, and from 4 MHz to 16 MHz at the
FMPLL input
— Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz
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VCO free-running frequency range from 25 MHz to 125 MHz
Four bypass modes: crystal or external reference with PLL on or off
Two normal modes: crystal or external reference
Programmable frequency modulation
– Triangle wave modulation
– Register programmable modulation frequency and depth
— Lock detect circuitry reports when the FMPLL has achieved frequency lock and continuously monitors lock status
to report loss of lock conditions
– User-selectable ability to generate an interrupt request upon loss of lock
– User-selectable ability to generate a system reset upon loss of lock
— Clock quality monitor (CQM) module provides loss-of-clock detection for the FMPLL reference and output
clocks
– User-selectable ability to generate an interrupt request upon loss of clock
– User-selectable ability to generate a system reset upon loss of clock
– Backup clock (reference clock or FMPLL free-running) can be applied to the system in case of loss of clock
Calibration bus interface (EBI)
— Available only in the calibration package
— 1.8 V to 3.3 V ± 10% I/O (1.6 V to 3.6 V)
— Memory controller with support for various memory types
— 16-bit data bus, up to 22-bit address bus
— Selectable drive strength
— Configurable bus speed modes
— Bus monitor
— Configurable wait states
System integration unit (SIU)
— Centralized GPIO control of 80 I/O pins
— Centralized pad control on a per-pin basis
– Pin function selection
– Configurable weak pull-up or pull-down
– Drive strength
– Slew rate
– Hysteresis
— System reset monitoring and generation
— External interrupt inputs, filtering and control
— Critical Interrupt control
— Non-Maskable Interrupt control
— Internal multiplexer subblock (IMUX)
– Allows flexible selection of eQADC trigger inputs (eTPU, eMIOS and external signals)
– Allows selection of interrupt requests between external pins and DSPI
Error correction status module (ECSM)
— Configurable error-correcting codes (ECC) reporting
— Single-bit error correction reporting
On-chip flash memory
— Up to 1.5 MB flash memory, accessed via a 64-bit wide bus interface
— 16 KB shadow block
MPC5634M Microcontroller Data Sheet, Rev. 8
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— Fetch Accelerator
– Provide single cycle flash access at 80 MHz
– Quadruple 128-bit wide prefetch/burst buffers
– Prefetch buffers can be configured to prefetch code or data or both
— Censorship protection scheme to prevent flash content visibility
— Flash divided into two independent arrays, allowing reading from one array while erasing/programming the other
array (used for EEPROM emulation)
— Memory block:
– For MPC5634M: 18 blocks (4 16 KB, 2 32 KB, 2 64 KB, 10 128 KB)
– For MPC5633M: 14 blocks (4 16 KB, 2 32 KB, 2 64 KB, 6 128 KB)
– For MPC5632M: 12 blocks (4 16 KB, 2 32 KB, 2 64 KB, 4 128 KB)
— Hardware programming state machine
On-chip static RAM
— For MPC5634M: 94 KB general purpose RAM of which 32 KB are on standby power supply
— For MPC5633M: 64 KB general purpose RAM of which 24 KB are on standby power supply
— For MPC5632M: 48 KB general purpose RAM of which 24 KB are on standby power supply
Boot assist module (BAM)
— Enables and manages the transition of MCU from reset to user code execution in the following configurations:
– Execution from internal flash memory
– Execution from external memory on the calibration bus
– Download and execution of code via FlexCAN or eSCI
Periodic interrupt timer (PIT)
— 32-bit wide down counter with automatic reload
— Four channels clocked by system clock
— One channel clocked by crystal clock
— Each channel can produce periodic software interrupt
— Each channel can produce periodic triggers for eQADC queue triggering
— One channel out of the five can be used as wake-up timer to wake device from low power stop mode
System timer module (STM)
— 32-bit up counter with 8-bit prescaler
— Clocked from system clock
— Four-channel timer compare hardware
— Each channel can generate a unique interrupt request
— Designed to address AutoSAR task monitor function
Software watchdog timer (SWT)
— 32-bit timer
— Clock by system clock or crystal clock
— Can generate either system reset or non-maskable interrupt followed by system reset
— Enabled out of reset
Enhanced modular I/O system (eMIOS)
— 16 timer channels (up to 14 channels in 144 LQFP)
— 24-bit timer resolution
— Supports a subset of the timer modes found in eMIOS on MPC5554
— 3 selectable time bases plus shared time or angle counter bus from eTPU2
— DMA and interrupt request support
MPC5634M Microcontroller Data Sheet, Rev. 8
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— Motor control capability
Second-generation enhanced time processor unit (eTPU2)
— Object-code compatible with eTPU—no changes are required to hardware or software if only eTPU features are
used
— Intelligent co-processor designed for timing control
— High level tools, assembler and compiler available
— 32 channels (each channel has dedicated I/O pin in all packages)
— 24-bit timer resolution
— 14 KB code memory and 3 KB data memory
— Double match and capture on all channels
— Angle clock hardware support
— Shared time or angle counter bus with eMIOS
— DMA and interrupt request support
— Nexus Class 1 debug support
— eTPU2 enhancements
– Counters and channels can run at full system clock speed
– Software watchdog
– Real-time performance monitor
– Instruction set enhancements for smaller more flexible code generation
– Programmable channel mode for customization of channel operation
Enhanced queued A/D converter (eQADC)
— Two independent on-chip RSD Cyclic ADCs
– 8-, 10-, and 12-bit resolution
– Differential conversions
– Targets up to 10-bit accuracy at 500 KSample/s (ADC_CLK = 7.5 MHz) and 8-bit accuracy at 1 MSample/s
(ADC_CLK = 15 MHz) for differential conversions
– Differential channels include variable gain amplifier for improved dynamic range (1; 2; 4)
– Differential channels include programmable pull-up and pull-down resistors for biasing and sensor diagnostics
(200 k; 100 k; low value of 5 k)
– Single-ended signal range from 0 to 5 V
– Sample times of 2 (default), 8, 64 or 128 ADC clock cycles
– Provides time stamp information when requested
– Parallel interface to eQADC command FIFOs (CFIFOs) and result FIFOs (RFIFOs)
– Supports both right-justified unsigned and signed formats for conversion results
– Temperature sensor to enable measurement of die temperature
– Ability to measure all power supply pins directly
— Automatic application of ADC calibration constants
– Provision of reference voltages (25% VREF and 75% VREF) for ADC calibration purposes
— Up to 341 input channels available to the two on-chip ADCs
— Four pairs of differential analog input channels
— Full duplex synchronous serial interface to an external device
– Has a free-running clock for use by the external device
– Supports a 26-bit message length
1. 176-pin and 208-pin packages have 34 input channels; 144-pin package has 32.
MPC5634M Microcontroller Data Sheet, Rev. 8
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– Transmits a null message when there are no triggered CFIFOs with commands bound for external CBuffers,
or when there are triggered CFIFOs with commands bound for external CBuffers but the external CBuffers are
full
— Parallel Side Interface to communicate with an on-chip companion module
— Zero jitter triggering for queue 0. (Queue 0 trigger causes current conversion to be aborted and the queued
conversions in the CBUFFER to be bypassed. Delay from Trigger to start of conversion is 13 system clocks + 1
ADC clock.)
— eQADC Result Streaming. Generation of a continuous stream of ADC conversion results from a single eQADC
command word. Controlled by two different trigger signals; one to define the rate at which results are generated
and the other to define the beginning and ending of the stream. Used to digitize waveforms during specific
time/angle windows, e.g., engine knock sensor sampling.
— Angular Decimation. The ability of the eQADC to sample an analog waveform in the time domain, perform
FIR/IIR filtering also in the time domain, but to down sample the results in the angle domain. Resulting in a time
domain filtered result at a given engine angle.
— Priority Based CFIFOs
– Supports six CFIFOs with fixed priority. The lower the CFIFO number, the higher its priority. When
commands of distinct CFIFOs are bound for the same CBuffer, the higher priority CFIFO is always served
first.
– Supports software and several hardware trigger modes to arm a particular CFIFO
– Generates interrupt when command coherency is not achieved
— External Hardware Triggers
– Supports rising edge, falling edge, high level and low level triggers
– Supports configurable digital filter
— Supports four external 8-to-1 muxes which can expand the input channel number from 341 to 59
Two deserial serial peripheral interface modules (DSPI)
— SPI
– Full duplex communication ports with interrupt and DMA request support
– Supports all functional modes from QSPI subblock of QSMCM (MPC5xx family)
– Support for queues in RAM
– 6 chip selects, expandable to 64 with external demultiplexers
– Programmable frame size, baud rate, clock delay and clock phase on a per frame basis
– Modified SPI mode for interfacing to peripherals with longer setup time requirements
– LVDS option for output clock and data to allow higher speed communication
— Deserial serial interface (DSI)
– Pin reduction by hardware serialization and deserialization of eTPU, eMIOS channels and GPIO
– 32 bits per DSPI module
– Triggered transfer control and change in data transfer control (for reduced EMI)
– Compatible with Microsecond Bus Version 1.0 downlink
Two enhanced serial communication interface (eSCI) modules
— UART mode provides NRZ format and half or full duplex interface
— eSCI bit rate up to 1 Mbps
— Advanced error detection, and optional parity generation and detection
— Word length programmable as 8, 9, 12 or 13 bits
— Separately enabled transmitter and receiver
— LIN support
1. 176-pin and 208-ball packages.
MPC5634M Microcontroller Data Sheet, Rev. 8
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— DMA support
— Interrupt request support
— Programmable clock source: system clock or oscillator clock
— Support Microsecond Bus (Timed Serial Bus - TSB) uplink Version 1.0
Two FlexCAN
— One with 32 message buffers; the second with 64 message buffers
— Full implementation of the CAN protocol specification, Version 2.0B
— Based on and including all existing features of the Freescale TouCAN module
— Programmable acceptance filters
— Short latency time for high priority transmit messages
— Arbitration scheme according to message ID or message buffer number
— Listen only mode capabilities
— Programmable clock source: system clock or oscillator clock
— Message buffers may be configured as mailboxes or as FIFO
Nexus port controller (NPC)
— Per IEEE-ISTO 5001-2003
— Real time development support for Power Architecture core and eTPU engine through Nexus class 2/1
— Read and write access (Nexus class 3 feature that is supported on this device)
– Run-time access of entire memory map
– Calibration
— Support for data value breakpoints / watchpoints
– Run-time access of entire memory map
– Calibration
Table constants calibrated using MMU and internal and external RAM
Scalar constants calibrated using cache line locking
— Configured via the IEEE 1149.1 (JTAG) port
IEEE 1149.1 JTAG controller (JTAGC)
— IEEE 1149.1-2001 Test Access Port (TAP) interface
— 5-bit instruction register that supports IEEE 1149.1-2001 defined instructions
— 5-bit instruction register that supports additional public instructions
— Three test data registers: a bypass register, a boundary scan register, and a device identification register
— Censorship disable register. By writing the 64-bit serial boot password to this register, Censorship may be disabled
until the next reset
— TAP controller state machine that controls the operation of the data registers, instruction register and associated
circuitry
On-chip Voltage Regulator for single 5 V supply operation
— On-chip regulator 5 V to 3.3 V for internal supplies
— On-chip regulator controller 5 V to 1.2 V (with external bypass transistor) for core logic
Low-power modes
— SLOW Mode. Allows device to be run at very low speed (approximately 1 MHz), with modules (including the
PLL) selectively disabled in software
— STOP Mode. System clock stopped to all modules including the CPU. Wake-up timer used to restart the system
clock after a predetermined time
MPC5634M Microcontroller Data Sheet, Rev. 8
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Introduction
1.1
Document overview
This document provides an overview and describes the features of the MPC5634M series of microcontroller units (MCUs). For
functional characteristics, refer to the device reference manual. Electrical specifications and package mechanical drawings are
included in this device data sheet. Pin assignments can be found in both the reference manual and data sheet.
1.2
Description
These 32-bit automotive microcontrollers are a family of system-on-chip (SoC) devices that contain all the features of the
MPC5500 family and many new features coupled with high performance 90 nm CMOS technology to provide substantial
reduction of cost per feature and significant performance improvement. The advanced and cost-efficient host processor core of
this automotive controller family is built on Power Architecture® technology. This family contains enhancements that improve
the architecture’s fit in embedded applications, includes additional instruction support for digital signal processing (DSP),
integrates technologies—such as an enhanced time processor unit, enhanced queued analog-to-digital converter, Controller
Area Network, and an enhanced modular input-output system—that are important for today’s lower-end powertrain
applications. This device family is a completely compatible extension to Freescale’s MPC5500 family. The device has a single
level of memory hierarchy consisting of up to 94 KB on-chip SRAM and up to 1.5 MB of internal flash memory. The device
also has an external bus interface (EBI) for ‘calibration’. This external bus interface has been designed to support most of the
standard memories used with the MPC5xx and MPC55xx families.
MPC5634M Microcontroller Data Sheet, Rev. 8
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2
Overview
This document provides electrical specifications, pin assignments, and package diagrams for the MPC5634M series of
microcontroller units (MCUs). For functional characteristics, refer to the MPC5634M Microcontroller Reference Manual.
The MPC5634M series microcontrollers are system-on-chip devices that are built on Power Architecture® technology and:
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Are 100% user-mode compatible with the Power Architecture instruction set
Contain enhancements that improve the architecture’s fit in embedded applications
Include additional instruction support for digital signal processing (DSP)
Integrate technologies such as an enhanced time processor unit, enhanced queued analog-to-digital converter,
Controller Area Network, and an enhanced modular input-output system
MPC5634M Microcontroller Data Sheet, Rev. 8
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Freescale Semiconductor
2.1
Device comparison
Table 1. MPC5634M family device summary
Feature
MPC5634M
MPC5633M
MPC5632M
1536
1024
768
Total SRAM size (KB)
94
64
48
Standby SRAM size (KB)
32
24
24
32-bit e200z335
with SPE support
32-bit e200z335
with SPE support
32-bit e200z335
with SPE support
Core frequency (MHz)
60/80
40/60/80
40/60
1
16 bits
16 bits
—
DMA (direct memory access) channels
32
32
32
eMIOS (enhanced modular input-output system)
channels
16
16
8
Up to 342
Up to 342
Up to 322
eSCI (serial communication interface)
2
2
2
DSPI (deserial serial peripheral interface)
2
2
2
Microsecond Bus compatible interface
2
2
2
eTPU (enhanced time processor unit)
Yes
Yes
Yes
Channels
32
32
32
Code memory (KB)
14
14
14
Parameter RAM (KB)
3
3
3
2
2
2
FMPLL (frequency-modulated phase-locked loop)
Yes
Yes
Yes
INTC (interrupt controller) channels
3644
3644
3644
JTAG controller
Yes
Yes
Yes
Class 2+
Class 2+
Class 2+
Yes
Yes
Yes
5
5
5
4 channels
4 channels
4 channels
Temperature sensor
Yes
Yes
Yes
Windowing software watchdog
Yes
Yes
Yes
144 LQFP
176 LQFP
208 MAPBGA
144 LQFP
176 LQFP
208 MAPBGA
144 LQFP
Flash memory size (KB)
Processor core
Calibration bus width
eQADC (enhanced queued analog-to-digital
converter) channels (on-chip)
FlexCAN (controller area network)
3
NDI (Nexus development interface) level
Non-maskable interrupt and critical interrupt
PIT (peripheral interrupt timers)
Task monitor timer
Packages
1
Calibration package only.
The 176-pin and 208-pin packages have 34 input channels; 144-pin package has 32.
3
One FlexCAN module has 64 message buffers; the other has 32 message buffers.
2
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
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2.2
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165 interrupt channels are reserved for compatibility with future devices. This device has 191 peripheral interrupt
sources plus 8 software interrupts available to the user.
MPC5634M features
Operating Parameters
— Fully static operation, 0 MHz – 80 MHz (plus 2% frequency modulation - 82 MHz)
— –40 C to 150 C junction temperature operating range
— Low power design
– Less than 400 mW power dissipation (nominal)
– Designed for dynamic power management of core and peripherals
– Software controlled clock gating of peripherals
– Low power stop mode, with all clocks stopped
— Fabricated in 90 nm process
— 1.2 V internal logic
— Single power supply with 5.0 V 5% (4.5 V to 5.25 V) with internal regulator to provide 3.3 V and 1.2 V
for the core
— Input and output pins with 5.0 V 5% (4.5 V to 5.25 V) range
– 35%/65% VDDE CMOS switch levels (with hysteresis)
– Selectable hysteresis
– Selectable slew rate control
— Nexus pins powered by 3.3 V supply
— Designed with EMI reduction techniques
– Phase-locked loop
– Frequency modulation of system clock frequency
– On-chip bypass capacitance
– Selectable slew rate and drive strength
High performance e200z335 core processor
— 32-bit Power Architecture Book E programmer’s model
— Variable Length Encoding Enhancements
– Allows Power Architecture instruction set to be optionally encoded in a mixed 16 and 32-bit instructions
– Results in smaller code size
— Single issue, 32-bit Power Architecture Book E compliant CPU
— In-order execution and retirement
— Precise exception handling
— Branch processing unit
– Dedicated branch address calculation adder
– Branch acceleration using Branch Lookahead Instruction Buffer
— Load/store unit
– One-cycle load latency
– Fully pipelined
– Big and Little Endian support
– Misaligned access support
– Zero load-to-use pipeline bubbles
— Thirty-two 64-bit general purpose registers (GPRs)
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Memory management unit (MMU) with 16-entry fully-associative translation look-aside buffer (TLB)
Separate instruction bus and load/store bus
Vectored interrupt support
Interrupt latency < 120 ns @ 80 MHz (measured from interrupt request to execution of first instruction of interrupt
exception handler)
— Non-maskable interrupt (NMI) input for handling external events that must produce an immediate response, e.g.,
power down detection. On this device, the NMI input is connected to the Critical Interrupt Input. (May not be
recoverable)
— Critical Interrupt input. For external interrupt sources that are higher priority than provided by the Interrupt
Controller. (Always recoverable)
— New ‘Wait for Interrupt’ instruction, to be used with new low power modes
— Reservation instructions for implementing read-modify-write accesses
— Signal processing extension (SPE) APU
– Operating on all 32 GPRs that are all extended to 64 bits wide
– Provides a full compliment of vector and scalar integer and floating point arithmetic operations (including
integer vector MAC and MUL operations) (SIMD)
– Provides rich array of extended 64-bit loads and stores to/from extended GPRs
– Fully code compatible with e200z6 core
— Floating point
– IEEE 754 compatible with software wrapper
– Scalar single precision in hardware, double precision with software library
– Conversion instructions between single precision floating point and fixed point
– Fully code compatible with e200z6 core
— Long cycle time instructions, except for guarded loads, do not increase interrupt latency
— Extensive system development support through Nexus debug port
Advanced microcontroller bus architecture (AMBA) crossbar switch (XBAR)
— Three master ports, four slave ports
– Masters: CPU Instruction bus; CPU Load/store bus (Nexus); eDMA
– Slave: Flash; SRAM; Peripheral Bridge; calibration EBI
— 32-bit internal address bus, 64-bit internal data bus
Enhanced direct memory access (eDMA) controller
— 32 channels support independent 8-bit, 16-bit, or 32-bit single value or block transfers
— Supports variable sized queues and circular queues
— Source and destination address registers are independently configured to post-increment or remain constant
— Each transfer is initiated by a peripheral, CPU, or eDMA channel request
— Each eDMA channel can optionally send an interrupt request to the CPU on completion of a single value or block
transfer
Interrupt controller (INTC)
— 191 peripheral interrupt request sources
— 8 software settable interrupt request sources
— 9-bit vector
– Unique vector for each interrupt request source
– Provided by hardware connection to processor or read from register
— Each interrupt source can be programmed to one of 16 priorities
— Preemption
– Preemptive prioritized interrupt requests to processor
MPC5634M Microcontroller Data Sheet, Rev. 8
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– ISR at a higher priority preempts ISRs or tasks at lower priorities
– Automatic pushing or popping of preempted priority to or from a LIFO
– Ability to modify the ISR or task priority. Modifying the priority can be used to implement the Priority Ceiling
Protocol for accessing shared resources.
— Low latency—three clocks from receipt of interrupt request from peripheral to interrupt request to processor
Frequency Modulating Phase-locked loop (FMPLL)
— Reference clock pre-divider (PREDIV) for finer frequency synthesis resolution
— Reduced frequency divider (RFD) for reducing the FMPLL output clock frequency without forcing the FMPLL
to re-lock
— System clock divider (SYSDIV) for reducing the system clock frequency in normal or bypass mode
— Input clock frequency range from 4 MHz to 20 MHz before the pre-divider, and from 4 MHz to 16 MHz at the
FMPLL input
— Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz
— VCO free-running frequency range from 25 MHz to 125 MHz
— Four bypass modes: crystal or external reference with PLL on or off
— Two normal modes: crystal or external reference
— Programmable frequency modulation
– Triangle wave modulation
– Register programmable modulation frequency and depth
— Lock detect circuitry reports when the FMPLL has achieved frequency lock and continuously monitors lock status
to report loss of lock conditions
– User-selectable ability to generate an interrupt request upon loss of lock
– User-selectable ability to generate a system reset upon loss of lock
— Clock quality monitor (CQM) module provides loss-of-clock detection for the FMPLL reference and output
clocks
– User-selectable ability to generate an interrupt request upon loss of clock
– User-selectable ability to generate a system reset upon loss of clock
– Backup clock (reference clock or FMPLL free-running) can be applied to the system in case of loss of clock
Calibration bus interface (EBI)
— Available only in the calibration package
— 1.8 V to 3.3 V ± 10% I/O (1.6 V to 3.6 V)
— Memory controller with support for various memory types
— 16-bit data bus, up to 22-bit address bus
— Selectable drive strength
— Configurable bus speed modes
— Bus monitor
— Configurable wait states
System integration unit (SIU)
— Centralized GPIO control of 80 I/O pins
— Centralized pad control on a per-pin basis
– Pin function selection
– Configurable weak pull-up or pull-down
– Drive strength
– Slew rate
– Hysteresis
— System reset monitoring and generation
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External interrupt inputs, filtering and control
Critical Interrupt control
Non-Maskable Interrupt control
Internal multiplexer subblock (IMUX)
– Allows flexible selection of eQADC trigger inputs (eTPU, eMIOS and external signals)
– Allows selection of interrupt requests between external pins and DSPI
Error correction status module (ECSM)
— Configurable error-correcting codes (ECC) reporting
— Single-bit error correction reporting
On-chip flash memory
— Up to 1.5 MB flash memory, accessed via a 64-bit wide bus interface
— 16 KB shadow block
— Fetch Accelerator
– Provide single cycle flash access at 80 MHz
– Quadruple 128-bit wide prefetch/burst buffers
– Prefetch buffers can be configured to prefetch code or data or both
— Censorship protection scheme to prevent flash content visibility
— Flash divided into two independent arrays, allowing reading from one array while erasing/programming the other
array (used for EEPROM emulation)
— Memory block:
– For MPC5634M: 18 blocks (4 16 KB, 2 32 KB, 2 64 KB, 10 128 KB)
– For MPC5633M: 14 blocks (4 16 KB, 2 32 KB, 2 64 KB, 6 128 KB)
– For MPC5632M: 12 blocks (4 16 KB, 2 32 KB, 2 64 KB, 4 128 KB)
— Hardware programming state machine
On-chip static RAM
— For MPC5634M: 94 KB general purpose RAM of which 32 KB are on standby power supply
— For MPC5633M: 64 KB general purpose RAM of which 24 KB are on standby power supply
— For MPC5632M: 48 KB general purpose RAM of which 24 KB are on standby power supply
Boot assist module (BAM)
— Enables and manages the transition of MCU from reset to user code execution in the following configurations:
– Execution from internal flash memory
– Execution from external memory on the calibration bus
– Download and execution of code via FlexCAN or eSCI
Periodic interrupt timer (PIT)
— 32-bit wide down counter with automatic reload
— Four channels clocked by system clock
— One channel clocked by crystal clock
— Each channel can produce periodic software interrupt
— Each channel can produce periodic triggers for eQADC queue triggering
— One channel out of the five can be used as wake-up timer to wake device from low power stop mode
System timer module (STM)
— 32-bit up counter with 8-bit prescaler
— Clocked from system clock
— Four-channel timer compare hardware
— Each channel can generate a unique interrupt request
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— Designed to address AutoSAR task monitor function
Software watchdog timer (SWT)
— 32-bit timer
— Clock by system clock or crystal clock
— Can generate either system reset or non-maskable interrupt followed by system reset
— Enabled out of reset
Enhanced modular I/O system (eMIOS)
— 16 timer channels (up to 14 channels in 144 LQFP)
— 24-bit timer resolution
— Supports a subset of the timer modes found in eMIOS on MPC5554
— 3 selectable time bases plus shared time or angle counter bus from eTPU2
— DMA and interrupt request support
— Motor control capability
Second-generation enhanced time processor unit (eTPU2)
— Object-code compatible with eTPU—no changes are required to hardware or software if only eTPU features are
used
— Intelligent co-processor designed for timing control
— High level tools, assembler and compiler available
— 32 channels (each channel has dedicated I/O pin in all packages)
— 24-bit timer resolution
— 14 KB code memory and 3 KB data memory
— Double match and capture on all channels
— Angle clock hardware support
— Shared time or angle counter bus with eMIOS
— DMA and interrupt request support
— Nexus Class 1 debug support
— eTPU2 enhancements
– Counters and channels can run at full system clock speed
– Software watchdog
– Real-time performance monitor
– Instruction set enhancements for smaller more flexible code generation
– Programmable channel mode for customization of channel operation
Enhanced queued A/D converter (eQADC)
— Two independent on-chip RSD Cyclic ADCs
– 8-, 10-, and 12-bit resolution
– Differential conversions
– Targets up to 10-bit accuracy at 500 KSample/s (ADC_CLK = 7.5 MHz) and 8-bit accuracy at 1 MSample/s
(ADC_CLK = 15 MHz) for differential conversions
– Differential channels include variable gain amplifier for improved dynamic range (1; 2; 4)
– Differential channels include programmable pull-up and pull-down resistors for biasing and sensor diagnostics
(200 k; 100 k; low value of 5 k)
– Single-ended signal range from 0 to 5 V
– Sample times of 2 (default), 8, 64 or 128 ADC clock cycles
– Provides time stamp information when requested
– Parallel interface to eQADC command FIFOs (CFIFOs) and result FIFOs (RFIFOs)
– Supports both right-justified unsigned and signed formats for conversion results
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– Temperature sensor to enable measurement of die temperature
– Ability to measure all power supply pins directly
— Automatic application of ADC calibration constants
– Provision of reference voltages (25% VREF and 75% VREF) for ADC calibration purposes
— Up to 341 input channels available to the two on-chip ADCs
— Four pairs of differential analog input channels
— Full duplex synchronous serial interface to an external device
– Has a free-running clock for use by the external device
– Supports a 26-bit message length
– Transmits a null message when there are no triggered CFIFOs with commands bound for external CBuffers,
or when there are triggered CFIFOs with commands bound for external CBuffers but the external CBuffers are
full
— Parallel Side Interface to communicate with an on-chip companion module
— Zero jitter triggering for queue 0. (Queue 0 trigger causes current conversion to be aborted and the queued
conversions in the CBUFFER to be bypassed. Delay from Trigger to start of conversion is 13 system clocks + 1
ADC clock.)
— eQADC Result Streaming. Generation of a continuous stream of ADC conversion results from a single eQADC
command word. Controlled by two different trigger signals; one to define the rate at which results are generated
and the other to define the beginning and ending of the stream. Used to digitize waveforms during specific
time/angle windows, e.g., engine knock sensor sampling.
— Angular Decimation. The ability of the eQADC to sample an analog waveform in the time domain, perform
FIR/IIR filtering also in the time domain, but to down sample the results in the angle domain. Resulting in a time
domain filtered result at a given engine angle.
— Priority Based CFIFOs
– Supports six CFIFOs with fixed priority. The lower the CFIFO number, the higher its priority. When
commands of distinct CFIFOs are bound for the same CBuffer, the higher priority CFIFO is always served
first.
– Supports software and several hardware trigger modes to arm a particular CFIFO
– Generates interrupt when command coherency is not achieved
— External Hardware Triggers
– Supports rising edge, falling edge, high level and low level triggers
– Supports configurable digital filter
— Supports four external 8-to-1 muxes which can expand the input channel number from 342 to 59
Two deserial serial peripheral interface modules (DSPI)
— SPI
– Full duplex communication ports with interrupt and DMA request support
– Supports all functional modes from QSPI subblock of QSMCM (MPC5xx family)
– Support for queues in RAM
– 6 chip selects, expandable to 64 with external demultiplexers
– Programmable frame size, baud rate, clock delay and clock phase on a per frame basis
– Modified SPI mode for interfacing to peripherals with longer setup time requirements
– LVDS option for output clock and data to allow higher speed communication
— Deserial serial interface (DSI)
– Pin reduction by hardware serialization and deserialization of eTPU, eMIOS channels and GPIO
– 32 bits per DSPI module
1. 176-pin and 208-pin packages have 34 input channels; 144-pin package has 32.
2. 176-pin and 208-ball packages.
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Freescale Semiconductor
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– Triggered transfer control and change in data transfer control (for reduced EMI)
– Compatible with Microsecond Bus Version 1.0 downlink
Two enhanced serial communication interface (eSCI) modules
— UART mode provides NRZ format and half or full duplex interface
— eSCI bit rate up to 1 Mbps
— Advanced error detection, and optional parity generation and detection
— Word length programmable as 8, 9, 12 or 13 bits
— Separately enabled transmitter and receiver
— LIN support
— DMA support
— Interrupt request support
— Programmable clock source: system clock or oscillator clock
— Support Microsecond Bus (Timed Serial Bus - TSB) uplink Version 1.0
Two FlexCAN
— One with 32 message buffers; the second with 64 message buffers
— Full implementation of the CAN protocol specification, Version 2.0B
— Based on and including all existing features of the Freescale TouCAN module
— Programmable acceptance filters
— Short latency time for high priority transmit messages
— Arbitration scheme according to message ID or message buffer number
— Listen only mode capabilities
— Programmable clock source: system clock or oscillator clock
— Message buffers may be configured as mailboxes or as FIFO
Nexus port controller (NPC)
— Per IEEE-ISTO 5001-2003
— Real time development support for Power Architecture core and eTPU engine through Nexus class 2/1
— Read and write access (Nexus class 3 feature that is supported on this device)
– Run-time access of entire memory map
– Calibration
— Support for data value breakpoints / watchpoints
– Run-time access of entire memory map
– Calibration
Table constants calibrated using MMU and internal and external RAM
Scalar constants calibrated using cache line locking
— Configured via the IEEE 1149.1 (JTAG) port
IEEE 1149.1 JTAG controller (JTAGC)
— IEEE 1149.1-2001 Test Access Port (TAP) interface
— 5-bit instruction register that supports IEEE 1149.1-2001 defined instructions
— 5-bit instruction register that supports additional public instructions
— Three test data registers: a bypass register, a boundary scan register, and a device identification register
— Censorship disable register. By writing the 64-bit serial boot password to this register, Censorship may be disabled
until the next reset
— TAP controller state machine that controls the operation of the data registers, instruction register and associated
circuitry
On-chip Voltage Regulator for single 5 V supply operation
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2.3
2.3.1
— On-chip regulator 5 V to 3.3 V for internal supplies
— On-chip regulator controller 5 V to 1.2 V (with external bypass transistor) for core logic
Low-power modes
— SLOW Mode. Allows device to be run at very low speed (approximately 1 MHz), with modules (including the
PLL) selectively disabled in software
— STOP Mode. System clock stopped to all modules including the CPU. Wake-up timer used to restart the system
clock after a predetermined time
MPC5634M feature details
e200z335 core
The e200z335 processor utilizes a four stage pipeline for instruction execution. The Instruction Fetch (stage 1), Instruction
Decode/Register file Read/Effective Address Calculation (stage 2), Execute/Memory Access (stage 3), and Register Writeback
(stage 4) stages operate in an overlapped fashion, allowing single clock instruction execution for most instructions.
The integer execution unit consists of a 32-bit Arithmetic Unit (AU), a Logic Unit (LU), a 32-bit Barrel shifter (Shifter), a
Mask-Insertion Unit (MIU), a Condition Register manipulation Unit (CRU), a Count-Leading-Zeros unit (CLZ), a 3232
Hardware Multiplier array, result feed-forward hardware, and support hardware for division.
Most arithmetic and logical operations are executed in a single cycle with the exception of the divide instructions. A
Count-Leading-Zeros unit operates in a single clock cycle. The Instruction Unit contains a PC incrementer and a dedicated
Branch Address adder to minimize delays during change of flow operations. Sequential prefetching is performed to ensure a
supply of instructions into the execution pipeline. Branch target prefetching is performed to accelerate taken branches.
Prefetched instructions are placed into an instruction buffer capable of holding six instructions.
Branches can also be decoded at the instruction buffer and branch target addresses calculated prior to the branch reaching the
instruction decode stage, allowing the branch target to be prefetched early. When a branch is detected at the instruction buffer,
a prediction may be made on whether the branch is taken or not. If the branch is predicted to be taken, a target fetch is initiated
and its target instructions are placed in the instruction buffer following the branch instruction. Many branches take zero cycle
to execute by using branch folding. Branches are folded out from the instruction execution pipe whenever possible. These
include unconditional branches and conditional branches with condition codes that can be resolved early.
Conditional branches which are not taken and not folded execute in a single clock. Branches with successful target prefetching
which are not folded have an effective execution time of one clock. All other taken branches have an execution time of two
clocks. Memory load and store operations are provided for byte, halfword, and word (32-bit) data with automatic zero or sign
extension of byte and halfword load data as well as optional byte reversal of data. These instructions can be pipelined to allow
effective single cycle throughput. Load and store multiple word instructions allow low overhead context save and restore
operations. The load/store unit contains a dedicated effective address adder to allow effective address generation to be
optimized. Also, a load-to-use dependency does not incur any pipeline bubbles for most cases.
The Condition Register unit supports the condition register (CR) and condition register operations defined by the Power
Architecture. The condition register consists of eight 4-bit fields that reflect the results of certain operations, such as move,
integer and floating-point compare, arithmetic, and logical instructions, and provide a mechanism for testing and branching.
Vectored and autovectored interrupts are supported by the CPU. Vectored interrupt support is provided to allow multiple
interrupt sources to have unique interrupt handlers invoked with no software overhead.
The hardware floating-point unit utilizes the IEEE-754 single-precision floating-point format and supports single-precision
floating-point operations in a pipelined fashion. The general purpose register file is used for source and destination operands,
thus there is a unified storage model for single-precision floating-point data types of 32 bits and the normal integer type.
Single-cycle floating-point add, subtract, multiply, compare, and conversion operations are provided. Divide instructions are
multi-cycle and are not pipelined.
The Signal Processing Extension (SPE) Auxiliary Processing Unit (APU) provides hardware SIMD operations and supports a
full complement of dual integer arithmetic operation including Multiply Accumulate (MAC) and dual integer multiply (MUL)
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
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in a pipelined fashion. The general purpose register file is enhanced such that all 32 of the GPRs are extended to 64 bits wide
and are used for source and destination operands, thus there is a unified storage model for 3232 MAC operations which
generate greater than 32-bit results.
The majority of both scalar and vector operations (including MAC and MUL) are executed in a single clock cycle. Both scalar
and vector divides take multiple clocks. The SPE APU also provides extended load and store operations to support the transfer
of data to and from the extended 64-bit GPRs. This SPE APU is fully binary compatible with e200z6 SPE APU used in
MPC5554 and MPC5553.
The CPU includes support for Variable Length Encoding (VLE) instruction enhancements. This enables the classic Power
Architecture instruction set to be represented by a modified instruction set made up from a mixture of 16- and 32-bit
instructions. This results in a significantly smaller code size footprint without noticeably affecting performance. The classic
Power Architecture instruction set and VLE instruction set are available concurrently. Regions of the memory map are
designated as PPC or VLE using an additional configuration bit in each of Table Look-aside Buffers (TLB) entries in the MMU.
The CPU core is enhanced by the addition of two additional interrupt sources; Non-Maskable Interrupt and Critical Interrupt.
These two sources are routed directly from package pins, via edge detection logic in the SIU to the CPU, bypassing completely
the Interrupt Controller. Once the edge detection logic is programmed, it cannot be disabled, except by reset. The non-maskable
Interrupt is, as the name suggests, completely un-maskable and when asserted will always result in the immediate execution of
the respective interrupt service routine. The non-maskable interrupt is not guaranteed to be recoverable. The Critical Interrupt
is very similar to the non-maskable interrupt, but it can be masked by other exceptional interrupts in the CPU and is guaranteed
to be recoverable (code execution may be resumed from where it stopped).
The CPU core has an additional ‘Wait for Interrupt’ instruction that is used in conjunction with low power STOP mode. When
Low Power Stop mode is selected, this instruction is executed to allow the system clock to be stopped. An external interrupt
source or the system wake-up timer is used to restart the system clock and allow the CPU to service the interrupt.
2.3.2
Crossbar
The XBAR multi-port crossbar switch supports simultaneous connections between three master ports and four slave ports. The
crossbar supports a 32-bit address bus width and a 64-bit data bus width.
The crossbar allows three concurrent transactions to occur from the master ports to any slave port; but each master must access
a different slave. If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher
priority master and grants it ownership of the slave port. All other masters requesting that slave port are stalled until the higher
priority master completes its transactions. Requesting masters are treated with equal priority and are granted access to a slave
port in round-robin fashion, based upon the ID of the last master to be granted access. The crossbar provides the following
features:
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3 master ports:
— e200z335 core complex Instruction port
— e200z335 core complex Load/Store port
— eDMA
4 slave ports
— FLASH
— calibration bus
— SRAM
— Peripheral bridge A/B (eTPU2, eMIOS, SIU, DSPI, eSCI, FlexCAN, eQADC, BAM, decimation filter, PIT, STM
and SWT)
32-bit internal address, 64-bit internal data paths
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2.3.3
eDMA
The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data
movements via 32 programmable channels, with minimal intervention from the host processor. The hardware micro architecture
includes a DMA engine which performs source and destination address calculations, and the actual data movement operations,
along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation
is utilized to minimize the overall block size. The eDMA module provides the following features:
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2.3.4
All data movement via dual-address transfers: read from source, write to destination
Programmable source and destination addresses, transfer size, plus support for enhanced addressing modes
Transfer control descriptor organized to support two-deep, nested transfer operations
An inner data transfer loop defined by a “minor” byte transfer count
An outer data transfer loop defined by a “major” iteration count
Channel activation via one of three methods:
— Explicit software initiation
— Initiation via a channel-to-channel linking mechanism for continuous transfers
— Peripheral-paced hardware requests (one per channel)
Support for fixed-priority and round-robin channel arbitration
Channel completion reported via optional interrupt requests
1 interrupt per channel, optionally asserted at completion of major iteration count
Error termination interrupts are optionally enabled
Support for scatter/gather DMA processing
Channel transfers can be suspended by a higher priority channel
Interrupt controller
The INTC (interrupt controller) provides priority-based preemptive scheduling of interrupt requests, suitable for statically
scheduled hard real-time systems. The INTC allows interrupt request servicing from up to 191 peripheral interrupt request
sources, plus 165 sources reserved for compatibility with other family members).
For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor
is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt
request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that
lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of
interrupt request, the priority of each interrupt request is software configurable.
When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC supports the priority
ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so that
all tasks which share the resource can not preempt each other.
Multiple processors can assert interrupt requests to each other through software settable interrupt requests. These same software
settable interrupt requests also can be used to break the work involved in servicing an interrupt request into a high priority
portion and a low priority portion. The high priority portion is initiated by a peripheral interrupt request, but then the ISR asserts
a software settable interrupt request to finish the servicing in a lower priority ISR. Therefore these software settable interrupt
requests can be used instead of the peripheral ISR scheduling a task through the RTOS.
The INTC provides the following features:
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356 peripheral interrupt request sources
8 software settable interrupt request sources
9-bit vector addresses
Unique vector for each interrupt request source
Hardware connection to processor or read from register
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
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Each interrupt source can be programmed to one of 16 priorities
Preemptive prioritized interrupt requests to processor
ISR at a higher priority preempts executing ISRs or tasks at lower priorities
Automatic pushing or popping of preempted priority to or from a LIFO
Ability to modify the ISR or task priority to implement the priority ceiling protocol for accessing shared resources
Low latency—three clocks from receipt of interrupt request from peripheral to interrupt request to processor
This device also includes a non-maskable interrupt (NMI) pin that bypasses the INTC and multiplexing logic.
2.3.5
FMPLL
The FMPLL allows the user to generate high speed system clocks from a 4 MHz to 20 MHz crystal oscillator or external clock
generator. Further, the FMPLL supports programmable frequency modulation of the system clock. The PLL multiplication
factor, output clock divider ratio are all software configurable. The PLL has the following major features:
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2.3.6
Input clock frequency from 4 MHz to 20 MHz
Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz, resulting in system clock frequencies from
16 MHz to 80 MHz with granularity of 4 MHz or better
Reduced frequency divider (RFD) for reduced frequency operation without forcing the PLL to relock
3 modes of operation
— Bypass mode with PLL off
— Bypass mode with PLL running (default mode out of reset)
— PLL normal mode
Each of the three modes may be run with a crystal oscillator or an external clock reference
Programmable frequency modulation
— Modulation enabled/disabled through software
— Triangle wave modulation up to 100 kHz modulation frequency
— Programmable modulation depth (0% to 2% modulation depth)
— Programmable modulation frequency dependent on reference frequency
Lock detect circuitry reports when the PLL has achieved frequency lock and continuously monitors lock status to
report loss of lock conditions
Clock Quality Module
— detects the quality of the crystal clock and cause interrupt request or system reset if error is detected
— detects the quality of the PLL output clock. If an error is detected, causes a system reset or switches the system
clock to the crystal clock and causes an interrupt request
Programmable interrupt request or system reset on loss of lock
Calibration EBI
The Calibration EBI controls data transfer across the crossbar switch to/from memories or peripherals attached to the VertiCal
connector in the calibration address space. The Calibration EBI is only available in the VertiCal Calibration System. The
Calibration EBI includes a memory controller that generates interface signals to support a variety of external memories. The
Calibration EBI memory controller supports legacy flash, SRAM, and asynchronous memories. In addition, the calibration EBI
supports up to three regions via chip selects (two chip selects are multiplexed with two address bits), along with programmed
region-specific attributes. The calibration EBI supports the following features:
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22-bit address bus (two most significant signals multiplexed with two chip selects)
16-bit data bus
Multiplexed mode with addresses and data signals present on the data lines
MPC5634M Microcontroller Data Sheet, Rev. 8
22
Freescale Semiconductor
NOTE
The calibration EBI must be configured in multiplexed mode when the extended Nexus
trace is used on the VertiCal Calibration System. This is because Nexus signals and address
lines of the calibration bus share the same balls in the calibration package.
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2.3.7
Memory controller with support for various memory types:
— Asynchronous/legacy flash and SRAM
— Most standard memories used with the MPC5xx or MPC55xx family
Bus monitor
— User selectable
— Programmable time-out period (with 8 external bus clock resolution)
Configurable wait states (via chip selects)
3 chip-select (Cal_CS[0], Cal_CS[2:3]) signals (Multiplexed with 2 most significant address signals)
2 write/byte enable (WE[0:1]/BE[0:1]) signals
Configurable bus speed modes
— system frequency
— 1/2 of system frequency
— 1/4 of system frequency
Optional automatic CLKOUT gating to save power and reduce EMI
Compatible with MPC5xx external bus (with some limitations)
Selectable drive strengths; 10 pF, 20 pF, 30 pF, 50 pF
SIU
The MPC5634M SIU controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO),
internal peripheral multiplexing, and the system reset operation. The reset configuration block contains the external pin boot
configuration logic. The pad configuration block controls the static electrical characteristics of I/O pins. The GPIO block
provides uniform and discrete input/output control of the I/O pins of the MCU. The reset controller performs reset monitoring
of internal and external reset sources, and drives the RSTOUT pin. Communication between the SIU and the e200z335 CPU
core is via the crossbar switch. The SIU provides the following features:
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System configuration
— MCU reset configuration via external pins
— Pad configuration control for each pad
— Pad configuration control for virtual I/O via DSPI serialization
System reset monitoring and generation
— Power-on reset support
— Reset status register provides last reset source to software
— Glitch detection on reset input
— Software controlled reset assertion
External interrupt
— 11 interrupt requests
— Rising or falling edge event detection
— Programmable digital filter for glitch rejection
— Critical Interrupt request
— Non-Maskable Interrupt request
GPIO
— GPIO function on 80 I/O pins
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
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— Virtual GPIO on 64 I/O pins via DSPI serialization (requires external deserialization device)
— Dedicated input and output registers for setting each GPIO and Virtual GPIO pin
Internal multiplexing
— Allows serial and parallel chaining of DSPIs
— Allows flexible selection of eQADC trigger inputs
— Allows selection of interrupt requests between external pins and DSPI
ECSM
The error correction status module provides status information regarding platform memory errors reported by error-correcting
codes.
2.3.9
Flash
Devices in the MPC5634M family provide up to 1.5 MB of programmable, non-volatile, flash memory. The non-volatile
memory (NVM) can be used for instruction and/or data storage. The flash module includes a Fetch Accelerator, that optimizes
the performance of the flash array to match the CPU architecture and provides single cycle random access to the flash @
80 MHz. The flash module interfaces the system bus to a dedicated flash memory array controller. For CPU ‘loads’, DMA
transfers and CPU instruction fetch, it supports a 64-bit data bus width at the system bus port, and a 128-bit read data interface
to flash memory. The module contains a four-entry, 128-bit prefetch buffer and a prefetch controller which prefetches sequential
lines of data from the flash array into the buffer. Prefetch buffer hits allow no-wait responses. Normal flash array accesses are
registered and are forwarded to the system bus on the following cycle, incurring three wait-states. Prefetch operations may be
automatically controlled, and are restricted to instruction fetch.
The flash memory provides the following features:
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Supports a 64-bit data bus for instruction fetch, CPU loads and DMA access. Byte, halfword, word and doubleword
reads are supported. Only aligned word and doubleword writes are supported.
Fetch Accelerator
— Architected to optimize the performance of the flash with the CPU to provide single cycle random access to the
flash up to 80 MHz system clock speed
— Configurable read buffering and line prefetch support
— Four line read buffers (128 bits wide) and a prefetch controller
Hardware and software configurable read and write access protections on a per-master basis
Interface to the flash array controller is pipelined with a depth of one, allowing overlapped accesses to proceed in
parallel for interleaved or pipelined flash array designs
Configurable access timing allowing use in a wide range of system frequencies
Multiple-mapping support and mapping-based block access timing (0-31 additional cycles) allowing use for emulation
of other memory types
Software programmable block program/erase restriction control
Erase of selected block(s)
Read page size of 128 bits (four words)
ECC with single-bit correction, double-bit detection
Program page size of 128 bits (four words) to accelerate programming
ECC single-bit error corrections are visible to software
Minimum program size is two consecutive 32-bit words, aligned on a 0-modulo-8 byte address, due to ECC
Embedded hardware program and erase algorithm
Erase suspend, program suspend and erase-suspended program
Shadow information stored in non-volatile shadow block
MPC5634M Microcontroller Data Sheet, Rev. 8
24
Freescale Semiconductor
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Independent program/erase of the shadow block
2.3.10
SRAM
The MPC5634M SRAM module provides a general-purpose up to 94 KB memory block. The SRAM controller includes these
features:
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Supports read/write accesses mapped to the SRAM memory from any master
32 KB or 24 KB block powered by separate supply for standby operation
Byte, halfword, word and doubleword addressable
ECC performs single-bit correction, double-bit detection on 32-bit data element
2.3.11
BAM
The BAM (Boot Assist Module) is a block of read-only memory that is programmed once by Freescale and is identical for all
MPC5634M MCUs. The BAM program is executed every time the MCU is powered-on or reset in normal mode. The BAM
supports different modes of booting. They are:
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Booting from internal flash memory
Serial boot loading (A program is downloaded into RAM via eSCI or the FlexCAN and then executed)
Booting from external memory on calibration bus
The BAM also reads the reset configuration half word (RCHW) from internal flash memory and configures the MPC5634M
hardware accordingly. The BAM provides the following features:
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Sets up MMU to cover all resources and mapping all physical address to logical addresses with minimum address
translation
Sets up the MMU to allow user boot code to execute as either Power Architecture code (default) or as Freescale VLE
code
Detection of user boot code
Automatic switch to serial boot mode if internal flash is blank or invalid
Supports user programmable 64-bit password protection for serial boot mode
Supports serial bootloading via FlexCAN bus and eSCI using Freescale protocol
Supports serial bootloading via FlexCAN bus and eSCI with auto baud rate sensing
Supports serial bootloading of either Power Architecture code (default) or Freescale VLE code
Supports booting from calibration bus interface
Supports censorship protection for internal flash memory
Provides an option to enable the core watchdog timer
Provides an option to disable the system watchdog timer
2.3.12
eMIOS
The eMIOS (Enhanced Modular Input Output System) module provides the functionality to generate or measuretime events.
The channels on this module provide a range of operating modes including the capability to perform dual input capture or dual
output compare as well as PWM output.
The eMIOS provides the following features:
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16 channels (24-bit timer resolution)
For compatibility with other family members selected channels and timebases are implemented:
— Channels 0 to 6, 8 to 15, and 23
— Timebases A, B and C
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
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Channels 1, 3, 5 and 6 support modes:
— General Purpose Input/Output (GPIO)
— Single Action Input Capture (SAIC)
— Single Action Output Compare (SAOC)
Channels 2, 4, 11 and 13 support all the modes above plus:
— Output Pulse Width Modulation Buffered (OPWMB)
Channels 0, 8, 9, 10, 12, 14, 15, 23 support all the modes above plus:
— Input Period Measurement (IPM)
— Input Pulse Width Measurement (IPWM)
— Double Action Output Compare (set flag on both matches) (DAOC)
— Modulus Counter Buffered (MCB)
— Output Pulse Width and Frequency Modulation Buffered (OPWFMB)
Three 24-bit wide counter buses
— Counter bus A can be driven by channel 23 or by the eTPU2 and all channels can use it as a reference
— Counter bus B is driven by channel 0 and channels 0 to 6 can use it as a reference
— Counter bus C is driven by channel 8 and channels 8 to 15 can use it as a reference
Shared time bases with the eTPU through the counter buses
Synchronization among internal and external time bases
2.3.13
eTPU2
The eTPU2 is an enhanced co-processor designed for timing control. Operating in parallel with the host CPU, eTPU2 processes
instructions and real-time input events, performs output waveform generation, and accesses shared data without host
intervention. Consequently, for each timer event, the host CPU setup and service times are minimized or eliminated. A powerful
timer subsystem is formed by combining the eTPU2 with its own instruction and data RAM. High-level assembler/compiler
and documentation allows customers to develop their own functions on the eTPU2.
The eTPU2 includes these distinctive features:
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The Timer Counter (TCR1), channel logic and digital filters (both channel and the external timer clock input
[TCRCLK]) now have an option to run at full system clock speed or system clock / 2.
Channels support unordered transitions: transition 2 can now be detected before transition 1. Related to this
enhancement, the transition detection latches (TDL1 and TDL2) can now be independently negated by microcode.
A new User Programmable Channel Mode has been added: the blocking, enabling, service request and capture
characteristics of this channel mode can be programmed via microcode.
Microinstructions now provide an option to issue Interrupt and Data Transfer requests selected by channel. They can
also be requested simultaneously at the same instruction.
Channel Flags 0 and 1 can now be tested for branching, in addition to selecting the entry point.
Channel digital filters can be bypassed.
The Timer Counter (TCR1), channel logic and digital filters (both channel and the external timer clock input
[TCRCLK]) now have an option to run at full system clock speed or system clock / 2.
Channels support unordered transitions: transition 2 can now be detected before transition 1. Related to this
enhancement, the transition detection latches (TDL1 and TDL2) can now be independently negated by microcode.
A new User Programmable Channel Mode has been added: the blocking, enabling, service request and capture
characteristics of this channel mode can be programmed via microcode.
Microinstructions now provide an option to issue Interrupt and Data Transfer requests selected by channel. They can
also be requested simultaneously at the same instruction.
Channel Flags 0 and 1 can now be tested for branching, in addition to selecting the entry point.
Channel digital filters can be bypassed.
MPC5634M Microcontroller Data Sheet, Rev. 8
26
Freescale Semiconductor
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32 channels, each channel is associated with one input and one output signal
— Enhanced input digital filters on the input pins for improved noise immunity.
— Identical, orthogonal channels: each channel can perform any time function. Each time function can be assigned
to more than one channel at a given time, so each signal can have any functionality.
— Each channel has an event mechanism which supports single and double action functionality in various
combinations. It includes two 24-bit capture registers, two 24-bit match registers, 24-bit greater-equal and
equal-only comparators
— Input and output signal states visible from the host
2 independent 24-bit time bases for channel synchronization:
— First time base clocked by system clock with programmable prescale division from 2 to 512 (in steps of 2), or by
output of second time base prescaler
— Second time base counter can work as a continuous angle counter, enabling angle based applications to match
angle instead of time
— Both time bases can be exported to the eMIOS timer module
— Both time bases visible from the host
Event-triggered microengine:
— Fixed-length instruction execution in two-system-clock microcycle
— 14 KB of code memory (SCM)
— 3 KB of parameter (data) RAM (SPRAM)
— Parallel execution of data memory, ALU, channel control and flow control sub-instructions in selected
combinations
— 32-bit microengine registers and 24-bit wide ALU, with 1 microcycle addition and subtraction, absolute value,
bitwise logical operations on 24-bit, 16-bit, or byte operands, single-bit manipulation, shift operations, sign
extension and conditional execution
— Additional 24-bit Multiply/MAC/Divide unit which supports all signed/unsigned Multiply/MAC combinations,
and unsigned 24-bit divide. The MAC/Divide unit works in parallel with the regular microcode commands
Resource sharing features support channel use of common channel registers, memory and microengine time:
— Hardware scheduler works as a “task management” unit, dispatching event service routines by predefined,
host-configured priority
— Automatic channel context switch when a “task switch” occurs, i.e., one function thread ends and another begins
to service a request from other channel: channel-specific registers, flags and parameter base address are
automatically loaded for the next serviced channel
— SPRAM shared between host CPU and eTPU2, supporting communication either between channels and host or
inter-channel
— Dual-parameter coherency hardware support allows atomic access to two parameters by host
Test and development support features:
— Nexus Class 1 debug, supporting single-step execution, arbitrary microinstruction execution, hardware
breakpoints and watchpoints on several conditions
— Software breakpoints
— SCM continuous signature-check built-in self test (MISC — multiple input signature calculator), runs
concurrently with eTPU2 normal operation
For MPC5634M, the eTPU2 has been further enhanced with these features:
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System enhancements
— Timebases and channels are run at full system clock speed
— Software watchdog with programmable timeout
— Real-time performance information
Channel enhancements
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
27
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— Programmable channel mode allows customization of channel function
— Channels 1 and 2 can optionally drive angle clock hardware
Programming enhancements
— Engine relative addressing mode
— More flexibility in requesting DMA and interrupt service
— Channel flags can be tested
2.3.14
eQADC
The enhanced queued analog to digital converter (eQADC) block provides accurate and fast conversions for a wide range of
applications. The eQADC provides a parallel interface to two on-chip analog to digital converters (ADC), and a single master
to single slave serial interface to an off-chip external device. Both on-chip ADCs have access to all the analog channels.
The eQADC prioritizes and transfers commands from six command conversion command ‘queues’ to the on-chip ADCs or to
the external device. The block can also receive data from the on-chip ADCs or from an off-chip external device into the six
result queues, in parallel, independently of the command queues. The six command queues are prioritized with Queue_0 having
the highest priority and Queue_5 the lowest. Queue_0 also has the added ability to bypass all buffering and queuing and abort
a currently running conversion on either ADC and start a Queue_0 conversion. This means that Queue_0 will always have a
deterministic time from trigger to start of conversion, irrespective of what tasks the ADCs were performing when the trigger
occurred. The eQADC supports software and external hardware triggers from other blocks to initiate transfers of commands
from the queues to the on-chip ADCs or to the external device. It also monitors the fullness of command queues and result
queues, and accordingly generates DMA or interrupt requests to control data movement between the queues and the system
memory, which is external to the eQADC.
The ADCs also support features designed to allow the direct connection of high impedance acoustic sensors that might be used
in a system for detecting engine knock. These features include differential inputs; integrated variable gain amplifiers for
increasing the dynamic range; programmable pull-up and pull-down resistors for biasing and sensor diagnostics.
The eQADC also integrates a programmable decimation filter capable of taking in ADC conversion results at a high rate,
passing them through a hardware low pass filter, then down-sampling the output of the filter and feeding the lower sample rate
results to the result FIFOs. This allows the ADCs to sample the sensor at a rate high enough to avoid aliasing of out-of-band
noise; while providing a reduced sample rate output to minimize the amount DSP processing bandwidth required to fully
process the digitized waveform.
The eQADC provides the following features:
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Dual on-chip ADCs
— 2 12-bit ADC resolution
— Programmable resolution for increased conversion speed (12 bit, 10 bit, 8 bit)
– 12-bit conversion time – 1 s (1M sample/sec)
– 10-bit conversion time – 867 ns (1.2M sample/second)
– 8-bit conversion time – 733 ns (1.4M sample/second)
— Up to 10-bit accuracy at 500 KSample/s and 9-bit accuracy at 1 MSample/s
— Differential conversions
— Single-ended signal range from 0 to 5 V
— Variable gain amplifiers on differential inputs (1, 2, 4)
— Sample times of 2 (default), 8, 64 or 128 ADC clock cycles
— Provides time stamp information when requested
— Parallel interface to eQADC CFIFOs and RFIFOs
— Supports both right-justified unsigned and signed formats for conversion results
Up to 341 input channels (accessible by both ADCs)
1. 176-pin and 208-pin packages have 34 input channels; 144-pin package has 32; 100-pin package has 23.
MPC5634M Microcontroller Data Sheet, Rev. 8
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Freescale Semiconductor
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23 additional internal channels for measuring control and monitoring voltages inside the device
— Including Core voltage, I/O voltage, LVI voltages, etc.
An internal bandgap reference to allow absolute voltage measurements
4 pairs of differential analog input channels
— Programmable pull-up/pull-down resistors on each differential input for biasing and sensor diagnostic (200 k,
100 k, 5 k)
Silicon die temperature sensor
— provides temperature of silicon as an analog value
— read using an internal ADC analog channel
— may be read with either ADC
Decimation Filter
— Programmable decimation factor (2 to 16)
— Selectable IIR or FIR filter
— Up to 4th order IIR or 8th order FIR
— Programmable coefficients
— Saturated or non-saturated modes
— Programmable Rounding (Convergent; Two’s Complement; Truncated)
— Pre-fill mode to pre-condition the filter before the sample window opens
Full duplex synchronous serial interface to an external device
— Free-running clock for use by an external device
— Supports a 26-bit message length
Priority based Queues
— Supports six Queues with fixed priority. When commands of distinct Queues are bound for the same ADC, the
higher priority Queue is always served first
— Queue_0 can bypass all prioritization, buffering and abort current conversions to start a Queue_0 conversion a
deterministic time after the queue trigger
— Supports software and hardware trigger modes to arm a particular Queue
— Generates interrupt when command coherency is not achieved
External hardware triggers
— Supports rising edge, falling edge, high level and low level triggers
— Supports configurable digital filter
Supports four external 8-to-1 muxes which can expand the input channels to 56 channels total
2.3.15
DSPI
The deserial serial peripheral interface (DSPI) block provides a synchronous serial interface for communication between the
MPC5634M MCU and external devices. The DSPI supports pin count reduction through serialization and deserialization of
eTPU and eMIOS channels and memory-mapped registers. The channels and register content are transmitted using a SPI-like
protocol. This SPI-like protocol is completely configurable for baud rate, polarity and phase, frame length, chip select assertion,
etc. Each bit in the frame may be configured to serialize either eTPU channels, eMIOS channels or GPIO signals. The DSPI
can be configured to serialize data to an external device that implements the Microsecond Bus protocol. There are two identical
DSPI blocks on the MPC5634M MCU. The DSPI pins support 5 V logic levels or Low Voltage Differential Signalling (LVDS)
to improve high speed operation.
The DSPIs have three configurations:
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Serial peripheral interface (SPI) configuration where the DSPI operates as an up to 16-bit SPI with support for queues
Enhanced deserial serial interface (DSI) configuration where DSPI serializes up to 32 bits with three possible sources
per bit
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
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— eTPU, eMIOS, new virtual GPIO registers as possible bit source
— Programmable inter-frame gap in continuous mode
— Bit source selection allows microsecond bus downlink with command or data frames up to 32 bits
— Microsecond bus dual receiver mode
Combined serial interface (CSI) configuration where the DSPI operates in both SPI and DSI configurations
interleaving DSI frames with SPI frames, giving priority to SPI frames
For queued operations, the SPI queues reside in system memory external to the DSPI. Data transfers between the memory and
the DSPI FIFOs are accomplished through the use of the eDMA controller or through host software.
The DSPI supports these SPI features:
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Full-duplex, synchronous transfers
Selectable LVDS Pads working at 40 MHz for SOUT, SIN and SCK pins
Master and Slave Mode
Buffered transmit operation using the TX FIFO with parameterized depth of 1 to 16 entries
Buffered receive operation using the RX FIFO with parameterized depth of 1 to 16 entries
TX and RX FIFOs can be disabled individually for low-latency updates to SPI queues
Visibility into the TX and RX FIFOs for ease of debugging
FIFO Bypass Mode for low-latency updates to SPI queues
Programmable transfer attributes on a per-frame basis:
— Parameterized number of transfer attribute registers (from two to eight)
— Serial clock with programmable polarity and phase
— Various programmable delays:
– PCS to SCK delay
– SCK to PCS delay
– Delay between frames
— Programmable serial frame size of 4 to 16 bits, expandable with software control
— Continuously held chip select capability
6 Peripheral Chip Selects, expandable to 64 with external demultiplexer
Deglitching support for up to 32 Peripheral Chip Selects with external demultiplexer
DMA support for adding entries to TX FIFO and removing entries from RX FIFO:
— TX FIFO is not full (TFFF)
— RX FIFO is not empty (RFDF)
6 Interrupt conditions:
— End of queue reached (EOQF)
— TX FIFO is not full (TFFF)
— Transfer of current frame complete (TCF)
— Attempt to transmit with an empty Transmit FIFO (TFUF)
— RX FIFO is not empty (RFDF)
— FIFO Underrun (slave only and SPI mode, the slave is asked to transfer data when the TxFIFO is empty)
— FIFO Overrun (serial frame received while RX FIFO is full)
Modified transfer formats for communication with slower peripheral devices
Continuous Serial Communications Clock (SCK)
Power savings via support for Stop Mode
Enhanced DSI logic to implement a 32-bit Timed Serial Bus (TSB) configuration, supporting the Microsecond Bus
downstream frame format
The DSPIs also support these features unique to the DSI and CSI configurations:
MPC5634M Microcontroller Data Sheet, Rev. 8
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Freescale Semiconductor
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2 sources of the serialized data:
— eTPU_A and eMIOS output channels
— Memory-mapped register in the DSPI
Destinations for the deserialized data:
— eTPU_A and eMIOS input channels
— SIU External Interrupt Request inputs
— Memory-mapped register in the DSPI
Deserialized data is provided as Parallel Output signals and as bits in a memory-mapped register
Transfer initiation conditions:
— Continuous
— Edge sensitive hardware trigger
— Change in data
Pin serialization/deserialization with interleaved SPI frames for control and diagnostics
Continuous serial communications clock
Support for parallel and serial chaining of up to four DSPI blocks
2.3.16
eSCI
The enhanced serial communications interface (eSCI) allows asynchronous serial communications with peripheral devices and
other MCUs. It includes special support to interface to Local Interconnect Network (LIN) slave devices. The eSCI block
provides the following features:
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Full-duplex operation
Standard mark/space non-return-to-zero (NRZ) format
13-bit baud rate selection
Programmable 8-bit or 9-bit, data format
Programmable 12-bit or 13-bit data format for Timed Serial Bus (TSB) configuration to support the Microsecond bus
standard
Automatic parity generation
LIN support
— Autonomous transmission of entire frames
— Configurable to support all revisions of the LIN standard
— Automatic parity bit generation
— Double stop bit after bit error
— 10- or 13-bit break support
Separately enabled transmitter and receiver
Programmable transmitter output parity
2 receiver wake up methods:
— Idle line wake-up
— Address mark wake-up
Interrupt-driven operation with flags
Receiver framing error detection
Hardware parity checking
1/16 bit-time noise detection
DMA support for both transmit and receive data
— Global error bit stored with receive data in system RAM to allow post processing of errors
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
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2.3.17
FlexCAN
The MPC5634M MCU contains two controller area network (FlexCAN) blocks. The FlexCAN module is a communication
controller implementing the CAN protocol according to Bosch Specification version 2.0B. The CAN protocol was designed to
be used primarily as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable
operation in the EMI environment of a vehicle, cost-effectiveness and required bandwidth. FlexCAN module ‘A’ contains 64
message buffers (MB); FlexCAN module ‘C’ contains 32 message buffers.
The FlexCAN module provides the following features:
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Based on and including all existing features of the Freescale TouCAN module
Full Implementation of the CAN protocol specification, Version 2.0B
— Standard data and remote frames
— Extended data and remote frames
— Zero to eight bytes data length
— Programmable bit rate up to 1 Mbit/s
Content-related addressing
64 / 32 message buffers of zero to eight bytes data length
Individual Rx Mask Register per message buffer
Each message buffer configurable as Rx or Tx, all supporting standard and extended messages
Includes 1056 / 544 bytes of embedded memory for message buffer storage
Includes a 256-byte and a 128-byte memories for storing individual Rx mask registers
Full featured Rx FIFO with storage capacity for six frames and internal pointer handling
Powerful Rx FIFO ID filtering, capable of matching incoming IDs against 8 extended, 16 standard or 32 partial (8 bits)
IDs, with individual masking capability
Selectable backwards compatibility with previous FlexCAN versions
Programmable clock source to the CAN Protocol Interface, either system clock or oscillator clock
Listen only mode capability
Programmable loop-back mode supporting self-test operation
3 programmable Mask Registers
Programmable transmit-first scheme: lowest ID, lowest buffer number or highest priority
Time Stamp based on 16-bit free-running timer
Global network time, synchronized by a specific message
Maskable interrupts
Warning interrupts when the Rx and Tx Error Counters reach 96
Independent of the transmission medium (an external transceiver is assumed)
Multi master concept
High immunity to EMI
Short latency time due to an arbitration scheme for high-priority messages
Low power mode, with programmable wake-up on bus activity
2.3.18
System timers
The system timers provide two distinct types of system timer:
•
•
Periodic interrupts/triggers using the Peripheral Interrupt Timer (PIT)
Operating system task monitors using the System Timer Module (STM)
MPC5634M Microcontroller Data Sheet, Rev. 8
32
Freescale Semiconductor
2.3.18.1
Peripheral Interrupt Timer (PIT)
The PIT provides five independent timer channels, capable of producing periodic interrupts and periodic triggers. The PIT has
no external input or output pins and is intended to be used to provide system ‘tick’ signals to the operating system, as well as
periodic triggers for eQADC queues. Of the five channels in the PIT, four are clocked by the system clock, one is clocked by
the crystal clock. This one channel is also referred to as Real Time Interrupt (RTI) and is used to wakeup the device from low
power stop mode.
The following features are implemented in the PIT:
•
•
•
•
•
•
5 independent timer channels
Each channel includes 32-bit wide down counter with automatic reload
4 channels clocked from system clock
1 channel clocked from crystal clock (wake-up timer)
Wake-up timer remains active when System STOP mode is entered. Used to restart system clock after predefined
time-out period
Each channel can optionally generate an interrupt request or a trigger event (to trigger eQADC queues) when the timer
reaches zero
2.3.18.2
System Timer Module (STM)
The System Timer Module (STM) is designed to implement the software task monitor as defined by AUTOSAR (see
http://www.autosar.org). It consists of a single 32-bit counter, clocked by the system clock, and four independent timer
comparators. These comparators produce a CPU interrupt when the timer exceeds the programmed value.
The following features are implemented in the STM:
•
•
•
•
One 32-bit up counter with 8-bit prescaler
Four 32-bit compare channels
Independent interrupt source for each channel
Counter can be stopped in debug mode
2.3.19
Software Watchdog Timer (SWT)
The Software Watchdog Timer (SWT) is a second watchdog module to complement the standard Power Architecture watchdog
integrated in the CPU core. The SWT is a 32-bit modulus counter, clocked by the system clock or the crystal clock, that can
provide a system reset or interrupt request when the correct software key is not written within the required time window.
The following features are implemented:
•
•
•
•
•
•
•
32-bit modulus counter
Clocked by system clock or crystal clock
Optional programmable watchdog window mode
Can optionally cause system reset or interrupt request on timeout
Reset by writing a software key to memory mapped register
Enabled out of reset
Configuration is protected by a software key or a write-once register
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
33
2.3.20
2.3.20.1
Debug features
Nexus port controller
The NPC (Nexus Port Controller) block provides real-time development support capabilities for the MPC5634M Power
Architecture-based MCU in compliance with the IEEE-ISTO 5001-2003 standard. This development support is supplied for
MCUs without requiring external address and data pins for internal visibility. The NPC block is an integration of several
individual Nexus blocks that are selected to provide the development support interface for the MPC5634M. The NPC block
interfaces to the host processor (e200z335), eTPU, and internal buses to provide development support as per the IEEE-ISTO
5001-2003 standard. The development support provided includes program trace and run-time access to the MCUs internal
memory map and access to the Power Architecture and eTPU internal registers during halt. The Nexus interface also supports
a JTAG only mode using only the JTAG pins. MPC5634M in the production 144 LQFP supports a 3.3 V reduced (4-bit wide)
Auxiliary port. These Nexus port pins can also be used as 5 V I/O signals to increase usable I/O count of the device. When using
this Nexus port as IO, Nexus trace is still possible using VertiCal calibration. In the VertiCal calibration package, the full 12-bit
Auxiliary port is available.
NOTE
In the VertiCal package, the full Nexus Auxiliary port shares balls with the addresses of the
calibration bus. Therefore multiplexed address/data bus mode must be used for the
calibration bus when using full width Nexus trace in VertiCal assembly.
The following features are implemented:
•
•
•
5-pin JTAG port (JCOMP, TDI, TDO, TMS, and TCK)
— Always available in production package
— Supports both JTAG Boundary Scan and debug modes
— 3.3 V interface
— Supports Nexus class 1 features
— Supports Nexus class 3 read/write feature
9-pin Reduced Port interface in 144 LQFP production package
— Alternate function as IO
— 5 V (in GPIO or alternate function mode), 3.3 V (in Nexus mode) interface
— Auxiliary Output port
– 1 MCKO (message clock out) pin
– 4 MDO (message data out) pins
– 2 MSEO (message start/end out) pins
– 1 EVTO (event out) pin
— Auxiliary input port
– 1 EVTI (event in) pin
17-pin Full Port interface in VertiCal calibration package
— 3.3 V interface
— Auxiliary Output port
– 1 MCKO (message clock out) pin
– 4 (reduced port mode) or 12 (full port mode) MDO (message data out) pins; 8 extra full port pins shared with
calibration bus
– 2 MSEO (message start/end out) pins
– 1 EVTO (event out) pin
— Auxiliary input port
– 1 EVTI (event in) pin
MPC5634M Microcontroller Data Sheet, Rev. 8
34
Freescale Semiconductor
•
Host processor (e200) development support features
— IEEE-ISTO 5001-2003 standard class 2 compliant
— Program trace via branch trace messaging (BTM). Branch trace messaging displays program flow discontinuities
(direct branches, indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires
between the discontinuities. Thus, static code may be traced.
— Watchpoint trigger enable of program trace messaging
— Data Value Breakpoints (JTAG feature of the e200z335 core): allows CPU to be halted when the CPU writes a
specific value to a memory location
– 4 data value breakpoints
– CPU only
– Detects ‘equal’ and ‘not equal’
– Byte, half word, word (naturally aligned)
NOTE
This feature is imprecise due to CPU pipelining.
•
•
•
•
— Subset of Power Architecture software debug facilities with OnCE block (Nexus class 1 features)
eTPU development support features
— IEEE-ISTO 5001-2003 standard class 1 compliant for the eTPU
— Nexus based breakpoint configuration and single step support (JTAG feature of the eTPU)
Run-time access to the on-chip memory map via the Nexus read/write access protocol. This feature supports accesses
for run-time internal visibility, calibration variable acquisition, calibration constant tuning, and external rapid
prototyping for powertrain automotive development systems.
All features are independently configurable and controllable via the IEEE 1149.1 I/O port
Power-on-reset status indication during reset via MDO[0] in disabled and reset modes
2.3.20.2
JTAG
The JTAGC (JTAG Controller) block provides the means to test chip functionality and connectivity while remaining transparent
to system logic when not in test mode. Testing is performed via a boundary scan technique, as defined in the IEEE 1149.1-2001
standard. All data input to and output from the JTAGC block is communicated in serial format. The JTAGC block is compliant
with the IEEE 1149.1-2001 standard and supports the following features:
•
•
•
•
•
•
IEEE 1149.1-2001 Test Access Port (TAP) interface 4 pins (TDI, TMS, TCK, and TDO)
A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions:
— BYPASS, IDCODE, EXTEST, SAMPLE, SAMPLE/PRELOAD, HIGHZ, CLAMP
A 5-bit instruction register that supports the additional following public instructions:
— ACCESS_AUX_TAP_NPC
— ACCESS_AUX_TAP_ONCE
— ACCESS_AUX_TAP_eTPU
— ACCESS_CENSOR
3 test data registers to support JTAG Boundary Scan mode
— Bypass register
— Boundary scan register
— Device identification register
A TAP controller state machine that controls the operation of the data registers, instruction register and associated
circuitry
Censorship Inhibit Register
— 64-bit Censorship password register
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
35
— If the external tool writes a 64-bit password that matches the Serial Boot password stored in the internal flash
shadow row, Censorship is disabled until the next system reset
2.4
MPC5634M series architecture
2.4.1
Block diagram
Figure 1 shows a top-level block diagram of the MPC5634M series.
JTAG
Calibration
Bus
Interface
S
Nexus
eTPU
NMI
Instructions
M
SPE
Data
NMI
MMU
SIU
Nexus 2+
M
critical
Clocks
Interrupt
Controller
(INTC)
CQM
DMA
Requests
from
Peripheral
Blocks
PLL
STM
PIT
SWT
SRAM
62 KB
S
S
M
eDMA
Interrupt
Requests from
Peripheral
Blocks & eDMA
Flash
1.5 MB
S
32 KB
e200z335
Nexus Port
3 x 4 64-bit
Crossbar Switch
JTAG Port
Voltage
Regulator
(1.2 V, 3.3 V,
STB RAM)
eDMA, FLASH, Bridge B,
crossbar, SRAM
Configuration
Vstby
BAM
Peripheral Bridge
Nexus
SIU
Interrupt
Request
16 Ch.
eMIOS
eTPU
Reset Control
2x
DSPIs
2x
eSCIs
eQADC
2x
CANs
ADCI
NEXUS 1
External
Interrupt
Request
Serial
Analog IF
32 Ch.+
Engine
IMUX
ADC ADC
RAM
14 KB/3 KB
GPIO &
Pad Control
Analog
AMUX
Decimation
Filter
...
I/O
...
...
...
Temp. Sensor
Figure 1. MPC5634M series block diagram
2.4.2
Block summary
Table 2 summarizes the functions of the blocks present on the MPC5634M series microcontrollers.
MPC5634M Microcontroller Data Sheet, Rev. 8
36
Freescale Semiconductor
Table 2. MPC5634M series block summary
Block
Function
e200z3 core
Executes programs and interrupt handlers.
Flash memory
Provides storage for program code, constants, and variables
RAM (random-access memory)
Provides storage for program code, constants, and variables
Calibration bus
Transfers data across the crossbar switch to/from peripherals attached to the
VertiCal connector
DMA (direct memory access)
Performs complex data movements with minimal intervention from the core
DSPI (deserial serial peripheral interface)
Provides a synchronous serial interface for communication with external
devices
eMIOS (enhanced modular input-output system) Provides the functionality to generate or measure events
eQADC (enhanced queued analog-to-digital
converter)
Provides accurate and fast conversions for a wide range of applications
eSCI (serial communication interface)
Allows asynchronous serial communications with peripheral devices and
other microcontroller units
eTPU (enhanced time processor unit)
Processes real-time input events, performs output waveform generation, and
accesses shared data without host intervention
FlexCAN (controller area network)
Supports the standard CAN communications protocol
FMPLL (frequency-modulated phase-locked
loop)
Generates high-speed system clocks and supports the programmable
frequency modulation of these clocks
INTC (interrupt controller)
Provides priority-based preemptive scheduling of interrupt requests
JTAG controller
Provides the means to test chip functionality and connectivity while remaining
transparent to system logic when not in test mode
NPC (Nexus Port Controller)
Provides real-time development support capabilities in compliance with the
IEEE-ISTO 5001-2003 standard
PIT (peripheral interrupt timer)
Produces periodic interrupts and triggers
Temperature sensor
Provides the temperature of the device as an analog value
SWT (Software Watchdog Timer)
Provides protection from runaway code
STM (System Timer Module)
Timer providing a set of output compare events to support AutoSAR and
operating system tasks
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
37
3
Pinout and signal description
This section contains the pinouts for all production packages for the MPC5634M family of devices. Please note the following:
•
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
AN[21]
AN[0] (DAN0+)
AN[1] (DAN0–)
AN[2] (DAN1+)
AN[3] (DAN1–)
AN[4] (DAN2+)
AN[5] (DAN2–)
AN[6] (DAN3+)
AN[7] (DAN3–)
REFBYPC
VRH
VRL
AN[23]
AN[25]
AN[28]
AN[31]
AN[33]
AN[35]
VDD
AN[12] / MA[0] / ETPU_A[19] / SDS
AN[13] / MA[1] / ETPU_A[21] / SDO
AN[14] / MA[2] / ETPU_A[27] / SDI
AN[15] / FCK / ETPU_A[29]
VSS
VDDEH7
•
Pins labeled “NC” are to be left unconnected. Any connection to an external circuit or voltage may cause unpredictable
device behavior or damage.
Pins labeled “NIC” have no internal connection.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
100–Pin
LQFP
signal details:
pin 15: eTPU_A[27] / IRQ[15] / DSPI_C_SOUT_LVDS+ /
DSPI_B_SOUT / GPIO[141]
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
TMS
TDI / eMIOS[5] / GPIO[232]
TCK
VSS
VDDEH7
TDO / eMIOS[6] / GPIO[228]
JCOMP
DSPI_B_PCS[3] / DSPI_C_SIN / GPIO[108]
DSPI_B_SIN / DSPI_C_PCS[2] / GPIO[103]
VDDEH6B
VSS
DSPI_B_SCK / DSPI_C_PCS[1] / GPIO[102]
DSPI_B_PCS[4] / DSPI_C_SCK / GPIO[109]
VDD
RSTOUT
CAN_C_TX / GPIO[87]
CAN_C_RX / GPIO[88]
RESET
VSS
VDDEH6A
VSSPLL
XTAL
EXTAL / EXTCLK
VDDPLL
VSS
eTPU_A[13] / DSPI_B_PCS[3] / GPIO[127]
eTPU_A[8] / eTPU_A[20] / DSPI_B_SOUT_LVDS+ / GPIO[122]
eTPU_A[7] / eTPU_A[19] / DSPI_B_SOUT_LVDS– / eTPU_A[6] / GPIO[121]
eTPU_A[6] / eTPU_A[18] / DSPI_B_SCK_LVDS+ / GPIO[120]
eTPU_A[5] / eTPU_A[17] / DSPI_B_SCK_LVDS– / GPIO[119]
VDDEH1B
eTPU_A[4] / eTPU_A[16] / GPIO[118]
VSS
eTPU_A[3] / eTPU_A[15] / GPIO[117]
eTPU_A[2] / eTPU_A[14] / GPIO[116]
eTPU_A[1] / eTPU_A[13] / GPIO[115]
eTPU_A[0] / eTPU_A[12] / eTPU_A[19] / GPIO[114]
VDD
eMIOS[0] / eTPU_A[0] / eTPU_A[25] / GPIO[179]
eMIOS[8] / eTPU_A[8] / SCI_B_TX / GPIO[187]
eMIOS[9] / eTPU_A[9] / SCI_B_RX / GPIO[188]
VSS
VDDEH6A
eMIOS[12] / DSPI_C_SOUT / eTPU_A[27] / GPIO[191]
eMIOS[14] / IRQ[0] / eTPU_A[29] / GPIO[193]
CAN_A_TX / SCI_A_TX / GPIO[83]
CAN_A_RX / SCI_A_RX / GPIO[84]
PLLREF / IRQ[4]/ETRIG[2] / GPIO[208]
BOOTCFG1 / IRQ[3] / ETRIG[3] / GPIO[212]
WKPCFG / NMI / DSPI_B_SOUT / GPIO[213]
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
AN[11] / ANZ
AN[9] / ANX
VDDA
VSSA
AN[39] / AN[10] / ANY
AN[38] / AN[8] / ANW
VDDREG
VRCCTL
VSTBY
VRC33
eTPU_A[31] / DSPI_C_PCS[4] / eTPU_A[13] / GPIO[145]
eTPU_A[30] / DSPI_C_PCS[3] / eTPU_A[11] / GPIO[144]
eTPU_A[29] / DSPI_C_PCS[2] / GPIO[143]
eTPU_A[28] / DSPI_C_PCS[1] / GPIO[142]
(see signal details, pin 15
eTPU_A[26] / IRQ[14] / DSPI_C_SOUT_LVDS– / GPIO[140]
eTPU_A[25] / IRQ[13] / DSPI_C_SCK_LVDS+ / GPIO[139]
eTPU_A[24] / IRQ[12] / DSPI_C_SCK_LVDS– / GPIO[138]
VSS
VDDEH1A
VDD
eTPU_A[15] / DSPI_B_PCS[5] / GPIO[129]
VDDEH1B
eTPU_A[14] / DSPI_B_PCS[4] / eTPU_A[9] / GPIO[128]
VSS
MPC5634M Microcontroller Data Sheet, Rev. 8
38
Freescale Semiconductor
3.1
144 LQFP pinout
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
AN[21]
AN[0] (DAN0+)
AN[1] (DAN0–)
AN[2] (DAN1+)
AN[3] (DAN1–)
AN[4] (DAN2+)
AN[5] (DAN2–)
AN[6] (DAN3+)
AN[7] (DAN3–)
REFBYPC
VRH
VRL
AN[22]
AN[23]
AN[24]
AN[25]
AN[27]
AN[28]
AN[30]
AN[31]
AN[32]
AN[33]
AN[34]
AN[35]
VDD
AN[12] / MA[0] / ETPU_A[19] / SDS
AN[13] / MA[1] / ETPU_A[21] / SDO
AN[14] / MA[2] / ETPU_A[27] / SDI
AN[15] / FCK / ETPU_A[29]
VSS
MDO[3] / eTPU_A[25] / GPIO[223]
VDDEH7
MDO[2] / eTPU_A[21] / GPIO[222]
MDO[1] / eTPU_A[19] / GPIO[221]
MDO[0] / eTPU_A[13] / GPIO[220]
MSEO[0] / eTPU_A[27] / GPIO[224]
Figure 2 shows the pinout for the 144-pin LQFP.
144-Pin
LQFP
signal details:
pin 14: eTPU_A[31] / DSPI_C_PCS[4] / eTPU_A[13] / GPIO[145]
pin 15: eTPU_A[30] / DSPI_C_PCS[3] / eTPU_A[11] / GPIO[144]
pin 18: eTPU_A[27] / IRQ[15] / DSPI_C_SOUT_LVDS+ / DSPI_B_SOUT / GPIO[141]
pin 19: eTPU_A[26] / IRQ[14] / DSPI_C_SOUT_LVDS– / GPIO[140]
pin 20: eTPU_A[25] / IRQ[13] / SCK_C_LVDS+ / GPIO[139]
pin 21: eTPU_A[24] / IRQ[12] / SCK_C_LVDS– / GPIO[138]
pin 23: eTPU_A[23] / IRQ[11] / eTPU_A[21] / GPIO[137]
pin 25: eTPU_A[22] / IRQ[10] / eTPU_A[17] / GPIO[136]
pin 35: eTPU_A[14] / DSPI_B_PCS[4] / eTPU_A[9] / GPIO[128]
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
TMS
TDI / eMIOS[5] / GPIO[232]
EVTO / eTPU_A[4] / GPIO[227]
TCK
VSS
EVTI / eTPU_A[2] / GPIO[231]
VDDEH7
MSEO[1] / eTPU_A[29] / GPIO[225]
TDO / eMIOS[6] / GPIO[228]
MCKO / GPIO[219]
JCOMP
DSPI_B_PCS[3] / DSPI_C_SIN / GPIO[108]
DSPI_B_SOUT / DSPI_C_PCS[5] / GPIO[104]
DSPI_B_SIN / DSPI_C_PCS[2] / GPIO[103]
DSPI_B_PCS[0] / GPIO[105]
VDDEH6B
DSPI_B_PCS[1] / GPIO[106]
VSS
DSPI_B_PCS[2] / DSPI_C_SOUT / GPIO[107]
DSPI_B_SCK / DSPI_C_PCS[1] / GPIO[102]
DSPI_B_PCS[4] / DSPI_C_SCK / GPIO[109]
DSPI_B_PCS[5] / DSPI_C_PCS[0] / GPIO[110]
VDD
RSTOUT
CAN_C_TX / GPIO[87]
SCI_A_TX / eMIOS[13] / GPIO[89]
SCI_A_RX / eMIOS[15] / GPIO[90]
CAN_C_RX / GPIO[88]
RESET
VSS
VDDEH6A
VSSPLL
XTAL
EXTAL / EXTCLK
VDDPLL
VSS
eTPU_A[13] / DSPI_B_PCS[3] / GPIO[127]
eTPU_A[12] / DSPI_B_PCS[1] / GPIO[126]
eTPU_A[11] / eTPU_A[23] / GPIO[125]
eTPU_A[10] / eTPU_A[22] / GPIO[124]
eTPU_A[9] / eTPU_A[21] / GPIO[123]
eTPU_A[8] / eTPU_A[20] / DSPI_B_SOUT_LVDS+ / GPIO[122]
eTPU_A[7] / eTPU_A[19] / DSPI_B_SOUT_LVDS– / eTPU_A[6] / GPIO[121]
eTPU_A[6] / eTPU_A[18] / DSPI_B_SCK_LVDS+ / GPIO[120]
eTPU_A[5] / eTPU_A[17] / DSPI_B_SCK_LVDS– / GPIO[119]
VDDEH1B
eTPU_A[4] / eTPU_A[16] / GPIO[118]
VSS
eTPU_A[3] / eTPU_A[15] / GPIO[117]
eTPU_A[2] / eTPU_A[14] / GPIO[116]
eTPU_A[1] / eTPU_A[13] / GPIO[115]
eTPU_A[0] / eTPU_A[12] / eTPU_A[19] / GPIO[114]
VDD
eMIOS[0] / eTPU_A[0] / eTPU_A[25] / GPIO[179]
eMIOS[2] / eTPU_A[2] / GPIO[181]
eMIOS[4] / eTPU_A[4] / GPIO[183]
eMIOS[8] / eTPU_A[8] / SCI_B_TX / GPIO[187]
eMIOS[9] / eTPU_A[9] / SCI_B_RX / GPIO[188]
VSS
eMIOS[10] / GPIO[189]
VDDEH6A
eMIOS[11] / GPIO[190]
eMIOS[12] / DSPI_C_SOUT / eTPU_A[27] / GPIO[191]
eMIOS[14] / IRQ[0] / eTPU_A[29] / GPIO[193]
eMIOS[23] / GPIO[202]
CAN_A_TX / SCI_A_TX / GPIO[83]
CAN_A_RX / SCI_A_RX / GPIO[84]
PLLREF / IRQ[4]/ETRIG[2] / GPIO[208]
SCI_B_RX / GPIO[92]
BOOTCFG1 / IRQ[3] / ETRIG[3] / GPIO[212]
WKPCFG / NMI / DSPI_B_SOUT / GPIO[213]
SCI_B_TX / GPIO[91]
AN[18]
AN[17]
AN[16]
AN[11] / ANZ
AN[9] / ANX
VDDA
VSSA
AN[39] / AN[10] / ANY
AN[38] / AN[8] / ANW
VDDREG
VRCCTL
VSTBY
VRC33
(see signal details, pin 14)
(see signal details, pin 15)
eTPU_A[29] / DSPI_C_PCS[2] / GPIO[143]
eTPU_A[28] / DSPI_C_PCS[1] / GPIO[142]
(see signal details, pin 18)
(see signal details, pin 19)
(see signal details, pin 20)
(see signal details, pin 21)
VSS
(see signal details, pin 23)
VDDEH1A
(see signal details, pin 25)
VDD
eTPU_A[21] / IRQ[9] / GPIO[135]
eTPU_A[20] / IRQ[8] / GPIO[134]
eTPU_A[19] / GPIO[133]
eTPU_A[18] / GPIO[132]
eTPU_A[17] / GPIO[131]
eTPU_A[16] / GPIO[130]
eTPU_A[15] / DSPI_B_PCS[5] / GPIO[129]
VDDEH1B
(see signal details, pin 35)
VSS
Figure 2. 144-pin LQFP pinout (top view; all 144-pin devices)
3.2
176 LQFP pinout (MPC5634M)
Figure 3 shows the 176-pin LQFP pinout for the MPC5634M (1536 KB flash memory).
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
39
NIC
AN[37]
AN[36]
AN[21]
AN[0] (DAN0+)
AN[1] (DAN0–)
AN[2] (DAN1+)
AN[3] (DAN1–)
AN[4] (DAN2+)
AN[5] (DAN2–)
AN[6] (DAN3+)
AN[7] (DAN3–)
REFBYPC
VRH
VRL
AN[22]
AN[23]
AN[24]
AN[25]
AN[27]
AN[28]
AN[30]
AN[31]
AN[32]
AN[33]
AN[34]
AN[35]
VDD
AN[12] / MA[0] / ETPU_A[19] / SDS
AN[13] / MA[1] / ETPU_A[21] / SDO
AN[14] / MA[2] / ETPU_A[27] / SDI
AN[15] / FCK / ETPU_A[29]
GPIO[207]
GPIO[206]
GPIO[99]
GPIO[98]
VSS
eTPU_A[25] / GPIO[223]
VDDEH7
eTPU_A[21] / GPIO[222]
eTPU_A[19] / GPIO[221]
eTPU_A[13] / GPIO[220]
eTPU_A[27] / GPIO[224]
VSS
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
176 - Pin
LQFP
signal details:
pin 21: eTPU_A[31] / DSPI_C_PCS[4] / eTPU_A[13] / GPIO[145]
pin 22: eTPU_A[30] / DSPI_C_PCS[3] / eTPU_A[11] / GPIO[144]
pin 23: eTPU_A[29] / DSPI_C_PCS[2] / GPIO[143]
pin 24: eTPU_A[28] / DSPI_C_PCS[1] / GPIO[142]
pin 25: eTPU_A[27] / IRQ[15] / DSPI_C_SOUT_LVDS+ / DSPI_B_SOUT / GPIO[141]
pin 26: eTPU_A[26] / IRQ[14] / DSPI_C_SOUT_LVDS– / GPIO[140]
pin 27: eTPU_A[25] / IRQ[13] / DSPI_C_SCK_LVDS+ / GPIO[139]
pin 28: eTPU_A[24] / IRQ[12] / DSPI_C_SCK_LVDS– / GPIO[138]
pin 30: eTPU_A[23] / IRQ[11] / eTPU_A[21] / GPIO[137]
pin 32: eTPU_A[22] / IRQ[10] / eTPU_A[17] / GPIO[136]
pin 40: eTPU_A[15] / DSPI_B_PCS[5] / GPIO[129]
pin 42: eTPU_A[14] / DSPI_B_PCS[4] / eTPU_A[9] / GPIO[128]
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
NIC
TMS
TDI / eMIOS[5] / GPIO[232]
eTPU_A[4] / GPIO[227]
TCK
VSS
eTPU_A[2] / GPIO[231]
VDDEH7
eTPU_A[29] / GPIO[225]
TDO / eMIOS[6] / GPIO[228]
GPIO[219]
JCOMP
ALT_EVTO
VDDE12
ALT_MSEO[0]
ALT_MSEO[1]
ALT_EVTI
VSS
DSPI_B_PCS[3] / DSPI_C_SIN / GPIO[108]
DSPI_B_SOUT / DSPI_C_PCS[5] / GPIO[104]
DSPI_B_SIN / DSPI_C_PCS[2] / GPIO[103]
DSPI_B_PCS[0] / GPIO[105]
VDDEH6B
DSPI_B_PCS[1] / GPIO[106]
VSS
DSPI_B_PCS[2] / DSPI_C_SOUT / GPIO[107]
DSPI_B_SCK / DSPI_C_PCS[1] / GPIO[102]
DSPI_B_PCS[4] / DSPI_C_SCK / GPIO[109]
DSPI_B_PCS[5] / DSPI_C_PCS[0] / GPIO[110]
VDD
RSTOUT
CAN_C_TX / GPIO[87]
SCI_A_TX / eMIOS[13] / GPIO[89]
SCI_A_RX / eMIOS[15] / GPIO[90]
CAN_C_RX / GPIO[88]
RESET
VSS
VDDEH6A
VSSPLL
XTAL
EXTAL / EXTCLK
VDDPLL
VSS
NIC
NIC
eTPU_A[13] / DSPI_B_PCS[3] / GPIO[127]
eTPU_A[12] / DSPI_B_PCS[1] / GPIO[126]
eTPU_A[11] / eTPU_A[23] / GPIO[125]
eTPU_A[10] / eTPU_A[22] / GPIO[124]
eTPU_A[9] / eTPU_A[21] / GPIO[123]
eTPU_A[8] / eTPU_A[20] / DSPI_B_SOUT_LVDS+ / GPIO[122]
eTPU_A[7] / eTPU_A[19] / DSPI_B_SOUT_LVDS– / eTPU_A[6] / GPIO[121]
eTPU_A[6] / eTPU_A[18] / DSPI_B_SCK_LVDS+ / GPIO[120]
eTPU_A[5] / eTPU_A[17] / DSPI_B_SCK_LVDS– / GPIO[119]
VDDEH1B
eTPU_A[4] / eTPU_A[16] / GPIO[118]
VSS
eTPU_A[3] / eTPU_A[15] / GPIO[117]
eTPU_A[2] / eTPU_A[14] / GPIO[116]
eTPU_A[1] / eTPU_A[13] / GPIO[115]
eTPU_A[0] / eTPU_A[12] / eTPU_A[19] / GPIO[114]
VDD
eMIOS[0] / eTPU_A[0] / eTPU_A[25] / GPIO[179]
eMIOS[1] / eTPU_A[1] / GPIO[180]
eMIOS[2] / eTPU_A[2] / GPIO[181]
NIC
eMIOS[4] / eTPU_A[4] / GPIO[183]
NIC
NIC
eMIOS[8] / eTPU_A[8] / SCI_B_TX / GPIO[187]
eMIOS[9] / eTPU_A[9] / SCI_B_RX / GPIO[188]
VSS
eMIOS[10] / GPIO[189]
VDDEH6A
eMIOS[11] / GPIO[190]
eMIOS[12] / DSPI_C_SOUT / eTPU_A[27] / GPIO[191]
eMIOS[13] / GPIO[192]
eMIOS[14] / IRQ[0] / eTPU_A[29] / GPIO[193]
eMIOS[15] / IRQ[1] / GPIO[194]
eMIOS[23] / GPIO[202]
CAN_A_TX / SCI_A_TX / GPIO[83]
CAN_A_RX / SCI_A_RX / GPIO[84
PLLREF / IRQ[4]/ETRIG[2] / GPIO[208]
SCI_B_RX / GPIO[92]
BOOTCFG1 / IRQ[3] / ETRIG[3] / GPIO[212]
WKPCFG / NMI / DSPI_B_SOUT / GPIO[213]
SCI_B_TX / GPIO[91]
NIC
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
AN[18]
AN[17]
AN[16]
AN[11] / ANZ
AN[9] / ANX
VDDA
VSSA
AN[39] / AN[10] / ANY
AN[38] / AN[8] / ANW
VDDREG
VRCCTL
VSTBY
VRC33
ALT_MCKO
VSS
VDDE12
ALT_MDO[0]
ALT_MDO[1]
ALT_MDO[2]
ALT_MDO[3]
(see signal details, pin 21)
(see signal details, pin 22)
(see signal details, pin 23)
(see signal details, pin 24)
(see signal details, pin 25)
(see signal details, pin 26)
(see signal details, pin 27)
(see signal details, pin 28)
VSS
(see signal details, pin 30)
VDDEH1A
(see signal details, pin 32)
VDD
eTPU_A[21] / IRQ[9] / GPIO[135]
eTPU_A[20] / IRQ[8] / GPIO[134]
eTPU_A[19] / GPIO[133]
eTPU_A[18] / GPIO[132]
eTPU_A[17] / GPIO[131]
eTPU_A[16] / GPIO[130]
(see signal details, pin 40)
VDDEH1B
(see signal details, pin 42)
VSS
NIC
Note: Pins marked “NIC” have no internal connection.
Figure 3. 176-pin LQFP pinout (MPC5634M; top view)
MPC5634M Microcontroller Data Sheet, Rev. 8
40
Freescale Semiconductor
3.3
176 LQFP pinout (MPC5633M)
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
NIC
NC
NC
AN[21]
AN[0] (DAN0+)
AN[1] (DAN0-)
AN[2] (DAN1+)
AN[3] (DAN1-)
AN[4] (DAN2+)
AN[5] (DAN2-)
AN[6] (DAN3+)
AN[7] (DAN3-)
REFBYPC
VRH
VRL
AN[22]
AN[23]
AN[24]
AN[25]
AN[27]
AN[28]
AN[30]
AN[31]
AN[32]
AN[33]
AN[34]
AN[35]
VDD
AN[12] / MA[0] / ETPU_A[19] / SDS
AN[13] / MA[1] / ETPU_A[21] / SDO
AN[14] / MA[2] / ETPU_A[27] / SDI
AN[15] / FCK / ETPU_A[29]
NC
NC
NC
NC
VSS
eTPU_A[25] / GPIO[223]
VDDEH7
eTPU_A[21] / GPIO[222]
eTPU_A[19] / GPIO[221]
eTPU_A[13] / GPIO[220]
eTPU_A[27] / GPIO[224]
VSS
Figure 4 shows the pinout for the 176-pin LQFP for the MPC5633M (1024 KB flash memory).
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
176-Pin
LQFP
signal details:
Pin 21: eTPU_A[31] / DSPI_C_PCS[4] / eTPU_A[13] / GPIO[145]
Pin 22: eTPU_A[30] / DSPI_C_PCS[3] / eTPU_A[11] / GPIO[144]
Pin 23: eTPU_A[29] / DSPI_C_PCS[2] / GPIO[143]
Pin 24: eTPU_A[28]/ DSPI_C_PCS[1] / GPIO[142]
Pin 25: eTPU_A[27] / IRQ[15] / DSPI_C_SOUT_LVDS+ / DSPI_B_SOUT / GPIO[141]
Pin 26: eTPU_A[26] / IRQ[14] / DSPI_C_SOUT_LVDS- / GPIO[140]
Pin 27: eTPU_A[25] / IRQ[13] / DSPI_C_SCK_LVDS+ / GPIO[139]
Pin 28: eTPU_A[24] / IRQ[12] / DSPI_C_SCK_LVDS- / GPIO[138]
Pin 30: eTPU_A[23] / IRQ[11] / eTPU_A[21] / GPIO[137]
Pin 32: eTPU_A[22] / IRQ[10] / eTPU_A[17] / GPIO[136]
Pin 40: eTPU_A[15] / DSPI_B_PCS[5] / GPIO[129]
Pin 42: eTPU_A[14] / DSPI_B_PCS[4] / eTPU_A[9] / GPIO[128]
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
NIC
TMS
TDI / eMIOS[5] / GPIO[232]
eTPU_A[4] / GPIO[227]
TCK
VSS
eTPU_A[2] / GPIO[231]
VDDEH7
eTPU_A[29] / GPIO[225]
TDO / eMIOS[6] / GPIO[228]
GPIO[219]
JCOMP
ALT_EVTO
VDDE12
ALT_MSEO[0]
ALT_MSEO[1]
ALT_EVTI
VSS
DSPI_B_PCS[3] / DSPI_C_SIN / GPIO[108]
DSPI_B_SOUT / DSPI_C_PCS[5] / GPIO[104]
DSPI_B_SIN / DSPI_C_PCS[2] / GPIO[103]
DSPI_B_PCS[0] / GPIO[105]
VDDEH6B
DSPI_B_PCS[1] / GPIO[106]
VSS
DSPI_B_PCS[2] / DSPI_C_SOUT / GPIO[107]
DSPI_B_SCK / DSPI_C_PCS[1] / GPIO[102]
DSPI_B_PCS[4] / DSPI_C_SCK / GPIO[109]
DSPI_B_PCS[5] / DSPI_C_PCS[0] / GPIO[110]
VDD
RSTOUT
CAN_C_TX / GPIO[87]
SCI_A_TX / eMIOS[13] / GPIO[89]
SCI_A_RX / eMIOS[15] / GPIO[90]
CAN_C_RX / GPIO[88]
RESET
VSS
VDDEH6A
VSSPLL
XTAL
EXTAL / EXTCLK
VDDPLL
VSS
NIC
NIC
eTPU_A[13] / DSPI_B_PCS[3] / GPIO[127]
eTPU_A[12] / DSPI_B_PCS[1] / GPIO[126]
eTPU_A[11] / eTPU_A[23] / GPIO[125]
eTPU_A[10] / eTPU_A[22] / GPIO[124]
eTPU_A[9] / eTPU_A[21] / GPIO[123]
eTPU_A[8]/eTPU_A[20]/DSPI_B_SOUT_LVDS+/GPIO[122]
eTPU_A[7]/eTPU_A[19]/DSPI_B_SOUT_LVDS-/eTPU_A[6]/GPIO[121]
eTPU_A[6] / eTPU_A[18] / DSPI_B_SCK_LVDS+ / GPIO[120]
eTPU_A[5] / eTPU_A[17] / DSPI_B_SCK_LVDS- / GPIO[119]
VDDEH1B
eTPU_A[4] / eTPU_A[16] / GPIO[118]
VSS
eTPU_A[3] / eTPU_A[15] / GPIO[117]
eTPU_A[2] / eTPU_A[14] / GPIO[116]
eTPU_A[1] / eTPU_A[13] / GPIO[115]
eTPU_A[0] / eTPU_A[12] / eTPU_A[19] / GPIO[114]
VDD
eMIOS[0] / eTPU_A[0] / eTPU_A[25] / GPIO[179]
NC
eMIOS[2] / eTPU_A[2] / GPIO[181]
NIC
eMIOS[4] / eTPU_A[4] / GPIO[183]
NIC
NIC
eMIOS[8] / eTPU_A[8] / SCI_B_TX / GPIO[187]
eMIOS[9] / eTPU_A[9] / SCI_B_RX / GPIO[188]
VSS
eMIOS[10] / GPIO[189]
VDDEH6A
eMIOS[11] / GPIO[190]
eMIOS[12] / DSPI_C_SOUT / eTPU_A[27] / GPIO[191]
NC
eMIOS[14] / IRQ[0] / eTPU_A[29] / GPIO[193]
NC
eMIOS[23] / GPIO[202]
CAN_A_TX / SCI_A_TX / GPIO[83]
CAN_A_RX / SCI_A_RX / GPIO[84]
PLLREF / IRQ[4]/ETRIG[2] / GPIO[208]
SCI_B_RX / GPIO[92]
BOOTCFG1 / IRQ[3] / ETRIG[3] / GPIO[212]
WKPCFG / NMI / DSPI_B_SOUT / GPIO[213]
SCI_B_TX / GPIO[91]
NIC
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
AN[18]
AN[17]
AN[16]
AN[11] / ANZ
AN[9] / ANX
VDDA
VSSA
AN[39] / AN[10] / ANY
AN[38] / AN[8] / ANW
VDDREG
VRCCTL
VSTBY
VRC33
ALT_MCKO
VSS
VDDE12
ALT_MDO[0]
ALT_MDO[1]
ALT_MDO[2]
ALT_MDO[3]
(see signal details, pin 21)
(see signal details, pin 22)
(see signal details, pin 23)
(see signal details, pin 24)
(see signal details, pin 25)
(see signal details, pin 26)
(see signal details, pin 27)
(see signal details, pin 28)
VSS
(see signal details, pin 30)
VDDEH1A
(see signal details, pin 32)
VDD
eTPU_A[21] / IRQ[9] / GPIO[135]
eTPU_A[20] / IRQ[8] / GPIO[134]
eTPU_A[19] / GPIO[133]
eTPU_A[18] / GPIO[132]
eTPU_A[17] / GPIO[131]
eTPU_A[16] / GPIO[130]
(see signal details, pin 40)
VDDEH1B
(see signal details, pin 42)
VSS
NIC
Notes:
1. Pins marked “NIC” have no internal connection.
2. Pins marked “NC” are not functional pins but may be connected to internal circuitry. Connections to external
circuits or other pins on this device can result in unpredictable system behavior or damage.
Figure 4. 176-pin LQFP pinout (MPC5633M; top view)
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
41
42
3.4
208 MAPBGA ballmap (MPC5634M)
Figure 5 shows the 208-pin MAPBGA ballmap for the MPC5634M (1536 KB flash memory) as viewed from above.
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
1
2
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
VSS
AN9
AN11
VDDA1
VSSA1
AN1
AN5
VRH
VRL
AN27
VSSA0
AN12- SDS
ALT_
MDO2
ALT_
MDO0
VRC33
VSS
B
VDD
VSS
AN38
AN21
AN0
AN4
REFBYPC
AN22
AN25
AN28
VDDA0
AN13-SDO
ALT_
MDO3
ALT_
MDO1
VSS
VDD
C
VSTBY
VDD
VSS
AN17
AN34
AN16
AN3
AN7
AN23
AN32
AN33
AN14-SDI
AN15
FCK
VSS
ALT_
MSEO0
TCK
D
VRC33
AN39
VDD
VSS
AN18
AN2
AN6
AN24
AN30
AN31
AN35
VDDEH7
VSS
TMS
ALT_EVTO
NIC1
E
ETPUA30
ETPUA31
AN37
VDD
VDDE7
TDI
ALT_EVTI
ALT_
MSEO1
F
ETPUA28
ETPUA29
ETPUA26
AN36
VDDEH6
TDO
ALT_MCKO
JCOMP
G
ETPUA24
ETPUA27
ETPUA25
ETPUA21
VSS
VSS
VSS
VSS
DSPI_B_
SOUT
DSPI_B_
PCS3
DSPI_B_
SIN
DSPI_B_
PCS0
H
ETPUA23
ETPUA22
ETPUA17
ETPUA18
VSS
VSS
VSS
VSS
GPIO99
DSPI_B_
PCS4
DSPI_B_
PCS2
DSPI_B_
PCS1
J
ETPUA20
ETPUA19
ETPUA14
ETPUA13
VSS
VSS
VSS
VSS
DSPI_B_
PCS5
SCI_A_TX
GPIO98
DSPI_B_
SCK
K
ETPUA16
ETPUA15
ETPUA7
VDDEH1
VSS
VSS
VSS
VSS
CAN_C_
TX
SCI_A_RX
RSTOUT
VDDREG
L
ETPUA12
ETPUA11
ETPUA6
ETPUA0
SCI_B_TX
CAN_C_
RX
WKPCFG
M
ETPUA10
ETPUA9
ETPUA1
ETPUA5
SCI_B_RX
PLLREF
BOOTCFG1
VSSPLL
N
ETPUA8
ETPUA4
ETPUA0
VSS
VDD
VRC33
EMIOS2
EMIOS10
VDDEH1/62
EMIOS12
eTPU_A193
VRC33
VSS
VRCCTL
NIC1
EXTAL
P
ETPUA3
ETPUA2
VSS
VDD
GPIO207
VDDE7
NIC1
EMIOS8
eTPU_A293
eTPU_A23
eTPU_A213
CAN_A_
TX
VDD
VSS
NIC1
XTAL
R
NIC1
VSS
VDD
GPIO206
EMIOS4
NIC1
EMIOS9
EMIOS11
EMIOS14
eTPU_A273
EMIOS23
CAN_A_
RX
NIC1
VDD
VSS
VDDPLL
T
VSS
VDD
NIC1
EMIOS0
EMIOS1
GPIO219
eTPU_A253
EMIOS13
EMIOS15
eTPU_A43
eTPU_A133
NIC1
VDDE5
CLKOUT
VDD
VSS
Pins marked “NIC” have no internal connection.
This ball may be changed to “NC” (no connection) in a future revision.
eTPU output only channel.
Figure 5. 208-pin MAPBGA ballmap (MPC5634M; top view)
RESET
Freescale Semiconductor
3.5
208 MAPBGA ballmap (MPC5633M only)
Figure 6 shows the 208-pin MAPBGA ballmap for the MPC5633M (1024 KB flash memory) as viewed from above.
MPC5644A Microcontroller Data Sheet, Rev. 8
1
2
3
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
VSS
AN9
AN11
VDDA1
VSSA1
AN1
AN5
VRH
VRL
AN27
VSSA0
AN12-SDS
ALT_
MDO2
ALT_
MDO0
VRC33
VSS
B
VDD
VSS
AN38
AN21
AN0
AN4
REFBYPC
AN22
AN25
AN28
VDDA0
AN13-SDO
ALT_
MDO3
ALT_
MDO1
VSS
VDD
C
VSTBY
VDD
VSS
AN17
AN34
AN16
AN3
AN7
AN23
AN32
AN33
AN14-SDI
AN15
FCK
VSS
ALT_
MSEO0
TCK
D
VRC33
AN39
VDD
VSS
AN18
AN2
AN6
AN24
AN30
AN31
AN35
VDDEH7
VSS
TMS
ALT_EVTO
NIC1
E
ETPUA30
ETPUA31
NC2
VDD
VDDE7
TDI
ALT_
EVTI
ALT_
MSEO1
F
ETPUA28
ETPUA29
ETPUA26
NC2
VDDEH6
TDO
ALT_MCKO
JCOMP
G
ETPUA24
ETPUA27
ETPUA25
ETPUA21
VSS
VSS
VSS
VSS
DSPI_B_
SOUT
DSPI_B_
PCS3
DSPI_B_
SIN
DSPI_B_
PCS0
H
ETPUA23
ETPUA22
ETPUA17
ETPUA18
VSS
VSS
VSS
VSS
NC2
DSPI_B_
PCS4
DSPI_B_
PCS2
DSPI_B_
PCS1
J
ETPUA20
ETPUA19
ETPUA14
ETPUA13
VSS
VSS
VSS
VSS
DSPI_B_
PCS5
SCI_A_TX
NC2
DSPI_B_
SCK
K
ETPUA16
ETPUA15
ETPUA7
VDDEH1
VSS
VSS
VSS
VSS
CAN_C_
TX
SCI_A_RX
RSTOUT
VDDREG
L
ETPUA12
ETPUA11
ETPUA6
ETPUA0
SCI_B_TX
CAN_C_
RX
WKPCFG
RESET
M
ETPUA10
ETPUA9
ETPUA1
ETPUA5
SCI_B_RX
PLLREF
BOOTCFG1
VSSPLL
N
ETPUA8
ETPUA4
ETPUA0
VSS
VDD
VRC33
EMIOS2
EMIOS10
P
ETPUA3
ETPUA2
VSS
VDD
NC2
VDDE7
NIC1
EMIOS8
R
NIC1
VSS
VDD
NC2
EMIOS4
NIC1
EMIOS9
EMIOS11
EMIOS14
T
VSS
VDD
NIC1
EMIOS0
NC2
GPIO219
eTPUA253
NC2
NC2
VDDEH1/63
EMIOS12
eTPUA293
eTPUA23
eTPUA273
eTPUA43
eTPUA194
VRC33
VSS
VRCCTL
NIC1
EXTAL
eTPUA213
CAN_A_
TX
VDD
VSS
NIC1
XTAL
EMIOS23
CAN_A_
RX
NC2
VDD
VSS
VDDPLL
eTPUA133
NIC1
VDDE5
CLKOUT
VDD
VSS
Pins marked “NIC” have no internal connection.
Pins marked “NC” may be connected to internal circuitry. Connections to external circuits or other pins on this device can result in unpredictable system behavior or damage.
This ball may be changed to “NC” (no connection) in a future revision.
eTPU output only channel.
Figure 6. 208-pin MAPBGA ballmap (MPC5633M; top view)
43
44
3.6
Signal summary
t
Table 3. MPC563xM signal properties
Function1
Name
Pad
Config.
Register
(PCR)2
Pin No.
PCR PA I/O
Field3 Type
Voltage4 /
Pad Type
Reset State5
Function / State
After Reset6
144
LQFP
176
LQFP
208 MAPB
GA
Dedicated GPIO
MPC5634M Microcontroller Data Sheet, Rev. 8
GPIO[98]
GPIO
PCR[98]
—
I/O
VDDEH7
Slow
– / Up
GPIO[98]/Up
—
1417
J158
GPIO[99]
GPIO
PCR[99]
—
I/O
VDDEH7
Slow
– / Up
GPIO[99]/Up
—
1427
H138
GPIO[206]9
GPIO
PCR[206]
—
I/O
VDDEH7
Slow
– / Up
GPIO[206]/Up
—
1437
R48
GPIO[207]9
GPIO
PCR[207]
—
I/O
VDDEH7
Slow
– / Up
GPIO[207]/Up
—
1447
P58
Reset / Configuration
Freescale Semiconductor
RESET
External Reset Input
RSTOUT
External Reset Output
PLLREF
IRQ[4]
ETRIG[2]
GPIO[208]
FMPLL Mode Selection
External Interrupt Request
eQADC Trigger Input
GPIO
BOOTCFG1
IRQ[3]
ETRIG[3]
GPIO[212]
WKPCFG
NMI
DSPI_B_SOUT
GPIO[213]
—
—
I
VDDEH6a
Slow
I / Up
RESET /
Up
80
97
L16
PCR[230]
—
O
VDDEH6a
Slow
RSTOUT/
Low
RSTOUT/
High
85
102
K15
PCR[208]
011
010
100
000
I
I
I
I/O
VDDEH6a
Slow
PLLREF / Up
– / Up
68
83
M14
Boot Config. Input
External Interrupt Request
eQADC Trigger Input
GPIO
PCR[212]
011
010
100
000
I
I
I
I/O
VDDEH6a
Slow
BOOTCFG1 /
Down
– / Down
70
85
M15
Weak Pull Config. Input
Non-Maskable Interrupt
DSPI_B Data Output
GPIO
PCR[213]
01
11
10
00
I
I
O
I/O
VDDEH6a
Slow
WKPCFG /
Up
– / Up
71
86
L15
O / Low
CAL_ADDR /
Low
—
—
—
Calibration10
CAL_ADDR[12:15]11
Calibration Address Bus
PCR[340]
—
O
VDDE12
Fast
Freescale Semiconductor
Table 3. MPC563xM signal properties (continued)
Name
Function
1
Pad
Config.
Register
(PCR)2
Pin No.
PCR PA I/O
Field3 Type
Voltage4 /
Pad Type
Reset
State5
Function / State
After Reset6
144
LQFP
176
LQFP
208 MAPB
GA
MPC5644A Microcontroller Data Sheet, Rev. 8
45
CAL_ADDR[16]21
ALT_MDO[0]12
Calibration Address Bus
Nexus Msg Data Out
PCR[345]
—
O
O
VDDE1213
VDDE714
Fast
O / Low15
MDO /
ALT_ADDR12 /
Low
—
17
A14
CAL_ADDR[17]21
ALT_MDO[1]12
Calibration Address Bus
Nexus Msg Data Out
PCR[345]
—
O
O
VDDE1213
VDDE714
Fast
O / Low15
ALT_MDO /
CAL_ADDR12 /
Low
—
18
B14
CAL_ADDR[18]21
ALT_MDO[2]12
Calibration Address Bus
Nexus Msg Data Out
PCR[345]
—
O
O
VDDE1213
VDDE714
Fast
O / Low15
ALT_MDO /
CAL_ADDR12 /
Low
—
19
A13
CAL_ADDR[19]21
ALT_MDO[3]12
Calibration Address Bus
Nexus Msg Data Out
PCR[345]
—
O
O
VDDE1213
VDDE714
Fast
O / Low15
ALT_MDO /
CAL_ADDR12 /
Low
—
20
B13
CAL_ADDR[20:27]
ALT_MDO[4:11]
Calibration Address Bus
Nexus Msg Data Out
PCR[345]
—
O
O
VDDE1213
Fast
O / Low
ALT_MDO /
CAL_ADDR16 /
Low
—
—
—
CAL_ADDR[28]21
ALT_MSEO[0]12
Calibration Address Bus
Nexus Msg Start/End Out
PCR[345]
—
O
O
VDDE1213
VDDE714
Fast
O / Low17
ALT_MSEO16 /
CAL_ADDR17/
Low
—
118
C15
CAL_ADDR[29]21
ALT_MSEO[1]12
Calibration Address Bus
Nexus Msg Start/End Out
PCR[345]
—
O
O
VDDE1213
VDDE714
Fast
O / Low17
ALT_MSEO16 /
CAL_ADDR17/
Low
—
117
E16
CAL_ADDR[30]21
ALT_EVTI12
Calibration Address Bus
Nexus Event In
PCR[345]
—
O
I
VDDE1213
VDDE714
Fast
—18
ALT_EVTI /
CAL_ADDR19
—
116
E15
ALT_EVTO
Nexus Event Out
PCR[344]
—
O
VDDE1213
VDDE714
Fast
O / Low
ALT_EVTO /
High
—
120
D15
ALT_MCKO
Nexus Msg Clock Out
PCR[344]
—
O
VDDE1213
VDDE714
Fast
O / Low
ALT_MCKO /
Enabled
—
14
F15
NEXUSCFG11
Nexus/Calibration bus
selector
—
I
VDDE12
Fast
I / Down
NEXUSCFG /
Down
—
—
—
CAL_CS[0]11
Calibration Chip Selects
PCR[336]
—
O
VDDE12
Fast
O / High
CAL_CS / High
—
—
—
CAL_CS[2]11
CAL_ADDR[10]
Calibration Chip Selects
Calibration Address Bus
PCR[338]
11
10
O
O
VDDE12
Fast
O / High
CAL_CS / High
—
—
—
—
46
Table 3. MPC563xM signal properties (continued)
Name
Function
1
Pad
Config.
Register
(PCR)2
CAL_CS[3]11
CAL_ADDR[11]
Calibration Chip Selects
Calibration Address Bus
PCR[339]
CAL_DATA[0:9]11
Calibration Data Bus
CAL_DATA[10:15]11
Pin No.
PCR PA I/O
Field3 Type
Voltage4 /
Pad Type
Reset
State5
Function / State
After Reset6
144
LQFP
176
LQFP
208 MAPB
GA
MPC5634M Microcontroller Data Sheet, Rev. 8
O
O
VDDE12
Fast
O / High
CAL_CS / High
—
—
—
PCR[341]
I/O
VDDE12
Fast
– / Up
– / Up
—
—
—
Calibration Data Bus
PCR[341]
I/O
VDDE12
Fast
– / Up
– / Up
—
—
—
CAL_OE11
Calibration Output Enable
PCR[342]
—
O
VDDE12
Fast
O / High
CAL_OE / High
—
—
—
CAL_RD_WR11
Calibration Read/Write
PCR[342]
—
O
VDDE12
Fast
O / High
CAL_RD_WR
/High
—
—
—
CAL_TS_ALE11
Calibration Transfer Start
Address Latch Enable
PCR[343]
O
O
VDDE12
Fast
O / High
CAL_TS / High
—
—
—
CAL_WE_BE[0:1]11
Calibration Write Enable
Byte Enable
PCR[342]
O
VDDE12
Fast
O / High
CAL_WE /
High
—
—
—
11
10
—
NEXUS20
Freescale Semiconductor
EVTI21
eTPU_A[2]
GPIO[231]
Nexus Event In
eTPU A Ch.
GPIO
PCR[231]
01
10
00
I
O
I/O
VDDEH7
Multi-V
–/–
–/–
103
126
P10
EVTO 21
eTPU_A[4]
GPIO[227]
Nexus Event Out
eTPU A Ch.
GPIO
PCR[227]
0122
10
00
O
O
I/O
VDDEH7
Multi-V
I / Up
I / Up
106
129
T10
MCKO21
GPIO[219]
Nexus Msg Clock Out
GPIO
PCR[219]
N/A22
00
O
I/O
VDDEH7
Multi-V
–/–
–/–
99
122
T6
MDO[0]21
eTPU_A[13]
GPIO[220]
Nexus Msg Data Out
eTPU A Ch.
GPIO
PCR[220]
01
10
00
O
O
I/O
VDDEH7
Multi-V
–/–
–/–
110
135
T11
MDO[1]21
eTPU_A[19]
GPIO[221]
Nexus Msg Data Out
eTPU A Ch.
GPIO
PCR[221]
0122
10
00
O
O
I/O
VDDEH7
Multi-V
–/–
–/–
111
136
N11
MDO[2]21
eTPU_A[21]
GPIO[222]
Nexus Msg Data Out
eTPU A Ch.
GPIO
PCR[222]
0122
10
00
O
O
I/O
VDDEH7
Multi-V
–/–
–/–
112
137
P11
Freescale Semiconductor
Table 3. MPC563xM signal properties (continued)
Name
Function
1
Pad
Config.
Register
(PCR)2
Pin No.
PCR PA I/O
Field3 Type
Voltage4 /
Pad Type
Reset
State5
Function / State
After Reset6
144
LQFP
176
LQFP
208 MAPB
GA
MPC5644A Microcontroller Data Sheet, Rev. 8
MDO[3]21
eTPU_A[25]
GPIO[223]
Nexus Msg Data Out
eTPU A Ch.
GPIO
PCR[223]
0122
10
00
O
O
I/O
VDDEH7
Multi-V
–/–
–/–
114
139
T7
MSEO[0]21
eTPU_A[27]
GPIO[224]
Nexus Msg Start/End Out
eTPU A Ch.
GPIO
PCR[224]
0122
10
00
O
O
I/O
VDDEH7
Multi-V
–/–
–/–
109
134
R10
MSEO[1]21
eTPU_A[29]
GPIO[225]
Nexus Msg Start/End Out
eTPU A Ch.
GPIO
PCR[225]
0122
10
00
O
O
I/O
VDDEH7
Multi-V
–/–
–/–
101
124
P9
JTAG / TEST
TCK
JTAG Test Clock Input
TDI23
eMIOS[5]
GPIO[232]
JTAG Test Data Input
eMIOS Ch.
GPIO
TDO23
eMIOS[6]
GPIO[228]
JTAG Test Data Output
eMIOS Ch.
GPIO
TMS
JTAG Test Mode Select Input
JCOMP
JTAG TAP Controller Enable
—
—
I
VDDEH7
Multi-V
TCK / Down
TCK / Down
105
128
C16
PCR[232]
0124
10
00
I
O
I/O
VDDEH7
Multi-V
–/–
–/–
107
130
E14
PCR[228]
0124
10
00
O
O
I/O
VDDEH7
Multi-V
–/–
–/–
100
123
F14
—
—
I
VDDEH7
Multi-V
TMS / Up
TMS / Up
108
131
D14
—
—
I
VDDEH7
Multi-V
JCOMP /
Down
JCOMP / Down
98
121
F16
CAN
CAN_A_TX
SCI_A_TX
GPIO[83]
CAN_A Transmit
eSCI_A Transmit
GPIO
PCR[83]
01
10
00
O
O
I/O
VDDEH6a
Slow
– / Up
– / Up25
66
81
P12
CAN_A_RX
SCI_A_RX
GPIO[84]
CAN_A Receive
eSCI_A Receive
GPIO
PCR[84]
01
10
00
I
I
I/O
VDDEH6a
Slow
– / Up
– / Up
67
82
R12
CAN_C_TX
GPIO[87]
CAN_C Transmit
GPIO
PCR[87]
01
00
O
I/O
VDDEH6a
Medium
– / Up
– / Up
84
101
K13
CAN_C_RX
GPIO[88]
CAN_C Receive
GPIO
PCR[88]
01
00
I
I/O
VDDEH6a
Slow
– / Up
– / Up
81
98
L14
47
48
Table 3. MPC563xM signal properties (continued)
Name
Function
1
Pad
Config.
Register
(PCR)2
Pin No.
PCR PA I/O
Field3 Type
Voltage4 /
Pad Type
Reset
State5
Function / State
After Reset6
144
LQFP
176
LQFP
208 MAPB
GA
eSCI
MPC5634M Microcontroller Data Sheet, Rev. 8
SCI_A_TX
eMIOS[13]
GPIO[89]
eSCI_A Transmit
eMIOS Ch.
GPIO
PCR[89]
01
10
00
O
O
I/O
VDDEH6a
Slow
– / Up
– / Up
83
100
J14
SCI_A_RX
eMIOS[15]
GPIO[90]
eSCI_A Receive
eMIOS Ch.
GPIO
PCR[90]
01
10
00
I
O
I/O
VDDEH6a
Slow
– / Up
– / Up
82
99
K14
SCI_B_TX
GPIO[91]
eSCI_B Transmit
GPIO
PCR[91]
01
00
I/O
I/O
VDDEH6a
Slow
– / Up
– / Up
72
87
L13
SCI_B_RX
GPIO[92]
eSCI_B Receive
GPIO
PCR[92]
01
00
I
I/O
VDDEH6a
Slow
– / Up
– / Up
69
84
M13
DSPI
Freescale Semiconductor
DSPI_B_SCK
DSPI_C_PCS[1]
GPIO[102]
DSPI_B Clock
DSPI_C Periph Chip Select
GPIO
PCR[102]
01
10
00
I/O
O
I/O
VDDEH6b
Medium
– / Up
– / Up
89
106
J16
DSPI_B_SIN
DSPI_C_PCS[2]
GPIO[103]
DSPI_B Data Input
DSPI_C Periph Chip Select
GPIO
PCR[103]
01
10
00
I
O
I/O
VDDEH6b
Medium
– / Up
– / Up
95
112
G15
DSPI_B_SOUT
DSPI_C_PCS[5]
GPIO[104]
DSPI_B Data Output
DSPI_C Periph Chip Select
GPIO
PCR[104]
01
10
00
O
O
I/O
VDDEH6b
Medium
– / Up
– / Up
96
113
G13
DSPI_B_PCS[0]
GPIO[105]
DSPI_B Periph Chip Select
GPIO
PCR[105]
01
00
O
I/O
VDDEH6b
Medium
– / Up
– / Up
94
111
G16
DSPI_B_PCS[1]
GPIO[106]
DSPI_B Periph Chip Select
GPIO
PCR[106]
01
00
O
I/O
VDDEH6b
Medium
– / Up
– / Up
92
109
H16
DSPI_B_PCS[2]
DSPI_C_SOUT
GPIO[107]
DSPI_B Periph Chip Select
DSPI_C Data Output
GPIO
PCR[107]
01
10
00
O
O
I/O
VDDEH6b
Medium
– / Up
– / Up
90
107
H15
DSPI_B_PCS[3]
DSPI_C_SIN
GPIO[108]
DSPI_B Periph Chip Select
DSPI_C Data Input
GPIO
PCR[108]
01
10
00
O
I
I/O
VDDEH6b
Medium
– / Up
– / Up
97
114
G14
DSPI_B_PCS[4]
DSPI_C_SCK
GPIO[109]
DSPI_B Periph Chip Select
DSPI_C Clock
GPIO
PCR[109]
01
10
00
O
I/O
I/O
VDDEH6b
Medium
– / Up
– / Up
88
105
H14
Freescale Semiconductor
Table 3. MPC563xM signal properties (continued)
Name
DSPI_B_PCS[5]
DSPI_C_PCS[0]
GPIO[110]
Function
1
DSPI_B Periph Chip Select
DSPI_C Periph Chip Select
GPIO
Pad
Config.
Register
(PCR)2
PCR[110]
Pin No.
PCR PA I/O
Field3 Type
01
10
00
O
O
I/O
Voltage4 /
Pad Type
VDDEH6b
Medium
Reset
State5
Function / State
After Reset6
144
LQFP
176
LQFP
208 MAPB
GA
– / Up
– / Up
87
104
J13
eQADC
MPC5644A Microcontroller Data Sheet, Rev. 8
AN[0]
DAN0+
Single Ended Analog Input
Positive Terminal Diff. Input
—
—
I
I
VDDA
I/–
AN[0] / –
143
172
B5
AN[1]
DAN0-
Single Ended Analog Input
Negative Terminal Diff. Input
—
—
I
I
VDDA
I/–
AN[1] / –
142
171
A6
AN[2]
DAN1+
Single Ended Analog Input
Positive Terminal Diff. Input
—
—
I
I
VDDA
I/–
AN[2] / –
141
170
D6
AN[3]
DAN1-
Single Ended Analog Input
Negative Terminal Diff. Input
—
—
I
I
VDDA
I/–
AN[3] / –
140
169
C7
AN[4]
DAN2+
Single Ended Analog Input
Positive Terminal Diff. Input
—
—
I
I
VDDA
I/–
AN[4] / –
139
168
B6
AN[5]
DAN2-
Single Ended Analog Input
Negative Terminal Diff. Input
—
—
I
I
VDDA
I/–
AN[5] / –
138
167
A7
AN[6]
DAN3+
Single Ended Analog Input
Positive Terminal Diff. Input
—
—
I
I
VDDA
I/–
AN[6] / –
137
166
D7
AN[7]
DAN3-
Single Ended Analog Input
Negative Terminal Diff. Input
—
—
I
I
VDDA
I/–
AN[7] / –
136
165
C8
AN[8]
See AN[38]-AN[8]-ANW
AN[9]
ANX
Single Ended Analog Input
External Multiplexed Analog
Input
—
—
I
I
VDDA
I/–
AN[9] / –
5
5
A2
AN[10]
See AN[39]-AN[10]-ANY
AN[11]
ANZ
Single Ended Analog Input
External Multiplexed Analog
Input
—
—
I
I
VDDA
I/–
AN[11] / –
4
4
A3
AN[12]
MA[0]
ETPU_A[19]
SDS
Single Ended Analog Input
Mux Address
ETPU_A Ch.
eQADC Serial Data Strobe
011
010
100
000
I
O
O
O
VDDEH7
I/–
AN[12] / –
119
148
A12
PCR[215]
49
50
Table 3. MPC563xM signal properties (continued)
Name
Function
1
Pad
Config.
Register
(PCR)2
Pin No.
PCR PA I/O
Field3 Type
Voltage4 /
Pad Type
Reset
State5
Function / State
After Reset6
144
LQFP
176
LQFP
208 MAPB
GA
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
AN[13]
MA[1]
ETPU_A[21]
SDO
Single Ended Analog Input
Mux Address
ETPU_A Ch.
eQADC Serial Data Out
PCR[216]
011
010
100
000
I
O
O
O
VDDEH7
I/–
AN[13] / –
118
147
B12
AN[14]
MA[2]
ETPU_A[27]
SDI
Single Ended Analog Input
Mux Address
ETPU_A Ch.
eQADC Serial Data In
PCR[217]
011
010
100
000
I
O
O
I
VDDEH7
I/–
AN[14] / –
117
146
C12
AN[15]
FCK
ETPU_A[29]
Single Ended Analog Input
eQADC Free Running Clock
ETPU_A Ch.
PCR[218]
011
010
100
I
O
O
VDDEH7
I/–
AN[15] / –
116
145
C13
AN[16]
Single Ended Analog Input
—
—
I
VDDA
I/–
AN[x] / –
3
3
C6
AN[17]
Single Ended Analog Input
—
—
I
VDDA
I/–
AN[x] / –
2
2
C4
AN[18]
Single Ended Analog Input
—
—
I
VDDA
I/–
AN[x] / –
1
1
D5
AN[21]
Single Ended Analog Input
—
—
I
VDDA
I/–
AN[x] / –
144
173
B4
AN[22]
Single Ended Analog Input
—
—
I
VDDA
I/–
AN[x] / –
132
161
B8
AN[23]
Single Ended Analog Input
—
—
I
VDDA
I/–
AN[x] / –
131
160
C9
AN[24]
Single Ended Analog Input
—
—
I
VDDA
I/–
AN[x] / –
130
159
D8
AN[25]
Single Ended Analog Input
—
—
I
VDDA
I/–
AN[x] / –
129
158
B9
AN[27]
Single Ended Analog Input
—
—
I
VDDA
I/–
AN[x] / –
128
157
A10
AN[28]
Single Ended Analog Input
—
—
I
VDDA
I/–
AN[x] / –
127
156
B10
AN[30]
Single Ended Analog Input
—
—
I
VDDA
I/–
AN[x] / –
126
155
D9
AN[31]
Single Ended Analog Input
—
—
I
VDDA
I/–
AN[x] / –
125
154
D10
AN[32]
Single Ended Analog Input
—
—
I
VDDA
I/–
AN[x] / –
124
153
C10
AN[33]
Single Ended Analog Input
—
—
I
VDDA
I/–
AN[x] / –
123
152
C11
AN[34]
Single Ended Analog Input
—
—
I
VDDA
I/–
AN[x] / –
122
151
C5
AN[35]
Single Ended Analog Input
—
—
I
VDDA
I/–
AN[x] / –
121
150
D11
7
F48
E38
AN[36]
Single Ended Analog Input
—
—
I
VDDA
I/–
AN[x] / –
—
174
AN[37]
Single Ended Analog Input
—
—
I
VDDA
I/–
AN[x] / –
—
1757
Freescale Semiconductor
Table 3. MPC563xM signal properties (continued)
Name
Function
1
Pad
Config.
Register
(PCR)2
Pin No.
PCR PA I/O
Field3 Type
Voltage4 /
Pad Type
Reset
State5
Function / State
After Reset6
144
LQFP
176
LQFP
208 MAPB
GA
MPC5644A Microcontroller Data Sheet, Rev. 8
AN[38]-AN[8]ANW
Single Ended Analog Input
Multiplexed Analog Input
—
—
I
VDDA
I/–
AN[38] / –
9
9
B3
AN[39]-AN[10]ANY
Single Ended Analog Input
Multiplexed Analog Input
—
—
I
VDDA
I/–
AN[39] / –
8
8
D2
VRH
Voltage Reference High
—
—
I
VDDA
–/–
VRH
134
163
A8
VRL
Voltage Reference Low
—
—
I
VSSA0
–/–
VRL
133
162
A9
REFBYPC
Bypass Capacitor Input
—
—
I
VRL
–/–
REFBYPC
135
164
B7
eTPU2
eTPU_A[0]
eTPU_A[12]
eTPU_A[19]
GPIO[114]
eTPU_A Ch.
eTPU_A Ch.
eTPU_A Ch.
GPIO
PCR[114]
011
010
100
000
I/O
O
O
I/O
VDDEH1b
Slow
– / WKPCFG
– / WKPCFG
52
61
L4, N3
eTPU_A[1]
eTPU_A[13]
GPIO[115]
eTPU_A Ch.
eTPU_A Ch.
GPIO
PCR[115]
01
10
00
I/O
O
I/O
VDDEH1b
Slow
– / WKPCFG
– / WKPCFG
51
60
M3
eTPU_A[2]
eTPU_A[14]
GPIO[116]
eTPU_A Ch.
eTPU_A Ch.
GPIO
PCR[116]
01
10
00
I/O
O
I/O
VDDEH1b
Slow
– / WKPCFG
– / WKPCFG
50
59
P2
eTPU_A[3]
eTPU_A[15]
GPIO[117]
eTPU_A Ch.
eTPU_A Ch.
GPIO
PCR[117]
01
10
00
I/O
O
I/O
VDDEH1b
Slow
– / WKPCFG
– / WKPCFG
49
58
P1
eTPU_A[4]
eTPU_A[16]
GPIO[118]
eTPU_A Ch.
eTPU_A Ch.
GPIO
PCR[118]
01
10
00
I/O
O
I/O
VDDEH1b
Slow
– / WKPCFG
– / WKPCFG
47
56
N2
eTPU_A[5]
eTPU_A[17]
DSPI_B_SCK_LVDSGPIO[119]
eTPU_A Ch.
eTPU_A Ch.
DSPI_B CLOCK LVDSGPIO
PCR[119]
001
010
100
000
I/O
O
O
I/O
VDDEH1b
Slow
– / WKPCFG
– / WKPCFG
45
54
M4
eTPU_A[6]
eTPU_A[18]
DSPI_B_SCK_LVDS+
GPIO[120]
eTPU_A Ch.
eTPU_A Ch.
DSPI_B Clock LVDS+
GPIO
PCR[120]
001
010
100
000
I/O
O
O
I/O
VDDEH1b
Medium
– / WKPCFG
– / WKPCFG
44
53
L3
51
52
Table 3. MPC563xM signal properties (continued)
Name
Function
1
Pad
Config.
Register
(PCR)2
Pin No.
PCR PA I/O
Field3 Type
Voltage4 /
Pad Type
Reset
State5
Function / State
After Reset6
144
LQFP
176
LQFP
208 MAPB
GA
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
eTPU_A[7]
eTPU_A[19]
DSPI_B_SOUT_LVDSeTPU_A[6]
GPIO[121]
eTPU_A Ch.
eTPU_A Ch.
DSPI_B Data Output LVDSeTPU_A Ch.
GPIO
PCR[121]
0001
0010
0100
1000
0000
I/O
O
O
O
I/O
VDDEH1b
Slow
– / WKPCFG
– / WKPCFG
43
52
K3
eTPU_A[8]
eTPU_A[20]
DSPI_B_SOUT_LVDS+
GPIO[122]
eTPU_A Ch.
eTPU_A Ch.
DSPI_B Data Output LVDS+
GPIO
PCR[122]
001
010
100
000
I/O
O
O
I/O
VDDEH1b
Slow
– / WKPCFG
– / WKPCFG
42
51
N1
eTPU_A[9]
eTPU_A[21]
GPIO[123]
eTPU_A Ch.
eTPU_A Ch.
GPIO
PCR[123]
01
10
00
I/O
O
I/O
VDDEH1b
Slow
– / WKPCFG
– / WKPCFG
41
50
M2
eTPU_A[10]
eTPU_A[22]
GPIO[124]
eTPU_A Ch.
eTPU_A Ch.
GPIO
PCR[124]
01
10
00
I/O
O
I/O
VDDEH1b
Slow
– / WKPCFG
– / WKPCFG
40
49
M1
eTPU_A[11]
eTPU_A[23]
GPIO[125]
eTPU_A Ch.
eTPU_A Ch.
GPIO
PCR[125]
01
10
00
I/O
O
I/O
VDDEH1b
Slow
– / WKPCFG
– / WKPCFG
39
48
L2
eTPU_A[12]
DSPI_B_PCS[1]
GPIO[126]
eTPU_A Ch.
DSPI_B Periph Chip Select
GPIO
PCR[126]
01
10
00
I/O
O
I/O
VDDEH1b
Medium
– / WKPCFG
– / WKPCFG
38
47
L1
eTPU_A[13]
DSPI_B_PCS[3]
GPIO[127]
eTPU_A Ch.
DSPI_B Periph Chip Select
GPIO
PCR[127]
01
10
00
I/O
O
I/O
VDDEH1b
Medium
– / WKPCFG
– / WKPCFG
37
46
J4
eTPU_A[14]
DSPI_B_PCS[4]
eTPU_A[9]
GPIO[128]
eTPU_A Ch.
DSPI_B Periph Chip Select
eTPU_A Ch.
GPIO
PCR[128]
001
010
100
000
I/O
O
O
I/O
VDDEH1b
Medium
– / WKPCFG
– / WKPCFG
35
42
J3
eTPU_A[15]
DSPI_B_PCS[5]
GPIO[129]
eTPU_A Ch.
DSPI_B Periph Chip Select
GPIO
PCR[129]
01
10
00
I/O
O
I/O
VDDEH1b
Medium
– / WKPCFG
– / WKPCFG
33
40
K2
eTPU_A[16]
GPIO[130]
eTPU_A Ch.
GPIO
PCR[130]
01
00
I/O
I/O
VDDEH1b
Slow
– / WKPCFG
– / WKPCFG
32
39
K1
eTPU_A[17]
GPIO[131]
eTPU_A Ch.
GPIO
PCR[131]
01
00
I/O
I/O
VDDEH1b
Slow
– / WKPCFG
– / WKPCFG
31
38
H3
Freescale Semiconductor
Table 3. MPC563xM signal properties (continued)
Name
Function
1
Pad
Config.
Register
(PCR)2
Pin No.
PCR PA I/O
Field3 Type
Voltage4 /
Pad Type
Reset
State5
Function / State
After Reset6
144
LQFP
176
LQFP
208 MAPB
GA
MPC5644A Microcontroller Data Sheet, Rev. 8
eTPU_A[18]
GPIO[132]
eTPU_A Ch.
GPIO
PCR[132]
01
00
I/O
I/O
VDDEH1b
Slow
– / WKPCFG
– / WKPCFG
30
37
H4
eTPU_A[19]
GPIO[133]
eTPU_A Ch.
GPIO
PCR[133]
01
00
I/O
I/O
VDDEH1b
Slow
– / WKPCFG
– / WKPCFG
29
36
J2
eTPU_A[20]
IRQ[8]
GPIO[134]
eTPU_A Ch.
External Interrupt Request
GPIO
PCR[134]
01
10
00
I/O
I
I/O
VDDEH1b
Slow
– / WKPCFG
– / WKPCFG
28
35
J1
eTPU_A[21]
IRQ[9]
GPIO[135]
eTPU_A Ch.
External Interrupt Request
GPIO
PCR[135]
01
10
00
I/O
I
I/O
VDDEH1a
Slow
– / WKPCFG
– / WKPCFG
27
34
G4
eTPU_A[22]
IRQ[10]
eTPU_A[17]
GPIO[136]
eTPU_A Ch.
External Interrupt Request
eTPU_A Ch. External
GPIO
PCR[136]
001
010
100
000
I/O
I
O
I/O
VDDEH1a
Slow
– / WKPCFG
– / WKPCFG
25
32
H2
eTPU_A[23]
IRQ[11]
eTPU_A[21]
GPIO[137]
eTPU_A Ch.
External Interrupt Request
eTPU_A Ch. External
GPIO
PCR[137]
001
010
100
000
I/O
I
O
I/O
VDDEH1a
Slow
– / WKPCFG
– / WKPCFG
23
30
H1
eTPU_A[24]26
IRQ[12]
DSPI_C_SCK_LVDSGPIO[138]
eTPU_A Ch.
External Interrupt Request
DSPI_C Clock LVDSGPIO
PCR[138]
001
010
100
000
I/O
I
O
I/O
VDDEH1a
Slow
– / WKPCFG
– / WKPCFG
21
28
G1
eTPU_A[25]26
IRQ[13]
DSPI_C_SCK_LVDS+
GPIO[139]
eTPU_A Ch.
External Interrupt Request
DSPI _C Clock LVDS+
GPIO
PCR[139]
001
010
100
000
I/O
I
O
I/O
VDDEH1a
Medium
– / WKPCFG
– / WKPCFG
20
27
G3
eTPU_A[26]26
IRQ[14]
DSPI_C_SOUT_LVDSGPIO[140]
eTPU_A Ch.
External Interrupt Request
DSPI_C Data Output LVDSGPIO
PCR[140]
001
010
100
000
I/O
I
O
I/O
VDDEH1a
Slow
– / WKPCFG
– / WKPCFG
19
26
F3
eTPU_A[27]26
IRQ[15]
DSPI_C_SOUT_LVDS+
DSPI_B_SOUT
GPIO[141]
PCR[141]
eTPU_A Ch.
External Interrupt Request
DSPI_C Data Output LVDS+
DSPI_B Data Output
GPIO
0001
0010
0100
1000
0000
I/O
I
O
O
I/O
VDDEH1a
Slow
– / WKPCFG
– / WKPCFG
18
25
G2
53
54
Table 3. MPC563xM signal properties (continued)
Name
Function
1
Pad
Config.
Register
(PCR)2
Pin No.
PCR PA I/O
Field3 Type
Voltage4 /
Pad Type
Reset
State5
Function / State
After Reset6
144
LQFP
176
LQFP
208 MAPB
GA
MPC5634M Microcontroller Data Sheet, Rev. 8
eTPU_A[28]26
DSPI_C_PCS[1]
GPIO[142]
eTPU_A Ch. (Output Only)
DSPI_C Periph Chip Select
GPIO
PCR[142]
10
01
00
I/O
O
I/O
VDDEH1a
Medium
– / WKPCFG
– / WKPCFG
17
24
F1
eTPU_A[29]26
DSPI_C_PCS[2]
GPIO[143]
eTPU_A Ch. (Output Only)
DSPI_C Periph Chip Select
GPIO
PCR[143]
10
01
00
I/O
O
I/O
VDDEH1a
Medium
– / WKPCFG
– / WKPCFG
16
23
F2
eTPU_A[30]
DSPI_C_PCS[3]
eTPU_A[11]
GPIO[144]
eTPU_A Ch.
DSPI_C Periph Chip Select
eTPU_A Ch.
GPIO
PCR[144]
011
010
001
000
I/O
O
O
I/O
VDDEH1a
Medium
– / WKPCFG
– / WKPCFG
15
22
E1
eTPU_A[31]
DSPI_C_PCS[4]
eTPU_A[13]
GPIO[145]
eTPU_A Ch.
DSPI_C Periph Chip Select
eTPU_A Ch.
GPIO
PCR[145]
011
010
001
000
I/O
O
O
I/O
VDDEH1a
Medium
– / WKPCFG
– / WKPCFG
14
21
E2
eMIOS
Freescale Semiconductor
eMIOS[0]
eTPU_A[0]
eTPU_A[25]27
GPIO[179]
eMIOS Ch.
eTPU_A Ch.
eTPU_A Ch.
GPIO
PCR[179]
001
010
100
000
I/O
O
O
I/O
VDDEH1b
Slow
– / WKPCFG
– / WKPCFG
54
63
T4
eMIOS[1]
eTPU_A[1]
GPIO[180]
eMIOS Ch.
eTPU_A Ch.
GPIO
PCR[180]
01
10
00
I/O
O
I/O
VDDEH1b
Slow
– / WKPCFG
– / WKPCFG
—
647
T58
eMIOS[2]
eTPU_A[2]
GPIO[181]
eMIOS Ch.
eTPU_A Ch.
GPIO
PCR[181]
01
10
00
I/O
O
I/O
VDDEH1b
Slow
– / WKPCFG
– / WKPCFG
55
65
N7
eMIOS[4]
eTPU_A[4]
GPIO[183]
eMIOS Ch.
eTPU_A Ch.
GPIO
PCR[183]
01
10
00
I/O
O
I/O
VDDEH6a
Slow
– / WKPCFG
– / WKPCFG
56
67
R5
eMIOS[8]
eTPU_A[8]28
SCI_B_TX
GPIO[187]
eMIOS Ch.
eTPU_A Ch.
eSCI_B Transmit
GPIO
PCR[187]
001
010
100
000
I/O
O
O
I/O
VDDEH6a
Slow
– / WKPCFG
– / WKPCFG
57
70
P8
eMIOS[9]
eTPU_A[9]28
SCI_B_RX
GPIO[188]
eMIOS Ch.
eTPU_A Ch.
eSCI_B Receive
GPIO
PCR[188]
001
010
100
000
I/O
O
I
I/O
VDDEH6a
Slow
– / WKPCFG
– / WKPCFG
58
71
R7
Freescale Semiconductor
Table 3. MPC563xM signal properties (continued)
Name
Function
1
Pad
Config.
Register
(PCR)2
Pin No.
PCR PA I/O
Field3 Type
Voltage4 /
Pad Type
Reset
State5
Function / State
After Reset6
144
LQFP
176
LQFP
208 MAPB
GA
MPC5644A Microcontroller Data Sheet, Rev. 8
eMIOS[10]
GPIO[189]
eMIOS Ch.
GPIO
PCR[189]
01
00
I/O
I/O
VDDEH6a
Slow
– / WKPCFG
– / WKPCFG
60
73
N8
eMIOS[11]
GPIO[190]
eMIOS Ch.
GPIO
PCR[190]
01
00
I/O
I/O
VDDEH6a
Slow
– / WKPCFG
– / WKPCFG
62
75
R8
eMIOS[12]29
DSPI_C_SOUT
eTPU_A[27]
GPIO[191]
eMIOS Ch.
DSPI C Data Output
eTPU_A Ch.
GPIO
PCR[191]
001
010
100
000
I/O
O
O
I/O
VDDEH6a
Medium
– / WKPCFG
– / WKPCFG
63
76
N10
eMIOS[13]
GPIO[192]
eMIOS Ch.
GPIO
PCR[192]
01
00
I/O
I/O
VDDEH6a
– / WKPCFG
– / WKPCFG
—
777
T88
eMIOS[14]
IRQ[0]
eTPU_A[29]
GPIO[193]
eMIOS Ch.
External Interrupt Request
eTPU_A Ch.
GPIO
PCR[193]
001
010
100
000
O
I
O
I/O
VDDEH6a
Slow
– / WKPCFG
– / WKPCFG
64
78
R9
eMIOS[15]
IRQ[1]
GPIO[194]
eMIOS Ch.
External Interrupt Request
GPIO
PCR[194]
01
10
00
O
I
I/O
VDDEH6a
Slow
– / WKPCFG
– / WKPCFG
—
797
T98
eMIOS[23]
GPIO[202]
eMIOS Ch.
GPIO
PCR[202]
01
00
I/O
I/O
VDDEH6a
Slow
– / WKPCFG
– / WKPCFG
65
80
R11
O/–
XTAL30 / –
76
93
P16
75
92
N16
Clock Synthesizer
XTAL
Crystal Oscillator Output
EXTAL
EXTCLK
Crystal Oscillator Input
External Clock Input
CLKOUT
System Clock Output
—
—
PCR[229]
—
O
VDDEH6a
EXTAL31/
—
I
VDDEH6a
I/–
–
—
O
VDDE5
Fast
CLKOUT /
Enabled
CLKOUT /
Enabled
—
—
T14
Power / Ground
55
VDDPLL
PLL Supply Voltage
—
—
I
VDDPLL
(1.2 V)
I/–
—
74
91
R16
VSSPLL32
PLL Ground
—
—
I
VSSPLL
I/–
—
77
94
M16
VSTBY
Power Supply for Standby
RAM
—
—
I
VSTBY
I/–
—
12
12
C1
VRC33
3.3 V Voltage Regulator
Bypass Capacitor
—
—
O
VRC33
O/–
—
13
13
A15, D1,
N6, N12
56
Table 3. MPC563xM signal properties (continued)
Name
Function
1
Pad
Config.
Register
(PCR)2
Pin No.
PCR PA I/O
Field3 Type
Voltage4 /
Pad Type
Reset
State5
Function / State
After Reset6
144
LQFP
176
LQFP
208 MAPB
GA
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
VRCCTL
Voltage Regulator Control
Output
—
—
O
NA
O/–
—
11
11
N14
VDDA33
Analog Power Input for
eQADC
—
—
I
VDDA (5.0 V)
I/–
—
6
6
—
VDDA0
Analog Power Input for
eQADC
—
—
I
VDDA
I/–
—
—
—
B11
VSSA0
Analog Ground Input for
eQADC
—
—
I
VSSA
I/–
—
—
—
A11
VDDA1
Analog Power Input for
eQADC
—
—
I
VDDA
I/–
—
—
—
A4
VSSA1
Analog Ground Input for
eQADC
—
—
I
VSSA
I/–
—
—
—
A5
VSSA34
Analog Ground Input for
eQADC
—
—
I
VSSA
I/–
—
7
7
—
VDDREG
Voltage Regulator Supply
—
—
I
VDDREG
(5.0 V)
I/–
—
10
10
K16
VDD
Internal Logic Supply Input
—
—
I
VDD (1.2 V)
I/–
—
26, 53, 33, 62, B1, B16, C2,
86, 120 103, D3, E4, N5,
149 P4, P13, R3,
R14, T2,
T15
VSS
Ground
—
—
–
VSS0
I/–
—
22, 36, 15, 29, A1, A16, B2,
48, 59, 43, 57,
B15, C3,
73, 79, 72, 90,
C14, D4,
96,
91,
D13, G7,
108,
104,
G8, G9,
1157,
115
G10, H7,
H8, H9,
127,
133, H10, J7, J8,
140 J9, J10, K7,
K8, K9, K10,
N4, N13,
P3, P14, R2,
R15, T1,
T16
VDDEH1A35
VDDEH1B35
I/O Supply Input
—
—
I
VDDEH136
(3.3–5.0 V)
I/–
—
24, 34,
46
31, 41
55
K4
Freescale Semiconductor
Table 3. MPC563xM signal properties (continued)
Name
Function
1
Pad
Config.
Register
(PCR)2
Pin No.
PCR PA I/O
Field3 Type
Voltage4 /
Pad Type
Reset
State5
Function / State
After Reset6
144
LQFP
176
LQFP
208 MAPB
GA
—
—
T13
VDDE5
I/O Supply Input
—
—
I
VDDE5
I/–
—
VDDEH6a37, 38
I/O Supply Input
—
—
I
VDDEH6
(3.3–5.0V)
I/–
—
VDDEH6
I/O Supply Input
—
—
I
I/–
—
—
—
F13
VDDEH7
I/O Supply Input
—
—
I
VDDEH739
(3.3–5.0 V)
I/–
—
102,
113
125,
138
D12
VDDE740
I/O Supply Input
—
—
I
VDDE7
(3.3 V)
I/–
—
—
16,
1197
E13, P6
VDDEH6b38
MPC5644A Microcontroller Data Sheet, Rev. 8
1
VDDEH6
78, 93,
95,
61
110, 74
—
For each pin in the table, each line in the Function column is a separate function of the pin. For all I/O pins the selection of primary pin function or secondary
function or GPIO is done in the SIU except where explicitly noted.
2 Values in this column refer to registers in the System Integration Unit (SIU). The actual register name is “SIU_PCR” suffixed by the PCR number. For example,
PCR[190] refers to the SIU register named SIU_PCR190.
3 The Pad Configuration Register (PCR) PA field is used by software to select pin function.
4 The VDDE and VDDEH supply inputs are broken into segments. Each segment of slow I/O pins (VDDEH) may have a separate supply in the 3.3 V to 5.0 V
range (–10%/+5%). Each segment of fast I/O (VDDE) may have a separate supply in the 1.8 V to 3.3 V range (+/– 10%).
5 Terminology is O - output, I - input, Up - weak pull up enabled, Down - weak pull down enabled, Low - output driven low, High - output driven high. A dash
for the function in this column denotes that both the input and output buffer are turned off.
6 Function after reset of GPI is general purpose input. A dash for the function in this column denotes that both the input and output buffer are turned off.
7 Not available on 1 MB version of 176-pin package.
8 Not available on 1 MB version of 208-pin package.
9 The GPIO functions on GPIO[206] and GPIO[207] can be selected as trigger functions in the SIU for the ADC by making the proper selections in the
SIU_ETISR and SIU_ISEL3 registers in the SIU.
10 Some signals in this section are available only on calibration package.
11 These pins are only available in the 496 CSP/MAPBGA calibration/development package.
12 On the calibration package, the Nexus function on this pin is enabled when the NEXUSCFG pin is high and Nexus is configured to full port mode. On the
176-pin and 208-pin packages, the Nexus function on this pin is enabled permanently.
13 In the calibration package, the I/O segment containing this pin is called VDDE12.
14 208-ball BGA package only
15 When configured as Nexus (208-pin package or calibration package with NEXUSCFG=1), and JCOMP is asserted during reset, MDO[0] is driven high until
the crystal oscillator becomes stable, at which time it is then negated.
16 The function of this pin is Nexus when NEXUSCFG is high.
17
High when the pin is configured to Nexus, low otherwise.
18 O/Low for the calibration with NEXUSCFG=0; I/Up otherwise.
57
58
19 ALT_ADDR/Low
for the calibration package with NEXUSCFG=0; EVTI/Up otherwise.
176-pin and 208-pin packages, the Nexus function is disabled and the pin/ball has the secondary function
21
This signal is not available in the 176-pin and 208-pin packages.
22 The primary function is not selected via the PA field when the pin is a Nexus signal. Instead, it is activated by the Nexus controller.
23 TDI and TDO are required for JTAG operation.
24
The primary function is not selected via the PA field when the pin is a JTAG signal. Instead, it is activated by the JTAG controller.
25 The function and state of the CAN_A and eSCI_A pins after execution of the BAM program is determined by the BOOTCFG1 pin.
26 ETPUA[24:29] are input and output. The input muxing is controlled by SIU_ISEL8 register.
27 eTPU_A[25] is an output only function.
28 Only the output channels of eTPU[8:9] are connected to pins.
29 Only the output of eMIOS[12] is connected to the pin. The DSPI_C_SOUT is not available in this device.
30 The function after reset of the XTAL pin is determined by the value of the signal on the PLLCFG[1] pin. When bypass mode is chosen XTAL has no function
and should be grounded.
31 The function after reset of the EXTAL_EXTCLK pin is determined by the value of the signal on the PLLCFG[1] pin. If the EXTCLK function is chosen, the
valid operating voltage for the pin is 1.62 V to 3.6 V. If the EXTAL function is chosen, the valid operating voltage is 3.3 V.
32 VSSPLL and VSSREG are connected to the same pin.
33 This pin is shared by two pads: VDDA_AN, using pad_vdde_hv, and VDDA_DIG, using pad_vdde_int_hv.
34 This pin is shared by two pads: VSSA_AN, using pad_vsse_hv, and VSSA_DIG, using pad_vsse_int_hv.
35 VDDEH1A, VDDEH1B, and VDDEH1AB are shorted together in all production packages. The separation of the signal names is present to support legacy
naming, however they should be considered as the same signal in this document.
36 LVDS pins will not work at 3.3 V.
37 The VDDEH6 segment may be powered from 3.0 V to 5.0 V for mux address or SSI functions, but must meet the VDDA specifications of 4.5 V to 5.25 V for
analog input function.
38 VDDEH6A and VDDEH6B are shorted together in all production packages. The separation of the signal names is present to support legacy naming, however
they should be considered as the same signal in this document.
39 If using JTAG or Nexus, the I/O segment that contains the JTAG and Nexus pins must be powered by a 5 V supply. The 3.3 V Nexus/JTAG signals are derived
from the 5 volt power supply.
40 In the calibration package this signal is named VDDE12.
20 In
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
Table 4. Pad types
Pad Type
Name
Supply Voltage
Slow
pad_ssr_hv
3.0 V – 5.25 V
Medium
pad_msr_hv
3.0 V – 5.25 V
Fast
pad_fc
3.0 V – 3.6 V
MultiV
pad_multv_hv
3.0 V - 5.25 V (high swing mode)
4.5 V - 5.25 V (low swing mode)
Analog
pad_ae_hv
0.0 - 5.25 V
LVDS
pad_lo_lv
—
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
59
3.7
Signal details
Table 5 contains details on the multiplexed signals that appear in Table 3, “MPC563xM signal properties”.
Table 5. Signal details
Signal
Module or Function
Description
CLKOUT
Clock Generation
MPC5634M clock output for the external/calibration bus interface
EXTAL
Clock Generation
Input pin for an external crystal oscillator or an external clock
source based on the value driven on the PLLREF pin at reset.
EXTCLK
Clock Generation
External clock input
PLLREF
Clock Generation
PLLREF is used to select whether the oscillator operates in xtal
mode or external reference mode from reset. PLLREF=0 selects
external reference mode.
XTAL
Clock Generation
Crystal oscillator input
SCK_B_LVDS–
SCK_B_LVDS+
DSPI
LVDS pair used for DSPI_B TSB mode transmission
SOUT_B_LVDS–
SOUT_B_LVDS+
DSPI
LVDS pair used for DSPI_B TSB mode transmission
SCK_C_LVDS–
SCK_C_LVDS+
DSPI
LVDS pair used for DSPI_C TSB mode transmission
SOUT_C_LVDS–
SOUT_C_LVDS+
DSPI
LVDS pair used for DSPI_C TSB mode transmission
PCS_B[0]
PCS_C[0]
DSPI_B – DSPI_C
Peripheral chip select when device is in master mode—slave
select when used in slave mode
PCS_B[1:5]
PCS_C[1:5]
DSPI_B – DSPI_C
Peripheral chip select when device is in master mode—not used
in slave mode
SCK_B
SCK_C
DSPI_B – DSPI_C
DSPI clock—output when device is in master mode; input when
in slave mode
SIN_B
SIN_C
DSPI_B – DSPI_C
DSPI data in
SOUT_B
SOUT_C
DSPI_B – DSPI_C
DSPI data out
CAL_ADDR[12:30]
Calibration Bus
The CAL_ADDR[12:30] signals specify the physical address of
the bus transaction.
CAL_CS[0:3]
Calibration Bus
CSx is asserted by the master to indicate that this transaction is
targeted for a particular memory bank on the Primary external
bus.
CAL_DATA[0:15]
Calibration Bus
The CAL_DATA[0:15] signals contain the data to be transferred
for the current transaction.
CAL_OE
Calibration Bus
OE is used to indicate when an external memory is permitted to
drive back read data. External memories must have their data
output buffers off when OE is negated. OE is only asserted for
chip-select accesses.
CAL_RD_WR
Calibration Bus
RD_WR indicates whether the current transaction is a read
access or a write access.
MPC5634M Microcontroller Data Sheet, Rev. 8
60
Freescale Semiconductor
Table 5. Signal details (continued)
Signal
CAL_TS_ALE
Module or Function
Calibration Bus
Description
The Transfer Start signal (TS) is asserted by the MPC5634M to
indicate the start of a transfer.
The Address Latch Enable (ALE) signal is used to demultiplex
the address from the data bus.
CAL_EVTO
Calibration Bus
Nexus Event Out
CAL_MCKO
Calibration Bus
Nexus Message Clock Out
NEXUSCFG
Nexus/Calibration Bus
Nexus/Calibration Bus selector
eMIOS[0:23]
eMIOS
eMIOS I/O channels
AN[0:39]
eQADC
Single-ended analog inputs for analog-to-digital converter
FCK
eQADC
eQADC free running clock for eQADC SSI.
MA[0:2]
eQADC
These three control bits are output to enable the selection for an
external Analog Mux for expansion channels.
REFBYPC
eQADC
Bypass capacitor input
SDI
eQADC
Serial data in
SDO
eQADC
Serial data out
SDS
eQADC
Serial data select
VRH
eQADC
Voltage reference high input
VRL
eQADC
Voltage reference low input
SCI_A_RX
SCI_B_RX
eSCI_A – eSCI_B
eSCI receive
SCI_A_TX
SCI_B_TX
eSCI_A – eSCI_B
eSCI transmit
ETPU_A[0:31]
eTPU
eTPU I/O channel
CAN_A_TX
CAN_C_TX
FlexCan_A –
FlexCAN_C
FlexCAN transmit
CAN_A_RX
CAN_C_RX
FlexCAN_A –
FlexCAN_C
FlexCAN receive
JCOMP
JTAG
Enables the JTAG TAP controller.
TCK
JTAG
Clock input for the on-chip test and debug logic.
TDI
JTAG
Serial test instruction and data input for the on-chip test and
debug logic.
TDO
JTAG
Serial test data output for the on-chip test logic.
TMS
JTAG
Controls test mode operations for the on-chip test and debug
logic.
EVTI
Nexus
EVTI is an input that is read on the negation of RESET to enable
or disable the Nexus Debug port. After reset, the EVTI pin is
used to initiate program synchronization messages or generate
a breakpoint.
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
61
Table 5. Signal details (continued)
Signal
Module or Function
Description
EVTO
Nexus
Output that provides timing to a development tool for a single
watchpoint or breakpoint occurrence.
MCKO
Nexus
MCKO is a free running clock output to the development tools
which is used for timing of the MDO and MSEO signals.
MDO[3:0]
Nexus
Trace message output to development tools. This pin also
indicates the status of the crystal oscillator clock following a
power-on reset, when MDO[0] is driven high until the crystal
oscillator clock achieves stability and is then negated.
MSEO[1:0]
Nexus
Output pin—Indicates the start or end of the variable length
message on the MDO pins
BOOTCFG[1]
SIU – Configuration
The BOOTCFG1 pin is sampled during the assertion of the
RSTOUT signal, and the value is used to update the RSR and
the BAM boot mode
The following values are for BOOTCFG[0:1}:
0 Boot from internal flash memory
1 FlexCAN/eSCI boot
WKPCFG
SIU – Configuration
The WKPCFG pin is applied at the assertion of the internal reset
signal (assertion of RSTOUT), and is sampled 4 clock cycles
before the negation of the RSTOUT pin.
The value is used to configure whether the eTPU and eMIOS
pins are connected to internal weak pull up or weak pull down
devices after reset. The value latched on the WKPCFG pin at
reset is stored in the Reset Status Register (RSR), and is
updated for all reset sources except the Debug Port Reset and
Software External Reset.
0: Weak pulldown applied to eTPU and eMIOS pins at reset
1: Weak pullup applied to eTPU and eMIOS pins at reset.
ETRIG[2:3]
SIU – eQADC Triggers
External signal eTRIGx triggers eQADC CFIFOx
IRQ[0:15]
SIU – External
Interrupts
The IRQ[0:15] pins connect to the SIU IRQ inputs. IMUX Select
Register 1 is used to select the IRQ[0:15] pins as inputs to the
IRQs.
MPC5634M Microcontroller Data Sheet, Rev. 8
62
Freescale Semiconductor
Table 5. Signal details (continued)
Signal
Module or Function
Description
NMI
SIU – External
Interrupts
Non-Maskable Interrupt
GPIO[n]
SIU – GPIO
Configurable general purpose I/O pins. Each GPIO input and
output is separately controlled by an 8-bit input (GPDI) or output
(GPDO) register. Additionally, each GPIO pins is configured
using a dedicated SIU_PCR register.
The GPIO pins are generally multiplexed with other I/O pin
functions.
SIU – Reset
RESET
The RESET pin is an active low input. The RESET pin is
asserted by an external device during a power-on or external
reset. The internal reset signal asserts only if the RESET pin
asserts for 10 clock cycles. Assertion of the RESET pin while the
device is in reset causes the reset cycle to start over.
The RESET pin has a glitch detector which detects spikes
greater than two clock cycles in duration that fall below the switch
point of the input buffer logic of the VDDEH input pins. The switch
point lies between the maximum VIL and minimum VIH
specifications for the VDDEH input pins.
RSTOUT
SIU – Reset
The RSTOUT pin is an active low output that uses a push/pull
configuration. The RSTOUT pin is driven to the low state by the
MCU for all internal and external reset sources. There is a delay
between initiation of the reset and the assertion of the RSTOUT
pin.
Table 6 gives the power/ground segmentation of the MPC563x MCU. Each segment provides the power and ground for the
given set of I/O pins, and can be powered by any of the allowed voltages regardless of the power on the other segments.
.
Table 6. MPC563x Power/Ground Segmentation
Power
Segment
144-LQFP
Pin
Number
176-LQFP
Pin
Number
208-BGA
Pin
Number
Voltage
Range1
I/O Pins Powered
by Segment
VDDA0
6
6
B11
5.0 V
AN[0:7], AN[9], AN[11],
AN[16:18], AN[21:25],
AN[27:28], AN[30:37],
AN38, AN39, VRL,
REFBYPC,
VRH
VDDE5
—
—
T13
1.8 V –
3.3 V
CLKOUT
VDDEH1
(a,b)
24, 34
31, 41
K4
3.3 V –
5.0 V
PCKCFG[2],
eTPU_A[0:31],
eMIOS[0:2]
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
63
Table 6. MPC563x Power/Ground Segmentation (continued)
144-LQFP
Pin
Number
176-LQFP
Pin
Number
208-BGA
Pin
Number
VDDEH6
(a,b)
78, 93
95, 110
VDDEH72
102, 113
VDDE123
VDDE7
—
Power
Segment
Voltage
Range1
I/O Pins Powered
by Segment
F13
3.3 V –
5.0 V
RESET, RSTOUT,
WKPCFG, BOOTCFG1,
PLLREF, SCK_B,
PCKCFG[0],
CAN_A_TX, CAN_A_RX,
CAN_C_TX, CAN_C_RX,
SCI_A_TX, SCI_A_RX,
SCI_B_TX, SCI_B_RX,
SCK_B, SIN_B, SOUT_B,
DSPI_B_PCS_B[0:5],
eMIOS[4],
eMIOS[8:15], eMIOS[23],
XTAL, EXTAL
125, 138
D12
3.3 V –
5.0 V
PCKCFG[1],
MDO[0:3], EVTI, EVTO,
MCKO, MSEO[0:1], TDO,
TDI, TMS, TCK, JCOMP,
AN[12:15]
(GPIO[98:99],
GPIO[206:207])
16, 119
E13, P6
1.8 V –
3.3 V
CAL_ADDR[12:30],
CAL_DATA[0:15],
CAL_CS[0], CAL_CS[2:3],
CAL_RD_WR,
CAL_WE[0:1], CAL_OE,
CAL_TS, ALT_MCKO,
ALT_EVTO, NEXUSCFG
1
These are nominal voltages. All VDDE and VDDEH voltages are –5%, +10% (VDDE 1.62 V to 3.6 V,
VDDEH 3.0 V to 5.5 V). VDDA is +5%, –10%.
2 The VDDEH7 segment may be powered from 3.0 V to 5.0 V for mux address or SSI functions, but must
meet the VDDA specifications of 4.5 V to 5.25 V for analog input function.
3
In the calibration package this signal is named VDDE12; it is named VDDE7 in all other packages.
,
MPC5634M Microcontroller Data Sheet, Rev. 8
64
Freescale Semiconductor
4
Electrical characteristics
This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing
specifications for the MPC5634M series of MCUs.
The electrical specifications are preliminary and are from previous designs, design simulations, or initial evaluation. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however for production silicon
these specifications will be met. Finalized specifications will be published after complete characterization and device
qualifications have been completed.
In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller
Characteristics is included in the Symbol column.
In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol
“SR” for System Requirement is included in the Symbol column.
4.1
Parameter classification
The electrical parameters shown in this document are guaranteed by various methods. To provide a better understanding, the
classifications listed in Table 7 are used and the parameters are tagged accordingly in the tables. Note that only controller
characteristics (“CC”) are classified. System requirements (“SR”) are operating conditions that must be provided to ensure
normal device operation.
Table 7. Parameter classifications
Classification tag
Tag description
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a statistically
relevant sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical
devices under typical conditions unless otherwise noted. All values shown in the typical column
are within this category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
4.2
Maximum ratings
Table 8. Absolute maximum ratings1
Value
Symbol
VDD
VFLASH
Parameter
SR
SR
Conditions
1.2 V core supply voltage2
Flash core
voltage3,4
5
Unit
min
max
– 0.3
1.32
V
– 0.3
3.6
V
VSTBY
SR
SRAM standby voltage
– 0.3
5.5
V
VDDPLL
SR
Clock synthesizer voltage
– 0.3
1.32
V
VRC336
SR
Voltage regulator control
input voltage4
– 0.3
3.6
V
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
65
Table 8. Absolute maximum ratings1 (continued)
Value
Symbol
VDDA
1
2
3
4
5
6
7
Parameter
SR
Analog supply voltage5
Conditions
max
– 0.3
5.5
V
– 0.3
3.6
V
– 0.3
5.5
V
VDDEH powered I/O
pads
–1.09
VDDEH + 0.3 V10
V
VDDE powered I/O pads
–1.010
VDDE + 0.3 V11
VDDA powered I/O pads
–1.0
VDDA + 0.3 V
– 0.3
5.5
V
– 0.3
5.5
V
– 0.1
0.1
V
– 0.3
5.5
V
Reference to VSSA
4,7
VDDE
SR
I/O supply voltage
VDDEH
SR
I/O supply voltage5
VIN
SR
DC input voltage8
VDDREG
SR
Voltage regulator supply
voltage6
VRH
SR
Analog reference high
voltage
VSS – VSSA
SR
VSS differential voltage
Unit
min
Reference to VRL
voltage6
VRH – VRL
SR
VREF differential
VRL – VSSA
SR
VRL to VSSA differential
voltage
– 0.3
0.3
V
VSSPLL – VSS
SR
VSSPLL to VSS differential
voltage
– 0.1
0.1
V
IMAXD
SR
Maximum DC digital input
current12
Per pin, applies to all
digital pins
–3
3
mA
IMAXA
SR
Maximum DC analog input
current13
Per pin, applies to all
analog pins
—
5
mA
TJ
SR
Maximum operating
temperature range14 – die
junction temperature
– 40.0
150.0
oC
TSTG
SR
Storage temperature range
– 55.0
150.0
oC
TSDR
SR
Maximum solder
temperature15
—
260.0
oC
MSL
SR
Moisture sensitivity level16
—
3
—
Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress
ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect
device reliability or cause permanent damage to the device.
Allowed 2 V for 10 hours cumulative time, remaining time at 1.2 V +10%.
The VFLASH supply is connected to VRC33 in the package substrate. This specification applies to calibration package
devices only.
Allowed 5.3 V for 10 hours cumulative time, remaining time at 3.3 V +10%.
Allowed 6.8 V for 10 hours cumulative time, remaining time at 5 V +10%.
The pin named as VRC33 is internally connected to the pads VFLASH and VRC33 in the 144 LQFP package. These
limits apply when the internal regulator is disabled and VRC33 power is supplied externally.
All functional non-supply I/O pins are clamped to VSS and VDDE, or VDDEH.
MPC5634M Microcontroller Data Sheet, Rev. 8
66
Freescale Semiconductor
8
AC signal overshoot and undershoot of up to 2.0 V of the input voltages is permitted for an accumulative duration of
60 hours over the complete lifetime of the device (injection current not limited for this duration).
9
Internal structures hold the voltage greater than –1.0 V if the injection current limit of 2 mA is met.
10
Internal structures hold the input voltage less than the maximum voltage on all pads powered by VDDEH supplies, if
the maximum injection current specification is met (2 mA for all pins) and VDDEH is within the operating voltage
specifications.
11
Internal structures hold the input voltage less than the maximum voltage on all pads powered by VDDE supplies, if the
maximum injection current specification is met (2 mA for all pins) and VDDE is within the operating voltage
specifications.
12
Total injection current for all pins (including both digital and analog) must not exceed 25 mA.
13
Total injection current for all analog input pins must not exceed 15 mA.
14
Lifetime operation at these specification limits is not guaranteed.
15
Solder profile per CDF-AEC-Q100.
16
Moisture sensitivity per JEDEC test method A112.
4.3
Thermal characteristics
Table 9. Thermal characteristics for 144-pin LQFP
Symbol
C
Parameter
Conditions
Value
Unit
Single layer board – 1s
43
°C/W
Four layer board – 2s2p
35
°C/W
CC
D Junction-to-Ambient, Natural Convection1
RJA
CC
D Junction-to-Ambient, Natural
Convection2
RJMA
CC
D Junction-to-Ambient (@200 ft/min)2
Single layer board –1s
34
°C/W
RJMA
CC
D Junction-to-Ambient (@200 ft/min)2
Four layer board – 2s2p
29
°C/W
22
°C/W
8
°C/W
2
°C/W
RJA
RJB
CC
D
Junction-to-Board2
(Top)3
RJCtop
CC
D Junction-to-Case
JT
CC
D Junction-to-Package Top, Natural
Convection4
1
Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board
meets JEDEC specification for this package.
2 Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package.
3
Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
4
Thermal characterization parameter indicating the temperature difference between the package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JT.
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
67
Table 10. Thermal characteristics for 176-pin LQFP1
Symbol
C
Parameter
Conditions
2
RJA
CC
D Junction-to-Ambient, Natural Convection
RJA
CC
D Junction-to-Ambient, Natural Convection2
2
RJMA
CC
D Junction-to-Moving-Air, Ambient
RJMA
CC
D Junction-to-Moving-Air, Ambient2
RJB
CC
D Junction-to-Board3
Value
Unit
Single layer board - 1s
38
°C/W
Four layer board - 2s2p
31
°C/W
@200 ft./min., single layer
board - 1s
30
°C/W
@200 ft./min., four layer
board - 2s2p
25
°C/W
20
°C/W
4
RJCtop
CC
D Junction-to-Case
5
°C/W
JT
CC
D Junction-to-Package Top, Natural
Convection5
2
°C/W
1
Thermal characteristics are targets based on simulation that are subject to change per device characterization.
Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board
meets JEDEC specification for this package.
3 Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package.
4 Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
5
Thermal characterization parameter indicating the temperature difference between the package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JT.
2
Table 11. Thermal characteristics for 208-pin MAPBGA1
Symbol
RJA
RJMA
RJA
3
4
5
6
Conditions
Value
Unit
CC
D Junction-to-ambient, natural convection2,3
One layer board - 1s
39
°C/W
CC
D Junction-to-ambient natural
convection2,4
Four layer board - 2s2p
24
°C/W
D Junction-to-ambient (@200
ft/min)2,4
Single layer board
31
°C/W
ft/min)2,4
Four layer board 2s2p
20
°C/W
Four layer board - 2s2p
13
°C/W
6
°C/W
2
°C/W
CC
CC
D Junction-to-ambient (@200
RJB
CC
D Junction-to-board5
JT
2
Parameter
RJMA
RJC
1
C
CC
CC
D Junction-to-case
6
D Junction-to-package top natural
convection7
Thermal characteristics are targets based on simulation that are subject to change per device characterization.
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate
method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.
MPC5634M Microcontroller Data Sheet, Rev. 8
68
Freescale Semiconductor
7
4.3.1
Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter
is written as Psi-JT.
General notes for specifications at maximum junction temperature
An estimation of the chip junction temperature, TJ, can be obtained from the equation:
TJ = TA + (RJA * PD)
Eqn. 1
where:
TA = ambient temperature for the package (oC)
RJA = junction-to-ambient thermal resistance (oC/W)
PD = power dissipation in the package (W)
The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for
estimations and comparisons. The difference between the values determined for the single-layer (1s) board compared to a
four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance
is not a constant. The thermal resistance depends on the:
•
•
•
•
Construction of the application board (number of planes)
Effective size of the board which cools the component
Quality of the thermal and electrical connections to the planes
Power dissipated by adjacent components
Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package
to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance
between the vias leave the planes virtually disconnected, the thermal performance is also greatly reduced.
As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit
board. The value obtained on a board with the internal planes is usually within the normal range if the application board has:
•
•
•
One oz. (35 micron nominal thickness) internal planes
Components are well separated
Overall power dissipation on the board is less than 0.02 W/cm2
The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the
ambient temperature varies widely within the application. For many natural convection and especially closed box applications,
the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the
device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the
local ambient conditions that determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using the following equation:
TJ = TB + (RJB * PD)
Eqn. 2
where:
TB = board temperature for the package perimeter (oC)
RJB = junction-to-board thermal resistance (oC/W) per JESD51-8S
PD = power dissipation in the package (W)
When the heat loss from the package case to the air does not factor into the calculation, an acceptable value for the junction
temperature is predictable. Ensure the application board is similar to the thermal test condition, with the component soldered to
a board with internal planes.
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
69
The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal
resistance:
RJA = RJC + RCA
Eqn. 3
where:
RJA = junction-to-ambient thermal resistance (oC/W)
RJC = junction-to-case thermal resistance (oC/W)
RCA = case to ambient thermal resistance (oC/W)
RJC is device related and is not affected by other factors. The thermal environment can be controlled to change the
case-to-ambient thermal resistance, RCA. For example, change the air flow around the device, add a heat sink, change the
mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding
the device. This description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat
sink to ambient. For most packages, a better model is required.
A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the
junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a
substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the
thermal performance when most of the heat is conducted to the printed circuit board. This model can be used to generate simple
estimations and for computational fluid dynamics (CFD) thermal models.
To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization
parameter (JT) to determine the junction temperature by measuring the temperature at the top center of the package case using
the following equation:
TJ = TT + (JT x PD)
Eqn. 4
where:
TT = thermocouple temperature on top of the package (oC)
JT = thermal characterization parameter (oC/W)
PD = power dissipation in the package (W)
The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests
on the package. Place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from
the junction. Place the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling
effects of the thermocouple wire.
References:
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134
USA
(408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or
303-397-7956.
JEDEC specifications are available on the web at http://www.jedec.org.
•
•
C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine
Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.
G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applications”, Electronic
Packaging and Production, pp. 53-58, March 1998.
MPC5634M Microcontroller Data Sheet, Rev. 8
70
Freescale Semiconductor
•
B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application
in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
71
4.4
Electromagnetic Interference (EMI) characteristics
Table 12. EMI testing specifications1
Symbol
Radiated
Emissions
1
4.5
Parameter
VEME
Conditions
fOSC/fBUS
Frequency
Device
Oscillator
150 kHz – 50 MHz
Configuration, test
Frequency = 8
50–150 MHz
conditions and EM
MHz;
testing per standard
System Bus
150–500 MHz
IEC61967-2; Supply Frequency = 80
500–1000 MHz
Voltage = 5.0V DC,
MHz;
Ambient
No PLL Frequency
IEC Level
Temperature =
Modulation
25°C, Worst-case
Orientation
Oscillator
150 kHz – 50 MHz
Frequency = 8
50–150 MHz
MHz;
System Bus
150–500 MHz
Frequency = 80
500–1000 MHz
MHz;
1% PLL
IEC Level
Frequency
Modulation
Level
(Typ)
Unit
26
dBV
24
24
21
K
—
20
dBV
19
14
7
L
—
IEC Classification Level: L = 24dBuV; K = 30dBuV.
Electromagnetic static discharge (ESD) characteristics
Table 13. ESD ratings1,2
Symbol
Parameter
Conditions
Value
Unit
—
SR
ESD for Human Body Model (HBM)
—
2000
V
R1
SR
HBM circuit description
—
1500
C
SR
—
100
pF
—
SR
500
V
ESD for field induced charge Model (FCDM) All pins
Corner pins
—
—
SR
SR
Number of pulses per pin
Number of pulses
750
Positive pulses (HBM)
1
—
Negative pulses (HBM)
1
—
1
—
—
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated
Circuits.
2 Device failure is defined as: “If after exposure to ESD pulses, the device does not meet the device specification
requirements, which includes the complete DC parametric and functional testing at room temperature and hot
temperature.”
MPC5634M Microcontroller Data Sheet, Rev. 8
72
Freescale Semiconductor
4.6
Power Management Control (PMC) and Power On Reset (POR)
electrical specifications
Table 14. PMC Operating conditions and external regulators supply voltage
ID
1
Name
Jtemp
C
SR
Parameter
Min
— Junction temperature
Typ
Max
Unit
27
150
°C
–40
1
2
Vddreg
SR
— PMC 5 V supply voltage VDDREG
4.75
5
5.25
V
3
Vdd
SR
— Core supply voltage 1.2 V VDD when external
regulator is used without disabling the internal
regulator (PMC unit turned on, LVI monitor
active)2
1.263
1.3
1.32
V
3a
—
SR
— Core supply voltage 1.2 V VDD when external
regulator is used with a disabled internal
regulator (PMC unit turned-off, LVI monitor
disabled)
1.14
1.2
1.32
V
4
Ivdd
SR
— Voltage regulator core supply maximum DC
output current4
400
—
—
mA
5
Vdd33
SR
— Regulated 3.3 V supply voltage when external
regulator is used without disabling the internal
regulator (PMC unit turned-on, internal 3.3 V
regulator enabled, LVI
monitor active)5
3.3
3.45
3.6
V
5a
—
SR
— Regulated 3.3 V supply voltage when external
regulator is used with a disabled internal
regulator (PMC unit turned-off, LVI monitor
disabled)
3
3.3
3.6
V
6
—
SR
— Voltage regulator 3.3 V supply maximum
required DC output current
80
—
—
mA
1
During start up operation the minimum required voltage to come out of reset state is 4.6 V.
An internal regulator controller can be used to regulate core supply.
3
The minimum supply required for the part to exit reset and enter in normal run mode is 1.28 V.
4 The onchip regulator can support a minimum of 400 mA although the worst case core current is 180 mA.
5 An internal regulator can be used to regulate 3.3 V supply.
2
Table 15. PMC electrical characteristics
ID
Name
C
Parameter
CC C Nominal bandgap voltage
reference
Min
Typ
Max
Unit
—
1.219
—
V
Vbg–7%
Vbg
Vbg+6%
V
1
Vbg
1a
—
CC P Untrimmed bandgap
reference voltage
1b
—
CC P Trimmed bandgap
reference voltage (5 V,
27 °C)1
Vbg–10mV
Vbg
Vbg+10mV
V
1c
—
CC C Bandgap reference
temperature variation
—
100
—
ppm
/°C
Notes
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
73
Table 15. PMC electrical characteristics (continued)
ID
Name
C
Parameter
Min
Typ
Max
Unit
1d
—
CC C Bandgap reference supply
voltage variation
—
3000
—
ppm
/V
2
Vdd
CC C Nominal VDD core supply
internal regulator target
DC output voltage2
—
1.28
—
V
2a
—
CC P Nominal VDD core supply
internal regulator target DC
output voltage variation at
power-on reset
Vdd – 6%
Vdd
Vdd + 10%
V
2b
—
CC P Nominal VDD core supply
internal regulator target DC
output voltage variation
after power-on reset
Vdd – 103
Vdd
Vdd + 3%
V
2c
—
CC C Trimming step Vdd
—
20
—
mV
2d
Ivrcctl
CC C Voltage regulator controller
for core supply maximum
DC output current
20
—
—
mA
3
Lvi1p2
CC C Nominal LVI for rising core
supply4,5
—
1.160
—
V
3a
—
CC C Variation of LVI for rising
core supply at power-on
reset5,6
1.120
1.200
1.280
V
3b
—
CC C Variation of LVI for rising
Lvi1p2–3%
core supply after power-on
reset5,6
Lvi1p2
Lvi1p2+3%
V
3c
—
CC C Trimming step LVI core
supply5
—
20
—
mV
3d
Lvi1p2_h
CC C LVI core supply hysteresis5
—
40
—
mV
4
Por1.2V_r
CC C POR 1.2 V rising
—
0.709
—
V
4a
—
4b
Por1.2V_f
4c
—
CC C POR 1.2 V falling variation
5
Vdd33
CC C Nominal 3.3 V supply
internal regulator DC output
voltage
—
3.39
—
V
5a
—
CC P Nominal 3.3 V supply
internal regulator DC output
voltage variation at
power-on reset6
Vdd33 –
8.5%
Vdd33
Vdd3 + 7%
V
CC C POR 1.2 V rising variation
CC C POR 1.2 V falling
Por1.2V_r– Por1.2V_r Por1.2V_r+
35%
35%
—
0.638
—
Por1.2V_f– Por1.2V_f Por1.2V_f+
35%
35%
Notes
V
V
V
MPC5634M Microcontroller Data Sheet, Rev. 8
74
Freescale Semiconductor
Table 15. PMC electrical characteristics (continued)
ID
Name
C
Parameter
Min
Typ
Max
Unit
Vdd33 –
7.5%
Vdd33
Vdd33 +
7%
V
Notes
With internal
load up
to Idd3p3
5b
—
CC P Nominal 3.3 V supply
internal regulator DC output
voltage variation after
power-on reset
5c
—
CC D Voltage regulator 3.3 V
output impedance at
maximum DC load
—
—
2
5d
Idd3p3
CC P Voltage regulator 3.3 V
maximum DC output
current
80
—
—
mA
5e Vdd33 ILim6 CC C Voltage regulator 3.3 V DC
current limit
—
130
—
mA
6
Lvi3p3
—
3.090
—
V
The Lvi3p3
specs are also
valid for the
Vddeh LVI
6a
—
CC C Variation of LVI for rising
3.3 V supply at power-on
reset5
Lvi3p3–6%
Lvi3p3
Lvi3p3+6%
V
See note 7
6b
—
CC C Variation of LVI for rising
Lvi3p3–3%
3.3 V supply after power-on
reset5
Lvi3p3
Lvi3p3+3%
V
See note 7
6c
—
CC C Trimming step LVI 3.3 V5
—
20
—
mV
—
60
—
mV
—
2.07
—
V
CC C Nominal LVI for rising 3.3 V
supply5
5
6d
Lvi3p3_h
CC C LVI 3.3 V hysteresis
7
Por3.3V_r
CC C Nominal POR for rising
3.3 V supply
7a
—
7b
Por3.3V_f
7c
—
CC C Variation of POR for falling
3.3 V supply
8
Lvi5p0
CC C Nominal LVI for rising 5 V
VDDREG supply5
8a
—
8b
8c
CC C Variation of POR for rising
3.3 V supply
CC C Nominal POR for falling
3.3 V supply
Por3.3V_r– Por3.3V_r Por3.3V_r+
35%
35%
—
1.95
—
Por3.3V_f– Por3.3V_f Por3.3V_f+
35%
35%
—
V
V
V
4.290
—
V
CC C Variation of LVI for rising 5 V Lvi5p0–6%
VDDREG supply at
power-on reset5
Lvi5p0
Lvi5p0+6%
V
—
CC C Variation of LVI for rising 5 V Lvi5p0–3%
VDDREG supply power-on
reset5
Lvi5p0
Lvi5p0+3%
V
—
CC C Trimming step LVI 5 V5
20
—
mV
—
The 3.3 V POR
specs
are also valid
for the
Vddeh POR
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
75
Table 15. PMC electrical characteristics (continued)
ID
1
2
3
4
5
6
7
Name
C
Parameter
Min
Typ
Max
Unit
8d
Lvi5p0_h
CC C LVI 5 V hysteresis5
—
60
—
mV
9
Por5V_r
CC C Nominal POR for rising 5 V
VDDREG supply
—
2.67
—
V
9a
—
CC C Variation of POR for rising
5 V VDDREG supply
Por5V_r –
35%
Por5V_r
Por5V_r +
50%
V
9b
Por5V_f
CC C Nominal POR for falling 5 V
VDDREG supply
—
2.47
—
V
9c
—
CC C Variation of POR for falling
5 V VDDREG supply
Por5V_f –
35%
Por5V_f
Por5V_f +
50%
V
Notes
The limits will be reviewed after data collection from 3 different lots in a full production environment.
Using external ballast transistor.
Min range is extended to 10% since Lvi1p2 is reprogrammed from 1.2 V to 1.16 V after power-on reset.
LVI for falling supply is calculated as LVI rising - LVI hysteresis.
The internal voltage regulator can be disabled by tying the VDDREG pin to ground. When the internal voltage
regulator is disabled, the LVI specifications are not applicable because all LVI monitors are disabled. POR
specifications remain valid when the internal voltage regulator is disabled as long as VDDEH and VDD33 supplies
are within the required ranges.
This parameter is the “inrush” current of the internal 3.3 V regulator when it is turned on. This spec. is the current
at which the regulator will go into current limit mode.
Lvi3p3 tracks DC target variation of internal Vdd33 regulator. Minimum and maximum Lvi3p3 correspond to
minimum and maximum Vdd33 DC target respectively.
MPC5634M Microcontroller Data Sheet, Rev. 8
76
Freescale Semiconductor
4.6.1
Regulator example
Resistor may or may not be
required. It depends on the
allowable power dissipation
of the npn bypass transistor
device.
VDDREG
10 F
1.1–5.6
MCU
10 F
VRCCTL
15
Emitter and collector capacitors
(6.8 F and 10 F) should be
matched (same type) and ESR
should be lower than 200 m
VDD
680 nF
VSS
4 6.8 F
4 220 nF
Mandatory decoupling
Notes:
capacitor network
1. The VRCCTL capacitor is required.
2. The bypass transistor MUST be operated out of its saturation region.
Figure 7. Core voltage regulator controller external components preferred configuration
4.6.2
Recommended power transistors
The following NPN transistors are recommended for use with the on-chip voltage regulator controller: ON SemiconductorTM
BCP68T1 or NJD2873 as well as Philips SemiconductorTM BCP68. The collector of the external transistor is preferably
connected to the same voltage supply source as the output stage of the regulator.
Table 16. Recommended operating characteristics
Symbol
hFE ()
PD
Parameter
DC current gain (Beta)
Absolute minimum power dissipation
Value
Unit
60 – 550
—
>1.0
(1.5 preferred)
W
1.0
A
200–6001
mV
0.4–1.0
V
ICMaxDC Minimum peak collector current
VCESAT Collector-to-emitter saturation voltage
VBE
1
Base-to-emitter voltage
Adjust resistor at bipolar transistor collector for 3.3 V/5.0 V to avoid VCE < VCESAT
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
77
4.7
Power up/down sequencing
There is no power sequencing required among power sources during power up and power down, in order to operate within
specification but use of the following sequence is strongly recommended when the internal regulator is bypassed:
5 V 3.3 V and 1.2 V
This is also the normal sequence when the internal regulator is enabled.
Although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive current spikes, etc.,
the state of the I/O pins during power up/down varies according to table Table 17 for all pins with fast pads and Table 18 for all
pins with medium, slow and multi-voltage pads.1
Table 17. Power sequence pin states for fast pads
VDDE
VRC33
VDD
Fast (pad_fc)
LOW
X
X
LOW
VDDE
LOW
X
HIGH
VDDE
VRC33
LOW
HIGH IMPEDANCE
VDDE
VRC33
VDD
FUNCTIONAL
Table 18. Power sequence pin states for medium, slow and multi-voltage pads
VDDEH
VDD
Medium (pad_msr_hv)
Slow (pad_ssr_hv)
Multi-voltage (pad_multv_hv)
LOW
X
LOW
VDDEH
LOW
HIGH IMPEDANCE
VDDEH
VDD
FUNCTIONAL
1.If an external 3.3 V external regulator is used to supply current to the 1.2 V pass transistor and this supply also supplies current for the other 3.3 V supplies, then the 5V supply must always be greater than or equal to the external 3.3 V
supply.
MPC5634M Microcontroller Data Sheet, Rev. 8
78
Freescale Semiconductor
4.8
DC electrical specifications
Table 19. DC electrical specifications1
Value2
Symbol
VDD
C
SR
Parameter
Conditions
— Core supply voltage
—
Unit
min
typ
max
1.14
—
1.32
V
3
V
VDDE
SR
— I/O supply voltage
—
1.62
—
3.6
VDDEH
SR
— I/O supply voltage
—
3.0
—
5.25
V
VRC33
SR
— 3.3 V external voltage4
—
3.0
—
3.6
V
VDDA
SR
— Analog supply voltage
6
5
—
4.75
—
5.25
V
—
VSSA – 0.3
—
VDDA+0.3
V
VINDC
SR
— Analog input voltage
VSS – VSSA
SR
— VSS differential voltage
—
–100
—
100
mV
VRL
SR
— Analog reference low
voltage
—
VSSA
—
VSSA+0.1
V
VRL – VSSA
SR
— VRL differential voltage
—
–100
—
100
mV
VRH
SR
— Analog reference high
voltage
—
VDDA – 0.1
—
VDDA
V
VRH – VRL
SR
— VREF differential
voltage
—
4.75
—
5.25
V
VDDF
SR
— Flash operating
voltage 7
—
1.14
—
1.32
V
VFLASH8
SR
— Flash read voltage
—
3.0
—
3.6
V
VSTBY
SR
— SRAM standby voltage Unregulated
mode
0.95
—
1.2
V
2.0
—
5.5
Regulated
mode
VDDREG
SR
— Voltage regulator
supply voltage9
—
4.75
—
5.25
V
VDDPLL
SR
— Clock synthesizer
operating voltage
—
1.14
—
1.32
V
VSSPLL – VSS
SR
— VSSPLL to VSS
differential voltage
—
–100
—
100
mV
VIL_S
CC
C Slow/medium pad I/O
input low voltage
Hysteresis
enabled
VSS–0.3
—
0.35*VDDEH
V
P
hysteresis
disabled
VSS–0.3
—
0.40*VDDEH
C Fast pad I/O input low Hysteresis
voltage
enabled
VSS–0.3
—
0.35*VDDE
P
VSS–0.3
—
0.40*VDDE
VIL_F
CC
hysteresis
disabled
V
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
79
Table 19. DC electrical specifications1 (continued)
Value2
Symbol
VIL_LS
VIL_HS
VIH_S
VIH_F
VIH_LS
VIH_HS
C
CC
CC
CC
CC
CC
CC
Parameter
C
Conditions
Unit
min
typ
max
Multi-voltage pad I/O
input low voltage in
low-swing
P
mode10,11,12,13
Hysteresis
enabled
VSS–0.3
—
0.8
Hysteresis
disabled
VSS–0.3
—
1.1
C Multi-voltage pad I/O
input low voltage in
high-swing mode
P
Hysteresis
enabled
VSS–0.3
—
0.35 VDDEH
Hysteresis
disabled
VSS–0.3
—
0.4 VDDEH
C Slow/medium pad I/O
input high voltage
Hysteresis
enabled
0.65 VDDEH
—
VDDEH+0.3
P
hysteresis
disabled
0.55 VDDEH
—
VDDEH+0.3
C Fast pad I/O input high Hysteresis
voltage
enabled
0.65 VDDE
—
VDDE+0.3
P
hysteresis
disabled
0.55 VDDE
—
VDDE+0.3
C Multi-voltage pad I/O
input high voltage in
low-swing
P
mode10,11,12,13,14
Hysteresis
enabled
2.5
—
VDDEH+0.3
Hysteresis
disabled
2.2
—
VDDEH+0.3
C Multi-voltage pad I/O
input high voltage in
high-swing mode15
P
Hysteresis
enabled
0.65 VDDEH
—
VDDEH+0.3
Hysteresis
disabled
0.55 VDDEH
—
VDDEH+0.3
V
V
V
V
V
V
VOL_S
CC
P Slow/medium
multi-voltage pad I/O
output low voltage18,16
—
—
—
0.2*VDDEH
V
VOL_F
CC
P Fast pad I/O output low
voltage17,18
—
—
—
0.2*VDDE
V
VOL_LS
CC
P Multi-voltage pad I/O
output low voltage in
low-swing
mode10,11,12,13,17
IOL = 2 mA
—
—
0.6
V
VOL_HS
CC
P Multi-voltage pad I/O
output low voltage in
high-swing mode17
—
—
—
0.2 VDDEH
V
VOH_S
CC
P Slow/medium pad I/O
output high
voltage18,16
—
0.8 VDDEH
—
—
V
VOH_F
CC
P Fast pad I/O output
high voltage17,18
—
0.8 VDDE
—
—
V
MPC5634M Microcontroller Data Sheet, Rev. 8
80
Freescale Semiconductor
Table 19. DC electrical specifications1 (continued)
Value2
Symbol
C
Parameter
Conditions
Unit
min
typ
max
VOH_LS
CC
P Multi-voltage pad I/O
output high voltage in
low-swing
mode10,11,12,13,17
IOH_LS =
0.5 mA
Min VDDEH =
4.75 V
2.1
—
3.7
V
VOH_HS
CC
P Multi-voltage pad I/O
output high voltage in
high-swing mode17
—
0.8 VDDEH
—
—
V
VHYS_S
CC
C Slow/medium/multi-vol
tage I/O input
hysteresis
—
0.1 * VDDEH
—
—
V
VHYS_F
CC
C Fast I/O input
hysteresis
—
0.1 * VDDE
—
—
V
VHYS_LS
CC
C Low-Swing-Mode
hysteresis
Multi-Voltage I/O Input enabled
Hysteresis
0.25
—
—
V
IDD+IDDPLL19
CC
P Operating current
1.2 V supplies
VDD = 1.32 V,
80 MHz
—
—
195
mA
CC
P
VDD = 1.32 V,
60 MHz
—
—
135
CC
P
VDD = 1.32 V,
40 MHz
—
—
98
CC
—
—
80
µA
CC
T Operating current 1 V TJ = 25 oC
supplies
T
TJ = 55 oC
—
—
100
µA
IDDSTBY150
CC
P Operating current
TJ=150 oC
—
—
700
A
IDDSLOW
IDDSTOP
CC
P VDD low-power mode
operating current @
C
1.32 V
Slow mode20
—
—
50
mA
mode21
—
—
50
IDD33
CC
T Operating current
3.3 V supplies @
80 MHz
VRC334,22
—
—
70
mA
IDDA
IREF
CC
P Operating current
5.0 V supplies @
P
80 MHz
VDDA
—
—
30
mA
Analog
reference
supply current
—
—
1.0
VDDREG
—
—
70
IDDSTBY
IDDREG
C
Stop
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
81
Table 19. DC electrical specifications1 (continued)
Value2
Symbol
IDDH1
IDDH6
IDDH7
IDD7
IDDH9
IDD12
IACT_S
IACT_F
IACT_MV_PU
IACT_MV_PD
C
CC
CC
CC
CC
CC
Parameter
Conditions
Unit
min
typ
max
See note 23
mA
A
D Operating current
23
supplies @
V
D DDE
80 MHz
D
VDDEH1
—
—
VDDEH6
—
—
VDDEH7
—
—
D
VDDE7
—
—
D
VDDEH9
—
—
D
VDDE12
—
—
C Slow/medium I/O weak 3.0 V – 3.6 V
pull up/down current24
P
4.75 V –
5.25 V
15
—
95
35
—
200
D Fast I/O weak pull
up/down current24
1.62 V –
1.98 V
36
—
120
D
2.25 V –
2.75 V
34
—
139
D
3.0 V – 3.6 V
42
—
158
C Multi-voltage pad weak VDDEH=
pullup current
3.0–3.6 V10,
pad_multv_hv,
all process
corners,
high swing
mode only
10
—
75
P
25
—
200
C Multivoltage pad weak VDDEH=
pulldown current
3.0–3.6 V10,
pad_multv_hv,
all process
corners,
high swing
mode only
10
—
60
P
25
—
200
4.75 V –
5.25 V
4.75 V –
5.25 V
A
A
A
IINACT_D
CC
P I/O input leakage
current25
—
–2.5
—
2.5
A
IIC
CC
T DC injection current
(per pin)
—
–1.0
—
1.0
mA
IINACT_A
CC
P Analog input current,
channel off, AN[0:7],
AN38, AN3926
—
–250
—
250
nA
P Analog input current,
channel off, all other
analog pins (ANx)26
—
–150
—
150
MPC5634M Microcontroller Data Sheet, Rev. 8
82
Freescale Semiconductor
Table 19. DC electrical specifications1 (continued)
Value2
Symbol
CL
C
CC
Parameter
Conditions
Unit
min
typ
max
D Load capacitance (fast DSC(PCR[8:9
I/O)27
]) = 0b00
—
—
10
D
DSC(PCR[8:9
]) = 0b01
—
—
20
D
DSC(PCR[8:9
]) = 0b10
—
—
30
D
DSC(PCR[8:9
]) = 0b11
—
—
50
pF
CIN
CC
D Input capacitance
(digital pins)
—
—
—
7
pF
CIN_A
CC
D Input capacitance
(analog pins)
—
—
—
10
pF
CIN_M
CC
D Input capacitance
(digital and analog
pins28)
—
—
—
12
pF
RPUPD200K
CC
P Weak Pull-Up/Down
Resistance29,30
200 k Option
—
130
—
280
k
RPUPDMATCH
CC
C 200K Option
2.5
%
RPUPD100K
CC
P Weak Pull-Up/Down
Resistance29,30
100 k Option
140
k
RPUPDMATCH
CC
C 100K Option
2.5
%
RPUPD5K
CC
D Weak Pull-Up/Down
Resistance29
5 k Option
TA (TL to TH)
SR
— Operating temperature
range - ambient
(packaged)
—
SR
— Slew rate on power
supply pins
1
2
3
4
5
6
7
–2.5
—
65
—
–2.5
5 V ± 5%
supply
1.4
—
7.5
k
—
–40.0
—
125.0
C
—
—
—
50
V/ms
These specifications are design targets and subject to change per device characterization.
TBD: To Be Defined.
VDDE must be lower than VRC33, otherwise there is additional leakage on pins supplied by VDDE.
These specifications apply when VRC33 is supplied externally, after disabling the internal regulator (VDDREG = 0).
ADC is functional with 4 V VDDA 4.75 V but with derated accuracy. This means the ADC will continue to function
at full speed with no bad behavior, but the accuracy will be degraded.
Internal structures hold the input voltage less than VDDA + 1.0 V on all pads powered by VDDA supplies, if the
maximum injection current specification is met (3 mA for all pins) and VDDA is within the operating voltage
specifications.
The VDDF supply is connected to VDD in the package substrate. This specification applies to calibration package
devices only.
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
83
8
VFLASH is only available in the calibration package.
Regulator is functional, with derated performance, with supply voltage down to 4.0 V.
10
Multi-voltage pads (type pad_multv_hv) must be supplied with a power supply between 4.75 V and 5.25 V.
11
The slew rate (SRC) setting must be 0b11 when in low-swing mode.
12 While in low-swing mode there are no restrictions in transitioning to high-swing mode.
13
Pin in low-swing mode can accept a 5 V input.
14
Values are pending characterization.
15
Pin in low-swing mode can accept a 5 V input.
16
Characterization based capability:
IOH_S = {6, 11.6} mA and IOL_S = {9.2, 17.7} mA for {slow, medium} I/O with VDDEH=4.5 V;
IOH_S = {2.8, 5.4} mA and IOL_S = {4.2, 8.1} mA for {slow, medium} I/O with VDDEH=3.0 V
17
Characterization based capability:
IOH_F = {12, 20, 30, 40} mA and IOL_F = {24, 40, 50, 65} mA for {00, 01,10, 11} drive mode with VDDE=3.0 V;
IOH_F = {7, 13, 18, 25} mA and IOL_F = {18, 30, 35, 50} mA for {00, 01, 10, 11} drive mode with VDDE=2.25 V;
IOH_F = {3, 7, 10, 15} mA and IOL_F = {12, 20, 27, 35} mA for {00, 01, 10, 11} drive mode with VDDE=1.62 V
18 All VOL/VOH values 100% tested with ± 2 mA load.
19 Run mode as follows:
System clock = 40/60/80 MHz + FM 2%
Code executed from flash memory
ADC0 at 16 MHz with DMA enabled
ADC1 at 8 MHz
eMIOS pads toggle in PWM mode with a rate between 100 kHz and 500 kHz
eTPU pads toggle in PWM mode with a rate between 10 kHz and 500 kHz
CAN configured for a bit rate of 500 kHz
DSPI configured in master mode with a bit rate of 2 MHz
eSCI transmission configured with a bit rate of 100 kHz
20 Bypass mode, system clock at 1 MHz (using system clock divider), PLL shut down, CPU running simple executive
code, 4 x ADC conversion every 10 ms, 2 × PWM channels at 1 kHz, all other modules stopped.
21 Bypass mode, system clock at 1 MHz (using system clock divider), CPU stopped, PIT running, all other modules
stopped.
22 When using the internal regulator only, a bypass capacitor should be connected to this pin. External circuits should
not be powered by the internal regulator. The internal regulator can be used as a reference for an external debugger.
23 Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on a
particular I/O segment, and the voltage of the I/O segment. See Table 20 for values to calculate power dissipation for
specific operation. The total power consumption of an I/O segment is the sum of the individual power consumptions
for each pin on the segment.
24 Absolute value of current, measured at V and V .
IL
IH
25 Weak pull up/down inactive. Measured at V
DDE = 3.6 V and VDDEH = 5.25 V. Applies to pad types: fast (pad_fc).
26 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half
for each 8 to 12 oC, in the ambient temperature range of 50 to 125 oC. Applies to pad types: pad_a and pad_ae.
27 Applies to CLKOUT, external bus pins, and Nexus pins.
28 Applies to the FCK, SDI, SDO, and SDS pins.
29 This programmable option applies only to eQADC differential input channels and is used for biasing and sensor
diagnostics.
30 When the pull-up and pull-down of the same nominal 200 K or 100 K value are both enabled, assuming no
interference from external devices, the resulting pad voltage will be 0.5*VDDE ± 2.5%
9
MPC5634M Microcontroller Data Sheet, Rev. 8
84
Freescale Semiconductor
4.9
I/O Pad current specifications
NOTE
MPC5634M devices use two sets of I/O pads (5 V and 3.3 V). See Table 3 and Table 4 in
Section 3.6, “Signal summary, for the pad type associated with each signal.
The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The power consumption
is the sum of all output pin currents for a particular segment. The output pin current can be calculated from Table 20 based on
the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency, and load
parameters that fall outside the values given in Table 20.
Table 20. I/O pad average IDDE specifications1
Pad Type
Slow
Medium
Fast
MultiV
(High
Swing
Mode)
MultiV
(Low
Swing
Mode)
C
Period
(ns)
Load2
(pF)
VDDE
(V)
Drive/Slew
Rate Select
IDDE Avg
(mA)3
IDDE RMS
(mA)
CC
D
37
50
5.25
11
9
—
CC
D
130
50
5.25
01
2.5
—
CC
D
650
50
5.25
00
0.5
—
CC
D
840
200
5.25
00
1.5
—
CC
D
24
50
5.25
11
14
—
CC
D
62
50
5.25
01
5.3
—
CC
D
317
50
5.25
00
1.1
—
CC
D
425
200
5.25
00
3
—
CC
D
10
50
3.6
11
22.7
68.3
CC
D
10
30
3.6
10
12.1
41.1
CC
D
10
20
3.6
01
8.3
27.7
CC
D
10
10
3.6
00
4.44
14.3
CC
D
10
50
1.98
11
12.5
31
CC
D
10
30
1.98
10
7.3
18.6
CC
D
10
20
1.98
01
5.42
12.6
CC
D
10
10
1.98
00
2.84
6.4
4
Symbol
IDRV_SSR_HV
IDRV_MSR_HV
IDRV_FC
IDRV_MULTV_HV
CC
D
15
50
5.25
11
21.2
—
CC
D
30
50
5.25
10
—5
—
01
6.2
4
—
4
—
CC
IDRV_MULTV_HV
D
50
50
5.25
CC
D
300
50
5.25
00
1.1
CC
D
300
200
5.25
00
4.04
—
CC
D
15
30
5.25
11
20.26
—
CC
D
30
30
11
NA
—
5.25
1
Numbers from simulations at best case process, 150 °C.
All loads are lumped.
3 Average current is for pad configured as output only.
2
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
85
4
Ratio from 5.5 V pad spec to 5.25 V data sheet.
Not specified.
6
Low swing mode is not a strong function of VDDE.
5
4.9.1
I/O pad VRC33 current specifications
The power consumption of the VRC33 supply is dependent on the usage of the pins on all I/O segments. The power
consumption is the sum of all output pin VRC33 currents for all I/O segments. The output pin VRC33 current can be calculated
from Table 21 based on the voltage, frequency, and load on all medium, slow, and multv_hv pins. The output pin VRC33 current
can be calculated from Table 22 based on the voltage, frequency, and load on all fast pins. Use linear scaling to calculate pin
currents for voltage, frequency, and load parameters that fall outside the values given in Table 21 and Table 22.
Table 21. I/O pad VRC33 average IDDE specifications1
Pad Type
Slow
Medium
C
Period
(ns)
Load2
(pF)
Slew Rate
Select
IDD33 Avg
(µA)
IDD33 RMS
(µA)
CC
D
100
50
11
0.8
235.7
CC
D
200
50
01
0.04
87.4
CC
D
800
50
00
0.06
47.4
CC
D
800
200
00
0.009
47
CC
D
40
50
11
2.75
258
CC
D
100
50
01
0.11
76.5
CC
D
500
50
00
0.02
56.2
CC
D
500
200
00
0.01
56.2
CC
D
40
50
11
2.75
258
CC
D
100
50
01
0.11
76.5
CC
D
500
50
00
0.02
56.2
CC
D
500
200
00
0.01
56.2
CC
D
40
30
11
2.75
258
CC
D
100
30
11
0.11
76.5
CC
D
500
30
11
0.02
56.2
CC
D
500
30
11
0.01
56.2
Symbol
IDRV_SSR_HV
IDRV_MSR_HV
MultiV3 (High IDRV_MULTV_HV
Swing Mode)
MultiV4 (Low IDRV_MULTV_HV
Swing Mode)
1
These are typical values that are estimated from simulation and not tested. Currents apply to output pins
only.
2 All loads are lumped.
3
Average current is for pad configured as output only.
4 In low swing mode, multi-voltage pads (pad_multv_hv) must operate in highest slew rate setting.
MPC5634M Microcontroller Data Sheet, Rev. 8
86
Freescale Semiconductor
Table 22. VRC33 pad average DC current1
Pad
Type
Fast
C
Period
(ns)
Load2
(pF)
VRC33
(V)
VDDE
(V)
Drive
Select
IDD33 Avg
(µA)
IDD33 RMS
(µA)
CC
D
10
50
3.6
3.6
11
2.35
6.12
CC
D
10
30
3.6
3.6
10
1.75
4.3
CC
D
10
20
3.6
3.6
01
1.41
3.43
CC
D
10
10
3.6
3.6
00
1.06
2.9
CC
D
10
50
3.6
1.98
11
1.75
4.56
CC
D
10
30
3.6
1.98
10
1.32
3.44
CC
D
10
20
3.6
1.98
01
1.14
2.95
CC
D
10
10
3.6
1.98
00
0.95
2.62
Symbol
IDRV_FC
1
These are typical values that are estimated from simulation and not tested. Currents apply to output pins
only.
2 All loads are lumped.
4.9.2
LVDS pad specifications
LVDS pads are implemented to support the MSC (Microsecond Channel) protocol which is an enhanced feature of the DSPI
module. The LVDS pads are compliant with LVDS specifications and support data rates up to 50 MHz.
Table 23. DSPI LVDS pad specification 1, 2
#
Characteristic
Symbol
C
Condition
Min.
Value
Typ.
Value
Max.
Value
Unit
Data Rate
4
Data Frequency
FLVDSCLK
CC
D
50
MHz
Driver Specs
5
Differential output voltage
VOD3
CC
P
SRC=0b00 or
0b11
150
430
CC
P
SRC=0b01
90
340
SRC=0b10
155
480
CC
P
CC
P
mV
6
Common mode voltage
(LVDS), VOS
VOS3
7
Rise/Fall time
TR/TF
CC
D
2
ns
8
Propagation delay (Low to
High)
TPLH
CC
D
4
ns
9
Propagation delay (High to
Low)
TPHL
CC
D
4
ns
tPDSYNC
CC
D
4
ns
CC
D
500
ns
10 Delay (H/L), sync Mode
11 Delay, Z to Normal (High/Low) TDZ
0.8
1.2
1.6
V
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
87
Table 23. DSPI LVDS pad specification 1, 2 (continued)
12 Diff Skew Itphla-tplhbI or
Itplhb-tphlaI
TSKEW
CC
D
0.5
ns
105
150
C
Termination
13 Trans. Line (differential Zo)
CC
D
95
14 Temperature
CC
D
–40
100
1
These are typical values that are estimated from simulation.
These specifications are subject to change per device characterization.
3
Preliminary target values. Actual specifications to be determined.
2
4.10
Oscillator and PLLMRFM electrical characteristics
Table 24. PLLMRFM electrical specifications1
(VDDPLL =1.14 V to 1.32 V, VSS = VSSPLL = 0 V, TA = TL to TH)
Value
Symbol
C
Parameter
Conditions
Unit
min
max
D PLL reference frequency range2
Crystal reference
4
20
C
External reference
4
80
—
4
16
MHz
—
256
512
MHz
—
16
80
MHz
MHz
fref_crystal
fref_ext
CC
fpll_in
CC
P Phase detector input frequency range
(after pre-divider)
fvco
CC
P VCO frequency range3
frequency2
MHz
fsys
CC
C On-chip PLL
fsys
CC
T System frequency in bypass mode4
Crystal reference
4
20
P
External reference
0
80
—
1 / fsys
ns
Lower limit
1.6
3.7
MHz
Upper limit
24
56
—
1.2
75
MHz
fSYS maximum
–5
5
% fCLKO
tCYC
fLORL
fLORH
CC
CC
D System clock period
D Loss of reference frequency
—
window5
D
6,7
fSCM
CC
P Self-clocked mode frequency
CJITTER
CC
T CLKOUT period Peak-to-peak (clock
jitter8,9,10,11
edge to clock edge)
T
tcst
VIHEXT
CC
CC
UT
Long-term jitter (avg.
over 2 ms interval)
T Crystal start-up time 12, 13
T EXTAL input high voltage
T
—
Mode14,
Crystal
0.8 Vxtal 1.5V15
–6
6
ns
—
10
ms
Vxtal +
0.4
—
V
External Reference14, VRC33/2
+ 0.4
16
VRC33
MPC5634M Microcontroller Data Sheet, Rev. 8
88
Freescale Semiconductor
Table 24. PLLMRFM electrical specifications1
(VDDPLL =1.14 V to 1.32 V, VSS = VSSPLL = 0 V, TA = TL to TH) (continued)
Value
Symbol
VILEXT
C
CC
Parameter
T EXTAL input low voltage
T
Conditions
Unit
min
max
Crystal Mode14,
0.65Vxtal1.25V15
—
Vxtal –
0.4
External Reference14,
0
VRC33/2
– 0.4
4 MHz
5
30
8 MHz
5
26
12 MHz
5
23
16 MHz
5
19
20 MHz
5
16
—
—
200
s
16
—
CC
T XTAL load capacitance12
12, 17
V
pF
tlpll
CC
P PLL lock time
tdc
CC
T Duty cycle of reference
—
40
60
%
fLCK
CC
T Frequency LOCK range
—
–6
6
% fsys
fUL
CC
T Frequency un-LOCK range
—
–18
18
% fsys
fCS
fDS
CC
D Modulation Depth
Center spread
±0.25
±4.0
%fsys
D
Down Spread
–0.5
–8.0
fMOD
CC
—
100
D Modulation frequency18
—
kHz
1
All values given are initial design targets and subject to change.
Considering operation with PLL not bypassed.
3 f
VCO is calculated as follows:
— In Legacy Mode fVCO = (fcrystal / (PREDIV + 1)) * (4 * (MFD + 4))
— In Enhanced Mode fvco = (fcrystal / (EPREDIV + 1)) * (EMFD + 4)
4 All internal registers retain data at 0 Hz.
5 “Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked
mode.
6 Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside the
fLOR window.
7 f
VCO self clock range is 20–150 MHz. fSCM represents fSYS after PLL output divider (ERFD) of 2 through 16 in
enhanced mode.
8 This value is determined by the crystal manufacturer and board design.
9 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
SYS.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.
Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the
CJITTER percentage for a given interval.
10 Proper PC board layout procedures must be followed to achieve specifications.
11 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C
JITTER and
either fCS or fDS (depending on whether center spread or down spread modulation is enabled).
12 This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for
this PLL, load capacitors should not exceed these limits. For a 20 MHz crystal the maximum load should be 17 pF.
13 Proper PC board layout procedures must be followed to achieve specifications.
14
This parameter is guaranteed by design rather than 100% tested.
2
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
89
15
Vxtal range is preliminary and subject to change pending characterization data.
VIHEXT cannot exceed VRC33 in external reference mode.
17
This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in
the synthesizer control register (SYNCR).
18
Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 kHz.
16
4.11
Temperature sensor electrical characteristics
Table 25. Temperature sensor electrical characteristics
Value
Symbol
4.12
C
Parameter
—
CC
C Temperature
monitoring range
—
CC
C Sensitivity
—
CC
P Accuracy
Conditions
TJ = –40 to 150 °C
Unit
min
typical
max
–40
—
150
°C
—
6.3
—
mV/°C
–10
—
10
°C
eQADC electrical characteristics
Table 26. eQADC conversion specifications (operating)
Value
Symbol
C
Parameter
Unit
min
max
2
16
MHz
2 + 13
128 + 14
ADCLK
cycles
—
10
s
1.25
—
mV
fADCLK
SR
— ADC clock (ADCLK) frequency
CC
CC
D Conversion cycles
TSR
CC
C Stop mode recovery time1
—
CC
D Resolution2
OFFNC
CC
C Offset error without calibration
0
160
Counts
OFFWC
CC
C Offset error with calibration
–4
4
Counts
GAINNC
CC
C Full scale gain error without calibration
–160
0
Counts
GAINWC
CC
C Full scale gain error with calibration
–4
4
Counts
–3
3
mA
–4
4
Counts
IINJ
CC
T Disruptive input injection
current 3, 4, 5, 6
current6,7,8
EINJ
CC
T Incremental error due to injection
TUE8
CC
C Total unadjusted error (TUE) at 8 MHz
–4
4
Counts
TUE16
CC
C Total unadjusted error at 16 MHz
–8
8
Counts
MPC5634M Microcontroller Data Sheet, Rev. 8
90
Freescale Semiconductor
Table 26. eQADC conversion specifications (operating) (continued)
Value
Symbol
GAINVGA1
C
4
5
6
7
8
9
8 MHz ADC
–4
4
Counts10
16 MHz ADC
–8
8
Counts
3
11
Counts
3
11
Counts
– Variable gain amplifier accuracy (gain=1)9
CC
C
CC
C
C
INL
DNL
–3
16 MHz ADC
–311
CC
– Variable gain amplifier accuracy (gain=2)9
CC
D
CC
D
CC
D
CC
D
CC
– Variable gain amplifier accuracy (gain=4)9
CC
D
CC
D
CC
D
CC
DIFFmax
CC
DIFFmax2
INL
11
8 MHz ADC
C
8 MHz ADC
–5
5
Counts
16 MHz ADC
–8
8
Counts
8 MHz ADC
–3
3
Counts
16 MHz ADC
–3
3
Counts
8 MHz ADC
–7
7
Counts
16 MHz ADC
–8
8
Counts
8 MHz ADC
–4
4
Counts
D
16 MHz ADC
–4
4
Counts
PREGAIN set
to 1X setting
–
(VRH VRL)/2
V
CC
C Maximum differential voltage
(DANx+ - DANx-) or (DANx- DANx+)
C
PREGAIN set
to 2X setting
–
(VRH VRL)/4
V
DIFFmax4
CC
C
PREGAIN set
to 4X setting
–
(VRH VRL)/8
V
DIFFcmv
CC
C Differential input Common mode
voltage (DANx- + DANx+)/212
(VRH VRL)/2 5%
(VRH VRL)/2 +
5%
V
GAINVGA4
3
max
CC
GAINVGA2
2
Unit
min
CC
CC
1
Parameter
DNL
INL
DNL
Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to the
time that the ADC is ready to perform conversions. Delay from power up to full accuracy = 8 ms.
At VRH – VRL = 5.12 V, one count = 1.25 mV. Without using pregain.
Below disruptive current conditions, the channel being stressed has conversion values of 0x3FF for analog inputs
greater then VRH and 0x0 for values less then VRL. Other channels are not affected by non-disruptive conditions.
Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within
the limit do not affect device reliability or cause permanent damage.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values using VPOSCLAMP = VDDA + 0.5 V and VNEGCLAMP = – 0.3 V, then use the larger of the
calculated values.
Condition applies to two adjacent pins at injection limits.
Performance expected with production silicon.
All channels have same 10 k < Rs < 100 k; Channel under test has Rs=10 k; IINJ=IINJMAX,IINJMIN
Variable gain is controlled by setting the PRE_GAIN bits in the ADC_ACR1-8 registers to select a gain factor of 1,
2, or 4. Settings are for differential input only. Tested at 1 gain. Values for other settings are guaranteed by as
indicated.
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
91
10
At VRH – VRL = 5.12 V, one LSB = 1.25 mV.
Guaranteed 10-bit monotonicity.
12
Voltages between VRL and VRH will not cause damage to the pins. However, they may not be converted accurately
if the differential voltage is above the maximum differential voltage. In addition, conversion errors may occur if the
common mode voltage of the differential signal violates the Differential Input common mode voltage specification.
11
MPC5634M Microcontroller Data Sheet, Rev. 8
92
Freescale Semiconductor
4.13
Platform flash controller electrical characteristics
Table 27. APC, RWSC, WWSC settings vs. frequency of operation1
Target Max Frequency
(MHz)
APC2
RWSC2
WWSC
213
000
000
01
413
001
001
01
3
010
010
01
3
82
011
011
01
All
111
111
111
62
1
Illegal combinations exist, all entries must be taken from the same row
APC must be equal to RWSC
3 Maximum Frequency includes FM modulation
2
4.14
Flash memory electrical characteristics
Table 28. Program and erase specifications
Symbol
Parameter
Min Value
Typical
Value1
Initial
Max2
Max3
Unit
Tdwprogram
P Double Word (64 bits) Program Time4
—
22
50
500
s
T16kpperase
P 16 KB Block Pre-program and Erase Time
—
300
500
5000
ms
T32kpperase
P 32 KB Block Pre-program and Erase Time
—
400
600
5000
ms
T64kpperase
P 64 KB Block Pre-program and Erase Time
—
600
900
5000
ms
T128kpperase
P 128 KB Block Pre-program and Erase Time
—
800
1300
7500
ms
1
Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to
change pending device characterization.
2 Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
3 The maximum program & erase times occur after the specified number of program/erase cycles. These maximum
values are characterized but not guaranteed.
4 Actual hardware programming times. This does not include software overhead.
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
93
Table 29. Flash module life
Value
Symbol
Conditions
Unit
Min
Typ
—
P/E
C Number of program/erase cycles per block
for 16 Kbyte blocks over the operating
temperature range (TJ)
—
100,000
P/E
C Number of program/erase cycles per block
for 32 and 64 Kbyte blocks over operating
temperature range (TJ)
—
10,000
100,000 cycles
P/E
C Number of program/erase cycles per block
for 128 Kbyte blocks over the operating
temperature range (TJ)
—
1,000
100,000 cycles
Blocks with 0 – 1,000
P/E cycles
20
—
years
Blocks with 10,000 P/E
cycles
10
—
years
Blocks with 100,000 P/E
cycles
5
—
years
Retention
1
Parameter
C Minimum data retention at 85 °C average
ambient temperature1
cycles
Ambient temperature averaged over duration of application, not to exceed recommended product operating
temperature range.
MPC5634M Microcontroller Data Sheet, Rev. 8
94
Freescale Semiconductor
4.15
AC specifications
4.15.1
Pad AC specifications
Table 30. Pad AC specifications (5.0 V)1,2
Name
C
Output Delay (ns)3,4
Low-to-High /
Rise/Fall Edge (ns)4,5 Drive Load SRC/DSC
High-to-Low
(pF)
Min
Max
Min
Max
MSB,LSB
CC
D
4.6/3.7
12/12
2.2/2.2
7/7
50
CC
D
13/10
32/32
9/9
22/22
200
1010
N/A
Medium6,7,8
CC
D
12/13
28/34
5.6/6
15/15
50
CC
D
23/23
52/59
11/14
31/31
200
CC
D
69/71
152/165
34/35
74/74
50
CC
D
95/90
205/220
44/51
96/96
200
CC
D
7.3/5.7
19/18
4.4/4.3
14/14
50
CC
D
24/19
58/58
17/15
42/42
200
01
00
119
1010
N/A
Slow8,11
119
CC
D
26/27
61/69
13/13
34/34
50
CC
D
49/45
115/115
27/23
61/61
200
CC
D
137/142
320/330
72/74
164/164
50
CC
D
182/172
420/420
90/85
200/200
200
CC
D
4.1/3.6
10.3/8.9
3.28/2.98
8/8
50
CC
D
10.4/10.2
24.2/23.6
12.7/11.54
29/29
200
01
00
1010
N/A
MultiV12
(High Swing Mode)
CC
D
8.38/6.11
16/12.9
5.48/4.81
11/11
50
CC
D
15.9/13.6
31/28.5
14.6/13.1
31/31
200
CC
D
61.7/10.4
92.2/24.3
42.0/12.2
63/63
50
85.5/37.3
132.6/
78.9
57.7/46.4
85/85
200
2.31/2.34
7.62/6.33
1.26/1.67
7/7
30
119
01
CC
MultiV
(Low Swing Mode)
119
CC
D
D
Fast13
00
N/A
pad_i_hv14
CC
D
0.5/0.5
1.9/1.9
0.3/0.3
1.5/1.5
0.5
N/A
pull_hv
CC
D
NA
6000
—
5000/5000
50
N/A
1
These are worst case values that are estimated from simulation and not tested. Values in the table are simulated
at fSYS = 80 MHz, VDD = 1.14 V to 1.32 V, VDDE = 1.62 V to 1.98 V, VDDEH = 4.5 V to 5.25 V, TA = TL to TH.
2 TBD: To Be Defined.
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
95
3
This parameter is supplied for reference and is not guaranteed by design and not tested.
Delay and rise/fall are measured to 20% or 80% of the respective signal.
5
This parameter is guaranteed by characterization before qualification rather than 100% tested.
6
In high swing mode, high/low swing pad Vol and Voh values are the same as those of the slew controlled output pads
7 Medium Slew-Rate Controlled Output buffer. Contains an input buffer and weak pullup/pulldown.
8
Output delay is shown in Figure 8. Add a maximum of one system clock to the output delay for delay with respect
to system clock.
9
Can be used on the tester.
10
This drive select value is not supported. If selected, it will be approximately equal to 11.
11
Slow Slew-Rate Controlled Output buffer. Contains an input buffer and weak pullup/pulldown.
12
Selectable high/low swing IO pad with selectable slew in high swing mode only.
13
Fast pads are 3.3 V pads.
14
Stand alone input buffer. Also has weak pull-up/pull-down.
4
Table 31. Pad AC specifications (3.3 V)1
Pad Type
Medium5,6,7
C
Output Delay (ns)2,3
Low-to-High /
High-to-Low
Rise/Fall Edge (ns)3,4
Min
Max
Min
Max
Drive Load
(pF)
MSB,LSB
CC
D
5.8/4.4
18/17
2.7/2.1
10/10
50
CC
D
16/13
46/49
11.2/8.6
34/34
200
CC
D
14/16
37/45
6.5/6.7
19/19
50
CC
D
27/27
69/82
15/13
43/43
200
CC
D
83/86
200/210
38/38
86/86
50
CC
D
113/109
270/285
53/46
120/120
200
CC
D
9.2/6.9
27/28
5.5/4.1
20/20
50
CC
D
30/23
81/87
21/16
63/63
200
MultiV
(High Swing Mode)
01
00
11
109
N/A
7,11
118
109
N/A
Slow7,10
SRC/DSC
CC
D
31/31
80/90
15.4/15.4
42/42
50
CC
D
58/52
144/155
32/26
82/85
200
CC
D
162/168
415/415
80/82
190/190
50
CC
D
216/205
533/540
106/95
250/250
200
CC
D
3.7/3.1
10/10
30
CC
D
46/49
37/37
200
01
00
118
109
N/A
CC
D
32
15/15
50
CC
D
72
46/46
200
CC
D
210
100/100
50
CC
D
295
134/134
200
01
00
MPC5634M Microcontroller Data Sheet, Rev. 8
96
Freescale Semiconductor
Table 31. Pad AC specifications (3.3 V)1 (continued)
Pad Type
C
Output Delay (ns)2,3
Low-to-High /
High-to-Low
Min
Max
Rise/Fall Edge (ns)3,4
Min
Drive Load
(pF)
Max
SRC/DSC
MSB,LSB
CC
D
2.5/2.5
1.2/1.2
10
00
CC
D
2.5/2.5
1.2/1.2
20
01
CC
D
2.5/2.5
1.2/1.2
30
10
CC
D
2.5/2.5
1.2/1.2
50
118
pad_i_hv12
CC
D
0.5/0.5
3/3
1.5/1.5
0.5
N/A
pull_hv
CC
D
NA
6000
5000/5000
50
N/A
Fast
0.4/0.4
1
These are worst case values that are estimated from simulation and not tested. The values in the table are
simulated at fSYS = 80 MHz, VDD = 1.14 V to 1.32 V, VDDE = 3 V to 3.6 V, VDDEH = 3 V to 3.6 V, TA = TL to TH.
2 This parameter is supplied for reference and is not guaranteed by design and not tested.
3 Delay and rise/fall are measured to 20% or 80% of the respective signal.
4 This parameter is guaranteed by characterization before qualification rather than 100% tested.
5 In high swing mode, high/low swing pad Vol and Voh values are the same as those of the slew controlled output pads
6 Medium Slew-Rate Controlled Output buffer. Contains an input buffer and weak pullup/pulldown.
7 Output delay is shown in Figure 8. Add a maximum of one system clock to the output delay for delay with respect
to system clock.
8 Can be used on the tester
9 This drive select value is not supported. If selected, it will be approximately equal to 11.
10 Slow Slew-Rate Controlled Output buffer. Contains an input buffer and weak pullup/pulldown.
11 Slow Slew-Rate Controlled Output buffer. Contains an input buffer and weak pullup/pulldown.
12 Stand alone input buffer. Also has weak pull-up/pull-down.
Table 32. Pad AC specifications (1.8 V)
Pad Type
C
Output Delay (ns)1,2
Low-to-High /
High-to-Low
Min
Rise/Fall Edge (ns)3
Max
Min
Drive Load
(pF)
Max
SRC/DSC
MSB,LSB
CC
D
3.0/3.0
2.0/1.5
10
00
CC
D
3.0/3.0
2.0/1.5
20
01
CC
D
3.0/3.0
2.0/1.5
30
10
CC
D
3.0/3.0
2.0/1.5
50
114
Fast
1
This parameter is supplied for reference and is not guaranteed by design and not tested.
Delay and rise/fall are measured to 20% or 80% of the respective signal.
3
This parameter is guaranteed by characterization before qualification rather than 100% tested.
4 Can be used on the tester.
2
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
97
VDDE/2
Pad
Data Input
Rising
Edge
Output
Delay
Falling
Edge
Output
Delay
VOH
Pad
Output
VOL
Figure 8. Pad output delay
4.16
AC timing
4.16.1
IEEE 1149.1 interface timing
Table 33. JTAG pin AC electrical characteristics1
#
Symbol
C
Characteristic
Min.
Value
Max.
Value
Unit
1
tJCYC
CC
D TCK Cycle Time
100
—
ns
2
tJDC
CC
D TCK Clock Pulse Width
40
60
ns
3
tTCKRISE
CC
D TCK Rise and Fall Times (40% – 70%)
—
3
ns
4
tTMSS, tTDIS
CC
D TMS, TDI Data Setup Time
5
—
ns
5
tTMSH, tTDIH
CC
D TMS, TDI Data Hold Time
25
—
ns
6
tTDOV
CC
D TCK Low to TDO Data Valid
—
23
ns
7
tTDOI
CC
D TCK Low to TDO Data Invalid
0
—
ns
8
tTDOHZ
CC
D TCK Low to TDO High Impedance
—
20
ns
9
tJCMPPW
CC
D JCOMP Assertion Time
100
—
ns
10
tJCMPS
CC
D JCOMP Setup Time to TCK Low
40
—
ns
11
tBSDV
CC
D TCK Falling Edge to Output Valid
—
50
ns
MPC5634M Microcontroller Data Sheet, Rev. 8
98
Freescale Semiconductor
Table 33. JTAG pin AC electrical characteristics1 (continued)
#
1
Symbol
C
Characteristic
Min.
Value
Max.
Value
Unit
12
tBSDVZ
CC
D TCK Falling Edge to Output Valid out of High
Impedance
—
50
ns
13
tBSDHZ
CC
D TCK Falling Edge to Output High Impedance
—
50
ns
14
tBSDST
CC
D Boundary Scan Input Valid to TCK Rising Edge
50
—
ns
15
tBSDHT
CC
D TCK Rising Edge to Boundary Scan Input
Invalid
50
—
ns
JTAG timing specified at VDD = 1.14 V to 1.32 V, VDDEH = 4.5 V to 5.25 V with multi-voltage pads programmed to
Low-Swing mode, TA = TL to TH, and CL = 30 pF with DSC = 0b10, SRC = 0b00. These specifications apply to JTAG
boundary scan only. See Table 34 for functional specifications.
TCK
2
3
2
1
3
Figure 9. JTAG test clock input timing
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
99
TCK
4
5
TMS, TDI
6
8
7
TDO
Figure 10. JTAG test access port timing
TCK
10
JCOMP
9
Figure 11. JTAG JCOMP timing
MPC5634M Microcontroller Data Sheet, Rev. 8
100
Freescale Semiconductor
TCK
11
13
Output
Signals
12
Output
Signals
14
15
Input
Signals
Figure 12. JTAG boundary scan timing
4.16.2
Nexus timing
Table 34. Nexus debug port timing1
#
1
Symbol
tMCYC
CC
C
Characteristic
Min. Value Max. Value
Unit
D MCKO Cycle Time
22,3
8
tCYC
1004
—
ns
40
60
%
– 0.1
0.2
tMCYC
0.1
0.2
tMCYC
– 0.1
0.2
tMCYC
1a
tMCYC
CC
D Absolute Minimum MCKO Cycle Time
2
tMDC
CC
D MCKO Duty Cycle
5
3
tMDOV
CC
D MCKO Low to MDO Data Valid
4
tMSEOV
CC
D MCKO Low to MSEO Data Valid5
Valid5
6
tEVTOV
CC
D MCKO Low to EVTO Data
7
tEVTIPW
CC
D EVTI Pulse Width
4.0
—
tTCYC
8
tEVTOPW
CC
D EVTO Pulse Width
1
—
tMCYC
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
101
Table 34. Nexus debug port timing1 (continued)
#
9
1
2
3
4
5
6
7
8
Symbol
tTCYC
CC
C
Characteristic
Min. Value Max. Value
Unit
D TCK Cycle Time
46,7
—
tCYC
1008
—
ns
9a
tTCYC
CC
D Absolute Minimum TCK Cycle Time
10
tTDC
CC
D TCK Duty Cycle
40
60
%
11
tNTDIS
CC
D TDI Data Setup Time
5
—
ns
12
tNTDIH
CC
D TDI Data Hold Time
25
—
ns
13
tNTMSS
CC
D TMS Data Setup Time
5
—
ns
14
tNTMSH
CC
D TMS Data Hold Time
25
—
ns
15
tJOV
CC
D TCK Low to TDO Data Valid
10
20
ns
All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing
specified at VDD = 1.14 V to 1.32 V, VDDEH = 4.5 V to 5.25 V with multi-voltage pads programmed to Low-Swing
mode, TA = TL to TH, and CL = 30 pF with DSC = 0b10.
Achieving the absolute minimum MCKO cycle time may require setting the MCKO divider to more than its minimum
setting (NPC_PCR[MCKO_DIV] depending on the actual system frequency being used.
This is a functionally allowable feature. However, this may be limited by the maximum frequency specified by the
Absolute minimum MCKO period specification.
This may require setting the MCKO divider to more than its minimum setting (NPC_PCR[MCKO_DIV]) depending
on the actual system frequency being used.
MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
Achieving the absolute minimum TCK cycle time may require a maximum clock speed (system frequency / 8) that
is less than the maximum functional capability of the design (system frequency / 4) depending on the actual system
frequency being used.
This is a functionally allowable feature. However, this may be limited by the maximum frequency specified by the
Absolute minimum TCK period specification.
This may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability
of the design (system frequency / 4) depending on the actual system frequency being used.
1
2
MCKO
3
4
6
MDO
MSEO
EVTO
Output Data Valid
Figure 13. Nexus output timing
MPC5634M Microcontroller Data Sheet, Rev. 8
102
Freescale Semiconductor
TCK
EVTI
EVTO
9
7
7
8
8
Figure 14. Nexus event trigger and test clock timings
TCK
11
13
12
14
TMS, TDI
15
TDO
Figure 15. Nexus TDI, TMS, TDO timing
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
103
4.16.3
Calibration bus interface timing
Table 35. Calibration bus operation timing 1
66 MHz (ext. bus)2
#
Symbol
C
Characteristic
Unit
Min
Max
1
TC
CC
P
CLKOUT Period
15.2
—
ns
2
tCDC
CC
D CLKOUT duty cycle
45%
55%
TC
ns
Notes
Signals are
measured at 50%
VDDE.
3
tCRT
CC
D CLKOUT rise time
—
3
4
tCFT
CC
D CLKOUT fall time
—
3
ns
5
tCOH
CC
D CLKOUT Posedge to Output Signal
Invalid or High Z(Hold Time)
1.04/1.5
—
ns
Hold time selectable
via
SIU_ECCR[EBTS]
bit:
EBTS=0: 1.0ns
EBTS=1: 1.5ns
—
6.04/7.0
ns
Output valid time
selectable via
SIU_ECCR[EBTS]
bit:
EBTS=0: 5.5ns
EBTS=1: 6.5ns
5.0
—
ns
1.0
—
ns
6.5
—
ns
3
—
ns
ADDR[8:31]
CS[0:3]
DATA[0:31]
OE
RD_WR
TS
WE[0:3]/BE[0:3]
6
tCOV
CC
D CLKOUT Posedge to Output Signal Valid
(Output Delay)
ADDR[8:31]
CS[0:3]
DATA[0:31]
OE
RD_WR
TS
WE[0:3]/BE[0:3]
7
tCIS
CC
D Input Signal Valid to CLKOUT Posedge
(Setup Time)
DATA[0:31]
8
tCIH
CC
D CLKOUT Posedge to Input Signal Invalid
(Hold Time)
DATA[0:31]
9
10
1
2
3
4
5
tAPW
tAAI
CC
CC
D ALE Pulse Width5
D ALE Negated to Address
Invalid5
Calibration bus timing specified at fSYS = 80 MHz, VDD = 1.14 V to 1.32 V, VDDE = 1.62 V to 3.6 V (unless stated
otherwise), TA = TL to TH, and CL = 30 pF with DSC = 0b10.
The external bus is limited to half the speed of the internal bus. The maximum external bus frequency is 66 MHz.
Refer to Fast Pad timing in Table 31 and Table 32 (different values for 3.3 V vs. 1.8 V).
The EBTS=0 timings are only valid/ tested at VDDE=2.25–3.6 V, whereas EBTS=1 timings are valid/tested at
1.6–3.6 V.
Measured at 50% of ALE.
MPC5634M Microcontroller Data Sheet, Rev. 8
104
Freescale Semiconductor
Voh_f
VDDE/2
Vol_f
CLKOUT
2
3
2
4
1
Figure 16. CLKOUT timing
VDDE/2
CLKOUT
6
5
VDDE/2
5
OUTPUT
BUS
VDDE/2
6
5
5
OUTPUT
SIGNAL
VDDE/2
6
OUTPUT
SIGNAL
VDDE/2
Figure 17. Synchronous output timing
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
105
CLKOUT
VDDE/2
7
8
INPUT
BUS
VDDE/2
7
8
INPUT
SIGNAL
VDDE/2
Figure 18. Synchronous input timing
ipg_clk
CLKOUT
ALE
TS
A/D
DATA
ADDR
9
10
Figure 19. ALE signal timing
MPC5634M Microcontroller Data Sheet, Rev. 8
106
Freescale Semiconductor
4.16.4
eMIOS timing
Table 36. eMIOS timing1
#
1
Symbol
C
Characteristic
Min.
Value
Max.
Value
Unit
1
tMIPW
CC
D
eMIOS Input Pulse Width
4
—
tCYC
2
tMOPW
CC
D
eMIOS Output Pulse Width
1
—
tCYC
eMIOS timing specified at fSYS = 80 MHz, VDD = 1.14 V to 1.32 V, VDDEH = 4.5 V to 5.25 V, TA = TL to TH, and CL
= 50 pF with SRC = 0b00.
4.16.5
DSPI timing
Table 37. DSPI timing1,2
40 MHz
#
1
Symbol
tSCK
CC
C
60 MHz
80 MHz
Characteristic
D SCK Cycle Time3,4
Delay5
Unit
Min.
Max.
Min.
Max.
Min.
Max.
48.8 ns
5.8 ms
28.4 ns
3.5 ms
24.4 ns
2.9 ms
—
46
—
26
—
22
—
ns
45
—
25
—
21
—
ns
2
tCSC
CC
D PCS to SCK
3
tASC
CC
D After SCK Delay6
4
tSDC
CC
D SCK Duty Cycle
5
tA
CC
D Slave Access Time
(SS active to SOUT
driven)
—
25
—
25
—
25
ns
6
tDIS
CC
D Slave SOUT Disable
Time
(SS inactive to SOUT
High-Z or invalid)
—
25
—
25
—
25
ns
7
tPCSC
CC
D PCSx to PCSS time
4
—
4
—
4
—
ns
8
tPASC
CC
D PCSS to PCSx time
5
—
5
—
5
—
ns
9
tSUI
CC
ns
(½tSC) – (½tSC) + (½tSC) – (½tSC) + (½tSC) – (½tSC) +
2
2
2
2
2
2
ns
Data Setup Time for Inputs
D Master (MTFE = 0)
20
—
20
—
20
—
D Slave
2
—
2
—
2
—
D Master (MTFE = 1,
CPHA = 0)7
–4
—
6
—
8
—
D Master (MTFE = 1,
CPHA = 1)
20
—
20
—
20
—
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
107
Table 37. DSPI timing1,2 (continued)
40 MHz
#
Symbol
C
11
12
1
2
3
4
5
6
7
tHI
tSUO
tHO
80 MHz
Unit
Min.
10
60 MHz
Characteristic
CC
Max.
Min.
Max.
Min.
Max.
Data Hold Time for Inputs
D Master (MTFE = 0)
–4
—
–4
—
–4
—
D Slave
7
—
7
—
7
—
D Master (MTFE = 1,
CPHA = 0)7
45
—
25
—
21
—
D Master (MTFE = 1,
CPHA = 1)
–4
—
–4
—
–4
—
CC
ns
Data Valid (after SCK edge)
D Master (MTFE = 0)
—
6
—
6
—
6
D Slave
—
25
—
25
—
25
D Master (MTFE = 1,
CPHA=0)
—
45
—
25
—
21
D
—
6
—
6
—
6
Master (MTFE = 1,
CPHA=1)
CC
ns
Data Hold Time for Outputs
D Master (MTFE = 0)
–5
—
–5
—
–5
—
D Slave
5.5
—
5.5
—
5.5
—
D Master (MTFE = 1,
CPHA = 0)
8
—
4
—
3
—
D Master (MTFE = 1,
CPHA = 1)
–5
—
–5
—
–5
—
ns
All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad type M or MH. DSPI signals using pad
types of S or SH have an additional delay based on the slew rate. DSPI timing is specified at VDDEH = 3.0–5.25 V,
TA = TL to TH, and CL = 50 pF with SRC = 0b11.
Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency
modulation (FM). 42 MHz parts allow for 40 MHz system clock + 2% FM; 62 MHz parts allow for a 60 MHz system
clock + 2% FM, and 82 MHz parts allow for 80 MHz system clock + 2% FM.
The minimum DSPI Cycle Time restricts the baud rate selection for given system clock rate. These numbers are
calculated based on two MPC5634M devices communicating over a DSPI link.
The actual minimum SCK cycle time is limited by pad performance.
The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK].
The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC].
This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b10.
MPC5634M Microcontroller Data Sheet, Rev. 8
108
Freescale Semiconductor
2
3
These numbers
reference Table 37.
PCSx
1
4
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
9
SIN
10
First Data
Last Data
Data
12
SOUT
First Data
11
Data
Last Data
Figure 20. DSPI classic SPI timing – master, CPHA = 0
These numbers
reference Table 37.
PCSx
SCK Output
(CPOL=0)
10
SCK Output
(CPOL=1)
9
SIN
Data
First Data
12
SOUT
First Data
Last Data
11
Data
Last Data
Figure 21. DSPI classic SPI timing – master, CPHA = 1
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
109
These numbers
reference Table 37.
3
2
SS
1
4
SCK Input
(CPOL=0)
4
SCK Input
(CPOL=1)
5
First Data
SOUT
9
6
Data
Last Data
Data
Last Data
10
First Data
SIN
11
12
Figure 22. DSPI classic SPI timing – slave, CPHA = 0
SS
These numbers
reference Table 37.
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
12
SOUT
First Data
9
SIN
Data
Last Data
Data
Last Data
6
10
First Data
Figure 23. DSPI classic SPI timing – slave, CPHA = 1
MPC5634M Microcontroller Data Sheet, Rev. 8
110
Freescale Semiconductor
These numbers
reference Table 37.
3
PCSx
4
1
2
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
9
SIN
10
First Data
12
SOUT
Last Data
Data
11
First Data
Data
Last Data
Figure 24. DSPI modified transfer format timing – master, CPHA = 0
These numbers
reference Table 37.
PCSx
SCK Output
(CPOL=0)
SCK Output
(CPOL=1)
10
9
SIN
First Data
Data
12
First Data
SOUT
Data
Last Data
11
Last Data
Figure 25. DSPI modified transfer format timing – master, CPHA = 1
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
111
SS
These numbers
reference Table 37.
3
2
1
SCK Input
(CPOL=0)
4
4
SCK Input
(CPOL=1)
12
11
5
First Data
SOUT
Data
Last Data
10
9
Data
First Data
SIN
6
Last Data
Figure 26. DSPI modified transfer format timing – slave, CPHA =0
These numbers
reference Table 37.
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
12
First Data
SOUT
9
Last Data
Data
Last Data
10
First Data
SIN
Data
6
Figure 27. DSPI modified transfer format timing – slave, CPHA =1
7
8
PCSS
PCSx
Figure 28. DSPI PCS strobe (PCSS) timing
MPC5634M Microcontroller Data Sheet, Rev. 8
112
Freescale Semiconductor
4.16.6
eQADC SSI timing
Table 38. eQADC SSI timing characteristics (pads at 3.3 V or at 5.0 V)1
CLOAD = 25pF on all outputs. Pad drive strength set to maximum.
#
Symbol
C
Rating
Min
Typ
Max
Unit
1/17 fSYS_CLK
12 fSYS_CLK
Hertz
2 tSYS_CLK
17tSYS_CLK
seconds
1
fFCK
CC
D
FCK Frequency 2, 3
1
tFCK
CC
D
FCK Period (tFCK = 1/ fFCK)
2
tFCKHT CC
D
Clock (FCK) High Time
tSYS_CLK 6.5
9* tSYS_CLK
6.5
ns
3
tFCKLT
CC
D
Clock (FCK) Low Time
tSYS_CLK 6.5
8* tSYS_CLK
6.5
ns
4
tSDS_LL CC
D
SDS Lead/Lag Time
–7.5
+7.5
ns
5
tSDO_LL CC
D
SDO Lead/Lag Time
–7.5
+7.5
ns
6
tDVFE
CC
D
Data Valid from FCK Falling Edge
(tFCKLT+tSDO_LL)
1
ns
7
tEQ_SU CC
D
eQADC Data Setup Time (Inputs)
22
ns
8
tEQ_HO CC
D
eQADC Data Hold Time (Inputs)
1
ns
1
SS timing specified at fSYS = 80 MHz, VDD = 1.14 V to 1.32 V, VDDEH = 4.5 V to 5.25 V, TA = TL to TH, and CL = 50 pF
with SRC = 0b00.
2 Maximum operating frequency is highly dependent on track delays, master pad delays, and slave pad delays.
3 FCK duty is not 50% when it is generated through the division of the system clock by an odd number.
1
2
3
FCK
4
4
SDS
5
SDO
25th
6
1st (MSB)
5
2nd
26th
External Device Data Sample at
FCK Falling Edge
8
7
SDI
1st (MSB)
2nd
25th
26th
eQADC Data Sample at
FCK Rising Edge
Figure 29. eQADC SSI timing
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
113
5
Packages
5.1
Package mechanical data
5.1.1
144 LQFP
MPC5634M Microcontroller Data Sheet, Rev. 8
114
Freescale Semiconductor
Figure 30. 144 LQFP package mechanical drawing (part 1)
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
115
Figure 31. 144 LQFP package mechanical drawing (part 2)
MPC5634M Microcontroller Data Sheet, Rev. 8
116
Freescale Semiconductor
Figure 32. 144 LQFP package mechanical drawing (part 3)
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
117
5.1.2
176 LQFP
Figure 33. 176 LQFP package mechanical drawing (part 1)
MPC5634M Microcontroller Data Sheet, Rev. 8
118
Freescale Semiconductor
Figure 34. 176 LQFP package mechanical drawing (part 2)
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
119
Figure 35. 176 LQFP package mechanical drawing (part 3)
MPC5634M Microcontroller Data Sheet, Rev. 8
120
Freescale Semiconductor
5.1.3
208 MAPBGA
Figure 36. 208 MAPBGA package mechanical drawing (part 1)
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
121
Figure 37. 208 MAPBGA package mechanical drawing (part 2)
MPC5634M Microcontroller Data Sheet, Rev. 8
122
Freescale Semiconductor
6
Ordering information
Table 39 shows the orderable part numbers for the MPC5634M series.
Table 39. Orderable part number summary
Flash/SRAM
(Kbytes)
Package
Speed
(MHz)
SPC5632MF0MLQA6
768 / 48
144 LQFP Pb-free
60
SPC5632MF0MLQA4
768 / 48
144 LQFP Pb-free
40
SPC5633MF0MMGA8
1024 / 64
208 MAPBGA Pb-free
80
SPC5633MF0MLUA8
1024 / 64
176 LQFP Pb-free
80
SPC5633MF0MLQA8
1024 / 64
144 LQFP Pb-free
80
SPC5633MF0MMGA6
1024 / 64
208 MAPBGA Pb-free
60
SPC5633MF0MLUA6
1024 / 64
176 LQFP Pb-free
60
SPC5633MF0MLQA6
1024 / 64
144 LQFP Pb-free
60
SPC5633MF0MLQA4
1024 / 64
144 LQFP Pb-free
40
SPC5634MF0MMGA8
1536 / 94
208 MAPBGA Pb-free
80
SPC5634MF0MLUA8
1536 / 94
176 LQFP Pb-free
80
SPC5634MF0MLQA8
1536 / 94
144 LQFP Pb-free
80
SPC5634MF0MMGA6
1536 / 94
208 MAPBGA Pb-free
60
SPC5634MF0MLUA6
1536 / 94
176 LQFP Pb-free
60
SPC5634MF0MLQA6
1536 / 94
144 LQFP Pb-free
60
Part Number
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
123
Example code:
S
PC
56
3
4
M
F0
M
LU
A
8
Qualification Status
Power Architecture Core
Automotive Platform
Core Version
Flash Size (core dependent)
Product
Fab/Mask rev.
Temperature Spec.
Package Code
Silicon rev.
Maximum Frequency
Qualification Status
Flash Size (z3 core)
Package Code
M = MC status
S = Auto qualified
P = PC status
2 = 768 KB
4 = 1.5 MB
LQ = 144 LQFP
LU = 176 LQFP
MG = 208 MAPBGA
Product Family
Silicon rev.
M= MPC5634M
A = rev. 1 or later
Fab/Mask rev.
Maximum Frequency
F0 = ATMC Rev. 0
4 = 40 MHz
3 = 1 MB
Automotive Platform
56 = Power Architecture in 90 nm
57 = Power Architecture in 65 nm
Core Version
3 = e200z3
6 = 60 MHz
8 = 80 MHz
Figure 38. Commercial product code structure
MPC5634M Microcontroller Data Sheet, Rev. 8
124
Freescale Semiconductor
7
Document revision history
Table 40 summarizes revisions to this document.
Table 40. Revision history
Revision
Date
Description of Changes
Rev. 1
4/2008
Initial release
Rev. 2
12/2008
• Maximum amount of flash increased from 1 MB to 1.5 MB. Flash memory type has
changed. Rev. 1 and later devices use LC flash instead of FL flash.
• Additional packages offered—now includes100 LQFP and 176 LQFP. Please note that
the pinouts can vary for the same package depending on the amount of flash memory
included in the device.
• Device comparison table added.
• Feature details section added
• Signal summary table expanded. Now includes PCR register numbers and signal
selection values and pin numbers for all production packages.
• Electrical characteristics updated.
• DSPI timing data added for 40 MHz and 60 MHz.
• Thermal characteristics data updated. Data added for 100- and 176-pin packages.
• DSPI LVDS pad specifications added.
Rev. 3
2/2009
Electrical characteristics updated
• Flash memory electrical characteristics updated for LC flash
• Power management control (PMC) and Power on Reset (POR) specifications updated
• EMI characteristics data added
• Maximum ratings updated
• I/O pad current specifications updated
• I/O Pad VRC33 current specifications added
• Temperature sensor electrical characteristics added
Pad type added to “Voltage” column of signal summary table
Many signal names have changed to make them more understandable
• DSPI: PCS_C[n] is now DSPI_C_PCS[n]; SOUT_C is now DSPI_C_SOUT, SIN_C is
now DSPI_C_SIN, and SCK_C is now DSPI_C_SCK
• CAN: CNTXB is now CAN_B_TX and CNRXB is now CAN_B_RC
• SCI: RXDB is now SCI_B_RX and TXDB is now SCI_B_TX
• In cases where multiple instances of the same IP block is incorporated into the device,
e.g., 2 SCI blocks, the above nomenclature applies to all blocks
“No connect” pins on pinouts clarified
• Pins labelled “NIC” have no internal connection and should be tied to ground
• Pins labelled “NC” are not functional pins but may be connected to internal circuits
They are to be left floating
Some of the longer multiplexed signal names appearing on pinouts have been moved to
the inside of the package body to avoid having to use smaller fonts
Orderable parts table updated
Part number decoder added
MPC5634M Microcontroller Data Sheet, Rev. 8
Freescale Semiconductor
125
Table 40. Revision history (continued)
Revision
Date
Rev.4
12/2009
Description of Changes
208-pin MAPBGA ballmap for the MPC5633M (1024 KB flash memory) has changed.
Power Management Control (PMC) and Power On Reset (POR) electrical specifications
updated
Temperature sensor data added
Specifications now indicate how each controller characteristic parameter is guaranteed.
I/O pad current specifications updated
I/O Pad VRC33 current specifications updated
PAD AC characteristics updated
VGA gain specifications added to eQADC electrical characteristics
DC electrical specifications updated:
• Footnote added to RPUPD100K and RPUPD200K: When the pull-up and pull-down of
the same nominal 200 K or 100 K value are both enabled, assuming no interference
from other devices, the resulting pad voltage will be 0.5*VDDE ± 2.5%
• IOL condition added to VOL_LS.
• IOH condition added to VOH_LS.
• Minimum VOH_LS is 2.3 V (was 2.7 V).
• Separate IDDPLL removed from IDD spec because we can only measure IDD + IDDPLL.
IDD increased by 15 mA (to 195 mA) to account for IDDPLL. IDD now documented as
IDD + IDDPLL. Footnote added detailing runtime configuration used to measure
IDD + IDDPLL.
• Specifications for IDDSTBY and IDDSTBY150 reformatted to make more clear.
• VSTBY is now specified by two ranges. The area in between those ranges is
indeterminate.
LVDS pad specifications updated:
• Min value for VOD at SRC=0b01 is 90 mV (was 120); and 160 mV (was 180) at
SRC = 0b10
Changes to Signal Properties table:
• VDDE7 removed as voltage segment from Calibration bus pins. Calibration bus pins
are powered by VDDE12 only.
• GPIO[139] and GPIO[87] pins changed to Medium pads
• Some signal names have changed on 176-pin QFP package pinout: “CAL_x” signals
renamed to “ALT_x”.
Changes to Pad Types table:
• Column heading changed from “Voltage” to “Supply Voltage”
• MultiV pad high swing mode voltage changed to 3.0 V – 5.25 V (was 4.5 V – 5.25 V)
• MultiV pad low swing mode voltage changed to 4.5 V – 5.25 V (was 3.0 V – 3.6 V)
Signal details table added
Power/ground segmentation table added
100-pin package is no longer available
MPC5634M Microcontroller Data Sheet, Rev. 8
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Freescale Semiconductor
Table 40. Revision history (continued)
Revision
Date
Rev. 5
04/2010
Description of Changes
Updates to features list:
• MMU is 16-entry (previously noted as 8-entry)
• ECSM features include single-bit error correction reporting
• eTPU2 is object code compatible with previous eTPU versions
Updates to feature details:
• Programming feature: eTPU2 channel flags can be tested
Pinout/ballmap changes:
144 pin LQFP package:
• Pin 46 is now VDDEH1B (was VDDEH4A)
• Pin 61 is now VDDEH6A (was VDDEH4B)
176 pin LQFP package (1.5M devices)
• Pin 55 is now VDDEH1B (was VDDEH4A)
• Pin 74 is now VDDEH6A (was VDDEH4B)
176 pin LQFP package (1.5M devices)
• Pin 55 is now VDDEH1B (was VDDEH4A)
• Pin 74 is now VDDEH6A (was VDDEH4B)
208 ball BGA package (all devices)
Ball N9 changed to VDDEH1/6 (was VDDEH6). In a future revision of the device this may
be changed to NC (no connect).
Changes to calibration ball names on devices with 1 MB flash memory:
• CAL_MDO0 changed to ALT_MDO0
• CAL_MDO1 changed to ALT_MDO1
• CAL_MDO2 changed to ALT_MDO2
• CAL_MDO3 changed to ALT_MDO3
• CAL_MSEO0 changed to ALT_MSEO0
• CAL_MSEO1 changed to ALT_MSEO1
• CAL_EVTI changed to ALT_EVTI
• CAL_EVTO changed to ALT_EVTO
• CAL_MCKO changed to ALT_MCKO
Power/ground segment changes:
• The following pins are on VDDE7 I/O segment only on the 208-ball BGA package:
ALT_MDO[0:3], ALT_MSEO[0:1], ALT_EVTI, ALT_EVTO, ALT_MCKO.
• Power segments VDDEH4, VDDEH4A and VDDEH4B have been removed.
CLKOUT power segment is VDDE5 (was VDDE12)
Thermal characteristics for 176-pin LQFP updated (all parameter values)
MPC5634M Microcontroller Data Sheet, Rev. 8
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127
Table 40. Revision history (continued)
Revision
Date
Description of Changes
Rev. 5
(cont.)
04/2010
PMC Operating conditions and external regulators supply voltage specifications updated
• (2) PMC 5 V supply voltage VDDREG min value is 4.5 V (was 4.75 V)
PMC electrical characteristics specifications updated
• (1d) Bandgap reference supply voltage variation is 3000 ppm/V (was 1500 ppm/V)
• (5a) Nominal 3.3 V supply internal regulator DC output voltage variation at power-on
reset min value is Vdd33-8.5% (was unspecified previously)
• (5a) Nominal 3.3 V supply internal regulator DC output voltage variation at power-on
reset max value is Vdd3+7% (was unspecified previously)
• (9a) Variation of POR for rising 5 V VDDREG supply max value is Por5V_r + 50% (was
Por5V_r + 35%)
• (9c) Variation of POR for falling 5 V VDDREG supply max value is Por5V_f + 50% (was
Por5V_f + 35%)
• (9c) note added: Minimum loading (<10 mA) for reading trim values from flash,
powering internal RC oscillator, and IO consumption during POR.
“Core Voltage Regulator Controller External Components Preferred Configuration” circuit
diagram updated
Changes to DC Electrical Specifications:
• Footnote added to VDDE. VDDE must be less than VRC33 or there is additional leakage
on pins supplied by VDDE.
• Low range SRAM standby voltage (VSTBY) minimum changed to 0.95 V (was 0.9 V)
• Low range SRAM standby voltage (VSTBY) maximum changed to 1.2 V (was 1.3 V)
• High range SRAM standby voltage (VSTBY) minimum changed to 2.0 V (was 2.5 V)
• VIL_LS max value (Hysteresis disabled) changed to 0.9 V (was 1.1 V)
• VOH_LS min value changed to 2 V (was 2.3 V)
• IDDSLOW max value is 50 mA
• IDDSTOP max value is 50 mA
• IDDA max value is 30 mA (was 15.0 mA)
• IDD4 and VDDEH4 removed—they no longer exist
I/O pad average IDDE specifications table updated
I/O pad VRC33 average IDDE specifications table updated
LVDS pad specifications table updated
• VOS min value is 0.9 V (was 1.075 V)
• VOS max value is 1.6 V (was 1.325 V)
Updates to PLLMRFM electrical specifications:
• Maximum values for XTAL load capacitance added. The maximum value varies with
frequency.
• For a 20 MHz crystal the maximum load should be 17 pF.
Temperature sensor accuracy is ±10 °C (was ±5 °C)
Updates to eQADC conversion specifications (operating):
• Offset error without calibration max value is 160 (was 100)
• Full scale gain error without calibration min value is –160 (was –120)
Changes to Platform flash controller electrical characteristics:
• APC, RWSC, WWSC settings vs. frequency of operation table updated
MPC5634M Microcontroller Data Sheet, Rev. 8
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Freescale Semiconductor
Table 40. Revision history (continued)
Revision
Date
Rev. 5
(cont.)
04/2010
Description of Changes
Changes to flash memory specifications:
• TBKPRG 64 KB specification removed (not present in this device)
• T64kpperase specification added
• Flash module life P/E spec for 32 Kbyte blocks also applies to 64 Kbyte blocks
Pad AC specifications (3.3 V) table updated
Rev. 6
04/2010
“Core Voltage Regulator Controller External Components Preferred Configuration” circuit
diagram updated.
• Clarification added to note: Emitter and collector capacitors (6.8 F and 10 F) should
be matched (same type) and ESR should be lower than 200 mW. (Added emphasis
that only 6.8 F emitter capacitors need to be matched with collector capacitor.
• 220 F emitter capacitors changed to 220 nF.
Rev. 7
4/2010
No specification or product information changes:
• Mechanical outline drawings section renamed to “Packages” and restructured.
•
Rev. 8
01/2011
Removed the 208 BGA package from the device-summary table.
Revised the “PMC Operating conditions and external regulators supply voltage” table.
Revised the “PMC electrical characteristics” table.
Revised the pad AC specifications.
Revised the “DC electrical specifications” table.
Revised the “DSPI LVDS pad specification” table:
Revised the “PLLMRFM electrical specifications” table.
Change to “Temperature sensor electrical characteristics” table:
• Accuracy is guaranteed by production test
Revised the “eQADC conversion specifications (operating)” table.
Changes to “Calibration bus operation timing” table:
• CLKOUT period is guaranteed by production test. All other parameters are guaranteed
by design
Changes to “Program and erase specifications” table in “Flash memory electrical
characteristics” section.
• Deleted Bank Program (512KB) (TBKPRG) parameter
• TYP P/E values added for 32- and 64 KB blocks and for 128 KB blocks.
Changes to Recommended operating characteristics for external power transistor:
• VCESAT should be between 200 and 600 mV
• VBE should be 0.4V to 1.0V
Removed footnote 8 from Vddeh in Maximum ratings.
Deleted engineering names for pads in Power UP/DOWN Sequencing Section
Changed “sin_c” to DSPI_C_SIN” and “sck_c” to DSPI_C_SCK” on 144 pin LQFP
package.
Updated the “Electromagnetic Interference Characteristics” table to reflect new parameter
levels, test conditions.
In the “APC, RWSC, WWSC settings vs. frequency of operation” table, changed 82 MHz
entry for WWC from “11” to “01”, added an extra row for “All 111 111 11”
MPC5634M Microcontroller Data Sheet, Rev. 8
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Document Number: MPC5634M
Rev. 8
February 2011
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