NTB35N15 Product Preview Power MOSFET 37 Amps, 150 Volts N–Channel Enhancement–Mode D2PAK http://onsemi.com Features • Source–to–Drain Diode Recovery Time Comparable to a Discrete 37 AMPERES 150 VOLTS 50 m @ VGS = 10 V Fast Recovery Diode • Avalanche Energy Specified • IDSS and RDS(on) Specified at Elevated Temperature • Mounting Information Provided for the D2PAK Package Typical Applications N–Channel • PWM Motor Controls • Power Supplies • Converters D G MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Drain–to–Source Voltage VDSS 150 Vdc Drain–to–Source Voltage (RGS = 1.0 M) VDGR 150 Vdc Gate–to–Source Voltage – Continuous – Non–Repetitive (tp10 ms) VGS VGSM 20 40 Drain Current – Continuous @ TA = 25°C – Continuous @ TA = 100°C – Pulsed (Note 2) Total Power Dissipation @ TA = 25°C Derate above 25°C Total Power Dissipation @ TA = 25°C (Note 1) Operating and Storage Temperature Range Single Pulse Drain–to–Source Avalanche Energy – Starting TJ = 25°C (VDD = 100 Vdc, VGS = 10 Vdc, IL(pk) = 21.6 A, L = 3.0 mH, RG = 25 ) Thermal Resistance – Junction–to–Case – Junction–to–Ambient – Junction–to–Ambient (Note 1) Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds ID ID IDM PD S Vdc MARKING DIAGRAM & PIN ASSIGNMENT Adc 4 Drain 37 23 111 4 1 178 1.43 2.0 Watts W/°C Watts TJ, Tstg –55 to +150 °C EAS 700 mJ 2 D2PAK CASE 418B STYLE 2 0.7 62.5 50 TL 260 1 Gate 2 Drain 3 Source NTB35N15 = Device Code LL = Location Code Y = Year WW = Work Week °C/W RJC RJA RJA NTB35N15 LLYWW 3 ORDERING INFORMATION °C 1. When surface mounted to an FR4 board using the minimum recommended pad size, (Cu. Area 0.412 in2). 2. Pulse Test: Pulse Width = 10 s, Duty Cycle = 2%. Device Package Shipping NTB35N15 D2PAK 50 Units/Rail NTB35N15T4 D2PAK 800/Tape & Reel This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 2002 May, 2002 – Rev. 2 1 Publication Order Number: NTB35N15/D NTB35N15 ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 150 – – 240 – – – – – – 5.0 50 – – ±100 2.0 – 2.9 –8.56 4.0 – – – 0.042 – 0.050 0.120 – 1.55 1.78 gFS – 26 – mhos Ciss – 2275 3200 pF Coss – 450 650 Crss – 90 175 td(on) – 20 35 tr – 125 225 td(off) – 90 175 OFF CHARACTERISTICS Drain–to–Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = 150 Vdc, TJ = 25°C) (VGS = 0 Vdc, VDS = 150 Vdc, TJ = 125°C) IDSS Gate–Body Leakage Current (VGS = ±20 Vdc, VDS = 0) IGSS Vdc mV/°C Adc nAdc ON CHARACTERISTICS Gate Threshold Voltage VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain–to–Source On–State Resistance (VGS = 10 Vdc, ID = 18.5 Adc) (VGS = 10 Vdc, ID = 18.5 Adc, TJ = 125°C) RDS(on) Drain–to–Source On–Voltage (VGS = 10 Vdc, ID = 18.5 Adc) VDS(on) Forward Transconductance (VDS = 10 Vdc, ID = 18.5 Adc) Vdc mV/°C Vdc DYNAMIC CHARACTERISTICS (VDS = 25 Vdc, VGS = 0 Vdc, f=1 1.0 0 MH MHz)) Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 3 & 4) (VDD = 120 Vdc, ID = 37 Adc, VGS = 10 Vdc, Vd RG = 9.1 ) Turn–On Delay Time Rise Time Turn–Off Delay Time Fall Time ns tf – 120 210 Qtot – 70 100 Qgs – 14 – Qgd – 32 – (IS = 37 Adc, VGS = 0 Vdc) (IS = 37 Adc, VGS = 0 Vdc, TJ = 125°C) VSD – – 1.00 0.88 1.5 – Vdc (IS = 37 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ A/s)) trr – 170 – ns ta – 112 – tb – 58 – QRR – 1.14 – (VDS = 120 Vdc, ID = 37 Adc, VGS = 10 Vdc) Vd ) Total Gate Charge Gate–to–Source Charge Gate–to–Drain Charge nC BODY–DRAIN DIODE RATINGS (Note 3) Diode Forward On–Voltage Reverse Recovery Time Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. 4. Switching characteristics are independent of operating junction temperature. http://onsemi.com 2 C NTB35N15 70 70 60 VGS = 5.5 V VGS = 9 V 50 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) 60 VGS = 8 V 40 VGS = 7 V VGS = 5 V 30 20 VDS ≥ 10 V TJ = 25°C VGS = 10 V VGS = 6 V VGS = 4.5 V 10 50 40 30 TJ = 100°C 20 TJ = 25°C 10 TJ = –55°C VGS = 4 V 0 0 1 2 3 4 5 6 7 8 9 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 0 10 2 VGS = 10 V 0.08 TJ = 100°C 0.06 TJ = 25°C 0.02 TJ = –55°C 0 0 10 20 30 40 50 ID, DRAIN CURRENT (AMPS) 60 70 RDS(on), DRAIN–TO–SOURCE RESISTANCE () 0.1 0.04 0.055 TJ = 25°C 0.05 VGS = 10 V 0.045 VGS = 15 V 0.04 0.035 0.03 0 Figure 3. On–Resistance versus Drain Current and Temperature 10 20 30 40 50 ID, DRAIN CURRENT (AMPS) 60 70 Figure 4. On–Resistance versus Drain Current and Gate Voltage 2.5 10,000 VGS = 0 V 2.25 2.0 7 Figure 2. Transfer Characteristics TJ = 150°C ID = 18.5 A VGS = 10 V IDSS, LEAKAGE (nA) RDS(on), DRAIN–TO–SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN–TO–SOURCE RESISTANCE () Figure 1. On–Region Characteristics 3 4 5 6 VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) 1.75 1.5 1.25 1.0 0.75 1000 100 TJ = 100°C 0.5 0.25 0 –50 –25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) 10 150 30 40 50 60 70 80 90 100 110 120 130 140 150 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 5. On–Resistance Variation with Temperature Figure 6. Drain–to–Source Leakage Current versus Voltage http://onsemi.com 3 NTB35N15 POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off–state condition when calculating td(on) and is read at a voltage corresponding to the on–state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG – VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn–on and turn–off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG – VGSP)] td(off) = RG Ciss In (VGG/VGSP) 6000 VDS = 0 V C, CAPACITANCE (pF) 5000 VGS = 0 V TJ = 25°C Ciss 4000 3000 Crss Ciss 2000 1000 0 10 Coss Crss 5 VGS 0 VDS 10 5 15 20 25 GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation http://onsemi.com 4 12 120 QT 8 80 VGS Q1 Q2 60 40 4 2 0 20 ID = 37 A TJ = 25°C 0 10 VDD = 75 V ID = 37 A VGS = 10 V 100 VDS 6 1000 20 30 40 50 QG, TOTAL GATE CHARGE (nC) 60 0 70 td(off) t, TIME (ns) 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) NTB35N15 tf tr 100 td(on) 10 1 Figure 8. Gate–To–Source and Drain–To–Source Voltage versus Total Charge 10 RG, GATE RESISTANCE (OHMS) 100 Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN–TO–SOURCE DIODE CHARACTERISTICS 40 VGS = 0 V TJ = 25°C I S , SOURCE CURRENT (AMPS) 35 30 25 20 15 10 5 0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) 1 Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non–linearly with an increase of peak current in avalanche and peak junction temperature. Although many E–FETs can withstand the stress of drain–to–source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain–to–source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance – General Data and Its Use.” Switching between the off–state and the on–state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) – TC)/(RJC). A Power MOSFET designated E–FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 5 NTB35N15 SAFE OPERATING AREA VGS = 20 V SINGLE PULSE TC = 25°C 100 10 s 100 s 10 1 1 ms 10 ms dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 10 1.0 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 0.1 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 0.1 EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) I D , DRAIN CURRENT (AMPS) 1000 700 ID = 21.6 A 600 500 400 300 200 100 0 25 1000 Figure 11. Maximum Rated Forward Biased Safe Operating Area 150 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature 1.0 D = 0.5 0.2 0.1 0.1 P(pk) 0.05 0.02 t1 0.01 t2 DUTY CYCLE, D = t1/t2 SINGLE PULSE 0.01 0.00001 0.0001 0.001 0.01 t, TIME (s) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) – TC = P(pk) RJC(t) 0.1 Figure 13. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 6 1.0 10 NTB35N15 INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.33 8.38 0.08 2.032 0.42 10.66 0.24 6.096 0.04 1.016 0.12 3.05 0.63 17.02 inches mm http://onsemi.com 7 NTB35N15 SOLDER STENCIL GUIDELINES pattern of the opening in the stencil for the drain pad is not critical as long as it allows approximately 50% of the pad to be covered with paste. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0.008 inches thick and may be made of brass or stainless steel. For packages such as the SC–59, SC–70/SOT–323, SOD–123, SOT–23, SOT–143, SOT–223, SO–8, SO–14, SO–16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or “tombstoning” may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area. The opening for the leads is still a 1:1 registration. Figure 15 shows a typical stencil for the DPAK and D2PAK packages. The ÇÇ ÇÇ ÇÇ ÇÇ ÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÇÇ ÇÇÇ ÇÇÇ ÇÇ ÇÇÇ ÇÇÇ ÇÇÇ SOLDER PASTE OPENINGS STENCIL Figure 15. Typical Stencil for DPAK and D2PAK Packages SOLDERING PRECAUTIONS • When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less. • After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. • Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. • Always preheat the device. • The delta temperature between the preheat and soldering should be 100°C or less.* • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C. • The soldering temperature and time shall not exceed 260°C for more than 10 seconds. * * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. * * Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering. http://onsemi.com 8 NTB35N15 TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177–189°C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joint. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating “profile” for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 “RAMP” 200°C STEP 2 STEP 3 VENT HEATING “SOAK” ZONES 2 & 5 “RAMP” DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 “SOAK” 160°C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205° TO 219°C “SPIKE” PEAK AT 170°C SOLDER JOINT 150°C 150°C 100°C 140°C 100°C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5°C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 16. Typical Solder Heating Profile http://onsemi.com 9 NTB35N15 PACKAGE DIMENSIONS D2PAK CASE 418B–04 ISSUE G C E V W –B– 4 A 1 2 S 3 –T– SEATING PLANE K W J G D H 3 PL 0.13 (0.005) M T B M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 418B-01 THRU 418B-03 OBSOLETE, NEW STANDARD 418B-04. DIM A B C D E F G H J K L M N P R S V STYLE 2: PIN 1. 2. 3. 4. http://onsemi.com 10 INCHES MIN MAX 0.340 0.380 0.380 0.405 0.160 0.190 0.020 0.035 0.045 0.055 0.310 0.350 0.100 BSC 0.080 0.110 0.018 0.025 0.090 0.110 0.052 0.072 0.280 0.320 0.197 REF 0.079 REF 0.039 REF 0.575 0.625 0.045 0.055 GATE DRAIN SOURCE DRAIN MILLIMETERS MIN MAX 8.64 9.65 9.65 10.29 4.06 4.83 0.51 0.89 1.14 1.40 7.87 8.89 2.54 BSC 2.03 2.79 0.46 0.64 2.29 2.79 1.32 1.83 7.11 8.13 5.00 REF 2.00 REF 0.99 REF 14.60 15.88 1.14 1.40 NTB35N15 Notes http://onsemi.com 11 NTB35N15 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: [email protected] JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031 Phone: 81–3–5740–2700 Email: [email protected] ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. N. American Technical Support: 800–282–9855 Toll Free USA/Canada http://onsemi.com 12 NTB35N15/D