TI1 OPA680U/2K5 Wideband, voltage feedback operational amplifier Datasheet

®
OPA680
OPA
680
OPA
680
OPA6
80
Wideband, Voltage Feedback
OPERATIONAL AMPLIFIER With Disable
TM
FEATURES
APPLICATIONS
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WIDEBAND +5V OPERATION: 220MHz (G = 2)
UNITY GAIN STABLE: 400MHz (G = 1)
HIGH OUTPUT CURRENT: 150mA
OUTPUT VOLTAGE SWING: ±4.0V
HIGH SLEW RATE: 1800V/µs
LOW SUPPLY CURRENT: 6.4mA
LOW DISABLED CURRENT: 300µA
ENABLE/DISABLE TIME: 25ns/100ns
DESCRIPTION
VIDEO LINE DRIVER
xDSL LINE DRIVER/RECEIVER
HIGH SPEED IMAGING CHANNELS
ADC BUFFERS
PORTABLE INSTRUMENTS
TRANSIMPEDANCE AMPLIFIERS
ACTIVE FILTERS
drift, guarantees lower maximum supply current than competing products. System power may be reduced further using
the optional disable control pin. Leaving this disable pin
open, or holding it high, will operate the OPA680 normally.
If pulled low, the OPA680 supply current drops to less than
300µA while the output goes to a high impedance state. This
feature may be used for either power savings or to implement video MUX applications.
The OPA680 represents a major step forward in unity gain
stable, voltage feedback op amps. A new internal architecture provides slew rate and full power bandwidth previously
found only in wideband current feedback op amps. A new
output stage architecture delivers high currents with a minimal headroom requirement. These combine to give exceptional single supply operation. Using a single +5V supply,
the OPA680 can deliver a 1V to 4V output swing with over
100mA drive current and 150MHz bandwidth. This combination of features makes the OPA680 an ideal RGB line
driver or single supply ADC input driver.
OPA680 RELATED PRODUCTS
Voltage Feedback
The OPA680’s low 6.4mA supply current is precisely
trimmed at 25°C. This trim, along with low temperature
SINGLES
DUALS
TRIPLES
OPA680
OPA2680
OPA3680
Current Feedback
OPA681
OPA2681
OPA3681
Fixed Gain
OPA682
OPA2682
OPA3682
+5V
3kΩ
+5V
+3.5V
1.2kΩ
Clock
0.1µF
400Ω
50Ω
REFT
DIS
40Ω
0.5Vp-p 0.1µF
VIN
+VS
0.1µF
OPA680
2Vp-p
1.15kΩ
Analog
Input
ADS822
10-Bit
40MSPS
22pF
+2.5V
CM
0.1µF
REFB
Gnd
3kΩ
Single-Supply, High Speed, 10-Bit Digitzer
+1.5V
0.1µF
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
®
©
SBOS083
1997 Burr-Brown Corporation
PDS-1426E
1
Printed in U.S.A. October, 1999
OPA680
SPECIFICATIONS: VS = ±5V
RF = 402Ω, RL = 100Ω, and G = +2, (Figure 1 for AC performance only), unless otherwise noted.
OPA680P, U, N
TYP
PARAMETER
AC PERFORMANCE (Figure 1)
Small Signal Bandwidth
Gain-Bandwidth Product
Bandwidth for 0.1dB Gain Flatness
Peaking at a Gain of +1
Large-Signal Bandwidth
Slew Rate
Rise/Fall Time
Settling Time to 0.02%
0.1%
Harmonic Distortion
2nd Harmonic
3rd Harmonic
Input Voltage Noise
Input Current Noise
Differential Gain
Differential Phase
DC PERFORMANCE(4)
Open-Loop Voltage Gain (AOL )
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Average Bias Current Drift (magnitude)
Input Offset Current
Average Offset Current Drift
INPUT
Common-Mode Input Range (CMIR)(5)
Common-Mode Rejection Ratio (CMRR)
Input Impedance
Differential-Mode
Common-Mode
OUTPUT
Voltage Output Swing
Current Output, Sourcing
Current Output, Sinking
Closed-Loop Output Impedance
DISABLE (Disabled Low)
Power Down Supply Current (+VS)
Disable Time
Enable Time
Off Isolation
Output Capacitance in Disable
Turn On Glitch
Turn Off Glitch
Enable Voltage
Disable Voltage
Control Pin Input Bias Current (VDIS)
POWER SUPPLY
Specified Operating Voltage
Maximum Operating Voltage Range
Max Quiescent Current
Min Quiescent Current
Power Supply Rejection Ratio (+PSRR)
THERMAL CHARACTERISTICS
Specified Operating Range P, U, N Package
Thermal Resistance, θJA
P 8-Pin DIP
U SO-8
N SOT23-6
CONDITIONS
+25°C
G = +1, VO = 0.5Vp-p, RF = 25Ω
G = +2, VO = 0.5Vp-p
G = +10, VO = 0.5Vp-p
G ≥ 10
G = +2, VO < 0.5Vp-p
VO < 0.5Vp-p
G = +2, VO = 5Vp-p
G = +2, 4V Step
G = +2, VO = 0.5V Step
G = +2, VO = 5V Step
G = +2, VO = 2V Step
G = +2, VO = 2V Step
400
220
30
300
30
4
175
1800
1.4
2.8
12
8
G = +2, f = 5MHz, VO = 2Vp-p
RL = 100Ω
RL ≥ 500Ω
RL = 100Ω
RL ≥ 500Ω
f > 1MHz
f > 1MHz
G = +2, NTSC, VO = 1.4Vp, RL = 150
G = +2, NTSC, VO = 1.4Vp, RL = 150
–68
–80
–80
–88
4.8
2.5
0.05
0.03
VO = 0V, RL = 100Ω
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
VCM = 0V
GUARANTEED
+25°C(2)
0°C to
70°C(3)
–40°C to
+85°C(3)
210
20
200
200
20
200
190
20
200
1400
1200
900
–63
–70
–75
–85
5.3
2.8
–62
–68
–73
–83
5.9
3.0
54
58
±1.0
±4.5
+8
+14
±0.1
±0.7
VCM = ±1V
±3.5
59
±3.4
VCM = 0
VCM = 0
190 || 0.6
3.2 || 0.9
No Load
100Ω Load
VO = 0
VO = 0
G = +2, f = 100kHz
±4.0
±3.9
+190
–150
0.03
VDIS = 0
–300
100
25
70
4
±50
±20
3.3
1.8
100
G = +2, 5MHz
G = +2, RL = 150Ω, VIN = 0
G = +2, RL = 150Ω, VIN = 0
VDIS = 0
±3.8
±3.7
+160
–135
MIN/ TEST
MAX LEVEL(1)
MHz
MHz
MHz
MHz
MHz
dB
MHz
V/µs
ns
ns
ns
ns
typ
min
min
min
typ
typ
typ
min
typ
typ
typ
typ
C
B
B
B
C
C
C
B
C
C
C
C
–60
–65
–70
–80
6.1
3.6
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
%
deg
max
max
max
max
max
max
typ
typ
B
B
B
B
B
B
C
C
52
±5.2
±10
+19
–70
±1.0
±1
50
±6.0
±10
+32
–150
±1.2
±1.5
dB
mV
µV/°C
µA
nA/°C
µA
nA/°C
min
max
max
max
max
max
max
A
A
B
A
B
A
B
±3.3
53
±3.2
52
V
dB
min
min
A
A
kΩ || pF
MΩ || pF
typ
typ
C
C
V
V
mA
mA
Ω
min
min
min
min
typ
A
A
A
A
C
typ
typ
typ
typ
typ
typ
typ
min
max
max
C
C
C
C
C
C
C
A
A
A
±3.7
±3.6
+140
–130
±3.6
±3.3
+80
–80
3.5
1.7
160
3.6
1.6
160
3.7
1.5
160
µA
ns
ns
dB
pF
mV
mV
V
V
µA
±6
±6
7.0
6.0
58
±6
7.2
5.3
56
V
V
mA
mA
dB
typ
max
max
min
min
C
A
A
A
A
–40 to +85
°C
typ
C
100
125
150
°C/W
°C/W
°C/W
typ
typ
typ
C
C
C
±5
VS = ±5V
VS = ±5V
Input Referred
56
UNITS
6.4
6.4
65
6.8
6.0
60
Junction-to-Ambient
NOTES: (1) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.
(C) Typical value only for information. (2) Junction Temperature = Ambient for 25°C guaranteed specifications. (3) Junction Temperature = Ambient at low temperature
limit: Junction Temperature = Ambient +23°C at high temperature limit for over temperature guaranteed specifications. (4) Current is considered positive out of node.
VCM is the input common-mode voltage. (5) Tested < 3dB below minimum CMRR specification at ±CMIR limits.
®
OPA680
2
SPECIFICATIONS: VS = +5V
RF = 402Ω, RL = 100Ω to VS /2, G = +2, (Figure 2 for AC performance only), unless otherwise noted.
OPA680P, U, N
TYP
Gain-Bandwidth Product
Bandwidth for 0.1dB Gain Flatness
Peaking at a Gain of +1
Large-Signal Bandwidth
Slew Rate
Rise Time/Fall Time
Settling Time to 0.02%
0.1%
Harmonic Distortion
2nd Harmonic
3rd Harmonic
Input Voltage Noise
Input Current Noise
Differential Gain
Differential Phase
+25°C(2)
–40°C to
+85°C(3)
160
20
200
160
19
190
140
18
180
700
670
550
–55
–66
–66
–76
5.3
2.8
–54
–63
–64
–74
6.0
3.0
54
CONDITIONS
+25°C
G = +1, VO < 0.5Vp-p, RF = ±25Ω
G = +2, VO < 0.5Vp-p
G = +10, VO < 0.5Vp-p
G ≥ 10
G = +2, VO < 0.5Vp-p
VO < 0.5Vp-p
G = +2, VO = 2Vp-p
G = +2, 2V Step
G = +2, VO = 0.5V Step
G = +2, VO = 2V Step
G = +2, VO = 2V Step
G = +2, VO = 2V Step
G = +2, f = 5MHz, VO = 2Vp-p
RL = 100Ω to VS /2
RL ≥ 500Ω to VS /2
RL = 100Ω to VS /2
RL ≥ 500Ω to VS /2
f > 1MHz
f > 1MHz
G = +2, NTSC, VO = 1.4Vp, RL = 150 to VS /2
G = +2, NTSC, VO = 1.4Vp, RL = 150 to VS /2
300
220
25
250
20
5
200
1000
1.6
2.0
12
8
VO = 2.5V, RL = 100Ω to 2.5V
VCM = 2.5V
VCM = 2.5V
VCM = 2.5V
VCM = 2.5V
VCM = 2.5V
VCM = 2.5V
58
±2.0
±6.0
+8
+15
±0.1
±0.6
VCM = 2.5V ±0.5V
1.5
3.5
59
1.6
3.4
56
VCM = 2.5V
VCM = 2.5V
92 || 1.4
2.2 || 1.5
No Load
RL = 100Ω to 2.5V
No Load
RL = 100Ω to 2.5V
4
3.9
1
1.1
+150
–110
0.03
PARAMETER
AC PERFORMANCE (Figure 2)
Small Signal Bandwidth
GUARANTEED
0°C to
70°C(3)
DC PERFORMANCE(4)
Open-Loop Voltage Gain (AOL)
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Average Bias Current Drift (magnitude)
Input Offset Current
Average Offset Current Drift
INPUT
Least Positive Input Voltage(5)
Most Positive Input Voltage(5)
Common-Mode Rejection Ratio (CMRR)
Input Impedance
Differential-Mode
Common-Mode
OUTPUT
Most Positive Output Voltage
Least Positive Output Voltage
Current Output, Sourcing
Current Output, Sinking
Closed-Loop Output Impedance
DISABLE (Disable Low)
Power Down Supply Current (+VS)
Disable Time
Enable Time
Off Isolation
Output Capacitance in Disable
Turn On Glitch
Turn Off Glitch
Enable Voltage
Disable Voltage
Control Pin Input Bias Current (VDIS)
POWER SUPPLY
Specified Single Supply Operating Voltage
Maximum Single Supply Operating Voltage
Max Quiescent Current
Min Quiescent Current
Power Supply Rejection Ratio (+PSRR)
TEMPERATURE RANGE
Specification: P, U, N
Thermal Resistance, θJA
P 8-Pin DIP
U SO-8
N SOT23-6
G =+2, f = 100kHz
VDIS = 0
G = +2, 5MHz
G = +2, RL = 150Ω, VIN = VS /2
G = +2, RL = 150Ω, VIN = VS /2
VDIS = 0
MIN/ TEST
MAX LEVEL(1)
MHz
MHz
MHz
MHz
MHz
dB
MHz
V/µs
ns
ns
ns
ns
typ
min
min
min
typ
typ
typ
min
typ
typ
typ
typ
C
B
B
B
C
C
C
B
C
C
C
C
–51
–59
–62
–71
6.2
3.4
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
%
deg
max
max
max
max
max
max
typ
typ
B
B
B
B
B
B
C
C
52
±7
–10
+18
–52
±1.0
±0.5
50
±8.5
–12
+32
–80
±1.2
±1.0
dB
mV
µV/°C
µA
nA/°C
µA
nA/°C
min
max
max
max
max
max
max
A
A
B
A
B
A
B
1.7
3.3
53
1.8
3.2
52
V
V
dB
max
min
min
A
A
A
kΩ || pF
MΩ || pF
typ
typ
C
C
V
V
V
V
mA
mA
Ω
min
min
min
max
max
min
typ
A
A
A
A
A
A
C
µA
ns
ns
dB
pF
mV
mV
V
V
µA
typ
typ
typ
typ
typ
typ
typ
min
max
typ
C
C
C
C
C
C
C
A
A
C
V
V
mA
mA
dB
typ
max
max
min
typ
C
B
A
A
C
–40 to +85
°C
typ
C
100
125
150
°C/W
°C/W
°C/W
typ
typ
typ
C
C
C
–60
–70
–72
–80
5
2.5
0.06
0.03
–250
100
25
65
4
±50
±20
3.3
1.8
100
3.8
3.7
1.2
1.3
+110
–80
3.6
3.5
1.4
1.5
+110
–70
3.5
3.4
1.5
1.7
+60
–50
3.5
1.7
3.6
1.6
3.7
1.5
12
6.0
4.0
12
6.0
4.0
12
6.0
3.8
5
VS = +5V
VS = +5V
Input Referred
UNITS
5.1
5.1
55
Junction-to-Ambient
NOTES: (1) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.
(C) Typical value only for information. (2) Junction Temperature = Ambient for 25°C guaranteed specifications. (3) Junction Temperature = Ambient at low temperature
limit: Junction Temperature = Ambient +23°C at high temperature limit for over temperature guaranteed specifications. (4) Current is considered positive out of node.
VCM is the input common-mode voltage. (5) Tested < 3dB below minimum CMRR specification at ±CMIR limits.
®
3
OPA680
ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS
Power Supply ............................................................................... ±6.5VDC
Internal Power Dissipation ..................................... See Thermal Analysis
Differential Input Voltage .................................................................. ±1.2V
Input Voltage Range ............................................................................ ±VS
Storage Temperature Range: P, U, N ........................... –40°C to +125°C
Lead Temperature (soldering, 10s) .............................................. +300°C
Junction Temperature (TJ ) ........................................................... +175°C
Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated circuits be handled and stored
using appropriate ESD protection methods.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes
could cause the device not to meet published specifications.
PIN CONFIGURATIONS
Top View
1
8
DIS
Inverting Input
2
7
+VS
Non-Inverting Input
3
6
Output
–VS
4
5
NC
Output
1
6
+VS
–VS
2
5
DIS
Non-Inverting Input
3
4
Inverting Input
6
NC
SOT23-6
4
DIP/SO-8
5
Top View
3
2
1
A80
Pin Orientation/Package Marking
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER(1)
OPA680P
OPA680U
"
OPA680N
"
8-Pin Plastic DIP
SO-8 Surface-Mount
"
6-Pin SOT23-6
"
006
182
"
332
"
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(2)
TRANSPORT
MEDIA
–40°C to +85°C
–40°C to +85°C
"
–40°C to +85°C
"
OPA680P
OPA680U
"
A80
"
OPA680P
OPA680U
OPA680U/2K5
OPA680N/250
OPA680N/3K
Rails
Rails
Tape and Reel
Tape and Reel
Tape and Reel
NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are
available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 3000 pieces of “OPA680N/3K” will get a single
3000-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no
responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice.
No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product
for use in life support devices and/or systems.
®
OPA680
4
TYPICAL PERFORMANCE CURVES: VS = ±5V
At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. See Figure 1.
LARGE-SIGNAL FREQUENCY RESPONSE
SMALL-SIGNAL FREQUENCY RESPONSE
6
VO = 0.5Vp-p
VO = 1Vp-p
VO = 2Vp-p
12
9
0
G = +2
–3
–6
–9
G = +5
–12
–15
6
Gain (3dB/div)
Normalized Gain (3dB/div)
3
15
G = +1
RF = 25Ω
3
VO = 7Vp-p
0
–3
VO = 4Vp-p
–6
G = +10
–18
–9
–21
–12
–15
–24
0.5
10
100
0.5
500
10
Frequency (MHz)
SMALL-SIGNAL PULSE RESPONSE
LARGE-SIGNAL PULSE RESPONSE
G = +2
VO = 5Vp-p
+3
Output Voltage (1V/div)
Output Voltage (100mV/div)
G = +2
VO = 0.5Vp-p
300
200
100
0
–100
–200
+2
+1
0
–1
–2
–3
–300
–4
–400
Time (5ns/div)
Time (5ns/div)
LARGE-SIGNAL DISABLE/ENABLE RESPONSE
4.0
2.0
0
Output Voltage
VO (0.4V/div)
2.0
1.6
0.8
G = +2
VIN = +1V
–45
–50
Feedthrough (5dB/div)
VDIS
VDIS (2V/div)
DISABLED FEEDTHROUGH vs FREQUENCY
6.0
0
500
+4
400
0.4
100
Frequency (MHz)
VDIS = 0
–55
–60
–65
–70
Forward
Reverse
–75
–80
–85
–90
–95
1
Time (50ns/div)
10
100
Frequency (MHz)
®
5
OPA680
TYPICAL PERFORMANCE CURVES: VS = ±5V
(CONT)
At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. See Figure 1.
5MHz 2nd HARMONIC DISTORTION
vs OUTPUT VOLTAGE
5MHz 3rd HARMONIC DISTORTION
vs OUTPUT VOLTAGE
–60
RL = 100Ω
–65
3rd Harmonic Distortion (dBc)
2nd Harmonic Distortion (dBc)
–60
RL = 200Ω
–70
–75
RL = 500Ω
–80
–85
–65
–70
RL = 100Ω
–75
RL = 200Ω
–80
–85
RL = 500Ω
–90
–90
0.1
1
10
0.1
10MHz 2nd HARMONIC DISTORTION
vs OUTPUT VOLTAGE
10MHz 3rd HARMONIC DISTORTION
vs OUTPUT VOLTAGE
–60
3rd Harmonic Distortion (dBc)
–65
RL = 100Ω
–70
RL = 200Ω
–75
RL = 500Ω
–80
–85
RL = 200Ω
–65
RL = 100Ω
–70
–75
–80
RL = 500Ω
–85
–90
–90
0.1
1
0.1
10
1
10
Output Voltage Swing (Vp-p)
Output Voltage Swing (Vp-p)
20MHz 2nd HARMONIC DISTORTION
vs OUTPUT VOLTAGE
20MHz 3rd HARMONIC DISTORTION
vs OUTPUT VOLTAGE
–50
–50
–55
3rd Harmonic Distortion (dBc)
RL = 100Ω
2nd Harmonic Distortion (dBc)
10
Output Voltage Swing (Vp-p)
–60
2nd Harmonic Distortion (dBc)
1
Output Voltage Swing (Vp-p)
RL = 200Ω
–60
RL = 500Ω
–65
–70
–75
–80
RL = 200Ω
–55
RL = 100Ω
–60
–65
–70
RL = 500Ω
–75
–80
0.1
1
10
0.1
Output Voltage Swing (Vp-p)
®
OPA680
1
Output Voltage Swing (Vp-p)
6
10
TYPICAL PERFORMANCE CURVES: VS = ±5V
(CONT)
At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. See Figure 1.
2nd HARMONIC DISTORTION vs FREQUENCY
3rd HARMONIC DISTORTION vs FREQUENCY
–40
VO = 2Vp-p
RL = 100Ω
–45
–50
G = +10
–55
–60
VO = 2Vp-p
RL = 100Ω
–45
3rd Harmonic Distortion (dBc)
2nd Harmonic Distortion (dBc)
–40
G = +5
–65
–70
–75
–80
G = +2
–85
–50
G = +10
–55
–60
–65
G = +5
–70
–75
–80
G = +2
–85
–90
–90
0.1
1
10
20
0.1
1
Frequency (MHz)
10
20
Frequency (MHz)
INPUT VOLTAGE AND CURRENT NOISE DENSITY
TWO-TONE, 3rd-ORDER SPURIOUS LEVEL
100
–40
10
Voltage Noise
3rd-Order Spurious Level (dBc)
Voltage Noise (nV/√Hz)
Current Noise (pA/√Hz)
50MHz
4.8nV/√Hz
Current Noise
2.5pA/√Hz
–50
–60
20MHz
–70
10MHz
–80
Load Power at matched 50Ω load
1
–90
100
1k
10k
100k
1M
10M
–8
–6
–4
Frequency (Hz)
RECOMMENDED RS vs CAPACITIVE LOAD
0
2
4
6
8
10
FREQUENCY RESPONSE vs CAPACITIVE LOAD
12
70
9
Gain-to-Capacitive Load (3dB/div)
80
60
50
RS (Ω)
–2
Single-Tone Load Power (dBm)
40
30
20
10
0
CL = 10pF
G = +2
CL = 22pF
6
3
CL = 47pF
0
VIN
–3
RS
VO
OPA680
–6
402Ω
–9
–12
CL
1kΩ
CL = 100pF
402Ω
–15
1kΩ is optional
–18
10
100
0
Capacitive Load (pF)
100MHz
200MHz
Frequency (20MHz/div)
®
7
OPA680
TYPICAL PERFORMANCE CURVES: VS = ±5V
(CONT)
At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. See Figure 1.
CMRR AND PSRR vs FREQUENCY
OPEN-LOOP GAIN AND PHASE
70
0
60
–30
Open-Loop Phase
80
–PSRR
70
+PSRR
50
–60
Open-Loop Gain
40
–90
30
–120
20
–150
10
–180
20
0
–210
10
–10
–240
60
CMRR
50
40
30
0
–20
10k
100k
1M
10M
100M
–270
10k
100k
1M
Frequency (Hz)
With 1.3kΩ
Pulldown
402Ω
Optional
1.3kΩ
Pulldown
dP
dG
0.1
402Ω
0.075
–5V
0.05
dG
dP
0.025
10
IB
5
VIO
0
IOS
–5
–10
–15
0
1
2
3
–40
4
–20
0
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
5
3
VO (Volts)
2
1
25Ω
Load Line
50Ω Load Line
–1
100Ω Load Line
–2
–3
–4
60
80
100
120
140
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
1W Internal
Power Limit
0
40
200
Output Current Limited
Output Current (50mA/div)
4
20
Ambient Temperature (°C)
Number of 150Ω Loads
10
Sourcing Output Current
Sinking Output Current
150
7.5
Quiescent Supply Current
100
5.0
50
2.5
1W Internal
Power Limit
Output Current Limit
–5
0
–300
–200
–100
0
100
200
300
IO (mA)
–20
0
20
40
60
80
Ambient Temperature (°C)
®
OPA680
0
–40
8
100
120
140
Supply Current (2.5mA/div)
dG/dP (%/degrees)
75Ω
Input Offset Voltage (mV)
Input Bias and Offset Current (µA)
No Pulldown
Video
Loads
OPA680
0.125
1G
TYPICAL DC DRIFT OVER TEMPERATURE
DIS
Video In
0.15
100M
15
+5V
0.175
10M
Frequency (Hz)
COMPOSITE VIDEO dG/dP
0.2
Open-Loop Phase (degrees)
90
Open-Loop Gain (dB)
Power Supply Rejection Ratio (dB)
Common-Mode Rejection Ratio (dB)
100
TYPICAL PERFORMANCE CURVES: VS = +5V
At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted. See Figure 2.
SMALL-SIGNAL FREQUENCY RESPONSE
6
VO = 0.5Vp-p
VO = 0.5Vp-p
9
0
VO = 1Vp-p
6
G = +2
–3
Gain (3dB/div)
Normalized Gain (3dB/div)
3
LARGE-SIGNAL FREQUENCY RESPONSE
12
G = +1
RF = 25Ω
–6
–9
G = +5
–12
–15
3
VO = 2Vp-p
0
–3
VO = 3Vp-p
–6
–9
G = +10
–18
–12
–21
–15
–24
–18
0.5
10
100
500
0.5
10
Frequency (MHz)
SMALL-SIGNAL PULSE RESPONSE
4.1
G = +2
VO = 0.5Vp-p
2.8
Output Voltage (400mV/div)
Output Voltage (100mV/div)
500
LARGE-SIGNAL PULSE RESPONSE
2.9
2.7
2.6
2.5
2.4
2.3
2.2
G = +2
VO = 2Vp-p
3.7
3.3
2.9
2.5
2.1
1.7
1.3
2.1
0.9
Time (5ns/div)
Time (5ns/div)
RECOMMENDED RS vs CAPACITIVE LOAD
FREQUENCY RESPONSE vs CAPACITIVE LOAD
70
12
Gain-to-Capacitive Load (3dB/div)
Noise Gain = 2.6
60
50
RS (Ω)
100
Frequency (MHz)
40
30
20
10
0
CL = 47pF
Signal Gain = +2
Noise Gain = 2.6
9
CL = 10pF
CL = 22pF
6
CL = 100pF
3
+5V
0
–3
0.1µF
714Ω
VI
–6
RS
58Ω
714Ω
714Ω
VO
OPA680
CL
–9
402Ω
–12
402Ω
–15
0.1µF
–18
1
10
100
0
Capacitive Load (pF)
100MHz
200MHz
Frequency (20MHz/div)
®
9
OPA680
TYPICAL PERFORMANCE CURVES: VS = +5V
(CONT)
At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω to VS /2, unless otherwise noted. See Figure 2.
2nd HARMONIC DISTORTION vs FREQUENCY
3rd HARMONIC DISTORTION vs FREQUENCY
–40
VO = 2Vp-p
RL = 100Ω to VS/2
–45
3rd Harmonic Distortion (dBc)
2nd Harmonic Distortion (dBc)
–40
G = +10
–50
–55
G = +5
–60
–65
G = +2
–70
VO = 2Vp-p
RL = 100Ω to VS/2
–45
–50
G = +10
–55
G = +5
–60
–65
–70
–75
G = +2
–75
–80
0.1
1
10
20
0.1
1
Frequency (MHz)
20
3rd HARMONIC DISTORTION vs FREQUENCY
2nd HARMONIC DISTORTION vs FREQUENCY
–40
–40
VO = 2Vp-p
VO = 2Vp-p
–45
–50
3rd Harmonic Distortion (dBc)
2nd Harmonic Distortion (dBc)
10
Frequency (MHz)
RL = 100Ω
–55
–60
RL = 200Ω
–65
–70
RL = 500Ω
–75
–80
–45
–50
RL = 500
–55
–60
RL = 200
–65
RL = 100
–70
–75
–80
0.1
1
10
0.1
20
1
10
20
Frequency (MHz)
Frequency (MHz)
TWO-TONE, 3RD-ORDER SPURIOUS LEVEL
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
10
–40
50MHz
Output Impedance (Ω)
3rd-Order Spurious Level (dBc)
+5V
–45
–50
–55
20MHz
–60
–65
–70
200Ω
OPA680
ZO
1
–5V
402Ω
402Ω
0.1
10MHz
–75
Load Power at Matched 50Ω Load
0.01
–80
–14
–12
–10
–8
–6
–4
–2
0
10k
2
®
OPA680
100k
1M
Frequency (Hz)
Single-Tone Load Power (dBm)
10
10M
100M
APPLICATIONS INFORMATION
matches the 200Ω source resistance seen at the inverting
input (see the DC Accuracy and Offset Control section). In
addition to the usual power supply decoupling capacitors to
ground, a 0.1µF capacitor is included between the two power
supply pins. In practical PC board layouts, this optionaladded capacitor will typically improve the 2nd harmonic
distortion performance by 3dB to 6dB.
WIDEBAND VOLTAGE FEEDBACK OPERATION
The OPA680 provides an exceptional combination of high
output power capability with a wideband, unity gain stable
voltage feedback op amp using a new high slew rate input
stage. Typical differential input stages used for voltage
feedback op amps are designed to steer a fixed-bias current
to the compensation capacitor, setting a limit to the achievable slew rate. The OPA680 uses a new input stage which
places the transconductance element between two input
buffers, using their output currents as the forward signal. As
the error voltage increases across the two inputs, an increasing current is delivered to the compensation capacitor. This
provides very high slew rate (1800V/µs) while consuming
relatively low quiescent current (6.4mA). This exceptional
full power performance comes at the price of a slightly
higher input noise voltage than alternative architectures. The
4.8nV/√Hz input voltage noise for the OPA680 is exceptionally low for this type of input stage.
Figure 2 shows the AC-coupled, gain of +2, single supply
circuit configuration which is the basis of the +5V Specifications and Typical Performance Curves. Though not a “railto-rail” design, the OPA680 requires minimal input and
output voltage headroom compared to other very wideband
voltage feedback op amps. It will deliver a 3Vp-p output
swing on a single +5V supply with >150MHz bandwidth.
The key requirement of broadband single-supply operation is
to maintain input and output signal swings within the useable
voltage ranges at both the input and the output. The circuit
of Figure 2 establishes an input midpoint bias using a simple
resistive divider from the +5V supply (two 698Ω resistors).
The input signal is then AC-coupled into the midpoint
voltage bias. The input voltage can swing to within 1.5V of
either supply pin, giving a 2Vp-p input signal range centered
between the supply pins. The input impedance matching
resistor (59Ω) used for testing is adjusted to give a 50Ω input
load when the parallel combination of the biasing divider
network is included. Again, an additional resistor (50Ω in
this case) is included directly in series with the non-inverting
input. This minimum recommended value provides part of
the DC source resistance matching for the non-inverting
input bias current. It is also used to form a simple parasitic
pole to roll off the frequency response at very high frequencies (>500MHz) using the input parasitic capacitance to
form a bandlimiting pole. The gain resistor (RG) is ACcoupled, giving the circuit a DC gain of +1, which puts the
input DC bias voltage (2.5V) at the output as well. The
Figure 1 shows the DC-coupled, gain of +2, dual power
supply circuit configuration used as the basis of the ±5V
Specifications and Typical Performance Curves. For test
purposes, the input impedance is set to 50Ω with a resistor to
ground and the output impedance is set to 50Ω with a series
output resistor. Voltage swings reported in the specifications
are taken directly at the input and output pins, while output
powers (dBm) are at the matched 50Ω load. For the circuit of
Figure 1, the total effective load will be 100Ω || 804Ω. The
disable control line is typically left open to guarantee normal
amplifier operation. Two optional components are included
in Figure 1. An additional resistor (175Ω) is included in
series with the non-inverting input. Combined with the 25Ω
DC source resistance looking back towards the signal generator, this gives an input bias current cancelling resistance that
+5V
0.1µF
+5V
+VS
6.8µF
+
+
0.1µF
50Ω Source
VI
50Ω Source
175Ω
50Ω
6.8µF
698Ω
DIS
VO
50Ω
0.1µF
50Ω Load
OPA680
0.1µF
VI
59Ω
50Ω
698Ω
DIS
VO
OPA680
100Ω
VS/2
RF
402Ω
RF
402Ω
RG
402Ω
RG
402Ω
+
6.8µF
0.1µF
0.1µF
–5V
FIGURE 2. AC-Coupled, G = +2, Single Supply, Specification and Test Circuit.
FIGURE 1. DC-Coupled, G = +2, Bipolar Supply, Specification and Test Circuit.
®
11
OPA680
output voltage can swing to within 1V of either supply pin
while delivering >100mA output current. A demanding 100Ω
load to a midpoint bias is used in this characterization circuit.
The new output stage circuit used in the OPA680 can deliver
large bipolar output currents into this midpoint load with
minimal crossover distortion, as shown in the +5V supply, 3rd
harmonic distortion plots.
73
VO = 2Vp-p, 10MHz
72
71
SFDR
70
69
SINGLE SUPPLY A/D CONVERTER INTERFACE
68
Most modern, high performance analog-to-digital converters
(such as the Burr-Brown ADS8xx and ADS9xx series) operate
on a single +5V (or lower) power supply. It has been a
considerable challenge for single supply op amps to deliver a
low distortion input signal at the ADC input for signal frequencies exceeding 5MHz. The high slew rate, exceptional output
swing and high linearity of the OPA680 make it an ideal single
supply ADC driver. The circuit on the front page shows one
possible interface. Figure 3 shows the test circuit of Figure 2
modified for a capacitive (A/D) load and with an optional
output pull-down resistor (RB).
67
66
65
0
1
2
3
4
5
6
7
High frequency DDS DACs require a low distortion
output amplifier to retain their SFDR performance into
real-world loads. A single-ended output drive implementation is shown in Figure 5. In this circuit, only one
side of the complementary output drive signal is used.
The diagram shows the signal output current connected
into the virtual ground summing junction of the OPA680,
which is set up as a transimpedance stage or “I-V
converter”. The unused current output of the DAC is
connected to ground. If the DAC requires its outputs
terminated to a compliance voltage other than ground
for operation, the appropriate voltage level may be
applied to the non-inverting input of the OPA680. The
Power supply decoupling not shown
DIS
50Ω
RS
30Ω
VI
1Vp-p
698Ω
50pF
402Ω
402Ω
RB
0.1µF
FIGURE 3. Single-Supply ADC Input Driver.
®
OPA680
2.5V DC
±1V AC
OPA680
59Ω
12
10
HIGH PERFORMANCE DAC TRANSIMPEDANCE
AMPLIFIER
+5V
0.1µF
9
FIGURE 4. SFDR vs IB.
The OPA680 in the circuit of Figure 3 provides >200MHz
bandwidth for a 2Vp-p output swing. Minimal 3rd harmonic
distortion or two-tone, 3rd-order intermodulation distortion
will be observed due to the very low crossover distortion in the
OPA680 output stage. The limit of output Spurious Free
Dynamic Range (SFDR) will be set by the 2nd harmonic
distortion. Without RB, the circuit of Figure 3 measured at
10MHz shows an SFDR of 65dBc. This may be improved by
pulling additional DC bias current (IB) out of the output stage
through the optional RB resistor to ground (the output midpoint
is at 2.5V for Figure 3). Adjusting IB gives the improvement in
SFDR shown in Figure 4. SFDR improvement is achieved for
IB values up to 6mA, with worse performance for higher
values.
698Ω
8
Output Pull-Down Current (mA)
IB
ADC Input
WIDEBAND VIDEO MULTIPLEXING
DC gain for this circuit is equal to RF. At high frequencies,
the DAC output capacitance will produce a zero in the
noise gain for the OPA680 that may cause peaking in the
closed-loop frequency response. CF is added across RF to
compensate for this noise gain peaking. To achieve a flat
transimpedance frequency response, the pole in the feedback network should be set to:
One common application for video speed amplifiers which
include a disable pin is to wire multiple amplifier outputs
together, then select which one of several possible video
inputs to source onto a single line. This simple “Wired-OR
Video Multiplexer” can be easily implemented using the
OP680 as shown in Figure 6.
1/2πRFCF = √GBP/4πRFCD
Typically, channel switching is performed either on sync or
retrace time in the video signal. The two inputs are approximately equal at this time. The “make-before-break” disable
characteristic of the OPA680 ensures that there is always
one amplifier controlling the line when using a wired-OR
circuit like that shown in Figure 6. Since both inputs may be
on for a short period during the transition between channels,
the outputs are combined through the output impedance
matching resistors (82.5Ω in this case). When one channel is
disabled, its feedback network forms part of the output
impedance and slightly attenuates the signal in getting out
onto the cable. The gain and output matching resistor have
been slightly increased to get a signal gain of +1 at the
matched load and provide a 75Ω output impedance to the
cable. The video multiplexer connection (Figure 6) also
insures that the maximum differential voltage across the
inputs of the unselected channel do not exceed the rated
±1.2V maximum for standard video signal levels.
which will give a closed-loop transimpedance bandwidth
f–3dB, of approximately:
f–3dB = √GBP/(2πRFCD)
50Ω
OPA680
High Speed
DAC
VO = IO RF
RF
CF
IO
CD
GBP → Gain Bandwidth
Product (Hz) for the OPA680
The section on Disable Operation shows the turn-on and
turn-off switching glitches using a grounded input for a
single channel is typically less than ±50mV. Where two
outputs are switched (as shown in Figure 6), the output line
is always under the control of one amplifier or the other due
to the “make-before-break” disable timing. In this case, the
switching glitches for two 0V inputs drop to <20mV.
IO
FIGURE 5. DAC Transimpedance Amplifier.
+5V
2kΩ
VDIS
+5V
50Ω
Video 1
DIS
OPA680
75Ω
82.5Ω
–5V
340Ω
402Ω
75Ω Cable
340Ω
+5V
82.5Ω
75Ω
Load
OPA680
50Ω
Video 2
RG-59
402Ω
DIS
75Ω
–5V
2kΩ
FIGURE 6. Two-Channel Video Multiplexer.
®
13
OPA680
+5V
1.87kΩ
0.1µF
137Ω
100pF
DIS
432Ω
VI
4VI
OPA680
1.87kΩ
150pF
5MHz, 2nd-Order
Butterworth Filter
1.5kΩ
500Ω
0.1µF
FIGURE 7. Single-Supply, High Frequency Active Filter.
SINGLE-SUPPLY ACTIVE FILTERS
unpopulated PC board delivered with descriptive documentation. The summary information for these boards is shown
below:
The high bandwidth provided by the OPA680, while operating on a single +5V supply, lends itself well to high
frequency active filter designs. Again, the key additional
requirement is to establish the DC operating point of the
signal near the supply midpoint for highest dynamic range.
Figure 7 shows an example design of a 5MHz low pass
Butterworth filter using the Sallen-Key topology.
Both the input signal and the gain setting resistor are ACcoupled using 0.1µF blocking capacitors (actually giving
bandpass response with the low frequency pole set to 32kHz
for the component values shown). As discussed for Figure 2,
this allows the midpoint bias formed by the two 1.87kΩ
resistors to appear at both the input and output pins. The
midband signal gain is set to +4 (12dB) in this case. The
capacitor to ground on the non-inverting input is intentionally set larger to dominate input parasitic terms. At a gain of
+4, the OPA680 on a single supply will show ~80MHz
small and large signal bandwidth. The resistor values have
been slightly adjusted to account for this limited bandwidth
in the amplifier stage. Tests of this circuit show a precise
5MHz, –3dB point with a maximally flat passband (above
the 32kHz AC-coupling corner), and a maximum stopband
attenuation of 36dB at the amplifier’s –3dB bandwidth of
80MHz.
PACKAGE
OPA680P
OPA680U
OPA680N
8-Pin DIP
8-Pin SO-8
6-Pin SOT23-6
DEM-OPA68xP
DEM-OPA68xU
DEM-OPA6xxN
LITERATURE
REQUEST
NUMBER
MKT-350
MKT-351
MKT-348
Contact the Burr-Brown Applications support line to request
any of these boards.
MACROMODELS AND APPLICATIONS SUPPORT
Computer simulation of circuit performance using SPICE is
often useful when analyzing the performance of analog
circuits and systems. This is particularly true for Video and
RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A
SPICE model for the OPA680 is available through either the
Burr-Brown Internet web page (http://www.burr-brown.com)
or as one model on a disk from the Burr-Brown Applications
Department (1-800-548-6132). The Application Department
is also available for design assistance at this number. These
models do a good job of predicting small-signal AC and
transient performance under a wide variety of operating
conditions. They do not do as well in predicting the harmonic distortion or dG/dP characteristics. These models do
not attempt to distinguish between the package types in their
small-signal AC performance.
DESIGN-IN TOOLS
DEMONSTRATION BOARDS
Several PC boards are available to assist in the initial evaluation of circuit performance using the OPA680 in its three
package styles. All of these are available free as an
®
OPA680
PRODUCT
BOARD
PART
NUMBER
14
OPERATING SUGGESTIONS
to reduce peaking in unity gain (voltage follower) applications. For example, by using a 402Ω feedback resistor along
with a 402Ω resistor across the two op amp inputs, the
voltage follower response will be similar to the gain of +2
response of Figure 2. Further reducing the value of the
resistor across the op amp inputs will further dampen the
frequency response due to increased noise gain.
OPTIMIZING RESISTOR VALUES
Since the OPA680 is a unity gain stable voltage feedback op
amp, a wide range of resistor values may be used for the
feedback and gain setting resistors. The primary limits on
these values are set by dynamic range (noise and distortion)
and parasitic capacitance considerations. For a non-inverting unity gain follower application, the feedback connection
should be made with a 25Ω resistor, not a direct short. This
will isolate the inverting input capacitance from the output
pin and improve the frequency response flatness. Usually,
for G > 1 application, the feedback resistor value should be
between 200Ω and 1.5kΩ. Below 200Ω, the feedback network will present additional output loading which can
degrade the harmonic distortion performance of the OPA680.
Above 1.5kΩ, the typical parasitic capacitance (approximately 0.2pF) across the feedback resistor may cause unintentional band-limiting in the amplifier response.
The OPA680 exhibits minimal bandwidth reduction going
to single supply (+5V) operation as compared with ±5V.
This is because the internal bias control circuitry retains
nearly constant quiescent current as the total supply voltage
between the supply pins is changed.
INVERTING AMPLIFIER OPERATION
Since the OPA680 is a general purpose, wideband voltage
feedback op amp, all of the familiar op amp application
circuits are available to the designer. Inverting operation is
one of the more common requirements and offers several
performance benefits. Figure 8 shows a typical inverting
configuration where the I/O impedances and signal gain
from Figure 1 are retained in an inverting circuit configuration.
A good rule of thumb is to target the parallel combination of
RF and RG (Figure 1) to be less than approximately 300Ω.
The combined impedance RF || RG interacts with the inverting input capacitance, placing an additional pole in the
feedback network and thus, a zero in the forward response.
Assuming a 2pF total parasitic on the inverting node, holding RF || RG < 300Ω will keep this pole above 250MHz. By
itself, this constraint implies that the feedback resistor RF
can increase to several kΩ at high gains. This is acceptable
as long as the pole formed by RF and any parasitic capacitance appearing in parallel is kept out of the frequency range
of interest.
+5V
+
0.1µF
6.8µF
0.1µF
DIS
BANDWIDTH VS GAIN: NON-INVERTING OPERATION
RG
146Ω
Voltage feedback op amps exhibit decreasing closed-loop
bandwidth as the signal gain is increased. In theory, this
relationship is described by the Gain Bandwidth Product
(GBP) shown in the specifications. Ideally, dividing GBP by
the non-inverting signal gain (also called the Noise Gain, or
NG) will predict the closed-loop bandwidth. In practice, this
only holds true when the phase margin approaches 90°, as it
does in high gain configurations. At low gains (increased
feedback factors), most amplifiers will exhibit a more complex response with lower phase margin. The OPA680 is
compensated to give a slightly peaked response in a noninverting gain of 2 (Figure 1). This results in a typical gain
of +2 bandwidth of 220MHz, far exceeding that predicted
by dividing the 300MHz GBP by 2. Increasing the gain will
cause the phase margin to approach 90° and the bandwidth
to more closely approach the predicted value of (GBP/NG).
At a gain of +10, the 30MHz bandwidth shown in the
Typical Specifications agrees with that predicted using the
simple formula and the typical GBP of 300MHz.
50Ω
Source
RO
50Ω
OPA680
50Ω Load
RF
402Ω
RG
200Ω
RM
67Ω
0.1µF
+
6.8µF
–5V
FIGURE 8. Gain of –2 Example Circuit.
In the inverting configuration, three key design consideration must be noted. The first is that the gain resistor (RG)
becomes part of the signal channel input impedance. If input
impedance matching is desired (which is beneficial whenever the signal is coupled through a cable, twisted pair, long
PC board trace or other transmission line conductor), RG
may be set equal to the required termination value and RF
adjusted to give the desired gain. This is the simplest
approach and results in optimum bandwidth and noise performance. However, at low inverting gains, the resultant
feedback resistor value can present a significant load to the
Frequency response in a gain of +2 may be modified to
achieve exceptional flatness simply by increasing the noise
gain to 2.5. One way to do this, without affecting the +2
signal gain, is to add an 804Ω resistor across the two inputs
in the circuit of Figure 1. A similar technique may be used
®
15
OPA680
amplifier output. For an inverting gain of 2, setting RG to
50Ω for input matching eliminates the need for RM but
requires a 100Ω feedback resistor. This has the interesting
advantage that the noise gain becomes equal to 2 for a 50Ω
source impedance—the same as the non-inverting circuits
considered above. However, the amplifier output will now
see the 100Ω feedback resistor in parallel with the external
load. In general, the feedback resistor should be limited to
the 200Ω to 1.5kΩ range. In this case, it is preferable to
increase both the RF and RG values as shown in Figure 8,
and then achieve the input matching impedance with a third
resistor (RM) to ground. The total input impedance becomes
the parallel combination of RG and RM.
show the zero-voltage output current limit and the zerocurrent output voltage limit, respectively. The four quadrants give a more detailed view of the OPA680’s output
drive capabilities, noting that the graph is bounded by a
“Safe Operating Area” of 1W maximum internal power
dissipation. Superimposing resistor load lines onto the plot
shows that the OPA680 can drive ±2.5V into 25Ω or ±3.5V
into 50Ω without exceeding the output capabilities or the
1W dissipation limit. A 100Ω load line (the standard test
circuit load) shows the full ±3.9V output swing capability,
as shown in the typical specifications.
The minimum specified output voltage and current specifications over temperature are set by worst-case simulations at
the cold temperature extreme. Only at cold startup will the
output current and voltage decrease to the numbers shown in
the guaranteed tables. As the output transistors deliver power,
their junction temperatures will increase, decreasing their
VBE’s (increasing the available output voltage swing) and
increasing their current gains (increasing the available output current). In steady-state operation, the available output
voltage and current will always be greater than that shown
in the over-temperature specifications since the output stage
junction temperatures will be higher than the minimum
specified operating ambient.
The second major consideration, touched on in the previous paragraph, is that the signal source impedance becomes
part of the noise gain equation and hence influences the
bandwidth. For the example in Figure 8, the RM value
combines in parallel with the external 50Ω source impedance, yielding an effective driving impedance of 50Ω ||
67Ω = 28.6Ω. This impedance is added in series with RG
for calculating the noise gain (NG). The resultant NG is 2.8
for Figure 8, as opposed to only 2 if RM could be eliminated
as discussed above. The bandwidth will therefore be slightly
lower for the gain of –2 circuit of Figure 8 than for the gain
of +2 circuit of Figure 1.
To maintain maximum output stage linearity, no output
short-circuit protection is provided. This will not normally
be a problem since most applications include a series matching resistor at the output that will limit the internal power
dissipation if the output side of this resistor is shorted to
ground. However, shorting the output pin directly to the
adjacent positive power supply pin (8-pin packages) will, in
most cases, destroy the amplifier. If additional short-circuit
protection is required, consider a small series resistor in the
power supply leads. This will, under heavy output loads,
reduce the available output voltage swing. A 5Ω series
resistor will limit the internal power dissipation to 1W for an
output short circuit while decreasing the available output
voltage swing only 0.5V for up to 100mA desired load
currents. Always place the 0.1µF power supply decoupling
capacitors after these supply current limiting resistors directly on the supply pins.
The third important consideration in inverting amplifier
design is setting the bias current cancellation resistor on the
non-inverting input (RB). If this resistor is set equal to the
total DC resistance looking out of the inverting node, the
output DC error, due to the input bias currents, will be
reduced to (Input Offset Current) • RF. If the 50Ω source
impedance is DC-coupled in Figure 8, the total resistance to
ground on the inverting input will be 228Ω. Combining this
in parallel with the feedback resistor gives the RB = 146Ω
used in this example. To reduce the additional high frequency noise introduced by this resistor, it is sometimes
bypassed with a capacitor. As long as RB <350Ω, the
capacitor is not required since the total noise contribution of
all other terms will be less than that of the op amp’s input
noise voltage. As a minimum, the OPA680 requires an RB
value of 50Ω to damp out parasitic-induced peaking—a
direct short to ground on the non-inverting input runs the
risk of a very high frequency instability in the input stage.
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an A/D converter—including
additional external capacitance which may be recommended
to improve A/D linearity. A high speed, high open-loop gain
amplifier like the OPA680 can be very susceptible to decreased stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin. When
the amplifier’s open-loop output resistance is considered,
this capacitive load introduces an additional pole in the
signal path that can decrease the phase margin. Several
external solutions to this problem have been suggested.
When the primary considerations are frequency response
flatness, pulse response fidelity and/or distortion, the simplest and most effective solution is to isolate the capacitive
OUTPUT CURRENT AND VOLTAGE
The OPA680 provides output voltage and current capabilities that are unsurpassed in a low cost monolithic op amp.
Under no-load conditions at +25°C, the output voltage
typically swings closer than 1V to either supply rail; the
guaranteed swing limit is within 1.2V of either rail. Into a
15Ω load (the minimum tested load), it is guaranteed to
deliver more than ±135mA.
The specifications described above, though familiar in the
industry, consider voltage and current limits separately. In
many applications, it is the voltage • current, or V-I product,
which is more relevant to circuit operation. Refer to the
“Output Voltage and Current Limitations” plot in the Typical Performance Curves. The X and Y axes of this graph
®
OPA680
16
load from the feedback loop by inserting a series isolation
resistor between the amplifier output and the capacitive
load. This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher
frequency. The additional zero acts to cancel the phase lag
from the capacitive load pole, thus increasing the phase
margin and improving stability.
100
90
Series Resistor (Ω)
80
The Typical Performance Curves show the recommended
RS versus capacitive load and the resulting frequency response at the load. Parasitic capacitive loads greater than
2pF can begin to degrade the performance of the OPA680.
Long PC board traces, unmatched cables, and connections to
multiple devices can easily exceed this value. Always consider this effect carefully, and add the recommended series
resistor as close as possible to the OPA680 output pin (see
Board Layout Guidelines).
NG = 4
10
100
Capacitive Load (pF)
FIGURE 10. Required RS vs Noise Gain
DISTORTION PERFORMANCE
The OPA680 provides good distortion performance into a
100Ω load on ±5V supplies. Relative to alternative solutions, it provides exceptional performance into lighter loads
and/or operating on a single +5V supply. Generally, until the
fundamental signal reaches very high frequency or power
levels, the 2nd harmonic will dominate the distortion with a
negligible 3rd harmonic component. Focusing then on the
2nd harmonic, increasing the load impedance improves
distortion directly. Remember that the total load includes the
feedback network; in the non-inverting configuration (Figure 1) this is sum of RF + RG, while in the inverting
configuration, it is just RF. Also, providing an additional
supply decoupling capacitor (0.1µF) between the supply
pins (for bipolar operation) improves the 2nd-order distortion slightly (3dB to 6dB).
R
402Ω
NG = 3
30
1
Power supply decoupling not shown.
VO
OPA680
40
0
+5V
RNG
NG = 2
50
10
175Ω
50Ω
60
20
The criterion for setting this RS resistor is a maximum
bandwidth, flat frequency response at the load. For the
OPA680 operating in a gain of +2, the frequency response
at the output pin is already slightly peaked without the
capacitive load requiring relatively high values of RS to
flatten the response at the load. Increasing the noise gain will
reduce the peaking as described previously. The circuit of
Figure 9 demonstrates this technique, allowing lower values
of RS to be used for a given capacitive load.
50Ω
70
CL
In most op amps, increasing the output voltage swing increases harmonic distortion directly. The new output stage
used in the OPA680 actually holds the difference between
fundamental power and the 2nd and 3rd harmonic powers
relatively constant with increasing output power until very
large output swings are required (>4Vp-p). This also shows
up in the two-tone, 3rd-order intermodulation spurious (IM3)
response curves. The 3rd-order spurious levels are extremely
low at low output power levels. The output stage continues
to hold them low even as the fundamental power reaches
very high levels. As the Typical Performance Curves show,
the spurious intermodulation powers do not increase as
predicted by a traditional intercept model. As the fundamental power level increases, the dynamic range does not decrease significantly. For 2 tones centered at 20MHz, with
10dBm/tone into a matched 50Ω load (i.e., 2Vp-p for each
tone at the load, which requires 8Vp-p for the overall twotone envelope at the output pin), the Typical Performance
Curves show 57dBc difference between the test tone powers
and the 3rd-order intermodulation spurious powers. This
exceptional performance improves further when operating at
lower frequencies.
402Ω
–5V
FIGURE 9. Capacitive Load Driving with Noise Gain Tuning.
This gain of +2 circuit includes a noise gain tuning resistor
across the two inputs to increase the noise gain, increasing
the unloaded phase margin for the op amp. Although this
technique will reduce the required RS resistor for a given
capacitive load, it does increase the noise at the output. It
also will decrease the loop gain, nominally decreasing the
distortion performance. If, however, the dominant distortion
mechanism arises from a high RS value, significant dynamic
range improvement can be achieved using this technique.
Figure 10 shows the required RS versus CLOAD parametric on
noise gain using this technique. This is the circuit of Figure
9 with RNG adjusted to increase the noise gain (increasing
the phase margin) then sweeping CLOAD and finding the
required RS to get a flat frequency response. This plot also
gives the required RS versus CLOAD for the OPA680 operated at higher signal gains.
®
17
OPA680
NOISE PERFORMANCE
as long as the impedances appearing at each op amp input
are limited to the previously recommend maximum value of
300Ω. Keeping both (RF || RG) and the non-inverting input
source impedance less than 300Ω will satisfy both noise and
frequency response flatness considerations. Since the resistor-induced noise is relatively negligible, additional capacitive decoupling across the bias current cancellation resistor
(RB) for the inverting op amp configuration of Figure 8 is not
required.
High slew rate, unity gain stable, voltage feedback op amps
usually achieve their slew rate at the expense of a higher
input noise voltage. The 4.8nV/√Hz input voltage noise for
the OPA680 is, however, much lower than comparable
amplifiers. The input-referred voltage noise, and the two
input-referred current noise terms, combine to give low
output noise under a wide variety of operating conditions.
Figure 11 shows the op amp noise analysis model with all
the noise terms included. In this model, all noise terms are
taken to be noise voltage or current density terms in either
nV/√Hz or pA/√Hz.
DC ACCURACY AND OFFSET CONTROL
The balanced input stage of a wideband voltage feedback op
amp allows good output DC accuracy in a wide variety of
applications. The power supply current trim for the OPA680
gives even tighter control than comparable products. Although the high speed input stage does require relatively
high input bias current (typically 14µA out of each input
terminal), the close matching between them may be used to
reduce the output DC error caused by this current. The total
output offset voltage may be considerably reduced by matching the DC source resistances appearing at the two inputs.
This reduces the output DC error due to the input bias
currents to the offset current times the feedback resistor.
Evaluating the configuration of Figure 1, using worst-case
+25°C input offset voltage and current specifications, gives
a worst-case output offset voltage equal to: – (NG = noninverting signal gain)
ENI
EO
OPA680
RS
IBN
ERS
RF
√ 4kTRS
IBI
RG
4kT
RG
√ 4kTRF
4kT = 1.6E –20J
at 290°K
±(NG • VOS(MAX)) ± (RF • IOS(MAX))
= ±(2 • 4.5mV) ± (402Ω • 0.7µA)
= ±9.3mV
FIGURE 11. Op Amp Noise Analysis Model.
The total output spot noise voltage can be computed as the
square root of the sum of all squared output noise voltage
contributors. Equation 1 shows the general form for the
output noise voltage using the terms shown in Figure 11.
A fine scale output offset null, or DC operating point
adjustment, is often required. Numerous techniques are
available for introducing DC offset control into an op amp
circuit. Most of these techniques eventually reduce to adding
a DC current through the feedback resistor. In selecting an
offset trim method, one key consideration is the impact on
the desired signal path frequency response. If the signal path
is intended to be non-inverting, the offset control is best
applied as an inverting summing signal to avoid interaction
with the signal source. If the signal path is intended to be
inverting, applying the offset control to the non-inverting
input may be considered. However, the DC offset voltage on
the summing junction will set up a DC current back into the
source which must be considered. Applying an offset adjustment to the inverting op amp input can change the noise gain
and frequency response flatness. For a DC-coupled inverting
amplifier, Figure 12 shows one example of an offset adjustment technique that has minimal impact on the signal frequency response. In this case, the DC offsetting current is
brought into the inverting input node through resistor values
that are much larger than the signal path resistors. This will
insure that the adjustment circuit has minimal effect on the
loop gain and hence the frequency response.
Equation 1:
EO =
(E
NI
2
)
+ ( I BN R S ) + 4kTR S NG 2 + ( I BI R F ) + 4kTR F NG
2
2
Dividing this expression by the noise gain (NG = (1+RF /RG))
will give the equivalent input-referred spot noise voltage at
the non-inverting input, as shown in Equation 2.
Equation 2:
I R 2 4kTR F
2
E N = E NI 2 + ( I BN R S ) + 4kTR S +  BI F  +
 NG 
NG
Evaluating these two equations for the OPA680 circuit and
component values shown in Figure 1 will give a total output
spot noise voltage of 11nV/√Hz and a total equivalent input
spot noise voltage of 5.5nV/√Hz. This is including the noise
added by the bias current cancellation resistor (175Ω) on the
non-inverting input. This total input-referred spot noise
voltage is only slightly higher than the 4.8nV/√Hz specification for the op amp voltage noise alone. This will be the case
®
OPA680
18
eventually turning on those two diodes (≈100µA). At this
point, any further current pulled out of VDIS goes through
those diodes holding the emitter-base voltage of Q1 at
approximately zero volts. This shuts off the collector current out of Q1, turning the amplifier off. The supply current
in the disable mode are only those required to operate the
circuit of Figure 13. Additional circuitry ensures that turnon time occurs faster than turn-off time (make-beforebreak).
+5V
Supply Decoupling
Not Shown
0.1µF
OPA680
328Ω
VO
–5V
RG
500Ω
+5V
5kΩ
RF
1kΩ
When disabled, the output and input nodes go to a high
impedance state. If the OPA680 is operating in a gain of +1,
this will show a very high impedance at the output and
exceptional signal isolation. If operating at a gain greater
than +1, the total feedback network resistance (RF + RG)
will appear as the impedance looking back into the output,
but the circuit will still show very high forward and reverse
isolation. If configured as an inverting amplifier, the input
and output will be connected through the feedback network
resistance (RF + RG) and the isolation will be very poor as
a result.
VI
±200mV Output Adjustment
20kΩ
10kΩ
0.1µF
VO
5kΩ
VI
=–
RF
RG
= –2
–5V
FIGURE 12. DC-Coupled, Inverting Gain of –2, with Offset
Adjustment.
One key parameter in disable operation is the output glitch
when switching in and out of the disabled mode. Figure 14
shows these glitches for the circuit of Figure 1 with the
input signal at 0V. The glitch waveform at the output pin is
plotted along with the DIS pin voltage.
DISABLE OPERATION
The OPA680 provides an optional disable feature that may
be used either to reduce system power or to implement a
simple channel multiplexing operation. If the DIS control
pin is left unconnected, the OPA680 will operate normally.
To disable, the control pin must be asserted LOW. Figure 13
shows a simplified internal circuit for the disable control
feature.
Output Voltage (20mV/div)
40
+VS
20
Output Voltage
(0V Input)
0
–20
–40
4.8V
VDIS
0.2V
15kΩ
Time (20ns/div)
Q1
FIGURE 14. Disable/Enable Glitch.
25kΩ
VDIS
The transition edge rate (dv/dt) of the DIS control line will
influence this glitch. For the plot of Figure 14, the edge rate
was reduced until no further reduction in glitch amplitude
was observed. This approximately 1V/ns maximum slew
rate may be achieved by adding a simple RC filter into the
DIS pin from a higher speed logic line. If extremely fast
transition logic is used, a 1kΩ series resistor between the
logic gate and the DIS input pin will provide adequate
bandlimiting using just the parasitic input capacitance on the
DIS pin while still ensuring adequate logic level swing.
110kΩ
IS
Control
–VS
FIGURE 13. Simplified Disable Control Circuit.
In normal operation, base current to Q1 is provided through
the 110kΩ resistor, while the emitter current through the
15kΩ resistor sets up a voltage drop that is inadequate to
turn on the two diodes in Q1’s emitter. As VDIS is pulled
LOW, additional current is pulled through the 15kΩ resistor
®
19
OPA680
THERMAL ANALYSIS
b) Minimize the distance (<0.25") from the power supply
pins to high frequency 0.1µF decoupling capacitors. At the
device pins, the ground and power plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. The power supply
connections should always be decoupled with these capacitors. An optional supply decoupling capacitor (0.1µF) across
the two power supplies (for bipolar operation) will improve
2nd harmonic distortion performance. Larger (2.2µF to
6.8µF) decoupling capacitors, effective at lower frequency,
should also be used on the main supply pins. These may be
placed somewhat farther from the device and may be shared
among several devices in the same area of the PC board.
Due to the high output power capability of the OPA680,
heatsinking or forced airflow may be required under extreme
operating conditions. Maximum desired junction temperature will set the maximum allowed internal power dissipation as described below. In no case should the maximum
junction temperature be allowed to exceed 175°C.
Operating junction temperature (TJ) is given by TA + PD•θJA.
The total internal power dissipation (PD) is the sum of
quiescent power (PDQ) and additional power dissipated in
the output stage (PDL) to deliver load power. Quiescent
power is simply the specified no-load supply current times
the total supply voltage across the part. PDL will depend on
the required output signal and load but would, for a grounded
resistive load, be at a maximum when the output is fixed at
a voltage equal to 1/2 of either supply voltage (for equal
bipolar supplies). Under this condition, PDL = VS2/(4•RL)
where RL includes feedback network loading.
c) Careful selection and placement of external components will preserve the high frequency performance of
the OPA680. Resistors should be a very low reactance type.
Surface-mount resistors work best and allow a tighter overall layout. Metal film or carbon composition axially-leaded
resistors can also provide good high frequency performance.
Again, keep their leads and PC board traces as short as
possible. Never use wirewound type resistors in a high
frequency application. Since the output pin and inverting
input pin are the most sensitive to parasitic capacitance,
always position the feedback and series output resistor, if
any, as close as possible to the output pin. Other network
components, such as non-inverting input termination resistors, should also be placed close to the package. Where
double-side component mounting is allowed, place the feedback resistor directly under the package on the other side of
the board between the output and inverting input pins. Even
with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant
time constants that can degrade performance. Good axial
metal film or surface-mount resistors have approximately
0.2pF in shunt with the resistor. For resistor values >1.5kΩ,
this parasitic capacitance can add a pole and/or zero below
500MHz that can effect circuit operation. Keep resistor
values as low as possible consistent with load driving considerations. The 402Ω feedback used in the typical performance specifications is a good starting point for design.
Note that a 25Ω feedback resistor, rather than a direct short,
is suggested for the unity gain follower application. This
effectively isolates the inverting input capacitance from the
output pin that would otherwise cause an additional peaking
in the gain of +1 frequency response.
Note that it is the power in the output stage and not into the
load that determines internal power dissipation.
As a worst-case example, compute the maximum TJ using an
OPA680N (SOT23-6 package) in the circuit of Figure 1
operating at the maximum specified ambient temperature of
+85°C and driving a grounded 20Ω load.
PD = 10V•7.2mA + 52/(4•(20Ω || 804Ω)) = 392mW
Maximum TJ = +85°C + (0.39W•150°C/W) = 144°C.
Although this is still well below the specified maximum
junction temperature, system reliability considerations may
require lower guaranteed junction temperatures. The highest
possible internal dissipation will occur if the load requires
current to be forced into the output for positive output
voltages or sourced from the output for negative output
voltages. This puts a high current through a large internal
voltage drop in the output transistors. The output V-I plot
shown in the Typical Performance Curves include a boundary for 1W maximum internal power dissipation under these
conditions.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high frequency
amplifier like the OPA680 requires careful attention to
board layout parasitics and external component types. Recommendations that will optimize performance include:
d) Connections to other wideband devices on the board
may be made with short direct traces or through on-board
transmission lines. For short connections, consider the trace
and the input to the next device as a lumped capacitive load.
Relatively wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up around
them. Estimate the total capacitive load and set RS from the
plot of Recommended RS vs Capacitive Load. Low parasitic
capacitive loads (<5pF) may not need an RS since the
OPA680 is nominally compensated to operate with a 2pF
parasitic load. Higher parasitic capacitive loads without an
RS are allowed as the signal gain increases (increasing the
a) Minimize parasitic capacitance to any AC ground for all
of the signal I/O pins. Parasitic capacitance on the output
and inverting input pins can cause instability: on the noninverting input, it can react with the source impedance to
cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be
opened in all of the ground and power planes around those
pins. Otherwise, ground and power planes should be unbroken elsewhere on the board.
®
OPA680
20
INPUT AND ESD PROTECTION
unloaded phase margin) If a long trace is required, and the
6dB signal loss intrinsic to a doubly terminated transmission
line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult
an ECL design handbook for microstrip and stripline layout
techniques). A 50Ω environment is normally not necessary
on board, and in fact, a higher impedance environment will
improve distortion as shown in the distortion versus load
plots. With a characteristic board trace impedance defined
(based on board material and trace dimensions), a matching
series resistor into the trace from the output of the OPA680
is used as well as a terminating shunt resistor at the input of
the destination device. Remember also that the terminating
impedance will be the parallel combination of the shunt
resistor and the input impedance of the destination device;
this total effective impedance should be set to match the
trace impedance. The high output voltage and current capability of the OPA680 allows multiple destination devices to
be handled as separate transmission lines, each with their
own series and shunt terminations. If the 6dB attenuation of
a doubly terminated transmission line is unacceptable, a
long trace can be series-terminated at the source end only.
Treat the trace as a capacitive load in this case and set the
series resistor value as shown in the plot of Recommended
RS vs Capacitive Load. This will not preserve signal integrity as well as a doubly terminated line. If the input impedance of the destination device is low, there will be some
signal attenuation due to the voltage divider formed by the
series output into the terminating impedance.
The OPA680 is built using a very high speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins are protected with
internal ESD protection diodes to the power supplies as
shown in Figure 15.
These diodes provide moderate protection to input overdrive
voltages above the supplies as well. The protection diodes
can typically support 30mA continuous current. Where higher
currents are possible (e.g., in systems with ±15V supply
parts driving into the OPA680), current-limiting series resistors should be added into the two inputs. Keep these resistor
values as low as possible since high values degrade both
noise performance and frequency response.
+V CC
External
Pin
Internal
Circuitry
–V CC
FIGURE 15. Internal ESD Protection.
e) Socketing a high speed part like the OPA680 is not
recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it
almost impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering the OPA680
onto the board. If socketing for the DIP package is desired,
high frequency flush mount pins (e.g., McKenzie Technology #710C) can give good results.
®
21
OPA680
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