Product Folder Sample & Buy Support & Community Tools & Software Technical Documents LMP91200 SNAS571E – JANUARY 2012 – REVISED FEBRUARY 2016 LMP91200 Configurable AFE for Low-Power Chemical-Sensing Applications 1 Features 2 Applications • • • 1 Active Guarding Key Specifications Unless otherwise noted, typical values at TA = 25°C, VS = (VDD-GND) = 3.3 V – pH Buffer Input Bias Current (0 < VINP < 3.3 V) – Maximum at 25°C: ±125 fA – Maximum at 85°C: ±445 fA – pH Buffer Input Bias Current (–500 mV < VINP– VCM < 500 mV), VS = (VDD – GND) = 0 V – Maximum at 25°C: ±600 fA – Maximum at 85°C: ±6.5 pA – pH Buffer Input Offset Voltage: ±200 µV – pH Buffer Input Offset Voltage Drift: ±2.5 μV/°C – Supply Current: 50 μA – Supply Voltage: 1.8 V to 5.5 V – Operating Temperature Range: –40°C to 125°C – Package: 16-Pin TSSOP pH Sensor Platforms 3 Description The LMP91200 device is a sensor AFE for use in low-power, analytical-sensing applications. The LMP91200 is designed for 2-electrode sensors. This device provides all of the functionality needed to detect changes based on a delta voltage at the sensor. Optimized for low-power applications, the LMP91200 works over a voltage range of 1.8 V to 5.5 V. With its extremely low input bias current it is optimized for use with pH sensors. Also, in absence of supply voltage the very low input bias current reduces degradation of the pH probe when connected to the LMP91200. Two guard pins provide support for high parasitic impedance wiring. Depending on the configuration, total current consumption for the device is 50 µA while measuring pH. Available in a 16-pin TSSOP package, the LMP91200 operates from –40°C to +125°C. Device Information(1) PART NUMBER LMP91200 PACKAGE TSSOP (16) BODY SIZE (NOM) 5.00 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application VDD NC LMP91200 VDD MCU GND GND NC VOUT ADC GUARD1 INP ± pH BUFFER + VOCM GUARD2 VREF VCM GND VCM BUFFER GND pH Electrode VCMHI 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMP91200 SNAS571E – JANUARY 2012 – REVISED FEBRUARY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 4 5 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 13 7.1 Overview ................................................................. 13 7.2 Functional Block Diagram ....................................... 14 7.3 Feature Description................................................. 14 8 Application and Implementation ........................ 15 8.1 Application Information............................................ 15 8.2 Typical Application ................................................. 15 9 Power Supply Recommendations...................... 17 10 Layout................................................................... 17 10.1 Layout Guidelines ................................................. 17 10.2 Layout Example .................................................... 17 11 Device and Documentation Support ................. 18 11.1 11.2 11.3 11.4 Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 18 18 18 18 12 Mechanical, Packaging, and Orderable Information ........................................................... 18 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (November 2015) to Revision E • Page Deleted SPI Function ............................................................................................................................................................. 1 Changes from Revision C (March 2013) to Revision D Page • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 • Deleted temperature sensor function. ................................................................................................................................... 1 Changes from Revision B (March 2013) to Revision C • 2 Page Changed layout of National Data Sheet to TI format ........................................................................................................... 17 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMP91200 LMP91200 www.ti.com SNAS571E – JANUARY 2012 – REVISED FEBRUARY 2016 5 Pin Configuration and Functions PW Package 16-Pin TSSOP Top View VDD 1 16 GND NC 2 15 GND NC 3 14 VDD GUARD1 4 13 GND INP 5 12 VOUT GUARD2 6 11 VOCM VCMHI 7 10 GND VCM 8 9 VREF LMP91200 Pin Functions (1) PIN NO. NAME TYPE DESCRIPTION 1 VDD P Positive Power Supply 2 NC A No connect. These pins should be left floating 3 NC A No connect. These pins should be left floating 4 GUARD1 A Active guard pin 5 INP A Noninverting analog input of pH buffer 6 GUARD2 A Active guard pin 7 VCMHI A High Impedance Common-Mode output 8 VCM A Buffered Common-Mode output 9 VREF A Voltage reference input 10 GND G Analog ground 11 VOCM A Output common-mode voltage 12 VOUT A Analog Output 13 GND G Connect to GND 14 VDD P Connect to VDD 15 GND G Connect to GND 16 GND G Connect to GND (1) D = Digital, A = Analog, P = Power, G = GND Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMP91200 3 LMP91200 SNAS571E – JANUARY 2012 – REVISED FEBRUARY 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) (3) MIN MAX UNIT Supply Voltage (VS = VDD – GND) –0.3 6 V Voltage between any two pins –0.3 VDD + 0.3 V 5 mA 150 °C 150 °C Current out at any pin Junction Temperature (4) Storage Temperature, Tstg (1) (2) (3) (4) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. For soldering specifications see product folder at www.ti.com and SNOA549. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. The maximum power dissipation is a function of TJ(MAX), RθJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA)/RθJA. All numbers apply for packages soldered directly onto a PCB. 6.2 ESD Ratings VALUE V(ESD) (1) (2) (3) Electrostatic discharge (1) Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (2) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (3) ±1000 Machine Model ±150 UNIT V Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX Supply Voltage (VS = VDD – GND) 1.8 5.5 UNIT V Temperature –40 125 °C 6.4 Thermal Information LMP91200 THERMAL METRIC (1) PW (TSSOP) UNIT 16 PINS RθJA (1) 4 Junction-to-ambient thermal resistance 31 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMP91200 LMP91200 www.ti.com SNAS571E – JANUARY 2012 – REVISED FEBRUARY 2016 6.5 Electrical Characteristics Unless otherwise specified, all limits specified for TA = 25°C. VS = (VDD – GND) = 3.3 V. VREF = 3.3 V. (1) (2) (3) PARAMETER MIN (4) TEST CONDITIONS TYP (5) MAX (4) 50 54 UNIT POWER SUPPLY Supply Current (6) (7) pH measurement mode AolpH Open-loop Gain INP = 1.65 V, 300 mV = VOUT = VDD – 300 mV VospH Input Voltage Offset (6) INP = 1/2 VREF TcVospH Input offset voltage drift (8) (9) INP = 1/2 VREF VOSpH_drift Long-term VOSpH drift (10) 500 hours OPL Is at the temperature extremes µA 59 pH BUFFER IbpH Input bias current at INP (9) (9) 120 at the temperature extremes at the temperature extremes dB 90 –200 200 –350 350 –2.5 µV 2.5 uV/°C 150 µV 0 V < INP < 3.3 V –125 125 0 V < INP < 3.3 V, 85°C –445 445 fA 0 V < INP < 3.3 V, 125°C –1.5 1.5 pA –500 mV < (INP – VCM) < 500 mV, VS = 0 V. –600 600 fA –500 mV < (INP – VCM) < 500 mV, 85°C, VS = 0 V. –6.5 6.5 pA –500 mV < (INP – VCM) < 500 mV, 125°C, VS = 0 V. –100 100 pA CL = 10 pF, RL = 1 MΩ fA GBWPpH Gain Bandwidth Product CMRRpH DC_Common-mode rejection INP = 1/2 VREF ratio PSRRpH DC_Power supply rejection ratio 1.8 V < VDD < 5 V INP = 1/2 VREF En_RMSpH Input referred noise (low frequency) (9) Integrated 0.1 Hz to 10 Hz 2.6 µVPP enpH Input referred noise (high frequency) (9) f = 1 kHz 90 nV/√Hz Sourcing, Vout to GND, INP = 1.65 V IscpH Output short circuit current (11) Sinking, Vout to VDD, INP = 1.65 V 220 KHz 80 dB 80 dB 13 at the temperature extremes mA 10 12 at the temperature extremes 8 mA (1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ >TA. (2) Positive current corresponds to current flowing into the device. (3) The voltage on any pin should not exceed 6 V relative to any other pins. (4) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using the Statistical Quality Control (SQC) method. (5) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped production material. (6) Boldface limits are production tested at 125°C. Limits are specified through correlations using the Statistical Quality Control (SQC) method. (7) Excluding all currents which flows out from the device. (8) Offset voltage average drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change. (9) This parameter is specified by design and/or characterization and is not tested in production. (10) Offset voltage long term drift is determined by dividing the change in VOS at time extremes of OPL procedure by the length of the OPL procedure. OPL procedure: 500 hours at 150°C are equivalent to about 15 years. (11) The short circuit test is a momentary open-loop test. Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMP91200 5 LMP91200 SNAS571E – JANUARY 2012 – REVISED FEBRUARY 2016 www.ti.com Electrical Characteristics (continued) Unless otherwise specified, all limits specified for TA = 25°C. VS = (VDD – GND) = 3.3 V. VREF = 3.3 V.(1)(2)(3) PARAMETER MIN (4) TEST CONDITIONS TYP (5) MAX (4) UNIT VCM BUFFER VCMHI_acc VCMHI accuracy Tc_VCMHI VCMHI temperature coefficient (9) (12) VCMHI_acc_VREF VCMHI_acc vs. VREF (9) (13) RoutVCMHI –1.6 1.6 mV –40°C < TA < 125°C –18 –5 8 µV/°C 1.8 V < VREF < 5 V –500 –100 300 µV/V VCMHI Output Impedance (9) VCMHI = 1/2 VREF 250 KΩ 120 AolVCM Open-loop Gain (6) VCMHI = 1/2 VREF, 300 mV < VCM < VDD – 300 mV VosVCM (VCM – VCMHI) (6) VCMHI = 1/2 VREF TcVosVCM Input offset voltage drift (VCM-VCMHI) (8) (9) VCMHI = 1/2 VREF ZoutVCM Output Impedance (9) f = 1 KHz PSRRVCM DC_Power supply rejection ratio 1.8 V < VDD < 5 V, VCMHI = 1/2 VREF En_RMSVCM Input referred noise (low frequency) (9) Integrated 0.1 Hz to 10 Hz 2.6 µVPP enVCM Input referred noise (high frequency) (9) f = 1 KHz 90 nV/√Hz Sourcing, Vout to GND VCMHI = 1/2 VREF IscVCM Output short circuit current (11) Sinking, Vout to VDD VCMHI = 1/2 VREF at the temperature extremes at the temperature extremes dB 90 –200 200 –350 350 –2.5 2.5 µV µV/°C Ω 4 80 dB 16 at the temperature extremes 10 12 at the temperature extremes mA 8 (12) VCMHI voltage average drift is determined by dividing the change in VCMHI at the temperature extremes by the total temperature change. (13) VCMHI_acc vs. VREF is determined by dividing the change in VCMHI_acc at the VREF extremes by the total VREF change. 6 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMP91200 LMP91200 www.ti.com SNAS571E – JANUARY 2012 – REVISED FEBRUARY 2016 Electrical Characteristics (continued) Unless otherwise specified, all limits specified for TA = 25°C. VS = (VDD – GND) = 3.3 V. VREF = 3.3 V.(1)(2)(3) PARAMETER MIN (4) TEST CONDITIONS TYP (5) MAX (4) UNIT PGA VosPGA Input Voltage Offset (6) +IN_PGA (Internal node) = at the temperature 500 mV extremes TcVosPGA Input offset voltage drift (9) (8) +IN_PGA (Internal node) = 500 mV +IN_PGA (Internal node) = 500 mV –275 275 –480 480 –2.5 µV 2.5 uV/°C 120 AolPGA Open loop Gain AvPGA Gain Av_accPGA Gain accuracy at the temperature extremes En_RMSPGA Input referred noise (low frequency) (9) Integrated 0.1 Hz to 10 Hz 2.6 µVPP enPGA Input referred noise (high frequency) (9) f = 1 kHz 90 nV/√Hz PSRRPGA DC_Power supply rejection ratio 1.8 V < VDD < 5 V, +IN_PGA (Internal node) = 500 mV IscPGA Output short circuit current (11) at the temperature extremes dB 90 5 Sourcing, Vout to GND +IN_PGA (Internal node) = 500 mV Sinking, Vout to VDD +IN_PGA (Internal node) = 500 mV -1.3% V/V 1.3% 80 dB 16 at the temperature extremes 10 12 at the temperature extremes mA 8 REFERENCE INPUT RinVREF Input impedance (9) 500 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMP91200 KΩ 7 LMP91200 SNAS571E – JANUARY 2012 – REVISED FEBRUARY 2016 www.ti.com 6.6 Typical Characteristics Unless otherwise specified, TA= 25°C, VS= (VDD – GND) = 3.3 V, VREF = 3.3 V. 100 500 Average Average -31 Average +31 60 300 40 200 20 0 -20 -40 100 0 -100 -200 -60 -300 -80 -400 TA=25°C -100 0.0 0.5 1.0 1.5 2.0 INP (V) 2.5 3.0 240 3.5 -0.50 5 Average Average -31 Average +31 INPUT BIAS (pA) INPUT BIAS (fA) 0 -60 -120 2 1 0 -1 -2 -180 -3 -240 -4 TA=85°C -300 0.5 1.0 1.5 2.0 INP (V) 2.5 3.0 3.5 -0.50 80 Average Average -31 Average +31 0 -200 -400 0.50 40 INPUT BIAS (pA) INPUT BIAS (fA) 200 0.00 0.25 INP-VCM (V) Average Average -31 Average +31 60 400 -0.25 Figure 4. pH Buffer Input Bias Current vs VINP - Device OFF 600 20 0 -20 -40 -600 -60 -800 TA=125°C -1000 0.5 1.0 1.5 2.0 INP (V) 2.5 3.0 TA=125°C -80 3.5 Figure 5. pH Buffer Input Bias Current vs VINP - Device ON 8 TA=85°C -5 Figure 3. pH Buffer Input Bias Current vs VINP - Device ON 0.0 0.50 3 60 800 0.00 0.25 INP-VCM (V) Average Average -31 Average +31 4 120 1000 -0.25 Figure 2. pH Buffer Input Bias Current vs VINP - Device OFF 180 0.0 TA=25°C -500 Figure 1. pH Buffer Input Bias Current vs VINP - Device ON 300 Average Average -31 Average +31 400 INPUT BIAS (fA) INPUT BIAS (fA) 80 -0.50 -0.25 0.00 0.25 INP-VCM (V) 0.50 Figure 6. pH Buffer Input Bias Current vs VINP - Device OFF Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMP91200 LMP91200 www.ti.com SNAS571E – JANUARY 2012 – REVISED FEBRUARY 2016 Typical Characteristics (continued) Unless otherwise specified, TA= 25°C, VS= (VDD – GND) = 3.3 V, VREF = 3.3 V. 500 5 Average Average -31 Average +31 400 3 INPUT BIAS (pA) INPUT BIAS (fA) 300 200 100 0 -100 -200 2 1 INP-VCM = 100mV 0 -1 INP-VCM = -100mV -2 -300 -3 -400 -4 INP=1.65V -500 -5 25 45 65 85 105 TEMPERATURE (°C) 125 25 Figure 7. pH Buffer Input Bias Current vs Temp - Device ON 50 75 100 TEMPERATURE (°C) 125 Figure 8. pH Buffer Input Bias Current vs Temp - Device OFF 35 18 UNITS TESTED > 5000 UNITS TESTED > 5000 30 PERCENTAGE (%) 15 PERCENTAGE (%) Average Average -31 Average +31 4 12 9 6 25 20 15 10 3 5 0 -200 -150 -100 -50 0 0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 50 100 150 200 VOSPH ( V) TCVOSPH ( V/°C) Figure 9. pH Buffer Input Voltage Offset Figure 10. pH Buffer TCVOS 100 110 VDD=1.8V VDD=3.3V VDD=5V 105 PSRR (dB) 105 95 90 100 95 85 90 80 -50 -25 0 25 50 75 100 125 Figure 11. pH Buffer DC CMRR vs Temperature -50 -25 0 25 50 75 TEMPERATURE (°C) 100 125 Figure 12. pH Buffer DC PSRR vs Temperature Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMP91200 9 LMP91200 SNAS571E – JANUARY 2012 – REVISED FEBRUARY 2016 www.ti.com Typical Characteristics (continued) Unless otherwise specified, TA= 25°C, VS= (VDD – GND) = 3.3 V, VREF = 3.3 V. 125 INTEGRATED NOISE (500nV/DIV) 100 75 VOSPH ( V) 50 25 0 -25 -50 -75 -100 -125 1 10 100 OPL TIME (h) TIME (1s/DIV) Figure 13. pH Buffer Time Domain Voltage Noise Figure 14. pH Buffer Input Offset Voltage Drift 100 120 90 110 80 100 CMRR (dB) CMRR (dB) VDD=VREF=3.3V 70 80 50 70 40 VDD=VREF=3.3V 90 60 0.00 1k 60 0.08 0.16 0.24 INP (V) 0.32 0.40 2.9 Figure 15. pH Buffer CMRR vs VINP - Lower Rail 3.0 3.1 INP (V) 3.2 3.3 Figure 16. pH Buffer CMRR vs VINP - upper rail 120 120 VDD=VREF=5V VDD=VREF=5V 110 CMRR (dB) CMRR (dB) 110 100 100 90 80 90 70 80 0.00 60 0.12 0.24 0.36 INP (V) 0.48 0.60 Figure 17. pH Buffer CMRR vs VINP - lower rail 10 4.4 4.5 4.6 4.7 4.8 INP (V) 4.9 5.0 Figure 18. pH Buffer CMRR vs VINP - upper rail Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMP91200 LMP91200 www.ti.com SNAS571E – JANUARY 2012 – REVISED FEBRUARY 2016 Typical Characteristics (continued) Unless otherwise specified, TA= 25°C, VS= (VDD – GND) = 3.3 V, VREF = 3.3 V. 90 90 INP=1.65V 80 85 80 60 PSRR (dB) CMRR (dB) 70 75 50 40 70 30 20 65 10 60 0 10 100 1k 10k FREQUENCY (Hz) 100k 10 Figure 19. pH Buffer CMRR vs Frequency 10k Figure 20. pH Buffer PSRR vs Frequency 15 40 UNITS TESTED > 5000 PERCENTAGE (%) 9 6 UNITS TESTED > 5000 35 12 PERCENTAGE (%) 100 1k FREQUENCY (Hz) 30 25 20 15 10 3 5 0 -200 -150 -100 -50 0 0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 50 100 150 200 VOSVCM ( V) TCVOSVCM ( V/°C) Figure 21. VCM Buffer Input Voltage Offset Figure 22. VCM Buffer TCVOS 110 105 VDD=1.8V VDD=3.3V VDD=5V 105 PSRR (dB) CMRR (dB) 100 95 100 90 95 85 90 -50 -25 0 25 50 75 TEMPERATURE (°C) 100 125 Figure 23. VCM Buffer DC CMRR vs Temperature -50 -25 0 25 50 75 TEMPERATURE (°C) 100 125 Figure 24. VCM Buffer DC PSRR vs Temperature Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMP91200 11 LMP91200 SNAS571E – JANUARY 2012 – REVISED FEBRUARY 2016 www.ti.com Typical Characteristics (continued) Unless otherwise specified, TA= 25°C, VS= (VDD – GND) = 3.3 V, VREF = 3.3 V. 90 VCMHI=1.65V INTEGRATED NOISE (500nV/DIV) 80 PSRR (dB) 70 60 50 40 30 20 10 10 TIME (1s/DIV) Figure 25. VCM Buffer Time Domain Voltage Noise 0.30 VCMHI=1/2VREF 0.25 0.25 0.20 0.20 ERROR (%) ERROR (%) VCMHI=1/2VREF 0.15 0.10 0.05 0.15 0.10 0.05 0.00 0.00 -0.05 -0.05 -0.10 -0.10 -25 0 25 50 75 TEMPERATURE (°C) 100 125 1.8 2.2 2.6 3.0 3.4 3.8 4.2 4.6 5.0 SUPPLY VOLTAGE (V) Figure 27. VCMHI Error vs Temp Figure 28. VCMHI Error vs Supply Voltage 15 30 UNITS TESTED >5000 +IN_PGA=500mV 27 UNITS TESTED >5000 +IN_PGA=500mV 24 PERCENTAGE (%) 12 PERCENTAGE (%) 10k Figure 26. VCM Buffer PSRR vs Frequency 0.30 -50 100 1k FREQUENCY (Hz) 9 6 3 21 18 15 12 9 6 3 0 0 -275-220-165-110 -55 0 55 110 165 220 275 VOSPGA( V) Figure 29. PGA Input Voltage Offset 12 Submit Documentation Feedback -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 TCVOSPGA( V/°C) Figure 30. PGA TCVOS Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMP91200 LMP91200 www.ti.com SNAS571E – JANUARY 2012 – REVISED FEBRUARY 2016 Typical Characteristics (continued) Unless otherwise specified, TA= 25°C, VS= (VDD – GND) = 3.3 V, VREF = 3.3 V. 50 +IN_PGA=500mV SUPPLY CURRENT ( A) 105.0 PSRR (dB) 102.5 100.0 97.5 95.0 45 40 35 92.5 30 90.0 -50 -25 -50 0 25 50 75 100 125 TEMPERATURE (°C) -25 0 25 50 75 TEMPERATURE (°C) 100 125 Figure 32. Supply Current vs Temperature Figure 31. PGA DC PSRR vs Temperature SUPPLY CURRENT ( A) 50 45 40 35 30 1.5 2.0 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 5.0 Figure 33. Supply Current vs Supply Voltage 7 Detailed Description 7.1 Overview The LMP91200 is a sensor AFE for use in low-power, analytical-sensing applications. The LMP91200 is designed for 2-electrode sensors. This device provides all of the functionality needed to detect changes based on a delta voltage at the sensor. Optimized for low-power applications, the LMP91200 works over a voltage range of 1.8 V to 5.5 V. With its extremely low input bias current, it is optimized for use with pH sensors. Also, in the absence of supply voltage, the very low input bias current reduces degradation of the pH probe when connected to the LMP91200. Two guard pins provide support for high parasitic impedance wiring. Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMP91200 13 LMP91200 SNAS571E – JANUARY 2012 – REVISED FEBRUARY 2016 www.ti.com 7.2 Functional Block Diagram VDD LMP91200 VOUT GUARD1 INP ± pH BUFFER + VOCM GUARD2 VREF VCM VCM BUFFER GND VCMHI 7.3 Feature Description 7.3.1 pH Buffer The pH Buffer is a unity gain buffer with a input bias current in the range of tens fA at room temperature. Its very low bias current introduces a negligible error in the measurement of the pH. The ph buffer is provided with 2 guard pins (GUARD1, GUARD2) in order to minimize the leakage of the input current and to make the design of a guard ring easy. 7.3.2 VCM Buffer Both buffered and unbuffered version of the common-mode voltage are available respectively at the VCM pin and VCMHI pin. A copy of the buffered version is present at VOCM pin in case of differential measurement. 14 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMP91200 LMP91200 www.ti.com SNAS571E – JANUARY 2012 – REVISED FEBRUARY 2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information 8.1.1 Theory of pH Measurement The pH electrode measurements are made by comparing the readings in a sample with the readings in standards whose pH has been defined (buffers). When a pH sensing electrode comes in contact with a sample, a potential develops across the sensing membrane surface and that membrane potential varies with pH. A reference electrode provides a second, unvarying potential to quantitatively compare the changes of the sensing membrane potential. These days, pH electrodes are composed of a sensing electrode with the reference electrode built into the same electrode body, and they are called combination electrodes. A high input impedance meter serves as the readout device and calculates the difference between the reference electrode and sensing electrode potentials in millivolts. The millivolts are then converted to pH units according to the Nernst equation. Electrode behavior is described by the Nernst equation: E = Eo + (2.3 RT/nF) log aH+ where • • • • E is the measured potential from the sensing electrode, Eo is related to the potential of the reference electrode, (2.3 RT/nF) is the Nernst factor, log aH+ is the pH, (aH+ = activity of Hydrogen ions). (1) 2.3 RT/nF includes the Gas Law constant (R), Faraday’s constant (F), the temperature in degrees Kelvin (T) and the stoichiometric number of ions involved in the process (n). For pH, where n = 1, the Nernst factor is 2.3 RT/F. Because R and F are constants, the factor and therefore electrode behavior is dependent on temperature. The Nernst Factor is equivalent to the electrode slope which is a measure of the electrode response to the ion being detected. When the temperature is 25°C, the theoretical Nernst slope is 59.16 mV/pH unit. 8.2 Typical Application VDD NC LMP91200 VDD MCU GND GND NC VOUT ADC GUARD1 INP ± pH BUFFER + VOCM GUARD2 VREF VCM GND VCM BUFFER GND pH Electrode VCMHI Figure 34. Typical Application Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMP91200 15 LMP91200 SNAS571E – JANUARY 2012 – REVISED FEBRUARY 2016 www.ti.com Typical Application (continued) 8.2.1 Design Requirements 8.2.1.1 pH Measurement The output of a pH electrode ranges from 415 mV to −415 mV as the pH changes from 0 to 14 at 25°C. The output impedance of a pH electrode is extremely high, ranging from 10 MΩ to 1000 MΩ. The low input bias current of the LMP91200 allows the voltage error produced by the input bias current and electrode resistance to be minimal. For example, if the output impedance of the pH electrode used is 10 MΩ and an operational amplifier with 3 nA of Ibias is used, the error caused due to the input bias current of the amplifier and the source resistance of the pH electrode is 30 mV! This error can be greatly reduced to 1.25 µV by using the LMP91200. The pH measurement with the LMP91200 is straightforward. The pH electrode must be connected between the VCM pin and the INP pin. The voltage at the VCM pin represents the internal zero of the system so the potential of the electrode (voltage at INP pin) will be referred to the VCM voltage. 8.2.2 Detailed Design Procedure The LMP91200 is configured to execute a pH measurement as described in the pH Measurement section. 8.2.3 Application Curves 0.10 PGA Gain = 5V/V INTEGRATED NOISE (500nV/DIV) 0.08 GAIN ERROR (%) 0.06 0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 -50 -25 0 25 50 75 TEMPERATURE (°C) 100 125 TIME (1s/DIV) Figure 35. PGA Gain Error vs Temp Figure 36. PGA Time Domain Voltage Noise 90 80 +INPGA=100mV PSRR (dB) 70 60 50 40 30 20 10 0 10 100 1k FREQUENCY (Hz) 10k Figure 37. PGA PSRR vs Frequency 16 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMP91200 LMP91200 www.ti.com SNAS571E – JANUARY 2012 – REVISED FEBRUARY 2016 9 Power Supply Recommendations VDD should be bypassed with 10-µF, 1-µF and 0.1-µF capacitors, placed as close as possible to the LMP91200 VDD pin (pin 1). An LDO is recommended for the supply rail, but a DC-DC switcher may be used if sufficient filtering is used to attenuate the switching frequency components. 10 Layout 10.1 Layout Guidelines Due to the high impedance of the ph Electrode in the pH measurement, careful circuit layout and assembly are required. Guarding techniques are highly recommended to reduce parasitic leakage current by isolating the input of the LMP91200 from large voltage gradients across the PCB. A guard is a low impedance conductor that surrounds an input line and its potential is raised to the voltage of the input line. The input pin should be fully guarded as shown in Figure 38. The guard traces should completely encircle the input connections. In addition, they should be located on both sides of the PCB and be connected together. The LMP91200 makes the guard ring easy to be implemented without any other external operational amplifier. The ring needs to be connected to the guard pins (GUARD1 and GUARD2), which are at the same potential as that of the INP pin. Solder mask should not cover the input and the guard area, including guard traces on either side of the PCB. Sockets are not recommended as they can be a significant leakage source. After assembly, a thorough cleaning using commercial solvent is necessary. Figure 38 shows a typical guard ring circuit when the LMP912000 is interfaced to a pH probe through a triaxial cable/connector (usually referred to as triax). The signal conductor and the guard of the triax should be kept at the same potential. Therefore, the leakage current between them is practically zero. Because the triax has an extra layer of insulation and a second conducting sheath, it offers greater rejection of interference than coaxial cable or connector. 10.2 Layout Example Figure 38. Circuit Board Guard Layout Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMP91200 17 LMP91200 SNAS571E – JANUARY 2012 – REVISED FEBRUARY 2016 www.ti.com 11 Device and Documentation Support 11.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.2 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 18 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Product Folder Links: LMP91200 PACKAGE OPTION ADDENDUM www.ti.com 9-Mar-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LMP91200MT/NOPB ACTIVE TSSOP PW 16 92 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR LMP912 00MT LMP91200MTX/NOPB ACTIVE TSSOP PW 16 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR LMP912 00MT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 18-Dec-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device LMP91200MTX/NOPB Package Package Pins Type Drawing TSSOP PW 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 18-Dec-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMP91200MTX/NOPB TSSOP PW 16 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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