CY62146E MoBL 4-Mbit (256K x 16) Static RAM Features applications such as cellular telephones. The device also has an automatic power down feature that reduces power consumption when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99% when deselected (CE HIGH). The input and output pins (I/O0 through I/O15) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) or during a write operation (CE LOW and WE LOW). ■ Very high speed: 45 ns ■ Wide voltage range: 4.5 V to 5.5 V ■ Ultra low standby power ❐ Typical standby current: 1 A ❐ Maximum standby current: 7 A ■ Ultra low active power ❐ Typical active current: 2 mA at f = 1 MHz ■ Easy memory expansion with CE and OE features ■ Automatic power down when deselected ■ Complementary metal oxide semiconductor (CMOS) for optimum speed and power ■ Available in Pb-free 44-pin thin small outline package (TSOP) II package To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See Table for a complete description of read and write modes. Functional Description The CY62146E is a high performance CMOS static RAM organized as 256K words by 16 bits. This device features advanced circuit design to provide ultra low active current. It is ideal for providing More Battery Life (MoBL) in portable Logic Block Diagram SENSE AMPS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS 256K x 16 RAM Array I/O0–I/O7 I/O8–I/O15 Cypress Semiconductor Corporation Document Number: 001-07970 Rev. *H • BHE WE CE OE BLE A17 A16 A15 A13 A14 A12 A11 COLUMN DECODER 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 29, 2011 CY62146E MoBL Contents Features ............................................................................. 1 Functional Description ..................................................... 1 Pin Configuration ............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 4 Thermal Resistance .......................................................... 4 Data Retention Characteristics ....................................... 5 Switching Characteristics ................................................ 6 Switching Waveforms ...................................................... 7 Document Number: 001-07970 Rev. *H Truth Table ...................................................................... 10 Ordering Information ...................................................... 11 Ordering Code Definitions ......................................... 11 Package Diagram ............................................................ 11 Acronyms ........................................................................ 12 Document Conventions ................................................. 12 Units of Measure ....................................................... 12 Document History Page ................................................. 13 Sales, Solutions, and Legal Information ...................... 14 Worldwide Sales and Design Support ....................... 14 Products .................................................................... 14 PSoC Solutions ......................................................... 14 Page 2 of 14 CY62146E MoBL Pin Configuration Figure 1. 44-Pin TSOP II (Top View) [1] A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 A12 Product Portfolio Power Dissipation Product CY62146ELL VCC Range (V) Range Ind’l/Auto-A [2] Speed (ns) Min Typ Max 4.5 5.0 5.5 Operating ICC, (mA) f = 1 MHz Typ 45 2 [2] f = fmax Standby, ISB2 (A) Max Typ [2] Max Typ [2] Max 2.5 15 20 1 7 Notes 1. NC pins are not connected on the die. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. Document Number: 001-07970 Rev. *H Page 3 of 14 CY62146E MoBL Maximum Ratings Output current into outputs (LOW) .............................. 20 mA Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature................................. –65 °C to +150 °C Ambient temperature with power applied ........................................... –55 °C to +125 °C Supply voltage to ground potential .................–0.5 V to 6.0 V DC voltage applied to outputs in high Z state [3, 4] ...........................................–0.5 V to 6.0 V DC input voltage [3, 4] .......................................–0.5 V to 6.0 V Static discharge voltage............................................ >2001 V (MIL-STD-883, Method 3015) Latch-up current ...................................................... >200 mA Operating Range Ambient Temperature Device Range CY62146ELL Industrial/ Auto-A VCC[5] –40 °C to +85 °C 4.5 V–5.5 V Electrical Characteristics Over the Operating Range 45 ns (Ind’l/Auto-A) Parameter Description Test Conditions VOH Output high voltage IOH = –1.0 mA VOL Output low voltage IOL = 2.1 mA Min Typ[6] 2.4 – Max Unit – – V – 0.4 V VIH Input high voltage 4.5 < VCC < 5.5 2.2 – VCC + 0.5 V VIL Input low voltage 4.5 < VCC < 5.5 –0.5 – 0.8 V GND < VI < VCC IIX Input leakage current –1 – +1 A IOZ Output leakage current GND < VO < VCC, output disabled –1 – +1 A ICC VCC operating supply current – 15 20 mA – 2 2.5 – 1 7 ISB2 [7] f = fmax = 1/tRC VCC = VCCmax IOUT = 0 mA, CMOS levels f = 1 MHz Automatic CE power CE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, down current — CMOS f = 0, VCC = VCC(max) inputs A Capacitance Parameter[8] Description CIN Input capacitance COUT Output capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = VCC(typ) Max Unit 10 pF 10 pF TSOP II Unit 77 C/W 13 C/W Thermal Resistance Parameter[8] Description JA Thermal resistance (Junction to ambient) JC Thermal resistance (Junction to case) Test Conditions Still Air, soldered on a 3 × 4.5 inch, two layer printed circuit board Notes 3. VIL(min) = –2.0 V for pulse durations less than 20 ns for I < 30 mA. 4. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns. 5. Full Device AC operation assumes a minimum of 100 s ramp time from 0 to VCC (min) and 200 s wait time after VCC stabilization. 6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 7. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs are left floating. 8. Tested initially after any design or process changes that may affect these parameters. Document Number: 001-07970 Rev. *H Page 4 of 14 CY62146E MoBL Figure 2. AC Test Loads and Waveforms R1 VCC VCC OUTPUT 30 pF 10% GND R2 Rise Time = 1 V/ns INCLUDING JIG AND SCOPE ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT V TH Parameters 5.0 V Unit R1 1800 R2 990 RTH 639 VTH 1.77 V Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR Description Conditions VCC for data retention [10] Data retention current VCC = 2 V, CE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V Min Typ[9] Max Unit 2 – – V – 1 7 A tCDR [11] Chip deselect to data retention time 0 – – ns tR [12] Operation recovery time 45 – – ns Figure 3. Data Retention Waveform DATA RETENTION MODE VCC VCC(min) tCDR VDR > 2.0 V VCC(min) tR CE Notes 9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 10. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs are left floating. 11. Tested initially and after any design or process changes that may affect these parameters. 12. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. Document Number: 001-07970 Rev. *H Page 5 of 14 CY62146E MoBL Switching Characteristics Over the Operating Range Parameter[13, 14] Description 45 ns (Ind’l/Auto-A) Min Max Unit Read Cycle tRC Read cycle time 45 – ns tAA Address to data valid – 45 ns tOHA Data hold from address change 10 – ns tACE CE LOW to data valid – 45 ns tDOE OE LOW to data valid – 22 ns tLZOE OE LOW to LOW Z[15] 5 – ns – 18 ns ns [15, 16] OE HIGH to High Z tHZOE tLZCE CE LOW to Low Z 10 – tHZCE CE HIGH to High Z[15, 16] – 18 ns tPU CE LOW to power-up 0 – ns tPD CE HIGH to power-down – 45 ns tDBE BLE/BHE LOW to data valid – 22 ns tLZBE BLE/BHE LOW to Low Z[15] 5 – ns – 18 ns [15] BLE/BHE HIGH to HIGH Z tHZBE Write Cycle [15, 16] [17] tWC Write cycle time 45 – ns tSCE CE LOW to write end 35 – ns tAW Address setup to write end 35 – ns tHA Address hold from write end 0 – ns tSA Address setup to write start 0 – ns tPWE WE pulse width 35 – ns tBW BLE/BHE LOW to write end 35 – ns tSD Data setup to write end 25 – ns tHD Data hold from write end 0 – ns tHZWE WE LOW to High Z[15, 16] – 18 ns 10 – ns tLZWE [15] WE HIGH to Low Z Notes 13. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1 V/ns) or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3 V, and output loading of the specified IOL/IOH as shown in AC Test Loads and Waveforms on page 5. 14. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification. 15. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 16. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 17. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. Document Number: 001-07970 Rev. *H Page 6 of 14 CY62146E MoBL Switching Waveforms Figure 4. Read Cycle No.1: Address Transition Controlled[18, 19] tRC RC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle No. 2: OE Controlled [19, 20] ADDRESS tRC CE tPD tHZCE tACE OE tHZOE tDOE tLZOE BHE/BLE tHZBE tDBE tLZBE HIGH IMPEDANCE HIGHIMPEDANCE DATA VALID DATA OUT tLZCE tPU VCC SUPPLY CURRENT ICC 50% 50% ISB Notes 18. The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL. 19. WE is HIGH for read cycle. 20. Address valid before or similar to CE, BHE, BLE transition LOW. Document Number: 001-07970 Rev. *H Page 7 of 14 CY62146E MoBL Switching Waveforms (continued) Figure 6. Write Cycle No 1: WE Controlled [21, 22, 23] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE/BLE OE DATA I/O tSD NOTE 24 tHD DATAIN tHZOE Figure 7. Write Cycle 2: CE Controlled [21, 22, 23] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD DATAIN NOTE 24 tHZOE Notes 21. WE is HIGH for read cycle. 22. Data I/O is high impedance if OE = VIH. 23. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state. 24. During this period, the I/Os are in output state. Do not apply input signals. Document Number: 001-07970 Rev. *H Page 8 of 14 CY62146E MoBL Switching Waveforms (continued) Figure 8. Write Cycle 3: WE controlled, OE LOW [25] tWC ADDRESS tSCE CE tBW BHE/BLE tAW tHA tSA tPWE WE tSD DATA I/O NOTE 26 tHD DATAIN tLZWE tHZWE Figure 9. Write Cycle 4: BHE/BLE Controlled, OE LOW [25] tWC ADDRESS CE tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tHZWE DATA I/O NOTE 26 tSD tHD DATAIN tLZWE Notes 25. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state. 26. During this period, the I/Os are in output state. Do not apply input signals. Document Number: 001-07970 Rev. *H Page 9 of 14 CY62146E MoBL Truth Table CE[27] WE OE BHE BLE H X X X[27] X[27] High Z Deselect/power down Standby (ISB) L X X H H High Z Output disabled Active (ICC) L H L L L Data out (I/O0–I/O15) Read Active (ICC) L H L H L Data out (I/O0–I/O7); I/O8–I/O15 in High-Z Read Active (ICC) L H L L H Data out (I/O8–I/O15); I/O0–I/O7 in High-Z Read Active (ICC) L H H L L High Z Output disabled Active (ICC) L H H H L High Z Output disabled Active (ICC) L H H L H High Z Output disabled Active (ICC) L L X L L Data in (I/O0–I/O15) Write Active (ICC) L L X H L Data in (I/O0–I/O7); I/O8–I/O15 in High Z Write Active (ICC) L L X L H Data in (I/O8–I/O15); I/O0–I/O7 in High Z Write Active (ICC) Inputs/Outputs Mode Power Note 27. Chip enable (CE) and byte enables (BHE and BLE) must be at CMOS levels (not floating) to meet the ISB2 / ICCDR spec. Intermediate voltage levels on these pins is not permitted. Document Number: 001-07970 Rev. *H Page 10 of 14 CY62146E MoBL Ordering Information Speed (ns) Package Diagram Ordering Code 45 Operating Range Package Type CY62146ELL-45ZSXI 51-85087 44-pin thin small outline package II (Pb-free) Industrial CY62146ELL-45ZSXA 51-85087 44-pin thin small outline package II (Pb-free) Automotive-A Contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions CY 621 4 6 E LL - 45 ZSX X Temperature Range: I = Industrial, A = Automotive-A Package type = 44-pin TSOP II (Pb-free) Speed Grade Separator Low Power E = Process Technology 90 nm Buswidth = ×16 Density = 4-Mbit Family Code: MoBL SRAM family Company ID: CY = Cypress Package Diagram Figure 10. 44-Pin TSOP II, 51-85087 PIN 1 I.D. 11.938 (0.470) 11.735 (0.462) 1 10.262 (0.404) 10.058 (0.396) 22 23 Z Z Z Z X Z AA 44 BOTTOM VIEW TOP VIEW 0.800 BSC (0.0315) 0.400(0.016) 0.300 (0.012) EJECTOR MARK (OPTIONAL) CAN BE LOCATED ANYWHERE IN THE BOTTOM PKG BASE PLANE 10.262 (0.404) 10.058 (0.396) 0.10 (.004) 18.517 (0.729) 18.313 (0.721) 0.150 (0.0059) 0.050 (0.0020) 1.194 (0.047) 0.991 (0.039) 0.210 (0.0083) 0.120 (0.0047) 0°-5° SEATING PLANE 0.597 (0.0235) 0.406 (0.0160) DIMENSION IN MM (INCH) MAX MIN. 51-85087-*C Document Number: 001-07970 Rev. *H Page 11 of 14 CY62146E MoBL Acronyms Acronym Description BHE byte high enable BLE byte low enable CE chip enable CMOS complementary metal oxide semiconductor I/O input/output OE output enable SRAM static random access memory TSOP thin small outline package VFBGA very fine ball gird array WE write enable Document Conventions Units of Measure Symbol Unit of Measure °C degrees Celsius A microamperes mA milliamperes MHz megahertz ns nanoseconds pF picofarads V volts ohms W watts Document Number: 001-07970 Rev. *H Page 12 of 14 CY62146E MoBL Document History Page Document Title: CY62146E MoBL 4-Mbit (256K x 16) Static RAM Document Number: 001-07970 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 463213 See ECN NXR New Data Sheet *A 684343 See ECN VKN Added Preliminary Automotive-A Information Updated Ordering Information Table *B 925501 See ECN VKN Added footnote #8 related to ISB2 and ICCDR Added footnote #13 related AC timing parameters *C 1045260 See ECN VKN Converted Automotive-A specs from preliminary to final *D 2073548 See ECN *E 2943752 06/03/2010 VKN *F 3109050 12/13/2010 PRAS Changed Table Footnotes to Footnotes. Added Ordering Code Definitions. *G 3149059 01/20/2011 RAME Updated as per latest template Corrected Errors in Ordering Code Definitions Added Acronyms and Units of Measure table *H 3296704 06/29/11 RAME Removed reference to AN1064 SRAM system guidelines Document Number: 001-07970 Rev. *H VKN/AESA Corrected typo in the Data Retention Waveform and removed its irrelevant footnote Added Contents Added footnote related to chip enable in Truth Table Updated Package Diagram Added Sales, Solutions, and Legal Information Page 13 of 14 CY62146E MoBL Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2008-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-07970 Rev. *H Revised June 29, 2011 Page 14 of 14 MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.