IDT54/74FCT161T/AT/CT
IDT54/74FCT163T/AT/CT
FAST CMOS
SYNCHRONOUS
PRESETTABLE
BINARY COUNTERS
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
•
•
•
•
The IDT54/74FCT161T/163T, IDT54/74FCT161AT/ 163AT
and IDT54/74FCT161CT/163CT are high-speed synchronous modulo-16 binary counters built using an advanced dual
metal CMOS technology. They are synchronously presettable for application in programmable dividers and have two
types of count enable inputs plus a terminal count output for
versatility in forming synchronous multi-stage counters. The
IDT54/74FCT161T/AT/CT have asynchronous Master Reset
inputs that override all other inputs and force the outputs LOW.
The IDT54/74FCT163T/AT/CT have Synchronous Reset inputs that override counting and parallel loading and allow the
outputs to be simultaneously reset on the rising edge of the
clock.
•
•
•
•
•
Std., A and C speed grades
Low input and output leakage ≤1µA (max.)
CMOS power levels
True TTL input and output compatibility
– VOH = 3.3V (typ.)
– VOL = 0.3V (typ.)
High drive outputs (-15mA IOH, 48mA IOL)
Meets or exceeds JEDEC standard 18 specifications
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
Available in DIP, SOIC, QSOP, CERPACK and LCC
packages
FUNCTIONAL BLOCK DIAGRAMS
P1
P0
P2
P3
PE
'161 '163
CEP
CET
163
ONLY
TC
CP
CP
161
ONLY
CP
D CP D
CD
Q Q
Q0
Q0
DETAIL
A
DETAIL
A
DETAIL
A
Q1
Q2
Q3
DETAIL A
MR ('161)
SR ('163)
Q0
2611 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1995 Integrated Device Technology, Inc.
6.7
OCTOBER 1994
DSC-4219/4
1
IDT54/74FCT161T/AT/CT, IDT54/74FCT163T/AT/CT
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
INDEX
IDT54/74FCT861 10-BIT TRANSCEIVERS
1
CEP
GND
7
2
3
4
5
6
16
P16-1,
D16-1,
S016-1,
S016-7
&
E16-1
15
14
13
12
11
10
9
8
3
Vcc
TC
Q0
Q1
Q2
Q3
CET
PE
P0
P1
NC
P2
P3
1
17
L20-2
6
16
7
15
8
14
9 10 11 12 13
DIP/SOIC/QSOP/CERPACK
TOP VIEW
Q0
Q1
NC
Q2
Q3
2611 drw 03
LCC
TOP VIEW
FUNCTION TABLE(2)
PIN DESCRIPTION
Pin Names
20 19
18
5
2611 drw 02
*MR for '161
*SR for ‘163
2
4
CEP
GND
NC
PE
CET
*R
CP
P0
P1
P2
P3
CP
*R
NC
Vcc
TC
PIN CONFIGURATIONS
Description
Action on the Rising
Clock Edge(s)
SR(1)
PE
CET
CEP
Count Enable Trickle Input
L
X
X
X
Reset (Clear)
CP
Clock Pulse Input (Active Rising Edge)
H
L
X
X
Load (Pn→Qn)
MR (‘161)
SR (‘163)
Asynchronous Master Reset Input (Active LOW)
H
H
H
H
Count (Increment)
Synchronous Reset Input (Active LOW)
H
H
L
X
No Change (Hold)
P0-3
Parallel Data Inputs
H
H
X
L
No Change (Hold)
PE
Parallel Enable Input (Active LOW)
CEP
Count Enable Parallel Input
CET
Q0-3
Flip-Flop Outputs
TC
Terminal Count Output
2611 tbl 02
NOTES:
1. 163 only.
2. H = HIGH Voltage Level, L = LOW Voltage Level, X = Don’t Care.
2611 tbl 01
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Rating
Commercial
VTERM(2) Terminal Voltage
–0.5 to +7.0
with Respect to
GND
VTERM(3) Terminal Voltage
–0.5 to
with Respect to
VCC +0.5
GND
TA
Operating
0 to +70
Temperature
TBIAS
Temperature
–55 to +125
Under Bias
TSTG
Storage
–55 to +125
Temperature
PT
Power Dissipation
0.5
Military
–0.5 to +7.0
Unit
V
–0.5 to
VCC +0.5
V
–55 to +125
°C
–65 to +135
°C
–65 to +150
°C
0.5
W
I OUT
–60 to +120
mA
DC Output
Current
–60 to +120
Symbol
Parameter(1)
CIN
Input
Capacitance
COUT
Output
Capacitance
Conditions
VIN = 0V
Typ.
6
VOUT = 0V
8
Max. Unit
10
pF
12
NOTE:
1. This parameter is measured at characterization but not tested.
pF
2611 lnk 04
2611 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals only.
3. Outputs and I/O terminals only.
6.7
2
IDT54/74FCT161T/AT/CT, IDT54/74FCT163T/AT/CT
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
Test Conditions(1)
Parameter
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
(5)
COM'L
MIL
Min.
Typ.(2)
Max.
Unit
2.0V
2.7V
—
—
—
—
V
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
—
—
0.8
V
IIH
Input HIGH Current(4)
VCC = Max.
VI = 2.7V
—
—
±1
µA
IIL
Input LOW Current(4)
VCC = Max.
VI = 0.5V
—
—
±1
µA
(4)
II
Input HIGH Current
VIK
Clamp Diode Voltage
VCC = Max., VI = VCC (Max.)
—
—
±1
µA
VCC = Min., IN = –18mA
—
–0.7
–1.2
V
–60
–120
–225
mA
IOH = –6mA MIL.
IOH = –8mA COM’L.
2.4
3.3
—
V
IOH = –12mA MIL.
IOH = –15mA COM’L.
2.0
3.0
—
V
IOL= 32mA MIL.
IOL= 48mA COM’L.
—
0.3
0.5
V
—
200
—
mV
—
0.01
1
mA
(3)
IOS
Short Circuit Current
VCC = Max. , VO = GND
VOH
Output HIGH Voltage
VCC = Min.
VIN = VIH or VIL
VOL
Output LOW Voltage
VH
Input Hysteresis
ICC
Quiescent Power
Supply Current
VCC = Min.
VIN = VIH or VIL
—
VCC = Max.
VIN = GND or VCC
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is ±5µA at TA = -55°C.
5. Clock pin requires a minimum VIH of 2.5V.
6.7
2611 tbl 05
3
IDT54/74FCT161T/AT/CT, IDT54/74FCT163T/AT/CT
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
∆ICC
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Test Conditions(1)
VCC = Max.
VIN = 3.4V(3)
ICCD
Dynamic Power Supply Current (4)
VCC = Max., Outputs Open
Load Mode
CEP = CET = PE = GND
MR or SR = VCC
One Input Toggling
50% Duty Cycle
IC
Total Power Supply Current(6)
VCC = Max., Outputs Open
Load Mode
fCP = 10MHz
50% Duty Cycle
CEP = CET = PE = GND
MR or SR = VCC
One Bit Toggling
at fi = 5MHz
50% Duty Cycle
VCC = Max., Outputs Open
Load Mode
fCP = 10MHz
50% Duty Cycle
CEP = CET = PE = GND
MR or SR = VCC
Four Bits Toggling
at fi = 5MHz
50% Duty Cycle
Min.
—
Typ.(2)
0.5
Max.
2.0
Unit
mA
VIN = VCC
VIN = GND
—
0.15
0.25
mA/
MHz
VIN = VCC
VIN = GND
—
1.5
3.5
mA
VIN = 3.4V
VIN = GND
—
2.0
5.5
VIN = VCC
VIN = GND
—
3.8
7.3(5)
VIN = 3.4V
VIN = GND
—
5.0
12.3(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
6.7
2611 tbl 06
4
IDT54/74FCT161T/AT/CT, IDT54/74FCT163T/AT/CT
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
tPLH
tPHL
Propagation Delay
CP to Qn
(PE Input HIGH)
tPLH
tPHL
Condition(1)
IDT54/74FCT161AT
IDT54/74FCT161CT
IDT54/74FCT163T
IDT54/74FCT163AT
IDT54/74FCT163CT
Com'l.
Com'l.
Mil.
Mil.
Com'l
Mil.
Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max.
Unit
2.0
11.0
2.0
11.5
2.0
7.2
2.0
7.5
2.0
5.8
2.0
6.3
ns
Propagation Delay
CP to Qn
(PE Input LOW)
2.0
9.5
2.0
10.0
2.0
6.2
2.0
6.5
2.0
5.8
2.0
6.3
ns
tPLH
tPHL
Propagation Delay
CP to TC
2.0
15.0
2.0
16.5
2.0
9.8
2.0
10.8
2.0
7.4
2.0
8.3
ns
tPLH
tPHL
Propagation Delay
CET to TC
1.5
8.5
1.5
9.0
1.5
5.5
1.5
5.9
1.5
5.2
1.5
5.6
ns
tPHL
Propagation Delay
MR to Qn ('161)
2.0
13.0
2.0
14.0
2.0
8.5
2.0
9.1
2.0
6.0
2.0
6.6
ns
tPHL
Propagation Delay
MR to TC ('161)
2.0
11.5
2.0
12.5
2.0
7.5
2.0
8.2
2.0
7.0
2.0
7.7
ns
tSU
Set-up Time,
HIGH or LOW
Pn to CP
Hold Time,
HIGH or LOW
Pn to CP
5.0
—
5.5
—
4.0
—
4.5
—
4.0
—
4.5
—
ns
1.5
—
2.0
—
1.5
—
2.0
—
1.5
—
2.0
—
ns
Set-up Time,
HIGH or LOW
PE or SR to CP
Hold Time,
HIGH or LOW
PE or SR to CP
Set-up Time,
HIGH or LOW
CEP or CET to CP
Hold Time,
HIGH or LOW
CEP or CET to CP
11.5
—
13.5
—
9.5
—
11.5
—
9.5
—
11.5
—
ns
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
11.5
—
13.0
—
9.5
—
11.0
—
9.5
—
11.0
—
ns
0
—
0
—
0
—
0
—
0
—
0
—
ns
Clock Pulse
Width (Load)
HIGH or LOW
Clock Pulse
Width (Count)
HIGH or LOW
5.0
—
5.0
—
4.0(3)
—
4.0(3)
—
4.0(3)
—
4.0(3)
—
ns
7.0
—
8.0
—
6.0
—
7.0
—
6.0
—
7.0
—
ns
tW
MR Pulse Width,
LOW ('161)
5.0
—
5.0
—
4.0(3)
—
4.0(3)
—
4.0(3)
—
4.0(3)
—
ns
tREM
Recovery Time
MR to CP ('161)
6.0
—
6.0
—
5.0
—
5.0
—
5.0
—
5.0
—
ns
tH
tSU
tH
tSU
tH
tW
tW
CL = 50pF
RL = 500Ω
IDT54/74FCT161T
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This limit is guaranteed but not tested.
2611 tbl 07
6.7
5
IDT54/74FCT161T/AT/CT, IDT54/74FCT163T/AT/CT
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION
TEST CIRCUITS FOR ALL OUTPUTS
V CC
500Ω
Pulse
Generator
Switch
Open Drain
Disable Low
Closed
Enable Low
V OUT
VIN
Test
7.0V
Open
All Other Tests
D.U.T.
50pF
RT
2611 lnk 08
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
500Ω
CL
2611 drw 04
SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
tH
tSU
tREM
tSU
PULSE WIDTH
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
1.5V
tW
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
2611 drw 06
3V
1.5V
0V
tH
2611 drw 05
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
SAME PHASE
INPUT TRANSITION
tPLH
tPHL
OUTPUT
tPLH
OPPOSITE PHASE
INPUT TRANSITION
tPHL
3V
1.5V
0V
VOH
1.5V
VOL
DISABLE
3V
CONTROL
INPUT
tPZL
OUTPUT
NORMALLY
LOW
3V
1.5V
0V
SWITCH
CLOSED
tPLZ
2611 drw 07
SWITCH
OPEN
3.5V
3.5V
1.5V
tPZH
OUTPUT
NORMALLY
HIGH
1.5V
0V
0.3V
VOL
tPHZ
0.3V
1.5V
0V
VOH
0V
2611 drw 08
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
6.7
6
IDT54/74FCT161T/AT/CT, IDT54/74FCT163T/AT/CT
FAST CMOS SYNCHRONOUS PRESETTABLE BINARY COUNTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
X
Temperature
Range
FCT
X
XXXX
X
X
Family
Device
Type
Package
Process
Blank
B
Commercial
MIL-STD-883, Class B
P
D
L
SO
E
Q
Plastic DIP
CERDIP
Leadless Chip Carrier
Small Outline IC
CERPACK
Quarter-size Small Outline Package
161T
163T
161AT
163AT
Synchronous Binary Counter
with Asynchronous Master Reset
Blank
High Drive
54
74
-55°C to +125°C
0° to +70°C
2611 drw 09
6.7
7