MOTOROLA MC14553B 3-digit bcd counter Datasheet

 SEMICONDUCTOR TECHNICAL DATA
L SUFFIX
CERAMIC
CASE 620
The MC14553B 3–digit BCD counter consists of 3 negative edge triggered
BCD counters that are cascaded synchronously. A quad latch at the output
of each counter permits storage of any given count. The information is then
time division multiplexed, providing one BCD number or digit at a time. Digit
select outputs provide display control. All outputs are TTL compatible.
An on–chip oscillator provides the low–frequency scanning clock which
drives the multiplexer output selector.
This device is used in instrumentation counters, clock displays, digital
panel meters, and as a building block for general logic applications.
•
•
•
•
•
•
•
TTL Compatible Outputs
On–Chip Oscillator
Cascadable
Clock Disable Input
Pulse Shaping Permits Very Slow Rise Times on Input Clock
Output Latches
Master Reset
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
ORDERING INFORMATION
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Parameter
Value
Unit
– 0.5 to + 18.0
V
– 0.5 to VDD + 0.5
V
Input Current (DC or Transient), per Pin
± 10
mA
Iout
Output Current (DC or Transient), per Pin
+ 20
mA
PD
Power Dissipation, per Package†
Tstg
Storage Temperature
Symbol
VDD
Vin, Vout
Iin
TL
DC Supply Voltage
Input or Output Voltage (DC or Transient)
Lead Temperature (8–Second Soldering)
500
mW
– 65 to + 150
_C
260
_C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
BLOCK DIAGRAM
4
CIA
12
CLOCK
10
LE
11
DIS
13
MR
3
CIB Q0
9
Q1
7
Q2
6
Q3
O.F.
5
DS1
DS2
2
1
DS3
15
14
VDD = PIN 16
VSS = PIN 8
TRUTH TABLE
Inputs
Master
Reset
0
0
0
0
0
0
0
0
1
Clock
X
1
1
0
X
X
X
Disable
LE
Outputs
0
0
1
0
0
X
0
0
X
No Change
Advance
No Change
Advance
No Change
No Change
Latched
Latched
Q0 = Q1 = Q2 = Q3 = 0
X
X
X
X
1
0
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of
any voltage higher than maximum rated voltages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
to the range VSS
(Vin or Vout)
VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
v
v
X = Don’t Care
REV 3
1/94
MOTOROLA
Motorola, Inc. 1995
CMOS LOGIC DATA
MC14553B
1
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Symbol
Output Voltage
Vin = VDD or 0
– 55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
“0” Level
VOL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
Vin = 0 or VDD
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
“1” Level
VIH
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Vdc
Vdc
IOH
Output Drive Current
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Source —
Pin 3
5.0
10
15
– 0.25
– 0.62
– 1.8
—
—
—
– 0.2
– 0.5
– 1.5
– 0.36
– 0.9
– 3.5
—
—
—
0.14
0.35
1.1
—
—
—
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Source —
Other
Outputs
5.0
10
15
– 0.64
– 1.6
– 4.2
—
—
—
– 0.51
– 1.3
– 3.4
– 0.88
– 2.25
– 8.8
—
—
—
– 0.36
– 0.9
– 2.4
—
—
—
mAdc
5.0
10
15
0.5
1.1
1.8
—
—
—
0.4
0.9
1.5
0.88
2.25
8.8
—
—
—
0.28
0.65
1.20
—
—
—
mAdc
5.0
10
15
3.0
6.0
18
—
—
—
2.5
5.0
15
4.0
8.0
20
—
—
—
1.6
3.5
10
—
—
—
mAdc
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink —
Pin 3
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink — Other
Outputs
IOL
mAdc
Input Current
Iin
15
—
± 0.1
—
± 0.00001
± 0.1
—
± 1.0
µAdc
Input Capacitance
(Vin = 0)
Cin
—
—
—
—
5.0
7.5
—
—
pF
Quiescent Current
(Per Package)
MR = VDD
IDD
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.010
0.020
0.030
5.0
10
20
—
—
—
150
300
600
µAdc
IT
5.0
10
15
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
IT = (0.35 µA/kHz) f + IDD
IT = (0.85 µA/kHz) f + IDD
IT = (1.50 µA/kHz) f + IDD
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.
MC14553B
2
MOTOROLA CMOS LOGIC DATA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C)
Characteristic
Figure
Symbol
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
2a
tTLH,
tTHL
VDD
Min
Typ #
Max
Clock to BCD Out
2a
Clock to Overflow
Unit
5.0
10
15
—
—
—
100
50
40
200
100
80
tPLH,
tPHL
5.0
10
15
—
—
—
900
500
200
1800
1000
400
ns
2a
tPHL
5.0
10
15
—
—
—
600
400
200
1200
800
400
ns
Reset to BCD Out
2b
tPHL
5.0
10
15
—
—
—
900
500
300
1800
1000
600
ns
Clock to Latch Enable Setup Time
Master Reset to Latch Enable Setup Time
2b
tsu
5.0
10
15
600
400
200
300
200
100
—
—
—
ns
Removal Time
Latch Enable to Clock
2b
trem
5.0
10
15
– 80
– 10
0
– 200
– 70
– 50
—
—
—
ns
Clock Pulse Width
2a
tWH(cl)
5.0
10
15
550
200
150
275
100
75
—
—
—
ns
Reset Pulse Width
2b
tWH(R)
5.0
10
15
1200
600
450
600
300
225
—
—
—
ns
Reset Removal Time
—
trem
5.0
10
15
– 80
0
20
– 180
– 50
– 30
—
—
—
ns
Input Clock Frequency
2a
fcl
5.0
10
15
—
—
—
1.5
5.0
7.0
0.9
2.5
3.5
MHz
Input Clock Rise Time
2b
tTLH
5.0
10
15
Disable, MR, Latch Enable
Rise and Fall Times
—
tTLH,
tTHL
5.0
10
15
—
—
—
—
—
—
15
5.0
4.0
µs
Scan Oscillator Frequency
(C1 measured in µF)
1
fosc
5.0
10
15
—
—
—
1.5/C1
4.2/C1
7.0/C1
—
—
—
Hz
ns
No
Limit
ns
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
MOTOROLA CMOS LOGIC DATA
MC14553B
3
899
900
901
990
991
992
993
994
995
996
997
998
999
1000
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
UNITS CLOCK
UNITS Q0
UNITS Q1
UNITS Q2
UNITS Q3
TENS CLOCK
TENS Q0
TENS Q3
HUNDREDS
CLOCK
UP AT 980
UP AT 80
HUNDREDS Q0
HUNDREDS Q3
DISABLE
UP AT 800
(DISABLES CLOCK WHEN HIGH)
OVERFLOW
MASTER
RESET
SCAN
OSCILLATOR
DIGIT SELECT 1
UNITS
TENS
DIGIT SELECT 2
DIGIT SELECT 3
HUNDREDS
Figure 1. 3–Digit Counter Timing Diagram (Reference Figure 3)
VDD
Q3
Q2
Q1
Q0
O.F.
DS1
DS2
DS3
C
LE
DIS
MR
8
20 ns
CL
CLOCK
CL
CL
CL
90%
10%
tPLH
BCD OUT
CL
20 ns
tWL(cl)
1000
16
999
(a)
PULSE
GENERATOR
50%
10%
tTLH
90%
tPHL
50%
tTHL
OVERFLOW
1/fcl
tPHL
50%
VSS
tTLH
(b)
GENERATOR
1
GENERATOR
2
GENERATOR
3
CLOCK
VDD
C
LE
MR
DIS
Q3
Q2
Q1
Q0
O.F.
DS1
DS2
DS3
50%
90%
10%
tsu
trem
CL
CL
CL
LATCH
ENABLE
tPHL, tPLH
CL
CL
50%
BCD OUT
tsu
50%
tPHL
VSS
50%
MASTER RESET
tWH(R)
Figure 2. Switching Time Test Circuits and Waveforms
MC14553B
4
MOTOROLA CMOS LOGIC DATA
OPERATING CHARACTERISTICS
The MC14553B three–digit counter, shown in Figure 3,
consists of three negative edge–triggered BCD counters
which are cascaded in a synchronous fashion. A quad latch
at the output of each of the three BCD counters permits storage of any given count. The three sets of BCD outputs
(active high), after going through the latches, are time division multiplexed, providing one BCD number or digit at a
time. Digit select outputs (active low) are provided for display
control. All outputs are TTL compatible.
An on–chip oscillator provides the low frequency scanning
clock which drives the multiplexer output selector. The frequency of the oscillator can be controlled externally by a
capacitor between pins 3 and 4, or it can be overridden and
driven with an external clock at pin 4. Multiple devices can be
cascaded using the overflow output, which provides one
LATCH ENABLE
10
CLOCK
12
PULSE
SHAPER
pulse for every 1000 counts.
The Master Reset input, when taken high, initializes the
three BCD counters and the multiplexer scanning circuit.
While Master Reset is high the digit scanner is set to digit
one; but all three digit select outputs are disabled to prolong
display life, and the scan oscillator is inhibited. The Disable
input, when high, prevents the input clock from reaching the
counters, while still retaining the last count. A pulse shaping
circuit at the clock input permits the counters to continue operating on input pulses with very slow rise times. Information
present in the counters when the latch input goes high, will
be stored in the latches and will be retained while the latch
input is high, independent of other inputs. Information can be
recovered from the latches after the counters have been reset if Latch Enable remains high during the entire reset cycle.
C1A
4
SCAN
R
OSCILLATOR 3
C1B
C1
PULSE
GENERATOR
R SCANNER
Q0
Q1
Q2
R ÷ 10
Q3
UNITS
C
QUAD
LATCH
9
11
DISABLE
(ACTIVE
HIGH)
Q0
MULTIPLEXER
7
Q0
C
Q1
Q2
R ÷ 10
Q3
TENS
BCD
OUTPUTS
(ACTIVE
HIGH)
QUAD
LATCH
6
5
Q0
Q1
Q2
R
÷ 10 Q3
HUNDREDS
C
13
MR
(ACTIVE HIGH)
Q1
Q2
Q3
QUAD
LATCH
14
OVERFLOW
2
1
15
DS1 DS2 DS3
(LSD) DIGIT SELECT (MSD)
(ACTIVE LOW)
Figure 3. Expanded Block Diagram
MOTOROLA CMOS LOGIC DATA
MC14553B
5
Figure 4. Six–Digit Display
MC14553B
6
MOTOROLA CMOS LOGIC DATA
CLOCK
INPUT
VDD
STROBE
RESET
11
12
MC14553B
13
MR
C1B
C1A
LSD
5
9
a
A
3
B
b 10
2
11
C
c
12
4
D MC14543B d
6
13
Ph
e
1
15
f
LD
7
14
BI
g
O.F.
Q3 Q2 Q1 Q0 DS3 DS2 DS1
5
6
7
9 15
1 2
DIS
CLK
10
LE
14
3
4
0.001
µF
MC14553B
MR
13
C1 B
C1 A
DISPLAYS ARE LOW CURRENT LEDs
(I peak < 10 mA PER SEGMENT)
VDD
B
C
A
c
b
a
14
3
4
11
10
9
MSD
12
D MC14543B d
6
13
Ph
e
1
15
LD
f
7
g 14
BI
4
2
3
5
O.F.
Q3 Q2 Q1 Q0 DS3 DS2 DS1
5
6
7
9 15
1
2
DIS
CLK
VDD
11
12
LE
10
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
–A–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–B–
C
L
DIM
A
B
C
D
E
F
G
H
K
L
M
N
–T–
K
N
SEATING
PLANE
M
E
F
J
G
D
16 PL
0.25 (0.010)
16 PL
0.25 (0.010)
M
T A
T B
M
S
INCHES
MIN
MAX
0.750
0.785
0.240
0.295
–––
0.200
0.015
0.020
0.050 BSC
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
19.05
19.93
6.10
7.49
–––
5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0_
15 _
0.51
1.01
S
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
16
9
1
8
B
F
C
L
S
–T–
SEATING
PLANE
K
H
G
D
J
16 PL
0.25 (0.010)
MOTOROLA CMOS LOGIC DATA
M
T A
M
M
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
MC14553B
7
OUTLINE DIMENSIONS
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751G–02
ISSUE A
–A–
16
9
–B–
8X
P
0.010 (0.25)
1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
M
B
M
8
16X
J
D
0.010 (0.25)
M
T A
S
B
S
F
R X 45 _
C
–T–
14X
G
K
SEATING
PLANE
M
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
10.15
10.45
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0_
7_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.400
0.411
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0_
7_
0.395
0.415
0.010
0.029
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How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315
MFAX: [email protected] – TOUCHTONE 602–244–6609
INTERNET: http://Design–NET.com
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
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