NTD40N03R Power MOSFET 45 Amps, 25 Volts N−Channel DPAK Features • • • • • • http://onsemi.com Planar HD3e Process for Fast Switching Performance Low RDS(on) to Minimize Conduction Loss Low Ciss to Minimize Driver Loss Low Gate Charge Optimized for High Side Switching Requirements in High−Efficiency DC−DC Converters Pb−Free Packages are Available 45 AMPERES, 25 VOLTS RDS(on) = 12.6 m (Typ) N−CHANNEL D MAXIMUM RATINGS (TJ = 25°C unless otherwise specified) Value Unit Drain−to−Source Voltage VDSS 25 Vdc Gate−to−Source Voltage − Continuous VGS ±20 Vdc Thermal Resistance − Junction−to−Case Total Power Dissipation @ TC = 25°C Drain Current − Continuous @ TC = 25°C, Chip − Continuous @ TA = 25°C, Limited by Wires − Single Pulse (tp ≤ 10 s) RJC PD 3.0 50 °C/W W ID ID ID 45 32 100 A A A Thermal Resistance − Junction−to−Ambient (Note 1) Total Power Dissipation @ TA = 25°C Drain Current − Continuous @ TA = 25°C RJA 71.4 °C/W PD ID 2.1 9.2 W A Thermal Resistance − Junction−to−Ambient (Note 2) Total Power Dissipation @ TA = 25°C Drain Current − Continuous @ TA = 25°C RJA 100 °C/W PD ID 1.5 7.8 W A Operating and Storage Temperature Range TJ, Tstg −55 to 175 °C Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds TL 260 °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. When surface mounted to an FR4 board using 0.5 sq. in pad size. 2. When surface mounted to an FR4 board using minimum recommended pad size. G S 4 4 1 2 1 2 3 3 CASE 369D DPAK (Straight Lead) STYLE 2 CASE 369AA DPAK (Surface Mount) STYLE 2 MARKING DIAGRAM & PIN ASSIGNMENTS 4 Drain 4 Drain 1 Gate 2 Drain YWW T40 N03 Symbol YWW T40 N03 Parameter 3 Source 1 Gate 3 Source 2 Drain 40N03= Device Code Y = Year WW = Work Week ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. Semiconductor Components Industries, LLC, 2004 April, 2004 − Rev. 5 1 Publication Order Number: NTD40N03R/D NTD40N03R ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Characteristics Symbol Min Typ Max 25 − 28 − − − − − − − 1.0 10 − − ±100 1.0 − 1.7 − 2.0 − − − 18.6 12.6 23 16.5 − 20 − Ciss − 584 − Coss − 254 − Crss − 99 − td(on) − 4.5 − tr − 19.5 − td(off) − 16.7 − tf − 3.5 − QT − 5.78 − Q1 − 2.1 − Q2 − 2.5 − − − 0.85 0 85 0.71 1.2 1 2 − trr − 20.4 − ta − 8.25 − tb − 12.1 − QRR − 0.007 − Unit OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (Note 3) (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(br)DSS Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 150°C) IDSS Gate−Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C Adc nAdc ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (Note 3) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−Resistance (Note 3) (VGS = 4.5 Vdc, ID = 10 Adc) (VGS = 10 Vdc, ID = 10 Adc) RDS(on) Forward Transconductance (Note 3) (VDS = 10 Vdc, ID = 10 Adc) Vdc mV/°C m gFS Mhos DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance ((VDS = 20 Vdc,, VGS = 0 V,, f = 1 MHz)) Transfer Capacitance pF SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time (VGS = 10 Vdc, VDD = 10 Vdc, ID = 10 Adc, RG = 3 ) Fall Time Gate Charge (VGS = 4.5 Vdc, ID = 10 Adc, VDS = 10 Vdc) (Note 3) ns nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (IS = 10 Adc, VGS = 0 Vdc) (Note 3) (IS = 10 Adc, VGS = 0 Vdc, TJ = 125°C) Reverse Recovery Time (IS = 10 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) (Note 3) Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width ≤ 300 s, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 VSD Vdc ns C NTD40N03R 20 10 V 3.5 V VDS ≥ 10 V 3.4 V ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) 20 8V 16 6V 4V 12 3.2 V 8 3V 4 2.8 V 16 12 8 TJ = 25°C 4 TJ = 125°C VGS = 2.6 V 0 2 4 10 8 6 0 1 2 3 4 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 0.040 VGS = 10 V 0.032 0.024 TJ = 150°C 0.016 TJ = 125°C TJ = 25°C 0.008 TJ = −55°C 0 4 0 8 12 16 20 RDS(on), DRAIN−TO−SOURCE RESISTANCE () VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) TJ = 150°C 0.032 TJ = 125°C 0.024 TJ = 25°C 0.016 TJ = −55°C 0.008 VGS = 4.5 V 0 0 4 8 12 16 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance versus Drain Current and Temperature Figure 4. On−Resistance versus Drain Current and Temperature VGS = 0 V ID = 10 A VGS = 10 V 1.4 1.2 1 TJ = 150°C 1000 TJ = 125°C 0.8 0.6 −50 20 10,000 1.8 1.6 5 0.040 IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE () 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) TJ = −55°C 0 100 −25 0 25 50 75 100 125 150 0 5 10 15 20 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 3 25 1000 TJ = 25°C VDS = 0 V VGS = 0 V C, CAPACITANCE (pF) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) NTD40N03R Ciss 800 Crss Ciss 600 400 Coss 200 Crss 0 10 VGS 0 VDS 5 5 10 15 20 VGS 6 QT 4 Q2 Q1 2 ID = 10 A TJ = 25°C 0 0 2 4 6 8 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Qg, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge 100 20 IS, SOURCE CURRENT (AMPS) VDS = 10 V ID = 10 A VGS = 10 V tr td(off) 10 td(on) tf 1 18 VGS = 0 V 16 TJ = 25°C 14 12 10 8 6 4 2 0 1 10 100 0 0.2 0.4 0.6 0.8 RG, GATE RESISTANCE () VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Diode Forward Voltage versus Current 100 I D, DRAIN CURRENT (AMPS) t, TIME (ns) 8 SINGLE PULSE VGS = 20 V TC = 25°C 10 s 100 s 10 1 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 0.1 10 ms dc 1 10 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 11. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 4 100 1.0 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) NTD40N03R 1.0 D = 0.5 0.2 0.1 P(pk) 0.1 0.05 0.02 t1 0.01 SINGLE PULSE t2 DUTY CYCLE, D = t1/t2 RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RJC(t) 0.01 0.00001 0.0001 0.001 0.01 t, TIME (s) Figure 12. Thermal Response http://onsemi.com 5 0.1 1 10 NTD40N03R ORDERING INFORMATION Package Shipping† DPAK 75 Units/Rail NTD40N03RG DPAK (Pb−Free) 75 Units/Rail NTD40N03R−1 DPAK (Straight Lead) 75 Units/Rail Device NTD40N03R NTD40N03R−1G NTD40N03RT4 NTD40N03RT4G DPAK (Straight Lead, Pb−Free) 75 Units/Rail DPAK 2500 Tape & Reel DPAK (Pb−Free) 2500 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 6 NTD40N03R PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369AA−01 ISSUE O −T− C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. SEATING PLANE E R 4 Z A S 1 2 DIM A B C D E F J L R S U V Z 3 U F J L D STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN 2 PL 0.13 (0.005) M INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.025 0.035 0.018 0.024 0.033 0.045 0.018 0.023 0.090 BSC 0.180 0.215 0.025 0.040 0.020 −−− 0.035 0.050 0.155 −−− T SOLDERING FOOTPRINT* 6.20 0.244 3.0 0.118 2.58 0.101 5.80 0.228 1.6 0.063 6.172 0.243 SCALE 3:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.63 0.88 0.46 0.61 0.83 1.14 0.46 0.58 2.29 BSC 4.57 5.45 0.63 1.01 0.51 −−− 0.89 1.27 3.93 −−− NTD40N03R PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369D−01 ISSUE B C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. E R 4 Z A S 1 2 3 −T− SEATING PLANE K J F H D G 3 PL 0.13 (0.005) M DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN T ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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