A4936 3-Phase Brushless DC Motor Pre-Driver Features and Benefits Description • Drives 6 N-channel MOSFETs • Synchronous rectification for low power dissipation • Internal UVLO and thermal shutdown circuitry • Hall element inputs • PWM current limiting • Dead time protection • FG outputs • Standby mode • Lock detect protection • Overvoltage protection The A4936 is a complete 3-phase brushless DC motor pre-driver, supplying up to 28 V output for direct, high-current gate drive of an all N-channel power MOSFET 3-phase bridge. The device has three Hall-element inputs, a sequencer for commutation control, fixed off-time pulse width modulation (PWM) current control, and locked-rotor detection. Package: 32-contact QFN (suffix ET) Output current is scaled by the capability of the external MOSFETs. Locked rotor detection delay is set by an external capacitor on the CLD terminal. The PWM, DIR, and BRAKE and STOP inputs can be used to control motor speed, position, and torque. Motor speed can be determined using the FG output from an FG coil amplifier and comparator. The external MOSFETS can be PWMed using an external signal on the PWM input, or using the internal PWM current regulator. In either case, the A4936 synchronous rectification feature reduces power dissipation by turning-on the appropriate MOSFETs during current decay. The Hall elements can be inexpensive types, when used with noise filtering to prevent false commutation signals. The A4936 provides a regulated 7.5 V supply to power the three Hall elements. Not to scale Continued on the next page… Typical Application Diagram V+ System Control Logic A4936-DS BLDC Motor A4936 A4936 3-Phase Brushless DC Motor Pre-Driver Description (continued) Internal circuit protection includes thermal shutdown with hysteresis, undervoltage lockout, and dead time protection. Special power-up sequencing is not required. Operating temperature range is –20°C to 105°C. The device package is a 32-contact, 5 mm × 5 mm, 0.90 mm nominal overall height QFN, with exposed pad for enhanced thermal dissipation. This small-footprint package is lead (Pb) free, with 100% matte tin leadframe plating. Selection Guide Part Number Packing* Package A4936MET-T 73 pieces per tube A4936METTR-T 1500 pieces per reel *Contact Allegro® for additional packing options 32-pin QFN, 5 mm × 5 mm, 0.90 mm nominal overall height Absolute Maximum Ratings Characteristic Load Supply Voltage Symbol Notes Motor Phase Output Sx tw< 500 ns Hall Input VHx DC Logic Input Voltage Range VIN Ambient Operating Temperature TA Maximum Junction Temperature Storage Temperature Rating Unit 38 V –3 V –0.3 to 7 V VBB –0.3 to 7 V –20 to 105 °C TJ(max) 150 °C Tstg –40 to 150 °C Range M Thermal Characteristics may require derating at maximum conditions, see application information Characteristic Symbol Package Thermal Resistance (Junction to Ambient) RθJA Package Thermal Resistance (Junction to Exposed Pad) RθJP Test Conditions* On 4-layer PCB based on JEDEC standard Value Unit 32 ºC/W 2 ºC/W *Additional thermal information available on the Allegro website Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A4936 3-Phase Brushless DC Motor Pre-Driver Functional Block Diagram 100 nF CP1 100 nF HA+ BRAKE STOP PWM DIR CLD FGS SA HALL 32 31 30 29 28 27 26 25 GHA SB GHB SC GHC GLA GLB GLC Phase A Control Logic System Logic VIN SA GLA HC+ HC– 200 mV SENSE Phase A of three phases shown GHB SB GLB GHC SC GLC STOP FGFB DIR 10 11 12 13 14 15 16 100 nF GHA Gate Drive BRAKE NC GND HBIAS CP1 CP2 VBB VCP SENSE 9 HALL 24 23 22 21 20 19 18 17 PAD Enable HA+ HA– HB+ HB– 100 nF VCP VREG – 1 2 3 4 5 6 7 8 OVP Communication Logic VCP VBB + HA– HB+ HB– HC+ HC– FG+ FGFB FG– Charge Pump VREG HBIAS 2 kΩ HALL Pin-out Diagram Lock Detect CLD 100 nF CP2 PWM – FGS + FG– FG+ GND Terminal List Table Number Name Function Number Name Function 1 HA- Hall input A 18 GLB Low-side gate drive B 2 HB+ Hall input B 19 GLA Low-side gate drive A High-side gate drive C 3 HB- Hall input B 20 GHC 4 HC+ Hall input C 21 SC 5 HC- Hall input C 22 GHB 6 FG+ FG input 23 SB 7 FGFB FG amplifier feedback output 24 GHA 8 FG- FG input 25 SA 9 NC No internal connection 26 FGS FG output Ground 27 CLD Locked rotor detect timing capacitor Hall bias power supply output 28 DIR Logic input: motor direction High-side source connection C High-side gate drive B High-side source connection B High-side gate drive A High-side source connection A 10 GND 11 HBIAS 12 CP1 Charge pump capacitor terminal 29 PWM Logic input: external PWM control 13 CP2 Charge pump capacitor terminal 30 STOP Logic input: output disable 14 VBB Supply voltage 31 BRAKE 15 VCP Reservoir capacitor terminal 32 HA+ Hall input A 16 SENSE 17 GLC – PAD Exposed Thermal Pad Sense resistor connection Low-side gate drive C Logic input: motor brake Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A4936 3-Phase Brushless DC Motor Pre-Driver ELECTRICAL CHARACTERISTICS1,2 Valid at TA = 25°C, VIN = 24 V; unless otherwise noted Characteristics Symbol Test Conditions Typ.3 Max. 8.5 – VBBOV V – 5.1 6.5 mA Min. Unit General Supply Voltage Range Motor Supply Current VBB IBB Operating fPWM < 30 kHz, CLOAD = 1000 pF – 3 4 mA 7.2 7.5 7.8 V IHBIASlim 30 – – mA VIN(1) 2 – – V HBIAS VHBIAS HBIAS Current Limit Standby mode 0 mA ≤ IHBIAS ≤ 24 mA Control Logic Logic Input Voltage Logic Input Current – – 0.8 V IIN(1) VIN = 2 V –1.0 <1.0 1.0 μA IIN(0) VIN = 0.8 V –1.0 <–1.0 1.0 μA PWM pin 350 500 650 ns DIR, BRAKE, and STOP pins VIN(0) Input Pin Glitch Reject tGLITCH 700 1000 1300 ns HBIAS Wake-up Delay, Standby Mode tdHBIAS CHBIAS = 0.1 μF – 15 25 μs High-Side Gate Drive Output VGS(H) Relative to VBB, IGATE = 2 mA 7 – – V Gate Drive Low-Side Gate Drive Output VGS(L) IGATE = 2 mA 7 – – V Gate Drive Current (Sourcing) IGATE GHx = GLx = 4 V 20 30 – mA Gate Drive Pull-Down Resistance RGATE 10 28 40 Ω Dead Time tDEAD 700 1000 1300 ns Current Limit Input Threshold VREF 180 200 220 mV Fixed Off-Time tOFF 18 25 37 μs TJTSD 155 170 185 °C TJTSDhys – 20 – °C 6.2 7 7.85 V 0.4 0.75 1 V V Protection Thermal Shutdown Temperature Thermal Shutdown Hysteresis VBB UVLO Enable Threshold VBB UVLO Hysteresis VCP UVLO Lock Detect Duration VBB Overvoltage Threshold VBBUV Rising VBB VBBUVhys VCPUV Relative to VBB , VCP falling 4.6 – 6 tlock C = 0.1 μF 1.5 2 2.5 s VBBOV Rising VBB 30 33 37.5 V VIN = 0.2 to 3.5 V –1 0 1 μA Hall Logic Hall Input Current IHALL Common Mode Input Range VCMR 0.2 – 3.5 V AC Input Voltage Range VHALL 60 – – mVp-p Difference between Hall inputs at transitions – +10, –10 – mV TJ = 25°C 10 20 30 mV TJ = –20°C to 125°C 5 20 40 mV – 2 – μs Hall Thresholds Vth Hall Threshold Hysteresis VHYS Pulse Reject Filter tpulse Continued on the next page… Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A4936 3-Phase Brushless DC Motor Pre-Driver ELECTRICAL CHARACTERISTICS1,2 (continued) Valid at TA = 25°C, VIN = 24 V; unless otherwise noted Characteristics Symbol Test Conditions Min. Typ.3 Max. Unit FG FG Input Bias Current FG Input Offset Voltage IBFG –1 – 1 μA VOSFG –15 – 15 mV FGS Output High Leakage IOH VOH = 5 V –1 – 1 μA FGS Output Low Voltage VOL IOL = 2 mA – 0.2 0.4 V FG Amp Open Loop Gain AFG 45 60 – dB FG Amp Bias Voltage VBFG 2.2 2.5 2.8 V VFGhys 40 110 160 mV FG Comparator Hysteresis 1For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. 2Specifications throughout the allowed operating temperature range are guaranteed by design and characterization. 3Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum limits. Logic States Table* (See timing charts, below) Condition A B C Forward D E F A B C Reverse D E F HA HB HC DIR STOP + – + 1 0 + – – 1 0 + + – 1 0 – + – 1 0 – + + 1 0 – – + 1 0 + – + 0 0 + – – 0 0 + + – 0 0 – + – 0 0 – + + 0 0 – – + 0 0 – – – X X Fault + + + X X Brake X X X X 0 Coast X X X X 1 Standby X X X X 1 *X = Don’t care (can be 1 or 0), Z = High impedance BRAKE 0 0 0 0 0 0 0 0 0 0 0 0 X X 1 0 1 PWM 1 1 1 1 1 1 1 1 1 1 1 1 X X X X X GHA GLA GHB GLB GHC GLC SA SB SC HI HI LO LO LO LO LO LO LO HI HI LO LO LO LO LO LO LO LO LO HI HI LO HI HI LO LO LO LO LO LO HI LO LO LO LO HI HI LO LO HI LO LO LO LO HI LO LO LO LO LO HI LO LO LO LO HI LO LO HI HI LO LO LO LO HI LO LO LO LO LO LO HI HI LO HI HI LO LO LO LO LO LO LO LO LO HI HI LO LO LO LO LO LO LO HI HI LO LO HI LO LO HI HI Z LO LO Z LO LO Z HI HI Z Z Z LO Z Z LO Z HI HI Z LO HI Z LO LO Z HI Z Z LO Z Z Z LO LO Z HI HI Z HI HI Z LO LO Z Z LO Z Z DIR = 1 = Forward A B C D DIR = 0 = Reverse E F A HA HA HB HB HC HC SA SA SB SB SC SC B C D E F Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A4936 3-Phase Brushless DC Motor Pre-Driver Power-Up and Standby Mode Timing Diagram VBB VBBUV Charge Pump VCPUV HBIAS Voltage VHBIAS Standby Mode (Turn-off Hall bias supply) STOP BRAKE Don’t Care Don’t Care Outputs Enabled Outputs Disabled Outputs Enabled Power-Down Timing Diagram VBB VBBUV Charge Pump VCPUV HBIAS Voltage VHBIAS Outputs Enabled Outputs Disabled Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A4936 3-Phase Brushless DC Motor Pre-Driver Functional Description Current Regulation Load current is regulated by an internal fixed off-time PWM control circuit. When the outputs of the full bridge are turned on, current increases in the motor winding until it reaches a value, ITRIP , given by: ITRIP = 200 mV / RSENSE When ITRIP is reached, the sense comparator resets the source enable latch, turning off the source driver. At this point, load inductance causes the current to recirculate for the fixed off-time period. PWM Logic The PWM input terminal allows external PWM. PWM high turns on the selected sink-source pair. PWM low switches off the appropriate drivers and the load current decays. If PWM is held high, the current will rise until it reaches the level set by the internal current control circuit. Typically PWM frequency is in the 20 to 30 kHz range. The PWM logic is summarized in the following table: PWM Outputs Outputs State 1 On Drive 0 Source chopped Slow decay with synchronous rectification Fixed Off-Time The A4936 fixed off-time is set to 25 μs, nominal. PWM Blank Timer When a source driver turns on, a current spike occurs due to the reverse recovery currents of the clamp diodes as well as switching transients related to distributed capacitance in the load. To prevent this current spike from erroneously resetting the source enable latch, the sense comparator is blanked. The blanking timer runs after the off-time counter completes, in order to provide the blanking function. The blanking timer is reset when PWM is low or DIR is changed. With external PWM control, a DIR change or a PWM-on triggers the blanking function. The duration is fixed at 1.5 μs. Synchronous Rectification When a PWM-off cycle is triggered, either by a low input on PWM or by an internal fixed off-time cycle, load current recirculates. The A4936 synchronous rectification feature turns-on the appropriate MOSFETs during the current decay, and effectively shorts-out the body diodes with the low RDS(on) driver. This lowers power dissipation significantly and can eliminate the need for external Schottky diodes. Run Mode The motor phases are only energized when the STOP input is low. When the STOP input is high, all MOSFETs are held in the off state and the phase connections to the motor are high impedance. In this state a running motor will coast to stop. The STOP input overrides the PWM input. When STOP is high and BRAKE is high, the A4936 enters Standby mode. Brake Mode A logic high on the BRAKE pin activates Brake mode. A logic low allows normal operation. Braking turns on all three sink drivers, effectively shorting out the motor-generated BEMF. The BRAKE input overrides the PWM input and also the Lock Detect function. The STOP input must be low for Brake mode to operate. It is important to note that the internal PWM current control circuit does not limit the current when braking, because the current does not flow through the sense resistor. The maximum current can be approximated by VBEMF / RLOAD . Care should be taken to insure that the maximum ratings of the A4396 are not exceeded in the worse case braking situation of high speed and high inertial load. Standby Mode The reduced power Standby mode is provided to reduce current consumption when the motor is not required to be driven. The Hall bias supply and the charge pump are disabled and all MOSFETs are turned-off. The A4936 enters Standby mode when STOP and BRAKE are held high together. All other control inputs are ignored when in Standby mode. HBIAS Function This provides a power supply of 7.5 V, current-limited to 30 mA. This reference voltage is used to power the logic sections of the A4936 and also to power the external Hall elements. Charge Pump The internal charge pump is used to generate a supply above VBB to drive the high-side MOSFETs. The voltage on the VCP pin is internally monitored, and in case of a fault condition, the outputs of the device are disabled. Fault Shutdown In the event of a fault due to excessive junction temperature or due to low voltage on VCP or VBB, the outputs of the device are disabled until the fault condition is removed. At power-up the UVLO circuit disables the drivers. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A4936 3-Phase Brushless DC Motor Pre-Driver Overvoltage Protection VBB is monitored to determine if a hazardous voltage is present due to the motor generator pumping up the supply bus. When the voltage exceeds VBBOV , the synchronous rectification feature is disabled. Overtemperature Protection If die temperature exceeds approximately 165°C, the Thermal Shutdown function will disable the outputs until the internal temperature falls below the threshold, by the hysteresis. Lock Detect Function The A4936 monitors the Hall inputs and the control inputs to determine if a locked rotor condition is present. A locked rotor is determined to be present under either of these two different conditions: • The Hall inputs are not consistently changing. • The proper commutation sequence is not being followed. The motor can be locked in a condition in which it toggles between two specific Hall device states. If there are no Hall input changes within the lock time, tlock , or the Hall inputs toggle between two adjacent states for longer then tlock , then the outputs are disabled, and the fault is latched. The fault remains latched until cleared by any one of the following actions: • Rising or falling edge on the DIR pin. • VBB UVLO threshold exceeded (during power-up cycle). • PWM pin held low for > tlock / 2. The lock time, tlock , is set by a capacitor connected to the CLD pin. CLD produces a triangle waveform (1.67 V peak-to-peak) with frequency linearly related to the capacitor value. tlock is defined as 127 cycles of this triangle waveform, or: tlock = CLD × 20 where: tlock is the lock time in μs, and CLD is the value of the capacitor in μF. The Lock Detect function is disabled by connecting CLD to GND. When BRAKE is high, lock detection is disabled. It also is disabled if the PWM input remains low for the duration of the Hall input lock detection. FG Amplifier and Comparator A differential amplifier and a comparator are integrated into the A4936 to amplify and shape the FG signal from the FG coil underneath the motor. This coil is typically created with a copper PCB trace, and as the motor spins, the coil creates a low amplitude sinusoidal voltage with a frequency proportional to the motor speed. The FG input differential amplifier is biased at 2.5 V, and the gain is set by the impedance between the FGFB pin and the FG– input. This amplified signal is then compared to 2.5 V to create the FGS output signal. The recommended value for the gain setting feedback resistor is 50 to 500 kΩ. The recommended value for the capacitor between FB+ and GND is 10 nF to 10 μF. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A4936 3-Phase Brushless DC Motor Pre-Driver Package ET 32-Contact QFN 0.30 5.00 ±0.15 32 32 1 2 0.50 1.00 1 2 A 5.00 ±0.15 3.40 5.00 1 33X D SEATING PLANE 0.08 C +0.05 0.25 –0.07 0.90 ±0.10 0.50 BSC 3.40 C 5.00 C PCB Layout Reference View Concept Drawing For Reference Only; not for tooling use (reference JEDEC MO-220VHHD-6) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown 0.50±0.05 3.40 B 2 1 32 3.40 A Terminal #1 mark area B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) C Reference land pattern layout (reference IPC7351 QFN50P500X500X100-33V6M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Coplanarity includes exposed thermal pad and terminals Copyright ©2010, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9