IDT7187S IDT7187L CMOS STATIC RAM 64K (64K x 1-BIT) Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • High speed (equal access and cycle time) — Military: 25/35/45/55/70/85ns (max.) • Low power consumption • Battery backup operation—2V data retention (L version only) • JEDEC standard high-density 22-pin ceramic DIP, 22-pin leadless chip carrier • Produced with advanced CMOS high-performance technology • Separate data input and output • Input and output directly TTL-compatible • Military product compliant to MIL-STD-883, Class B The IDT7187 is a 65,536-bit high-speed static RAM organized as 64K x 1. It is fabricated using IDT’s highperformance, high-reliability CMOS technology. Access times as fast as 25ns are available. Both the standard (S) and low-power (L) versions of the IDT7187 provide two standby modes—ISB and ISB1. ISB provides low-power operation; ISB1 provides ultra-low-power operation. The low-power (L) version also provides the capability for data retention using battery backup. When using a 2V battery, the circuit typically consumes only 30µW. Ease of system design is achieved by the IDT7187 with full asynchronous operation, along with matching access and cycle times. The device is packaged in an industry standard 22-pin, 300 mil ceramic DIP, or 22-pin leadless chip carriers. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. FUNCTIONAL BLOCK DIAGRAM A A VCC A A GND 65,536-BIT MEMORY ARRAY ROW SELECT A A A CS DATA IN DATAOUT COLUMN I/O WE A A A A A A A 2986 drw 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc. MILITARY TEMPERATURE RANGE 1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. AUGUST 1996 6.2 2986/7 1 IDT7187S/L CMOS STATIC RAM 64K (64K x 1-BIT) MILITARY TEMPERATURE RANGE A1 A0 VCC A 15 PIN CONFIGURATIONS INDEX 3 20 DATAOUT WE GND 4 19 5 18 6 17 D22-1 7 16 8 15 9 14 10 13 11 12 VCC A15 A14 A13 A12 A11 A10 A9 A8 DATAIN CS 2 A2 A3 A4 A5 A6 A7 DATAOUT 22 21 1 3 20 19 4 18 5 6 L22-1 17 16 7 8 15 9 14 A14 A13 A12 A11 A10 A9 A8 10 11 12 13 2986 drw 02 CS 21 DATAIN 22 2 WE 1 GND A0 A1 A2 A3 A4 A5 A6 A7 2986 drw 03 22-PIN LCC TOP VIEW DIP TOP VIEW TRUTH TABLE(1) PIN DESCRIPTIONS Name Description Mode CS WE Output Power A0–A15 Address Inputs Standby H X High-Z Standby Chip Select Read L H DOUT Active Write Enable Write L L High-Z Active CS WE VCC NOTE: 1. H = VIH, L = VIL, X = don't care. Power DATAIN Data Input DATAOUT Data Output GND Ground 2986 tbl 02 2986 tbl 01 6.2 2 IDT7187S/L CMOS STATIC RAM 64K (64K x 1-BIT) MILITARY TEMPERATURE RANGE CAPACITANCE (TA = +25°C, F = 1.0MHZ) ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM Rating Com’l. Mil. Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 with Respect to GND V –55 to +125 °C Temperature Under Bias –55 to +125 –65 to +135 °C TSTG Storage Temperature –55 to +125 –65 to +150 °C PT Power Dissipation 1.0 1.0 W IOUT DC Output Current 50 50 mA TA Operating Temperature TBIAS 0 to +70 Parameter(1) Symbol Unit Conditions Max. Unit CIN Input Capacitance VIN = 0V 8 pF COUT Output Capacitance VOUT = 0V 8 pF NOTE: 2986 tbl 04 1. This parameter is determined by device characterization, but is not production tested. RECOMMENDED DC OPERATING CONDITIONS NOTE: 2986 tbl 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Symbol Parameter Min. Typ. Max. Unit V VCC Supply Voltage 4.5 5.0 5.5 GND Supply Voltage 0 0 0 V VIH Input High Voltage 2.2 — 6.0 V VIL Input Low Voltage –0.5(1) — 0.8 V NOTE: 2986 tbl 05 1. VIL (min.) = –3.0V for pulse width less than 20ns, once per cycle. RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Grade Temperature GND VCC Military –55°C to +125°C 0V 5V ± 10% Commercial 0°C to +70°C 0V 5V ± 10% 2986 tbl 06 DC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%) IDT7187S Symbol Parameter |ILI| Input Leakage Current |ILO| Output Leakage Current VOL Output Low Voltage VOH Output High Voltage Test Condition IDT7187L Min. Max. Min. Max. Unit MIL. COM’L. — — 10 5 — — 5 2 µA MIL. COM’L. — — 10 5 — — 5 2 µA IOL = 10mA, VCC = Min. IOL = 8mA, VCC = Min. 0.5 0.4 — — 0.5 0.4 V — IOH = –4mA, VCC = Min. 2.4 — 2.4 — VCC = Max., VIN = GND to VCC VCC = Max., CS = VIH, VOUT = GND to VCC V 2986 tbl 07 6.2 3 IDT7187S/L CMOS STATIC RAM 64K (64K x 1-BIT) MILITARY TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS(1) (VCC = 5V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V) 7187S25 7187L25 Symbol ICC1 ICC2 ISB ISB1 Parameter Power Com’l. 7187S35 7187L35 7187S45 7187L45 Mil. Com’l. Mil. Com’l. Mil. 7187S55/70 7187L55/70 7187S85 7187L85 Com’l. Mil. Com’l. Mil. Unit mA Operating Power Supply Current CS = VIL, Outputs Open VCC = Max., f = 0(2) S — 105 — 105 — 105 — 105 — 105 L — 85 — 85 — 85 — 85 — 85 Dynamic Operating Current CS = VIL, Outputs Open VCC = Max., f = fMAX(2) S — 130 — 120 — 120 — 120 — 120 L — 110 — 100 — 95 — 90 — 90 Standby Power Supply Current (TTL Level) CS ≥ VIH, VCC = Max., Outputs Open, f = fMAX(2) S — 55 — 50 — 50 — 50 — 50 L — 50 — 40 — 35 — 30/28 — 28 Full Standby Power Supply Current (CMOS Level) CS ≥ VHC, VCC=Max., VIN ≥ VHC or VIN ≤ VLC, f = 0(2) S — 20 — 20 — 20 — 20 — 20 L — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 NOTES: 1. All values are maximum guaranteed values. 2. At f = fMAX address and data inputs are cycling at the maximum frequency of read cycles of 1/tRC. f = 0 means no input lines change. mA mA mA 2986 tbl 08 DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES (L Version Only) VHC = VCC - 0.2V, VLC = 0.2V Typ. (1) VCC @ Symbol Parameter VDR VCC for Data Retention ICCDR Data Retention Current tCDR(3) Chip Deselect to Data Retention Time tR(3) Operation Recovery Time (3) |ILI| Test Condition — MIL. COM’L. CS ≥ VHC VIN ≥ VHC or ≤ VLC Input Leakage Current Max. VCC @ Min. 2.0v 3.0V 2.0V 3.0V Unit 2.0 — — — — V — — 10 10 15 15 600 150 900 225 µA 0 — — — — ns tRC(2) — — — — ns — — — 2 2 NOTES: 1. TA = +25°C. 2. tRC = Read Cycle Time. 3. This parameter is guaranteed, but not tested. LOW VCC DATA RETENTION WAVEFORM V CC CS DATA RETENTION MODE 4.5V 4.5V V DR ≥2V tCDR µA 2986 tbl 09 tR V IH V IH V DR 2986 drw 04 6.2 4 IDT7187S/L CMOS STATIC RAM 64K (64K x 1-BIT) MILITARY TEMPERATURE RANGE AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise/Fall Times 5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V AC Test Load See Figures 1 and 2 2986 tbl 10 5V 5V 480Ω 480Ω DATAOUT DATAOUT 255Ω 255Ω 30pF* 5pF* 2986 drw 05 2986 drw 06 Figure 1. AC Test Load Figure 2. AC Test Load (for tHZ, tLZ, tWZ and tOW) *Includes scope and jig capacitances AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges) 7187S25 7187L25 Symbol Parameter 7187S35/45(1) 7187L35/45(1) 7187S55(1) 7187L55(1) 7187S70(1) 7187L70(1) 7187S85(1) 7187L85(1) Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Read Cycle tRC Read Cycle Time 25 — 35/45 — 55 — 70 — 85 — ns tAA Address Access Time — 25 — 35/45 — 55 — 70 — 85 ns tACS Chip Select Access Time — 25 — 35/45 — 55 — 70 — 85 ns tOH Output Hold from Address Change 5 — 5 — 5 — 5 — 5 — ns Output Selection to Output in Low-Z 5 — 5 — 5 — 5 — 5 — ns tLZ (2) tHZ(2) Chip Deselect to Output in High-Z — 12 — 17/20 — 30 — 30 — 40 ns tPU (2) Chip Select to Power-Up Time 0 — 0 — 0 — 0 — 0 — ns tPD (2) Chip Deselect to Power-Down Time — 20 — 30/35 — 35 — 35 — 40 ns NOTES: 1. –55°C to +125°C temperature range only. 2. This parameter guaranteed but not tested. 2986 tbl 11 6.2 5 IDT7187S/L CMOS STATIC RAM 64K (64K x 1-BIT) MILITARY TEMPERATURE RANGE TIMING WAVEFORM OF READ CYCLE NO. 1 (1,2) tRC (5) ADDRESS tAA tOH PREVIOUS DATA VALID DATAOUT DATA VALID 2986 drw 07 TIMING WAVEFORM OF READ CYCLE NO. 2 (1,3) t RC (5) CS t HZ (4) tACS tLZ (4) t PU VCC SUPPLY CURRENT HIGH DATA VALID DATAOUT IMPEDANCE t PD ICC ISB 2986 drw 08 NOTES: 1. WE is HIGH for Read cycle. 2. CS is LOW for Read cycle. 3. Address valid prior to or coincident with CS transition LOW. 4. Transition is measured ±200mV from steady state voltage with specified loading in Figure 2. 5. All Read cycle timings are referenced from the last valid address to the first transitioning address. AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges) 7187S25 7187L25 Symbol Parameter 7187S35/45(1) 7187S55(1) 7187L35/45(1) 7187L55(1) 7187S70(1) 7187L70(1) 7187S85(1) 7187L85(1) Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Write Cycle tWC Write Cycle Time 25 — 35/45 — 55 — 70 — 85 — ns tCW Chip Select to End-of-Write 20 — 25/40 — 50 — 55 — 65 — ns tAW Address Valid to End-of-Write 20 — 25/40 — 50 — 55 — 65 — ns tAS Address Set-up Time 0 — 0 — 0 — 0 — 0 — ns tWP Write Pulse Width 20 — 20/25 — 35 — 40 — 45 — ns tWR Write Recovery Time 0 — 0 — 0 — 0 — 0 — ns tDW Data Valid to End-of-Write 15 — 15/25 — 25 — 30 — 35 — ns tDH Data Hold Time 5 — 5 — 5 — 5 — 5 — ns Write Enable to Output in High-Z — 12 — 15/30 — 30 — 30 — 40 ns Output Active from End-of-Write 0 — 0 — 0 — 0 — 0 — tWZ (2) tOW(2) NOTES: 1. –55°C to +125°C temperature range only. 2. This parameter guaranteed but not tested. ns 2986 tbl 12 6.2 6 IDT7187S/L CMOS STATIC RAM 64K (64K x 1-BIT) MILITARY TEMPERATURE RANGE TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING) (1,2,3,4) t WC ADDRESS t AW CS tWP t AS t WR WE t WZ (5) tOW (5) DATA OUT t DW DATA IN t DH VALID DATA 2986 drw 09 NOTES: 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE. 3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state. 5. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING) (1,2,4) t WC ADDRESS t AW CS tAS tCW tWR (3) WE t DW DATA IN t DH VALID DATA 2986 drw 10 NOTES: 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE. 3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state. 5. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). 6.2 7 IDT7187S/L CMOS STATIC RAM 64K (64K x 1-BIT) MILITARY TEMPERATURE RANGE ORDERING INFORMATION IDT7187 Device Type X XX X X Power Speed Package Process/ Temperature Range B Military (–55°C to +125°C) Compliant to MIL-STD-883, Class B D L22 300 mil Ceramic DIP (D22-1) Leadless Chip Carrier (L22-1) 25 35 45 55 70 85 Speed in nanoseconds S L Standard Power Low Power 2989 drw 11 6.2 8