Freescale MK10X256VLH150 K10 sub-family data sheet Datasheet

Freescale Semiconductor
Data Sheet: Product Preview
K10 Sub-Family Data Sheet
Document Number: K10P81M100SF2
Rev. 1, 11/2010
K10P81M100SF2
Supports the following:
MK10N512VLK100, MK10N512VMB100
• Human-machine interface
– Low-power hardware touch sensor interface (TSI)
– General-purpose input/output
• Analog modules
– 16-bit SAR ADC with PGA (x64)
– 12-bit DAC
– Analog comparator (CMP) containing a 6-bit DAC
and programmable reference input
– Voltage reference
Pr
el
im
in
ar
y
Features
• Operating Characteristics
– Voltage range: 1.71 to 3.6 V
– Flash write voltage range: 1.71 to 3.6 V
– Temperature range (ambient): -40 to 105°C
• Performance
– Up to 100 MHz ARM Cortex-M4 core with DSP
instructions delivering 1.25 Dhrystone MIPS per
MHz
• Memories and memory interfaces
– Up to 512 KB program flash memory on nonFlexMemory devices
– Up to 128 KB RAM
– Serial programming interface (EzPort)
– FlexBus external bus interface
• Clocks
– 1 to 32 MHz crystal oscillator
– 32 kHz crystal oscillator
– Multi-purpose clock generator
• System peripherals
– 10 low-power modes to provide power optimization
based on application requirements
– Memory protection unit with multi-master
protection
– 16-channel DMA controller, supporting up to 64
request sources
– External watchdog monitor
– Software watchdog
– Low-leakage wakeup unit
• Timers
– Programmable delay block
– Eight-channel motor control/general purpose/PWM
timers
– Two-channel quadrature decoder/general purpose
timers
– Periodic interrupt timers
– 16-bit low-power timer
– Carrier modulator transmitter
– Real-time clock
• Communication interfaces
– Controller Area Network (CAN) module
– SPI modules
– I2C modules
– UART modules
– Secure Digital host controller (SDHC)
– I2S
• Security and integrity modules
– Hardware CRC module to support fast cyclic
redundancy checks
– Hardware random-number generator
– 128-bit unique identification (ID) number per chip
This document contains information on a product under development. Freescale
reserves the right to change or discontinue this product without notice.
© 2010–2010 Freescale Semiconductor, Inc.
Preliminary
Table of Contents
1 Ordering parts...........................................................................4
6.1 Core modules....................................................................19
1.1 Determining valid orderable parts......................................4
6.1.1
Debug trace timing specifications.........................19
2 Part identification......................................................................4
6.1.2
JTAG electricals....................................................20
2.1 Description.........................................................................4
6.2 System modules................................................................23
2.2 Format...............................................................................4
6.3 Clock modules...................................................................23
2.3 Fields.................................................................................4
6.3.1
MCG Specifications...............................................23
2.4 Example............................................................................5
6.3.2
Oscillator Electrical Characteristics.......................25
3 Terminology and guidelines......................................................5
6.3.2.1
Oscillator DC Electrical Specifications 25
3.1 Definition: Operating requirement......................................5
6.3.2.2
Oscillator frequency specifications......26
6.3.3
32kHz Oscillator Electrical Characteristics............27
Pr
el
im
in
ar
y
3.2 Definition: Operating behavior...........................................6
3.3 Definition: Attribute............................................................6
6.3.3.1
3.4 Definition: Rating...............................................................7
32kHz Oscillator DC Electrical
Specifications......................................27
3.5 Result of exceeding a rating..............................................7
6.3.3.2
3.6 Relationship between ratings and operating
32kHz Oscillator Frequency
Specifications......................................27
requirements......................................................................7
6.4 Memories and memory interfaces.....................................28
3.7 Guidelines for ratings and operating requirements............8
6.4.1
3.8 Definition: Typical value.....................................................8
Flash (FTFL) Electrical Characteristics.................28
6.4.1.1
3.9 Typical Value Conditions...................................................9
Flash Timing Parameters — Program
and Erase............................................28
4 Ratings......................................................................................9
6.4.1.2
4.1 Thermal handling ratings...................................................9
Flash Timing Parameters —
Commands..........................................28
4.2 Moisture handling ratings..................................................10
6.4.1.3
4.3 ESD handling ratings.........................................................10
Flash (FTFL) Current and Power
Parameters..........................................29
4.4 Voltage and current operating ratings...............................10
6.4.1.4
Reliability Characteristics....................29
5 General.....................................................................................11
6.4.2
EzPort Switching Specifications............................29
5.1 Nonswitching electrical specifications...............................11
6.4.3
Flexbus Switching Specifications..........................30
5.1.1
Voltage and Current Operating Requirements......11
6.5 Security and integrity modules..........................................32
5.1.2
LVD and POR operating requirements.................12
6.6 Analog...............................................................................32
5.1.3
Voltage and current operating behaviors..............13
5.1.4
Power mode transition operating behaviors..........13
6.6.1.1
16-bit ADC operating conditions..........33
5.1.5
Power consumption operating behaviors..............14
6.6.1.2
16-bit ADC electrical characteristics....35
5.1.5.1
6.6.1.3
16-bit ADC with PGA operating
6.6.1
Diagram: Typical IDD_RUN operating
ADC electrical specifications.................................32
behavior...............................................16
conditions............................................38
5.1.6
EMC radiated emissions operating behaviors.......17
6.6.1.4
16-bit ADC with PGA characteristics...39
5.1.7
Designing with radiated emissions in mind...........18
6.6.2
CMP and 6-bit DAC electrical specifications.........40
5.1.8
Capacitance attributes..........................................18
6.6.3
12-bit DAC electrical characteristics.....................41
5.2 Switching electrical specifications.....................................18
6.6.3.1
12-bit DAC operating requirements.....41
5.3 Thermal specifications.......................................................18
6.6.3.2
12-bit DAC operating behaviors..........42
5.3.1
Thermal operating requirements...........................18
6.6.4
Voltage Reference Electrical Specifications..........44
5.3.2
Thermal attributes.................................................19
6.7 Timers................................................................................45
6 Peripheral operating requirements and behaviors....................19
6.8 Communication interfaces.................................................45
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
2
Preliminary
Freescale Semiconductor, Inc.
6.8.1
DSPI Switching Specifications for Low-speed
6.9.2
Operation..............................................................46
6.8.2
DSPI Switching Specifications (High-speed
TSI Electrical Specifications..................................52
7 Dimensions...............................................................................53
7.1 Obtaining package dimensions.........................................53
mode)....................................................................47
8 Pinout........................................................................................54
6.8.3
SDHC Specifications.............................................49
8.1 K10 Signal Multiplexing and Pin Assignments..................54
6.8.4
I2S Switching Specifications.................................50
8.2 K10 Pinouts.......................................................................57
6.9 Human-machine interfaces (HMI)......................................52
9 Revision History........................................................................58
General Switching Specifications..........................52
Pr
el
im
in
ar
y
6.9.1
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
3
Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Pr
el
im
in
ar
y
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to www.freescale.com and perform a part number search for
the following device numbers: PK10 and MK10.
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q K## M FFF T PP CCC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
K##
Kinetis family
• K10
M
Flash memory type
• N = Program flash only
• X = Program flash and FlexMemory
Table continues on the next page...
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
4
Preliminary
Freescale Semiconductor, Inc.
Terminology and guidelines
Field
Description
Values
Program flash memory size
•
•
•
•
•
•
32 = 32 KB
64 = 64 KB
128 = 128 KB
256 = 256 KB
512 = 512 KB
1M0 = 1 MB
T
Temperature range (°C)
• V = –40 to 105
PP
Package identifier
•
•
•
•
•
•
•
•
•
•
•
•
•
FM = 32 QFN (5 mm x 5 mm)
FT = 48 QFN (7 mm x 7 mm)
LF = 48 LQFP (7 mm x 7 mm)
FX = 64 QFN (9 mm x 9 mm)
LH = 64 LQFP (10 mm x 10 mm)
LK = 80 LQFP (12 mm x 12 mm)
MB = 81 MAPBGA (8 mm x 8 mm)
LL = 100 LQFP (14 mm x 14 mm)
ML = 104 MAPBGA (8 mm x 8 mm)
LQ = 144 LQFP (20 mm x 20 mm)
MD = 144 MAPBGA (13 mm x 13 mm)
MF = 196 MAPBGA (15 mm x 15 mm)
MJ = 256 MAPBGA (17 mm x 17 mm)
CCC
Maximum CPU frequency (MHz)
•
•
•
•
•
50 = 50 MHz
72 = 72 MHz
100 = 100 MHz
120 = 120 MHz
150 = 150 MHz
N
Packaging type
• R = Tape and reel
• (Blank) = Trays
Pr
el
im
in
ar
y
FFF
2.4 Example
This is an example part number:
MK10N512VMD100
3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
5
Terminology and guidelines
3.1.1 Example
This is an example of an operating requirement, which you must meet for the
accompanying operating behaviors to be guaranteed:
Symbol
1.0 V core supply volt‐
age
Min.
0.9
Max.
Unit
1.1
V
Pr
el
im
in
ar
y
VDD
Description
3.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a technical
characteristic that are guaranteed during operation if you meet the operating requirements
and any other specified conditions.
3.2.1 Example
This is an example of an operating behavior, which is guaranteed if you meet the
accompanying operating requirements:
Symbol
IWP
Description
Min.
Digital I/O weak pullup/ 10
pulldown current
Max.
130
Unit
µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute:
Symbol
CIN_D
Description
Min.
Input capacitance: digi‐ —
tal pins
Max.
Unit
7
pF
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
6
Preliminary
Freescale Semiconductor, Inc.
Terminology and guidelines
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
Pr
el
im
in
ar
y
3.4.1 Example
This is an example of an operating rating:
Symbol
VDD
Description
Min.
1.0 V core supply volt‐
age
–0.3
Max.
1.2
Unit
V
3.5 Result of exceeding a rating
Failures in time (ppm)
40
30
20
10
0
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
Operating rating
Measured characteristic
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
7
Terminology and guidelines
3.6 Relationship between ratings and operating requirements
mi
g(
era
Op
g
tin
h
or
g
dlin
an
in
rat
n.)
ing
t
era
Op
x.)
ma
.)
)
in.
t (m
en
m
re
ax
t (m
en
m
re
ui
req
g
tin
era
Op
g
dlin
an
ui
req
g
tin
(
ing
rat
h
or
era
Op
Fatal
range
Limited
operating
range
Normal
operating
range
Limited
operating
range
Fatal
range
- Probable permanent failure
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- Probable permanent failure
Handling range
Pr
el
im
in
ar
y
- No permanent failure
–∞
∞
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
IWP
Description
Digital I/O weak
pullup/pulldown
current
Min.
10
Typ.
70
Max.
130
Unit
µA
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
8
Preliminary
Freescale Semiconductor, Inc.
Ratings
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
5000
4500
4000
TJ
150 °C
3000
Pr
el
im
in
ar
y
IDD_STOP (μA)
3500
105 °C
2500
25 °C
2000
–40 °C
1500
1000
500
0
0.90
0.95
1.05
1.00
1.10
VDD (V)
3.9 Typical Value Conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Value
Unit
TA
Ambient temperature
25
°C
VDD
3.3 V supply voltage
3.3
V
4 Ratings
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
9
Ratings
4.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
Solder temperature, leaded
—
245
Pr
el
im
in
ar
y
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
-2000
+2000
V
1
VCDM
Electrostatic discharge voltage, charged-device model
-500
+500
V
2
Latch-up current at ambient temperature of 85°C
-100
+100
mA
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
4.4 Voltage and current operating ratings
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.8
V
IDD
Digital supply current
—
185
mA
VDIO
Digital input voltage (except RESET, EXTAL, and XTAL)
–0.3
5.5
V
VAIO
Analog, RESET, EXTAL, and XTAL input voltage
–0.3
VDD + 0.3
V
Table continues on the next page...
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
10
Preliminary
Freescale Semiconductor, Inc.
General
Symbol
ID
Description
Min.
Max.
Unit
Instantaneous maximum current single pin limit (applies to all
port pins)
–25
25
mA
VDDA
Analog supply voltage
VDD – 0.3
VDD + 0.3
V
IDDA
Analog supply current1
TBD
TBD
mA
VBAT
RTC battery supply voltage
–0.3
3.8
V
VRAM
VDD voltage required to retain RAM
1.2
—
V
TBD
—
V
VRFVBAT
VBAT voltage required to retain the VBAT register file
5 General
Pr
el
im
in
ar
y
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
5.1 Nonswitching electrical specifications
5.1.1 Voltage and Current Operating Requirements
Table 1. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
VDD
Supply voltage
1.71
3.6
V
VDDA
Analog supply voltage
1.71
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
–0.1
0.1
V
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
0.1
V
• 2.7 V ≤ VDD ≤ 3.6 V
0.7 × VDD
—
V
• 1.7 V ≤ VDD ≤ 2.7 V
0.75 × VDD
—
V
• 2.7 V ≤ VDD ≤ 3.6 V
—
0.35 × VDD
V
• 1.7 V ≤ VDD ≤ 2.7 V
—
0.3 × VDD
V
0.06 × VDD
—
V
VIH
VIL
VHYS
Notes
Input high voltage
Input low voltage
Input hysteresis
Table continues on the next page...
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
11
General
Table 1. Voltage and current operating requirements (continued)
Symbol
IIC
Description
Min.
Max.
Unit
DC injection current — single pin
Notes
1
• VIN > VDD
0
2
mA
• VIN < VSS
0
–0.2
mA
DC injection current — total MCU limit, includes sum
of all stressed pins
• VIN > VDD
1
• VIN < VSS
0
25
mA
0
–5
mA
Pr
el
im
in
ar
y
1. All functional non-supply pins are internally clamped to VSS and VDD. Input must be current limited to the value specified.
To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp
voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during
instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the
injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external
VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not
consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall
power consumption).
5.1.2 LVD and POR operating requirements
Table 2. LVD and POR operating requirements
Symbol
Description
Min.
Typ.
Max.
Unit
VPOR
Falling VDD POR detect voltage
TBD
1.1
TBD
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
TBD
2.56
TBD
V
Low-voltage warning thresholds — high range
VLVW1
• Level 1 falling (LVWV=00)
TBD
2.70
TBD
V
VLVW2
• Level 2 falling (LVWV=01)
TBD
2.80
TBD
V
VLVW3
• Level 3 falling (LVWV=10)
TBD
2.90
TBD
V
VLVW4
• Level 4 falling (LVWV=11)
TBD
3.00
TBD
V
VHYS
Low-voltage inhibit reset/recover hysteresis —
high range
VLVDL
Falling low-voltage detect threshold — low range
(LVDV=00)
60
TBD
TBD
Notes
1
mV
TBD
V
Low-voltage warning thresholds — low range
1
VLVW1
• Level 1 falling (LVWV=00)
TBD
1.80
TBD
V
VLVW2
• Level 2 falling (LVWV=01)
TBD
1.90
TBD
V
VLVW3
• Level 3 falling (LVWV=10)
TBD
2.00
TBD
V
VLVW4
• Level 4 falling (LVWV=11)
TBD
2.10
TBD
V
Table continues on the next page...
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
12
Preliminary
Freescale Semiconductor, Inc.
General
Table 2. LVD and POR operating requirements (continued)
Symbol
Description
Min.
Typ.
Max.
40
Unit
VHYS
Low-voltage inhibit reset/recover hysteresis —
low range
VBG
Bandgap voltage reference
TBD
1.00
TBD
V
tLPO
Internal low power oscillator period
TBD
1000
TBD
μs
Notes
mV
factory trimmed
Pr
el
im
in
ar
y
1. Rising thresholds are falling threshold + VHYS
5.1.3 Voltage and current operating behaviors
Table 3. Voltage and current operating behaviors
Symbol
Min.
Max.
Unit
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -10mA
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA
VDD – 0.5
—
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA
VDD – 0.5
—
V
—
100
mA
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 10mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3mA
—
0.5
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6mA
—
0.5
V
Output low current total for all ports
—
100
mA
IIN
Input leakage current (per pin)
—
1
μA
IOZ
Hi-Z (off-state) leakage current (per pin)
—
1
μA
Internal weak pullup and pulldown resistors
30
50
kΩ
VOH
Description
Notes
Output high voltage — high drive strength
Output high voltage — low drive strength
IOHT
Output high current total for all ports
VOL
Output low voltage — high drive strength
Output low voltage — low drive strength
IOLT
RPU and
RPD
1
1. Measured at VIL max and VDD min
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
13
General
5.1.4 Power mode transition operating behaviors
In the table below, all specifications except tPOR, assume the following clock
configuration:
• CPU and system clocks = 100MHz
• Bus and FlexBus clocks = 50 MHz
• Flash clock = 25 MHz
Table 4. Power mode transition operating behaviors
tPOR
Description
Min.
Max.
Unit
Pr
el
im
in
ar
y
Symbol
After a POR event, amount of time from the point VDD
reaches 1.8V to execution of the first instruction
across the operating temperature range of the chip.
—
300
μs
• RUN → VLLS1
—
4.1
μs
• VLLS1 → RUN
—
123.8
μs
• RUN → VLLS2
—
4.1
μs
• VLLS2 → RUN
—
49.3
μs
• RUN → VLLS3
—
4.1
μs
• VLLS3 → RUN
—
49.2
μs
• RUN → LLS
—
4.1
μs
• LLS → RUN
—
5.9
μs
• RUN → STOP
—
4.1
μs
• STOP → RUN
—
4.2
μs
• RUN → VLPS
—
4.1
μs
• VLPS → RUN
—
5.8
μs
Notes
1
RUN → VLLS1 → RUN
RUN → VLLS2 → RUN
RUN → VLLS3 → RUN
RUN → LLS → RUN
RUN → STOP → RUN
RUN → VLPS → RUN
1. Normal boot (FTFL_OPT[LPBOOT]=1)
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
14
Preliminary
Freescale Semiconductor, Inc.
General
5.1.5 Power consumption operating behaviors
Table 5. Power consumption operating behaviors
Symbol
Description
Min.
IDD_RUN
Run mode current — all peripheral clocks disa‐
bled, code executing from flash
• @ 1.8V
• @ 3.0V
IDD_RUN
Typ.
Max.
Unit
1
—
40
TBD
mA
—
42
TBD
mA
Run mode current — all peripheral clocks ena‐
bled, code executing from flash
• @ 1.8V
2
—
55
TBD
mA
Pr
el
im
in
ar
y
• @ 3.0V
—
IDD_RUN_M Run mode current — all peripheral clocks ena‐
bled and peripherals active, code executing from
AX
flash
• @ 1.8V
• @ 3.0V
Notes
56
TBD
mA
—
85
TBD
mA
—
85
TBD
mA
3
IDD_WAIT
Wait mode current at 3.0 V — all peripheral
clocks disabled
—
15
TBD
mA
IDD_STOP
Stop mode current at 3.0 V
—
1.4
TBD
mA
IDD_VLPR
Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
—
1.25
TBD
mA
5
IDD_VLPR
Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
—
TBD
TBD
mA
6
IDD_VLPW
Very-low-power wait mode current at 3.0 V
—
1.05
TBD
mA
7
IDD_VLPS
Very-low-power stop mode current at 3.0 V
—
30
TBD
μA
IDD_LLS
Low leakage stop mode current at 3.0 V
—
12
TBD
μA
—
8
TBD
μA
IDD_VLLS3
4
Very low-leakage stop mode 3 current at 3.0 V
• 128KB RAM devices
IDD_VLLS2
Very low-leakage stop mode 2 current at 3.0 V
—
4
TBD
μA
IDD_VLLS1
Very low-leakage stop mode 1 current at 3.0 V
—
2
TBD
μA
IDD_VBAT
Average current when CPU is not accessing
RTC registers at 3.0 V
—
550
TBD
nA
1. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock . MCG configured for FEI mode.
All peripheral clocks disabled.
2. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock. MCG configured for FEI mode. All
peripheral clocks enabled, but peripherals are not in active operation.
3. 100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock. MCG configured for FEI mode. All
peripheral clocks enabled, and peripherals are in active operation.
4. 25MHz core and system clock, 25MHz bus clock, and 12.5MHz FlexBus and flash clock. MCG configured for FEI mode.
5. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral
clocks disabled. Code executing from flash.
6. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral
clocks enabled but peripherals are not in active operation. Code executing from flash.
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
15
General
7. 2 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for fast IRCLK mode. All peripheral
clocks disabled.
5.1.5.1
Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE)
All peripheral clocks disabled except FTFL
LVD disabled
No GPIOs toggled
Code execution from flash
Pr
el
im
in
ar
y
•
•
•
•
•
Figure 1. Run mode supply current vs. core frequency — all peripheral clocks disabled
The following data was measured under these conditions:
•
•
•
•
•
MCG in FEI mode (39.0625 kHz IRC), except for 1 MHz core (FBE)
All peripheral clocks enabled but peripherals are not in active operation
LVD disabled
No GPIOs toggled
Code execution from flash
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
16
Preliminary
Freescale Semiconductor, Inc.
Pr
el
im
in
ar
y
General
Figure 2. Run mode supply current vs. core frequency — all peripheral clocks enabled
5.1.6 EMC radiated emissions operating behaviors
Table 6. EMC radiated emissions operating behaviors
Symbol
Description
Frequency
band (MHz)
Typ.
Unit
Notes
dBμV
1, 2
—
2, 3
VRE1
Radiated emissions voltage, band 1
0.15–50
TBD
VRE2
Radiated emissions voltage, band 2
50–150
TBD
VRE3
Radiated emissions voltage, band 3
150–500
TBD
VRE4
Radiated emissions voltage, band 4
500–1000
TBD
0.15–1000
TBD
VRE_IEC_SAE IEC and SAE level
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions, IEC Standard 61967-2, Integrated Circuits - Measurement of
Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method, and SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits—TEM/
Wideband TEM (GTEM) Cell Method.
2. VDD = 3 V, TA = 25 °C, fOSC = 16 MHz (crystal), fBUS = 20 MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method, and Appendix D of SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated
Circuits—TEM/Wideband TEM (GTEM) Cell Method.
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
17
General
5.1.7 Designing with radiated emissions in mind
1. To find application notes that provide guidance on designing your system to
minimize interference from radiated emissions, go to www.freescale.com and
perform a keyword search for “EMC design.”
5.1.8 Capacitance attributes
Symbol
Pr
el
im
in
ar
y
Table 7. Capacitance attributes
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
5.2 Switching electrical specifications
Table 8. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
Normal run mode
fSYS
System and core clock
—
100
MHz
fBUS
Bus clock
—
50
MHz
FlexBus clock
—
50
MHz
Flash clock
—
25
MHz
FB_CLK
fFLASH
VLPR mode
fSYS
System and core clock
—
2
MHz
fBUS
Bus clock
—
2
MHz
FlexBus clock
—
2
MHz
Flash clock
—
1
MHz
FB_CLK
fFLASH
5.3 Thermal specifications
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
18
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
5.3.1 Thermal operating requirements
Table 9. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
125
°C
TA
Ambient temperature
–40
105
°C
5.3.2 Thermal attributes
Symbol
Description
81
80 LQFP Unit
MAPBGA
Notes
Singlelayer (1s)
RθJA
Thermal resistance, junction to ambient (natural
convection)
TBD
TBD
°C/W
1
Four-layer
(2s2p)
RθJA
Thermal resistance, junction to ambient (natural
convection)
TBD
TBD
°C/W
1
Singlelayer (1s)
RθJMA
Thermal resistance, junction to ambient (200 ft./
min. air speed)
TBD
TBD
°C/W
1
Four-layer
(2s2p)
RθJMA
Thermal resistance, junction to ambient (200 ft./
min. air speed)
TBD
TBD
°C/W
1
—
RθJB
Thermal resistance, junction to board
TBD
TBD
°C/W
2
—
RθJC
Thermal resistance, junction to case
TBD
TBD
°C/W
3
—
ΨJT
Thermal characterization parameter, junction to
package top outside center (natural convection)
TBD
TBD
°C/W
4
Pr
el
im
in
ar
y
Board
type
6 Peripheral operating requirements and behaviors
6.1 Core modules
1.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions
—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material between
the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
19
Peripheral operating requirements and behaviors
6.1.1 Debug trace timing specifications
Table 10. Debug trace operating behaviors
Description
Min.
Max.
Unit
Tcyc
Clock period
Frequency dependent
MHz
Twl
Low pulse width
2
—
ns
Twh
High pulse width
2
—
ns
Tr
Clock and data rise time
—
3
ns
Tf
Clock and data fall time
—
3
ns
Ts
Data setup
3
—
ns
Th
Data hold
Pr
el
im
in
ar
y
Symbol
2
—
ns
Figure 3. TRACE_CLKOUT specifications
TRACE_CLKOUT
Ts
TRACE_D[3:0]
Th
Ts
Th
Figure 4. Trace data specifications
6.1.2 JTAG electricals
Table 11. JTAG electricals
Symbol
J1
J2
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
TCLK frequency of operation
MHz
• JTAG and CJTAG
0
25
• Serial Wire Debug
0
50
1/J1
—
TCLK cycle period
ns
Table continues on the next page...
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
20
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 11. JTAG electricals (continued)
Symbol
J3
Description
Min.
Max.
TCLK clock pulse width
Unit
ns
20
—
• Serial Wire Debug
10
—
J4
TCLK rise and fall times
—
3
ns
J5
Boundary scan input data setup time to TCLK rise
20
—
ns
J6
Boundary scan input data hold time after TCLK rise
0
—
ns
J7
TCLK low to boundary scan output data valid
—
30
ns
J8
TCLK low to boundary scan output high-Z
—
30
ns
J9
TMS, TDI input data setup time to TCLK rise
16
—
ns
J10
TMS, TDI input data hold time after TCLK rise
1
—
ns
J11
TCLK low to TDO data valid
—
4
ns
J12
TCLK low to TDO high-Z
—
4
ns
J13
TRST assert time
100
—
ns
J14
TRST setup time (negation) to TCLK high
8
—
ns
Pr
el
im
in
ar
y
• JTAG and CJTAG
J2
J3
J3
TCLK (input)
J4
J4
Figure 5. Test clock input timing
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
21
Peripheral operating requirements and behaviors
TCLK
J5
Data inputs
J6
Input data valid
J7
Data outputs
Output data valid
Pr
el
im
in
ar
y
J8
Data outputs
J7
Data outputs
Output data valid
Figure 6. Boundary scan (JTAG) timing
TCLK
J9
TDI/TMS
J10
Input data valid
J11
TDO
Output data valid
J12
TDO
J11
TDO
Output data valid
Figure 7. Test Access Port timing
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
22
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
TCLK
J14
J13
TRST
Figure 8. TRST timing
Pr
el
im
in
ar
y
6.2 System modules
There are no specifications necessary for the device's system modules.
6.3 Clock modules
6.3.1 MCG Specifications
Table 12. MCG specifications
Symbol
Description
Min.
Typ.
Max.
Unit
fints_ft
Internal reference frequency (slow clock) — facto‐
ry trimmed at nominal VDD and 25°C
—
32.768
—
kHz
fints_t
Internal reference frequency (slow clock) — user
trimmed
31.25
—
39.0625
kHz
tirefsts
Internal reference (slow clock) startup time
—
TBD
4
µs
Resolution of trimmed DCO output frequency at
fixed voltage and temperature — using SCTRIM
and SCFTRIM
—
± 0.1
± 0.3
%fdco
Δfdco_res_t Resolution of trimmed DCO output frequency at
fixed voltage and temperature — using SCTRIM
only
—
± 0.2
± 0.5
%fdco
Total deviation of trimmed DCO output frequency
over voltage and temperature
—
+ 0.5
± 3.5
%fdco
Δfdco_t
Total deviation of trimmed DCO output frequency
over fixed voltage and temperature range of 0–
70°C
—
± 0.5
± TBD
%fdco
fintf_ft
Internal reference frequency (fast clock) — factory
trimmed at nominal VDD and 25°C
3.875
4
4.125
MHz
fintf_t
Internal reference frequency (fast clock) — user
trimmed
3
—
5
MHz
Δfdco_res_t
Δfdco_t
Notes
- 1.0
Table continues on the next page...
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
23
Peripheral operating requirements and behaviors
Table 12. MCG specifications (continued)
Symbol
tirefstf
Description
Internal reference startup time (fast clock)
Min.
Typ.
Max.
Unit
—
TBD
TBD
µs
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
20
20.97
25
MHz
Notes
FLL
DCO output fre‐
quency range —
user trimmed
and DMX32=0
Low range (DRS=00)
1, 2
640 × fints_t
Pr
el
im
in
ar
y
fdco_t
Mid range (DRS=01)
40
41.94
50
MHz
60
62.91
75
MHz
80
83.89
100
MHz
—
23.99
—
MHz
—
47.97
—
MHz
—
71.99
—
MHz
—
95.98
—
MHz
1280 × fints_t
Mid-high range (DRS=10
192)0 × fints_t
High range (DRS=11)
2560 × fints_t
fdco_t_DMX3 DCO output fre‐
quency range —
2
reference =
32,768Hz and
DMX32=1
Low range (DRS=00)
3
732 × fints_t
Mid range (DRS=01)
1464 × fints_t
Mid-high range (DRS=10)
2197 × fints_t
High range (DRS=11)
2929 × fints_t
Jcyc_fll
FLL period jitter
—
TBD
TBD
ps
Jacc_fll
FLL accumulated jitter of DCO output over a 1µs
time window
—
TBD
TBD
ps
FLL target frequency acquisition time
—
—
1
ms
VCO operating frequency
48.0
—
100
MHz
fpll_ref
PLL reference frequency range
2.0
—
4.0
MHz
Jcyc_pll
PLL period jitter
—
400
—
ps
6, 7
Jacc_pll
PLL accumulated jitter over 1µs window
—
TBD
—
ps
6,7
tfll_acquire
4
5
PLL
fvco
Dlock
Lock entry frequency tolerance
± 1.49
—
± 2.98
%
Dunl
Lock exit frequency tolerance
± 4.47
—
± 5.97
%
tpll_lock
Lock detector detection time
—
—
0.15 +
1075(1/
fpll_ref)
ms
8
1. The resulting system clock frequencies should not exceed their maximum specified values.
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
24
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
2.
3.
4.
5.
This specification includes the 2% precision of the internal reference frequency (slow clock).
The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
This specification was obtained at TBD frequency.
This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
6. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
7. This specification was obtained at internal frequency of TBD.
8. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
Pr
el
im
in
ar
y
6.3.2 Oscillator Electrical Characteristics
This section provides the electrical characteristics of the module.
6.3.2.1
Oscillator DC Electrical Specifications
Table 13. Oscillator DC electrical specifications, (VSSOSC= 0 VDC) (TA = TL to TH)
Symbol
VDD33OSC
IDDOSC
IDDOSC
Description
Min.
Typ.
Max.
Unit
3.3 V supply voltage
1.71
—
3.6
V
Supply current — low-power mode
• 32 kHz
—
500
—
nA
• 1 MHz
—
100
—
μA
• 4 MHz
—
200
—
μA
• 8 MHz
—
300
—
μA
• 16 MHz
—
700
—
μA
• 24 MHz
—
1.2
—
mA
• 32 MHz
—
1.5
—
mA
Supply current — high gain mode
• 32 kHz
—
25
—
μA
• 1 MHz
—
200
—
μA
• 4 MHz
—
400
—
μA
• 8 MHz
—
800
—
μA
• 16 MHz
—
1.5
—
mA
• 24 MHz
—
3
—
mA
• 32 MHz
—
4
—
mA
Notes
1
1
Cx
EXTAL load capacitance
—
—
—
2, 3
Cy
XTAL load capacitance
—
—
—
2,3
Table continues on the next page...
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
25
Peripheral operating requirements and behaviors
Table 13. Oscillator DC electrical specifications, (VSSOSC= 0 VDC) (TA = TL to TH)
(continued)
RF
RS
Description
Min.
Typ.
Max.
Unit
Notes
Feedback resistor — low-frequency, low-power
mode
—
—
—
MΩ
2,3
Feedback resistor — low-frequency, high-gain
mode
—
10
—
MΩ
Feedback resistor — high-frequency, low-power
mode (1 – 8 MHz, 8 – 32 MHz)
—
—
—
MΩ
Feedback resistor — high-frequency, high-gain
mode (1 – 8 MHz, 8 – 32 MHz)
—
1
—
MΩ
Pr
el
im
in
ar
y
Symbol
Series resistor — low-frequency, low-power
mode
—
—
—
kΩ
Series resistor — low-frequency, high-gain mode
—
200
—
kΩ
Series resistor — high-frequency, low-power
mode
—
—
—
kΩ
—
6.6
—
kΩ
—
3.3
—
kΩ
—
0
—
kΩ
—
0
—
kΩ
—
0
—
kΩ
—
0
—
kΩ
—
0
—
kΩ
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
0.75 ×
VDD33OSC
VDD33OSC
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
0.75 ×
VDD33OSC
VDD33OSC
—
V
Series resistor — high-frequency, high-gain
mode
• 1 MHz resonator
• 2 MHz resonator
• 4 MHz resonator
• 8 MHz resonator
• 16 MHz resonator
• 20 MHz resonator
• 32 MHz resonator
Vpp
1. VDD33OSC=3.3 V, Temperature =27 °C, Cx/Cy=20 pF
2. See crystal or resonator manufacturer's recommendation
3. RF and Cx,Cy are integrated in low-frequency, low-power mode and must not be attached externally
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
26
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.3.2.2
Oscillator frequency specifications
Table 14. Oscillator frequency specifications, (VDD33OSC = VDD33OSC (min) to
VDD33OSC (max), TA = TL to TH)
Symbol
Description
Min.
Typ.
Max.
Unit
Oscillator crystal or resonator frequency — low
frequency mode
32
—
40
kHz
fosc_hi_1
Oscillator crystal or resonator frequency — high
frequency mode (low range)
1
—
8
MHz
fosc_hi_2
Oscillator crystal or resonator frequency — high
frequency mode (high range)
8
—
32
MHz
tdc_extal
Input clock duty cycle (external clock mode)
40
50
60
%
Crystal start-up time — 32 kHz low-frequency,
low-power mode
—
TBD
—
ms
Crystal start-up time — 32 kHz low-frequency,
high-gain mode
—
800
—
ms
Crystal start-up time — 8 MHz high-frequency,
low-power mode
—
4
—
ms
Crystal start-up time — 8 MHz high-frequency,
high-gain mode
—
3
—
ms
tcst
Pr
el
im
in
ar
y
fosc_lo
Notes
1, 2, 3
1. This parameter is characterized before qualification rather than 100% tested.
2. Proper PC board layout procedures must be followed to achieve specifications.
3. Crystal start up time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
6.3.3 32kHz Oscillator Electrical Characteristics
This section describes the module electrical characteristics.
6.3.3.1
32kHz Oscillator DC Electrical Specifications
Table 15. 32kHz Oscillator Module DC Electrical Specifications (VSSOSC= 0 VDC)
(TA = TL to TH)
Symbol
Description
Min.
Typ.
Max.
Unit
Supply voltage
1.71
—
3.6
V
Internal feedback resistor
—
100
—
MΩ
Cpara
Parasitical capacitance of EXTAL32 and XTAL32
—
2.5
—
pF
Cload
Internal load capacitance (programmable)
—
15
—
pF
Peak-to-peak amplitude of oscillation
—
0.6
—
V
VBAT
RF
Vpp
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
27
Peripheral operating requirements and behaviors
6.3.3.2
32kHz Oscillator Frequency Specifications
Table 16. 32kHz oscillator frequency specifications (VDD33OSC = VDD33OSC (min)
to VDD33OSC (max), TA = TL to TH)
Symbol
fosc_lo
tstart
Description
Min.
Typ.
Max.
Unit
Oscillator crystal
—
32
—
kHz
Crystal start-up time
—
1000
—
ms
Notes
1, 2
Pr
el
im
in
ar
y
1. This parameter is characterized before qualification rather than 100% tested.
2. Proper PC board layout procedures must be followed to achieve specifications.
6.4 Memories and memory interfaces
6.4.1 Flash (FTFL) Electrical Characteristics
This section describes the electrical characteristics of the FTFL module.
6.4.1.1
Flash Timing Parameters — Program and Erase
The following characteristics represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 17. NVM program/erase timing characteristics
Symbol
Description
Min.
Typ.
Max.
Unit
thvpgm4
Notes
Longword Program high-voltage time
—
20
TBD
μs
thversscr
Sector Erase high-voltage time
—
20
100
ms
1
thversblk
Erase Block high-voltage time
—
160
800
ms
1
Notes
1. Maximum time based on expectations at cycling end-of-life.
6.4.1.2
Flash Timing Parameters — Commands
Table 18. Flash command timing characteristics
Symbol
Min.
Typ.
Max.
Unit
Read 1s Block execution time
—
—
1.4
ms
trd1sec2k
Read 1s Section execution time (2 KB flash sec‐
tor)
—
—
40
μs
tpgmchk
Program Check execution time
—
—
35
μs
trd1blk
Description
Table continues on the next page...
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
28
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 18. Flash command timing characteristics (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
1
Read Resource execution time
—
—
35
μs
tpgm4
Program Longword execution time
—
50
TBD
μs
tersblk
Erase Flash Block execution time
—
160
800
ms
2
tersscr
Erase Flash Sector execution time
—
20
100
ms
2
Program Section execution time (2 KB flash sec‐
tor)
—
TBD
TBD
ms
trd1all
Read 1s All Blocks execution time
—
—
2.8
ms
trdonce
Read Once execution time
—
—
35
μs
Program Once execution time
—
50
TBD
μs
tersall
Erase All Blocks execution time
—
320
1600
ms
2
tvfykey
Verify Backdoor Access Key execution time
—
—
35
μs
1
tpgmsec2k
tpgmonce
Pr
el
im
in
ar
y
trdrsrc
1
1. Assumes 25MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
6.4.1.3
Flash (FTFL) Current and Power Parameters
Table 19. Flash (FTFL) current and power parameters
Symbol
Description
IDD_PGM
Worst case programming current in program flash
6.4.1.4
Typ.
Unit
10
mA
Reliability Characteristics
Table 20. NVM reliability characteristics
Symbol
Description
Min.
Typ.1
Max.
Unit
Notes
Program Flash
tnvmretp10k
Data retention after up to 10 K cycles
5
TBD
—
years
2
tnvmretp1k
Data retention after up to 1 K cycles
10
TBD
—
years
2
tnvmretp100
Data retention after up to 100 cycles
15
TBD
—
years
2
10 K
TBD
—
cycles
3
nnvmcycp
Cycling endurance
1. Typical data retention values are based on intrinsic capability of the technology measured at high temperature derated to
25°C. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin
EB618.
2. Data retention is based on Tjavg = 55°C (temperature profile over the lifetime of the application).
3. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
29
Peripheral operating requirements and behaviors
6.4.2 EzPort Switching Specifications
Table 21. EzPort switching specifications
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
EP1
EZP_CK frequency of operation (all commands except
READ)
—
fSYS/2
MHz
EP1a
EZP_CK frequency of operation (READ command)
—
fSYS/8
MHz
EP2
EZP_CS negation to next EZP_CS assertion
2 x tEZP_CK
—
ns
EP3
EZP_CS input valid to EZP_CK high (setup)
5
—
ns
EP4
EZP_CK high to EZP_CS input invalid (hold)
5
—
ns
EP5
EZP_D input valid to EZP_CK high (setup)
2
—
ns
EP6
EZP_CK high to EZP_D input invalid (hold)
5
—
ns
EP7
EZP_CK low to EZP_Q output valid (setup)
—
12
ns
EP8
EZP_CK low to EZP_Q output invalid (hold)
0
—
ns
EP9
EZP_CS negation to EZP_Q tri-state
—
12
ns
EZP_CK
Pr
el
im
in
ar
y
Num
EP3
EZP_CS
EP9
EP7
EZP_Q (output)
EP5
EZP_D (input)
EP2
EP4
EP8
EP6
Figure 9. EzPort Timing Diagram
6.4.3 Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
30
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be
derived from these values.
Table 22. Flexbus switching specifications
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Frequency of operation
—
50
Mhz
FB1
Clock period
20
—
ns
FB2
Address, data, and control output valid
TBD
11.5
ns
1
FB3
Address, data, and control output hold
0
—
ns
1
FB4
Data and FB_TA input setup
8.5
—
ns
2
FB5
Data and FB_TA input hold
0.5
—
ns
2
Pr
el
im
in
ar
y
Num
Notes
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
FB1
FB_CLK
FB5
FB_A[Y]
FB3
Address
FB4
FB2
FB_D[X]
Address
Data
FB_RW
FB_TS
AA=1
FB_CSn
AA=0
FB_OEn
FB_BE/BWEn
FB4
FB5
AA=1
FB_TA
AA=0
FB_TSIZ[1:0]
TSIZ
Figure 10. FlexBus read timing diagram
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
31
Peripheral operating requirements and behaviors
FB1
FB_CLK
FB3
FB_A[Y]
Address
FB2
FB_D[X]
Address
Data
Pr
el
im
in
ar
y
FB_RW
FB_TS
AA=1
FB_CSn
AA=0
FB_OEn
FB_BE/BWEn
FB4
FB5
AA=1
FB_TA
FB_TSIZ[1:0]
AA=0
TSIZ
Figure 11. FlexBus write timing diagram
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
6.6 Analog
6.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 23 and Table 24 are achievable on the
differential pins (ADCx_DP0, ADCx_DM0, ADC, ADCx_DP1, ADCx_DM1,
ADCx_DP3, and ADCx_DP3). The ADCx_DP2 and ADCx_DM2 ADC inputs are used
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
32
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
as the PGA inputs and are not direct device pins. Accuracy specifications for these pins
are defined in Table 25 and Table 26. All other ADC channels meet the 13-bit
differential/12-bit single-ended accuracy specifications.
6.6.1.1
16-bit ADC operating conditions
Table 23. 16-bit ADC operating conditions
Conditions
Min.
Typ.1
Max.
Unit
VDDA
Supply voltage
Absolute
1.71
—
3.6
V
ΔVDDA
Supply voltage
Delta to VDD (VDDVDDA)
-100
0
+100
mV
ΔVSSA
Ground voltage
Delta to VSS (VSSVSSA)
-100
0
+100
mV
VREFH
ADC reference
voltage high
1.13
VDDA
VDDA
V
VREFL
Reference volt‐
age low
VSSA
VSSA
VSSA
V
VADIN
Input voltage
VREFL
—
VREFH
V
CADIN
Input capaci‐
tance
• 16 bit modes
—
8
10
pF
• 8/10/12 bit
modes
—
4
5
—
2
5
RADIN
Pr
el
im
in
ar
y
Description
Symbol
Input resistance
Notes
2
2
kΩ
Table continues on the next page...
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
33
Peripheral operating requirements and behaviors
Table 23. 16-bit ADC operating conditions (continued)
Symbol
RAS
Description
Conditions
Analog source
resistance
16 bit modes
Min.
Typ.1
Max.
Unit
Notes
External to MCU
• fADCK > 8MHz
—
—
0.5
kΩ
• fADCK = 4–8MHz
—
—
1
kΩ
• fADCK < 4MHz
—
—
2
kΩ
• fADCK > 16MHz
—
—
0.5
kΩ
• fADCK > 8MHz
—
—
1
kΩ
Assumes
ADLSMP=0
Pr
el
im
in
ar
y
13/12 bit modes
• fADCK = 4–8MHz
—
—
2
kΩ
• fADCK < 4MHz
—
—
5
kΩ
• fADCK > 8MHz
—
—
2
kΩ
• fADCK = 4–8MHz
—
—
5
kΩ
• fADCK < 4MHz
—
—
10
kΩ
—
—
5
kΩ
—
—
10
kΩ
• 16 bit modes
1.0
—
TBD
MHz
• ≤13 bit modes
1.0
—
TBD
MHz
1.0
—
8.0
MHz
1.0
—
12.0
MHz
• 16 bit modes
1.0
—
5.0
MHz
• ≤13 bit modes
1.0
—
8.0
MHz
• 16 bit modes
1.0
—
2.5
MHz
• ≤13 bit modes
1.0
—
5.0
MHz
11/10 bit modes
9/8 bit modes
• fADCK > 8MHz
• fADCK < 8MHz
fADCK
ADC conversion
clock frequency
ADLPC=0, ADHSC=1
ADLPC=0, ADHSC=0
• 16 bit modes
• ≤13 bit modes
ADLPC=1, ADHSC=1
ADLPC=1, ADHSC=0
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. DC potential difference.
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
34
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
Z ADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
Z AS
R AS
ADC SAR
ENGINE
R ADIN
V ADIN
C AS
V AS
Pr
el
im
in
ar
y
R ADIN
INPUT PIN
R ADIN
INPUT PIN
R ADIN
INPUT PIN
C ADIN
Figure 12. ADC input impedance equivalency diagram
6.6.1.2
16-bit ADC electrical characteristics
Table 24. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol
IDDA
fADACK
Conditions1
Min.
Typ.2
Max.
Unit
Notes
• ADLPC=1, ADHSC=0
—
215
—
μA
• ADLPC=1, ADHSC=1
—
340
—
μA
ADLSMP=
0
• ADLPC=0, ADHSC=0
—
470
—
μA
• ADLPC=0, ADHSC=1
—
610
—
μA
Supply current
• Stop, reset, module off
—
0.01
0.8
μA
ADC asynchro‐
nous clock
source
• ADLPC=1, ADHSC=0
TBD
2.4
TBD
MHz
• ADLPC=1, ADHSC=1
TBD
4.0
TBD
MHz
• ADLPC=0, ADHSC=0
TBD
5.2
TBD
MHz
• ADLPC=0, ADHSC=1
TBD
6.2
TBD
MHz
Description
Supply current
Sample Time
ADCO=1
tADACK = 1/
fADACK
See Reference Manual chapter for sample times
Conversion Time See Reference Manual chapter for conversion times
Table continues on the next page...
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
35
Peripheral operating requirements and behaviors
Table 24. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
TUE
DNL
INL
EZS
Conditions1
Description
Total unadjusted
error
Min.
Typ.2
Max.
Unit
Notes
• 16 bit differential
—
±14.0
±TBD
LSB3
• 16 bit single-ended
—
±13.0
±TBD
• 13 bit differential
—
±1.5
±TBD
• 12 bit single-ended
—
±TBD
±TBD
Max hard‐
ware aver‐
aging
(AVGE =
%1, AVGS
= %11)
• 11 bit differential
—
±0.8
±TBD
• 10 bit single-ended
—
±TBD
±TBD
• 9 bit differential
—
±0.5
±1.0
• 8 bit single-ended
—
±0.5
±1.0
Pr
el
im
in
ar
y
Symbol
Differential nonlinearity
Integral non-line‐
arity
Zero-scale error
• 16 bit differential
—
±2.5
±TBD
• 16 bit single-ended
—
±2.5
±TBD
• 13 bit differential
—
±0.7
±TBD
• 12 bit single-ended
—
±0.7
±TBD
• 11 bit differential
—
±0.5
±TBD
• 10 bit single-ended
—
±TBD
±TBD
• 9 bit differential
—
±0.2
±0.5
• 8 bit single-ended
—
±0.2
±0.5
• 16 bit differential
—
-6 to +2.5
—
• 16 bit single-ended
—
-2 to +12
—
• 13 bit differential
—
±1.0
±TBD
• 12 bit single-ended
—
±1.0
±TBD
• 11 bit differential
—
±0.5
±TBD
• 10 bit single-ended
—
±0.5
±TBD
• 9 bit differential
—
±0.3
±0.5
• 8 bit single-ended
—
±0.3
±0.5
• 16 bit differential
—
±4.0
—
• 16 bit single-ended
—
±4.0
—
• 13 bit differential
—
±0.7
±TBD
• 12 bit single-ended
—
±0.7
±TBD
• 11 bit differential
—
±0.4
±TBD
• 10 bit single-ended
—
±0.4
±TBD
• 9 bit differential
—
±0.2
±0.5
• 8 bit single-ended
—
±0.2
±0.5
LSB3
Max hard‐
ware aver‐
aging
(AVGE =
%1, AVGS
= %11)
LSB3
Max aver‐
aging
LSB3
VADIN =
VSSA
Table continues on the next page...
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
36
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 24. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
EFS
EQ
ENOB
Conditions1
Description
Full-scale error
Min.
Typ.2
Max.
Unit
Notes
• 16 bit differential
—
0 to +10
—
LSB3
• 16 bit single-ended
—
0 to +14
—
VADIN =
VDDA
• 13 bit differential
—
±1.0
±TBD
• 12 bit single-ended
—
±TBD
±TBD
• 11 bit differential
—
±0.4
±TBD
• 10 bit single-ended
—
±0.4
±TBD
• 9 bit differential
—
±0.2
±0.5
• 8 bit single-ended
—
±0.2
±0.5
Pr
el
im
in
ar
y
Symbol
Quantization er‐
ror
• 16 bit modes
—
-1 to 0
—
• ≤13 bit modes
—
—
±0.5
Effective number 16 bit differential mode
of bits
• Avg=32
LSB3
TBD
13.6
TBD
bits
• Avg=16
TBD
TBD
TBD
bits
• Avg=8
TBD
14.1
TBD
bits
• Avg=4
TBD
TBD
TBD
bits
• Avg=1
TBD
13.2
TBD
bits
TBD
TBD
TBD
bits
TBD
TBD
TBD
bits
TBD
TBD
TBD
bits
TBD
TBD
TBD
bits
TBD
TBD
TBD
bits
4
16 bit single-ended mode
• Avg=32
• Avg=16
• Avg=8
• Avg=4
• Avg=1
SINAD
THD
Signal-to-noise
plus distortion
See ENOB
Total harmonic
distortion
16 bit differential mode
6.02 × ENOB + 1.76
• Avg=32
dB
—
-94
TBD
dB
—
TBD
TBD
dB
4
16 bit single-ended mode
• Avg=32
SFDR
Spurious free dy‐ 16 bit differential mode
namic range
• Avg=32
4
TBD
95
—
dB
TBD
TBD
—
dB
16 bit single-ended mode
• Avg=32
Table continues on the next page...
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
37
Peripheral operating requirements and behaviors
Table 24. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol
EIL
Conditions1
Description
Typ.2
Min.
Input leakage er‐
ror
Max.
IIn × RAS
Unit
Notes
mV
IIn = leak‐
age cur‐
rent
(refer to
the MCU's
voltage
and cur‐
rent oper‐
ating rat‐
ings)
VTEMP25
• –40°C to 25°C
—
TBD
—
mV/°C
• 25°C to 105°C
—
TBD
—
mV/°C
—
TBD
—
mV
Pr
el
im
in
ar
y
Temp sensor
slope
Temp sensor
voltage
25°C
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. 1 LSB = (VREFH - VREFL)/2N
4. Input data is 1 kHz sine wave.
6.6.1.3
16-bit ADC with PGA operating conditions
Table 25. 16-bit ADC with PGA operating conditions
Description
Conditions
Min.
Typ.1
Max.
Unit
VDDA
Supply voltage
Absolute
1.71
—
3.6
V
VREFPGA
PGA ref voltage
Symbol
VADIN
Input voltage
RPGA
Input impedance
RPGAD
Differntial input
impedance
VREFOUT VREFOUT VREFOUT
V
VSSA
—
VDDA
V
Gain = 1, 2, 4, 8
TBD
64
TBD
kΩ
Gain = 16, 32
TBD
32
TBD
Gain = 64
TBD
16
TBD
Gain = 1, 2, 4, 8
TBD
128
TBD
Gain = 16, 32
TBD
64
TBD
Gain = 64
TBD
32
TBD
—
100
1.25
—
RAS
Analog source
resistance
Gain = 16, 32
TS
ADC sampling
time
Gain = 64
Notes
2, 3
kΩ
IN+ to IN-
—
Ω
4
—
µs
5
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 6 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. ADC must be configured to use the internal voltage reference (VREFOUT)
3. PGA reference connected to the VREFOUT pin. If the user wishes to drive VREFOUT with a voltage other than the output
of the VREF module, the VREF module must be disabled.
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
38
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
4. The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
5. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
time should be allowed for Fin=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at
8 MHz ADC clock. The ADLSTS bits can be adjusted for different ADC clock frequency
6.6.1.4
16-bit ADC with PGA characteristics
Table 26. 16-bit ADC with PGA characteristics
Symbol
Description
IDDA_PGA
Supply current
G
Leakage current
Gain2
Typ.1
Max.
Unit
TBD
590
TBD
μA
—
<1
TBD
μA
• PGAG=0
TBD
1
TBD
dB
• PGAG=1
TBD
2
TBD
dB
• PGAG=2
TBD
3.9
TBD
dB
• PGAG=3
TBD
TBD
TBD
dB
• PGAG=4
TBD
TBD
TBD
dB
• PGAG=5
TBD
29.9
TBD
dB
• PGAG=6
TBD
TBD
TBD
dB
—
—
±0.5
dB
—
—
4
kHz
—
—
40
kHz
TBD
TBD
—
dB
VDDA= 3V
±100mV,
fVDDA= 50Hz,
60Hz
• Gain=1
TBD
TBD
—
dB
• Gain=64
TBD
TBD
—
dB
VCM=
500mVpp,
fVCM= 50Hz,
100Hz
PGA disabled
Pr
el
im
in
ar
y
ILKG
Min.
Conditions
GA
Gain error
BW
Input signal band‐
width
PSRR
Power supply re‐
jection ration
CMRR
Common mode
rejection ratio
• 16-bit modes
• < 16-bit modes
Gain=1
Notes
RAS < 100Ω
RAS < 100Ω
VOFS
Input offset volt‐
age
—
0.2
TBD
mV
Gain=1, ADC
Averaging=32
TGSW
Gain switching
settling time
—
TBD
10
µs
3
dG/dT
Gain drift over
temperature
—
TBD
TBD
ppm/°C
0 to 50°C
—
TBD
TBD
ppm/°C
—
TBD
TBD
ppm/°C
0 to 50°C, ADC
Averaging=32
—
TBD
TBD
%/V
—
TBD
TBD
%/V
VDDA from 1.71
to 3.6V
dVOFS/dT
Offset drift over
temperature
dG/dVDDA
Gain drift over
supply voltage
• Gain=1
• Gain=64
Gain=1
• Gain=1
• Gain=64
Table continues on the next page...
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
39
Peripheral operating requirements and behaviors
Table 26. 16-bit ADC with PGA characteristics (continued)
Symbol
EIL
Description
Conditions
Input leakage er‐
ror
All modes
Min.
Typ.1
Max.
IIn × RAS
Unit
Notes
mV
IIn = leakage
current
(refer to the
MCU's voltage
and current op‐
erating ratings)
SNR
THD
SFDR
ENOB
SINAD
Maximum differ‐
ential input signal
swing
[(VREFPGA × 2.33) - 0.2] / (2 ×
Gain)
V
4
Average=32
Signal-to-noise
ratio
• Gain=1
• Gain=64
TBD
8.3
—
dB
TBD
57.7
—
dB
Total harmonic
distortion
• Gain=1
• Gain=64
TBD
87.3
—
dB
TBD
85.3
—
dB
Spurious free dy‐
namic range
• Gain=1
• Gain=64
TBD
92.42
—
dB
TBD
92.54
—
dB
Effective number
of bits
• Gain=1, Average=4
TBD
12.3
—
bits
• Gain=1, Average=8
TBD
12.7
—
bits
• Gain=64, Average=4
TBD
8.4
—
bits
• Gain=64, Average=8
TBD
8.7
—
bits
• Gain=1, Average=32
TBD
13.4
—
bits
• Gain=2, Average=32
TBD
13.1
—
bits
• Gain=4, Average=32
TBD
12.6
—
bits
• Gain=8, Average=32
TBD
11.8
—
bits
• Gain=16, Average=32
TBD
11.1
—
bits
• Gain=32, Average=32
TBD
10.2
—
bits
• Gain=64, Average=32
TBD
9.3
—
bits
Pr
el
im
in
ar
y
VPP,DIFF
Signal-to-noise
plus distortion ra‐
tio
See ENOB
6.02 × ENOB + 1.76
Average=32,
fin=100Hz
Average=32,
fin=100Hz
dB
1. Typical values assume VDDA =3.0V, Temp=25°C, fADCK=6MHz unless otherwise stated.
2. Gain = 2PGAGx
3. When the PGA gain is changed, it takes some time to settle the output for the ADC to work properly. During a gain
switching, a few ADC outputs should be discarded (minimum two data samples, may be more depending on ADC
sampling rate and time of the switching).
4. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the
PGA reference voltage and gain setting.
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
40
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.6.2 CMP and 6-bit DAC electrical specifications
Table 27. Comparator and 6-bit DAC electrical specifications
Symbol
VDD
Description
Min.
Typ.
Max.
Unit
Supply voltage
1.71
—
3.6
V
IDDHS
Supply current, High-speed mode (EN=1, PMODE=1,
VDDA >= VLVI_trip)
—
—
200
μA
IDDLS
Supply current, low-speed mode (EN=1, PMODE=0)
—
—
20
μA
IDDOFF
Supply current, OFF Mode (EN=0,)
—
—
100
nA
VSS – 0.3
—
VDD
V
Analog input voltage
VAIO
Analog input offset voltage
VH
Pr
el
im
in
ar
y
VAIN
—
—
20
mV
• HYSTCTR = 00
—
5
—
mV
• HYSTCTR = 01
—
10
—
mV
• HYSTCTR = 10
—
20
—
mV
• HYSTCTR = 11
—
30
—
mV
Analog comparator hysteresis
VCMPOh
Output high
VDD – 0.5
—
—
V
VCMPOl
Output low
—
—
0.5
V
tDHS
Propagation delay, high-speed mode (EN=1,
PMODE=1)
20
50
120
ns
tDLS
Propagation delay, low-speed mode (EN=1,
PMODE=1)
120
250
420
ns
Analog comparator initialization delay
—
—
TBD
ns
6-bit DAC current adder (enabled)
—
—
8
μA
IDAC6b
INL
6-bit DAC integral non-Llnearity
–0.5
—
0.5
LSB1
DNL
6-bit DAC differential non-linearity
–0.3
—
0.3
LSB
Notes
1. 1 LSB = Vreference/64
6.6.3 12-bit DAC electrical characteristics
6.6.3.1
Symbol
12-bit DAC operating requirements
Table 28. 12-bit DAC operating requirements
Desciption
Min.
Max.
Unit
VDDA
Supply voltage
1.71
3.6
V
VDACR
Reference voltage
1.15
3.6
V
Temperature
−40
105
°C
TA
1
Table continues on the next page...
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
41
Peripheral operating requirements and behaviors
Table 28. 12-bit DAC operating requirements (continued)
Symbol
Desciption
Min.
Max.
Unit
Notes
2
CL
Output load capacitance
—
100
pF
IL
Output load current
—
1
mA
1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREFO)
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC
6.6.3.2
Table 29. 12-bit DAC operating behaviors
Min.
Typ.
Max.
Unit
12
—
12
b
IDDA_DACLP Supply current — low-power mode
—
—
150
μA
IDDA_DACH Supply current — high-speed mode
—
—
700
μA
n
P
Description
Pr
el
im
in
ar
y
Symbol
12-bit DAC operating behaviors
Resolution
Notes
tDACLP
Full-scale settling time (0x080 to 0xF7F) — lowpower mode
—
100
200
μs
1
tDACHP
Full-scale settling time (0x080 to 0xF7F) — highpower mode
—
15
30
μs
1
tCCDACLP
Code-to-code settling time (0xBF8 to 0xC08) —
low-power mode
—
—
5
μs
1
tCCDACHP
Code-to-code settling time (0xBF8 to 0xC08) —
high-speed mode
1
TBD
—
μs
1
Vdacoutl
DAC output voltage range low — high-speed
mode, no load, DAC set to 0x000
0
100
—
mV
Vdacouth
DAC output voltage range high — high-speed
mode, no load, DAC set to 0xFFF
VDACR
−100
—
VDACR
mV
INL
Integral non-linearity error — high speed mode
±3
—
±8
LSB
2
DNL
Differential non-linearity error — VDACR > 2 V
±0.5
—
±1
LSB
3
DNL
Differential non-linearity error — VDACR = VRE‐
FO (1.15 V)
±0.5
—
±1
LSB
4
VOFFSET
Offset error
±0.4
—
±0.8
%FSR
5
EG
Gain error
±0.1
—
±0.6
%FSR
5
90
dB
PSRR
Power supply rejection ratio, VDDA > = 2.4 V
60
TCO
Temperature coefficient offset voltage
—
TBD
—
μV/C
TGE
Temperature coefficient gain error
—
TBD
—
ppm of
FSR/C
AC
Offset aging coefficient
—
—
TBD
μV/yr
Output resistance load = 3 kΩ
—
—
250
Ω
Rop
Table continues on the next page...
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
42
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 29. 12-bit DAC operating behaviors (continued)
Symbol
SR
Min.
Typ.
Max.
Slew rate -80h→ F7Fh→ 80h
1.2
1.7
—
• Low power (SPLP)
0.05
0.12
—
—
—
-80
Channel to channel cross talk
BW
3dB bandwidth
Notes
V/μs
• High power (SPHP)
CT
Unit
dB
kHz
• High power (SPHP)
550
—
—
• Low power (SPLP)
40
—
—
Pr
el
im
in
ar
y
1.
2.
3.
4.
5.
Description
Settling within ±1 LSB
The INL is measured for 0+100mV to VDACR−100 mV
The DNL is measured for 0+100 mV to VDACR−100 mV
The DNL is measured for 0+100mV to VDACR−100 mV with VDDA > 2.4V
Calculated by a best fit curve from VSS+100 mV to VREF−100 mV
Figure 13. Typical INL error vs. digital code
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
43
Pr
el
im
in
ar
y
Peripheral operating requirements and behaviors
Figure 14. Offset at half scale vs. temperature
6.6.4 Voltage Reference Electrical Specifications
Table 30. VREF full-range operating requirements
Symbol
Description
Min.
Max.
Unit
Supply voltage
1.71
3.6
V
TA
Temperature
−40
105
°C
CL
Output load capacitance
—
100
nF
VDDA
Notes
Table 31. VREF full-range operating behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
Vout
Voltage reference output with factory trim
TBD
1.2
TBD
V
Vout
Voltage reference output without factory trim
1.15
—
1.24
V
Vdrift
Temperature drift (Vmax -Vmin across the full
temperature range)
—
—
7
mV
Notes
See Fig‐
ure 15
Table continues on the next page...
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
44
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 31. VREF full-range operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Tc
Temperature coefficient
—
—
TBD
ppm/°C
Ac
Aging coefficient
—
—
TBD
ppm/year
Ioff
Powered down current (off mode, VREFEN = 0,
VRSTEN = 0)
—
—
0.10
µA
Ibg
Bandgap only (MODE_LV = 00) current
—
TBD
75
µA
Itr
Tight-regulation buffer (MODE_LV =10) current
—
—
1.1
mA
Load regulation (MODE_LV = 10) current
—
—
100
µV/mA
100
—
TBD
µs
—
—
TBD
mV
–60
—
TBD
dB
Buffer startup time
DC
Line regulation (power supply rejection)
Pr
el
im
in
ar
y
Tstup
Notes
Table 32. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
TA
Temperature
0
50
°C
Notes
Table 33. VREF limited-range operating behaviors
Symbol
Vout
Description
Min.
Max.
Unit
Voltage reference output with factory trim
TBD
TBD
µA
TBD
Notes
Figure 15. Typical output vs.temperature
TBD
Figure 16. Typical output vs. VDD
6.7 Timers
See General Switching Specifications.
6.8 Communication interfaces
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
45
Peripheral operating requirements and behaviors
6.8.1 DSPI Switching Specifications for Low-speed Operation
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 34. Master Mode DSPI Timing (Low-speed mode)
Description
Min.
Max.
Unit
Notes
1.71
3.6
V
1
—
12.5
MHz
4 x tBCLK
—
ns
Pr
el
im
in
ar
y
Num
Operating voltage
Frequency of operation
DS1
DSPI_SCK output cycle time
DS2
DSPI_SCK output high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS3
DSPI_PCSn to DSPI_SCK output valid
(tSCK/2) - 4
—
ns
DS4
DSPI_SCK to DSPI_PCSn output hold
(tSCK/2) - 4
—
ns
DS5
DSPI_SCK to DSPI_SOUT valid
—
10
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
-2
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
15
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
DSPI_PCSn
DS3
DSPI_SCK
(CPOL=0)
DS7
DSPI_SIN
DS1
DS2
DS8
Data
First data
Last data
DS5
DSPI_SOUT
DS4
First data
DS6
Data
Last data
Figure 17. DSPI Classic SPI Timing — Master Mode
Table 35. Slave Mode DSPI Timing (Low-speed Mode)
Num
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
1.71
3.6
V
—
6.25
MHz
Table continues on the next page...
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
46
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 35. Slave Mode DSPI Timing (Low-speed Mode) (continued)
Num
Description
Min.
Max.
Unit
8 x tBCLK
—
ns
(tSCK/2) - 4
(tSCK/2) + 4
ns
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
DS11
DSPI_SCK to DSPI_SOUT valid
—
20
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
5
—
ns
DS14
DSPI_SCK to DSIP_SIN input hold
15
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
15
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
15
ns
DSPI_SS
Pr
el
im
in
ar
y
DS9
DS10
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DS15
DS12
First data
DS13
DSPI_SIN
DS9
DS16
DS11
Data
Last data
DS14
First data
Data
Last data
Figure 18. DSPI Classic SPI Timing — Slave Mode
6.8.2 DSPI Switching Specifications (High-speed mode)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 36. Master Mode DSPI Timing (High-speed mode)
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Frequency of operation
—
25
MHz
2 x tBCLK
—
ns
(tSCK/2) − 2
(tSCK/2) + 2
ns
DS1
DSPI_SCK output cycle time
DS2
DSPI_SCK output high/low time
Table continues on the next page...
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
47
Peripheral operating requirements and behaviors
Table 36. Master Mode DSPI Timing (High-speed mode) (continued)
Num
Description
Min.
Max.
Unit
DSPI_PCSn to DSPI_SCK output valid
(tSCK/2) − 2
—
ns
DS4
DSPI_SCK to DSPI_PCSn output hold
(tSCK/2) − 2
—
ns
DS5
DSPI_SCK to DSPI_SOUT valid
—
8.5
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
−2
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
TBD
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
DSPI_PCSn
Pr
el
im
in
ar
y
DS3
DS3
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
DS1
DS2
DS4
DS8
DS7
Data
First data
Last data
DS5
DS6
First data
Data
Last data
Figure 19. DSPI Classic SPI Timing — Master Mode
Table 37. Slave Mode DSPI Timing (High-speed mode)
Num
Description
Operating voltage
Min.
Max.
Unit
2.7
3.6
V
12.5
MHz
4 x tBCLK
—
ns
(tSCK/2) − 2
(tSCK/2 + 2
ns
Frequency of operation
DS9
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
DS11
DSPI_SCK to DSPI_SOUT valid
—
TBD
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2
—
ns
DS14
DSPI_SCK to DSIP_SIN input hold
7
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
14
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
14
ns
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
48
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
DSPI_SS
DS10
DS9
DSPI_SCK
DS15
(CPOL=0)
DSPI_SOUT
DS12
First data
DS13
DSPI_SIN
DS16
DS11
Data
Last data
DS14
Data
Last data
Pr
el
im
in
ar
y
First data
Figure 20. DSPI Classic SPI Timing — Slave Mode
6.8.3 SDHC Specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
Table 38. SDHC switching specifications
Num
Symbol
Description
Min.
Max.
Unit
Clock frequency (low speed)
0
400
kHz
Clock frequency (SD\SDIO full speed)
0
25
MHz
Clock frequency (MMC full speed)
0
20
MHz
Clock frequency (identification mode)
0
400
kHz
Clock low time
7
—
ns
Clock high time
7
—
ns
Card input clock
SD1
fpp
fpp
fpp
fOD
SD2
tWL
SD3
tWH
SD4
tTLH
Clock rise time
—
3
ns
SD5
tTHL
Clock fall time
—
3
ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6
tOD
SDHC output delay (output valid)
-5
6.5
ns
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD7
tTHL
SDHC input setup time
5
—
ns
SD8
tTHL
SDHC input hold time
0
—
ns
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
49
Peripheral operating requirements and behaviors
SD3
SD2
SD1
SDHC_CLK
SD6
Output SDHC_CMD
Output SDHC_DAT[3:0]
SD7
SD8
Pr
el
im
in
ar
y
Input SDHC_CMD
Input SDHC_DAT[3:0]
Figure 21. SDHC timing
6.8.4 I2S Switching Specifications
This section provides the AC timings for the I2S in master (clocks driven) and slave
modes (clocks input). All timings are given for non-inverted serial clock polarity
(TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0,
RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all
the timings remain valid by inverting the clock signal (I2S_BCLK) and/or the frame sync
(I2S_FS) shown in the figures below.
Table 39. I2S master mode timing
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
S1
I2S_MCLK cycle time
S2
I2S_MCLK pulse width high/low
S3
I2S_BCLK cycle time
S4
I2S_BCLK pulse width high/low
S5
I2S_BCLK to I2S_FS output valid
S6
I2S_BCLK to I2S_FS output invalid
S7
2 x tSYS
ns
45%
55%
MCLK period
5 x tSYS
—
ns
45%
55%
BCLK period
—
15
ns
-2.5
—
ns
I2S_BCLK to I2S_TXD valid
—
15
ns
S8
I2S_BCLK to I2S_TXD invalid
-3
—
ns
S9
I2S_RXD/I2S_FS input setup before I2S_BCLK
20
—
ns
S10
I2S_RXD/I2S_FS input hold after I2S_BCLK
0
—
ns
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
50
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
S1
S2
S2
I2S_MCLK (output)
S3
I2S_BCLK (output)
S4
S4
S5
S6
I2S_FS (output)
S10
S9
I2S_FS (input)
S7
S8
S7
S8
I2S_TXD
I2S_RXD
S10
Pr
el
im
in
ar
y
S9
Figure 22. I2S timing — master mode
Table 40. I2S alave mode timing
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
8 x tSYS
—
ns
S11
I2S_BCLK cycle time (input)
S12
I2S_BCLK pulse width high/low (input)
45%
55%
MCLK period
S13
I2S_FS input setup before I2S_BCLK
10
—
ns
S14
I2S_FS input hold after I2S_BCLK
3
—
ns
S15
I2S_BCLK to I2S_TXD/I2S_FS output valid
—
20
ns
S16
I2S_BCLK to I2S_TXD/I2S_FS output invalid
0
—
ns
S17
I2S_RXD setup before I2S_BCLK
10
—
ns
S18
I2S_RXD hold after I2S_BCLK
2
—
ns
S11
S12
I2S_BCLK (input)
S12
S15
S16
I2S_FS (output)
S13
S14
I2S_FS (input)
S15
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 23. I2S timing — slave modes
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
51
Peripheral operating requirements and behaviors
6.9 Human-machine interfaces (HMI)
6.9.1 General Switching Specifications
These general purpose specifications apply to all signals configured for GPIO, SCI,
FlexCAN, CMT, and I2C signals.
Table 41. General switching specifications
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter disa‐
bled) — Synchronous path
1.5
—
Bus clock
cycles
1
GPIO pin interrupt pulse width (digital glitch filter disa‐
bled, analog filter enabled) — Asynchronous path
100
—
ns
2
GPIO pin interrupt pulse width (digital glitch filter disa‐
bled, analog filter disabled) — Asynchronous path
16
—
ns
2
External reset pulse width (digital glitch filter disabled)
TBD
—
Mode select (EZP_CS) hold time after reset deasser‐
tion
2
—
Pr
el
im
in
ar
y
Symbol
Bus clock
cycles
Port rise and fall time (high drive strength)
• Slew disabled
—
12
ns
• Slew enabled
—
36
ns
Port rise and fall time (low drive strength)
1.
2.
3.
4.
• Slew disabled
—
32
ns
• Slew enabled
—
36
ns
3
4
The greater synchronous and asynchronous timing must be met.
This is the shortest pulse that is guaranteed to be recognized.
75pF load
15pF load
6.9.2 TSI Electrical Specifications
Table 42. Touch Sensing Input module specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDDTSI
Operating voltage
1.71
—
3.6
V
Target electrode capacitance range
1
20
500
pF
Reference oscillator frequency
—
5.5
TBD
MHz
CELE
fREFmax
Notes
1
Table continues on the next page...
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
52
Preliminary
Freescale Semiconductor, Inc.
Dimensions
Table 42. Touch Sensing Input module specifications (continued)
Description
Min.
Typ.
Max.
Unit
fELEmax
Electrode oscillator frequency
—
0.5
TBD
MHz
Internal reference capacitor
TBD
1
TBD
pF
Oscillator delta voltage
TBD
600
TBD
mV
IREF
Reference oscillator current source base current
TBD
1
TBD
μA
2
IELE
Electrode oscillator current source base current
TBD
1
TBD
μA
3
Pres5
Electrode capacitance measurement precision
—
TBD
TBD
%
4
Pres20
Electrode capacitance measurement precision
—
TBD
TBD
%
5
Pres100
Electrode capacitance measurement precision
—
TBD
TBD
%
6
Max‐
Sens20
Max sensitivity @ 20pF electrode
0.15
0.326
600
fF
7
Maximum sensitivity
0.006
0.326
24
fF
8
Resolution
—
—
16
bits
Response time @ 20pF
—
30
—
μs
Current added in run mode
—
TBD
—
μA
Low power mode current adder
—
1
TBD
μA
CREF
VDELTA
MaxSens
Res
TCon20
ITSI_RUN
ITSI_LP
Pr
el
im
in
ar
y
Symbol
Notes
9
1. The TSI module is functional with capacitance values outside of this range. However, optimal performance is not
guaranteed.
2. The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current
3. The programmable current source value is generated by multiplying the SCANC[EXTCHRG] value and the base current
4. Measured with a 5pF electrode, reference oscillator frequency of 10MHz, PS = 128, NCSC = 8; Iext = 16
5. Measured with a 20pF electrode, reference oscillator frequency of 10MHz, PS = 128, NCSC = 2; Iext = 16
6. Measured with a 20pF electrode, reference oscillator frequency of 10MHz, PS = 16, NCSC = 3; Iext = 16
7. 6.2ms scan time
8. 1pF electrode capacitance with 4.96ms scan time
9. Time that takes to do one complete measurement of the electrode. Sensitivity resolution of 0.0133pF
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to www.freescale.com and perform a keyword search for
the drawing’s document number:
If you want the drawing for this package
Then use this document number
80-pin LQFP
98ASS23174W
81-pin MAPBGA
98ASH98051A
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
53
Pinout
8 Pinout
8.1 K10 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
Pr
el
im
in
ar
y
80
QFP
1
ADC1_SE4a
ADC1_SE4a
PTE0
SPI1_PCS1
UART1_TX
SDHC0_D1
I2C1_SDA
2
ADC1_SE5a
ADC1_SE5a
PTE1
SPI1_SOUT
UART1_RX
SDHC0_D0
I2C1_SCL
3
ADC1_SE6a
ADC1_SE6a
PTE2
SPI1_SCK
UART1_CTS_ SDHC0_DCLK
b
4
ADC1_SE7a
ADC1_SE7a
PTE3
SPI1_SIN
UART1_RTS_ SDHC0_CMD
b
5
DISABLED
PTE4
SPI1_PCS0
UART3_TX
SDHC0_D3
6
DISABLED
PTE5
SPI1_PCS2
UART3_RX
SDHC0_D2
7
VDD
VDD
8
VSS
VSS
9
ADC0_SE4a
ADC0_SE4a
PTE16
SPI0_PCS0
UART2_TX
FTM_CLKIN0
FTM0_FLT3
10
ADC0_SE5a
ADC0_SE5a
PTE17
SPI0_SCK
UART2_RX
FTM_CLKIN1
LPT00_ALT3
11
ADC0_SE6a
ADC0_SE6a
PTE18
SPI0_SOUT
UART2_CTS_ I2C0_SDA
b
12
ADC0_SE7a
ADC0_SE7a
PTE19
SPI0_SIN
UART2_RTS_ I2C0_SCL
b
13
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
14
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
15
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
16
PGA1_DM/
ADC1_DM0/
ADC0_DM3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
17
VDDA
VDDA
18
VREFH
VREFH
19
VREFL
VREFL
20
VSSA
VSSA
21
VREF_OUT
VREF_OUT
22
DAC0_OUT
DAC0_OUT
EzPort
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
54
Preliminary
Freescale Semiconductor, Inc.
Pinout
80
QFP
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
XTAL32
XTAL32
24
EXTAL32
EXTAL32
25
VBAT
VBAT
26
JTAG_TCLK/
SWD_CLK/
EZP_CLK
TSI0_CH1
PTA0
UART0_CTS_ FTM0_CH5
b
JTAG_TCLK/
SWD_CLK
EZP_CLK
27
JTAG_TDI/
EZP_DI
TSI0_CH2
PTA1
UART0_RX
FTM0_CH6
JTAG_TDI
EZP_DI
28
JTAG_TDO/
TSI0_CH3
TRACE_SWO/
EZP_DO
PTA2
UART0_TX
FTM0_CH7
JTAG_TDO/
EZP_DO
TRACE_SWO
29
JTAG_TMS/
SWD_DIO
TSI0_CH4
PTA3
UART0_RTS_ FTM0_CH0
b
30
NMI_b/
EZP_CS_b
TSI0_CH5
PTA4
FTM0_CH1
31
JTAG_TRST
PTA5
FTM0_CH2
32
CMP2_IN0
CMP2_IN0
PTA12
CAN0_TX
FTM1_CH0
I2S0_TXD
FTM1_QD_PH
A
33
CMP2_IN1
CMP2_IN1
PTA13
CAN0_RX
FTM1_CH1
I2S0_TX_FS
FTM1_QD_PH
B
34
DISABLED
PTA14
SPI0_PCS0
UART0_TX
I2S0_TX_BCL
K
35
DISABLED
PTA15
SPI0_SCK
UART0_RX
I2S0_RXD
36
DISABLED
PTA16
SPI0_SOUT
UART0_CTS_
b
I2S0_RX_FS
37
ADC1_SE17
ADC1_SE17
PTA17
SPI0_SIN
UART0_RTS_
b
I2S0_MCLK
38
VDD
VDD
39
VSS
VSS
40
EXTAL
EXTAL
PTA18
FTM0_FLT2
FTM_CLKIN0
41
XTAL
XTAL
PTA19
FTM1_FLT0
FTM_CLKIN1
42
RESET_b
RESET_b
43
ADC0_SE8/
ADC1_SE8/
TSI0_CH0
ADC0_SE8/
ADC1_SE8/
TSI0_CH0
PTB0
I2C0_SCL
FTM1_CH0
FTM1_QD_PH
A
44
ADC0_SE9/
ADC1_SE9/
TSI0_CH6
ADC0_SE9/
ADC1_SE9/
TSI0_CH6
PTB1
I2C0_SDA
FTM1_CH1
FTM1_QD_PH
B
45
ADC0_SE12/
TSI0_CH7
ADC0_SE12/
TSI0_CH7
PTB2
I2C0_SCL
UART0_RTS_
b
FTM0_FLT3
46
ADC0_SE13/
TSI0_CH8
ADC0_SE13/
TSI0_CH8
PTB3
I2C0_SDA
UART0_CTS_
b
FTM0_FLT0
47
ADC1_SE14
ADC1_SE14
PTB10
SPI1_PCS0
UART3_RX
FB_AD19
FTM0_FLT1
48
ADC1_SE15
ADC1_SE15
PTB11
SPI1_SCK
UART3_TX
FB_AD18
FTM0_FLT2
49
VSS
VSS
50
VDD
VDD
Pr
el
im
in
ar
y
23
JTAG_TMS/
SWD_DIO
NMI_b
CMP2_OUT
EZP_CS_b
I2S0_RX_BCL JTAG_TRST
K
I2S0_CLKIN
LPT0_ALT1
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
55
Pinout
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
51
TSI0_CH9
TSI0_CH9
PTB16
SPI1_SOUT
UART0_RX
FB_AD17
EWM_IN
52
TSI0_CH10
TSI0_CH10
PTB17
SPI1_SIN
UART0_TX
FB_AD16
EWM_OUT_b
53
TSI0_CH11
TSI0_CH11
PTB18
CAN0_TX
FTM2_CH0
I2S0_TX_BCL FB_AD15
K
FTM2_QD_PH
A
54
TSI0_CH12
TSI0_CH12
PTB19
CAN0_RX
FTM2_CH1
I2S0_TX_FS
FTM2_QD_PH
B
55
ADC0_SE14/
TSI0_CH13
ADC0_SE14/
TSI0_CH13
PTC0
SPI0_PCS4
PDB0_EXTRG I2S0_TXD
FB_AD14
56
ADC0_SE15/
TSI0_CH14
ADC0_SE15/
TSI0_CH14
PTC1
SPI0_PCS3
UART1_RTS_ FTM0_CH0
b
FB_AD13
57
ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
PTC2
SPI0_PCS2
UART1_CTS_ FTM0_CH1
b
FB_AD12
58
CMP1_IN1
CMP1_IN1
PTC3
SPI0_PCS1
UART1_RX
FTM0_CH2
FB_CLKOUT
59
VSS
VSS
60
VDD
VDD
61
DISABLED
PTC4
SPI0_PCS0
UART1_TX
FTM0_CH3
FB_AD11
CMP1_OUT
62
DISABLED
PTC5
SPI0_SCK
LPT0_ALT2
FB_AD10
CMP0_OUT
63
CMP0_IN0
CMP0_IN0
PTC6
SPI0_SOUT
64
CMP0_IN1
CMP0_IN1
PTC7
SPI0_SIN
65
ADC1_SE4b/
CMP0_IN2
ADC1_SE4b/
CMP0_IN2
PTC8
66
ADC1_SE5b/
CMP0_IN3
ADC1_SE5b/
CMP0_IN3
PTC9
67
ADC1_SE6b/
CMP0_IN4
ADC1_SE6b/
CMP0_IN4
PTC10
I2C1_SCL
I2S0_RX_FS
FB_AD5
68
ADC1_SE7b
ADC1_SE7b
PTC11
I2C1_SDA
I2S0_RXD
FB_RW_b
69
VSS
VSS
70
VDD
VDD
71
DISABLED
PTC16
CAN1_RX
UART3_RX
FB_CS5_b/
FB_TSIZ1/
FB_BE23_16_
BLS15_8_b
72
DISABLED
PTC17
CAN1_TX
UART3_TX
FB_CS4_b/
FB_TSIZ0/
FB_BE31_24_
BLS7_0_b
73
DISABLED
PTD0
SPI0_PCS0
UART2_RTS_
b
FB_ALE/
FB_CS1_b/
FB_TS_b
74
ADC0_SE5b
PTD1
SPI0_SCK
UART2_CTS_
b
FB_CS0_b
75
DISABLED
PTD2
SPI0_SOUT
UART2_RX
FB_AD4
76
DISABLED
PTD3
SPI0_SIN
UART2_TX
FB_AD3
77
DISABLED
PTD4
SPI0_PCS1
UART0_RTS_ FTM0_CH4
b
FB_AD2
FB_OE_b
ALT6
ALT7
EzPort
Pr
el
im
in
ar
y
80
QFP
ADC0_SE5b
PDB0_EXTRG
FB_AD9
FB_AD8
I2S0_MCLK
I2S0_CLKIN
FB_AD7
I2S0_RX_BCL FB_AD6
K
FTM2_FLT0
EWM_IN
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
56
Preliminary
Freescale Semiconductor, Inc.
Pinout
80
QFP
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
78
ADC0_SE6b
ADC0_SE6b
PTD5
SPI0_PCS2
UART0_CTS_ FTM0_CH5
b
FB_AD1
EWM_OUT_b
79
ADC0_SE7b
ADC0_SE7b
PTD6
SPI0_PCS3
UART0_RX
FTM0_CH6
FB_AD0
FTM0_FLT0
80
DISABLED
PTD7
CMT_IRO
UART0_TX
FTM0_CH7
ALT7
EzPort
FTM0_FLT1
8.2 K10 Pinouts
Pr
el
im
in
ar
y
The below figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
57
PTE0
PTC10
PTC9
PTC8
PTC7
PTC6
PTC5
PTC4
67
66
65
64
63
62
61
PTC17
72
PTC11
PTD0
73
68
PTD1
74
VSS
PTD2
75
69
PTD3
76
PTC16
PTD4
77
VDD
PTD5
78
71
PTD6
79
70
PTD7
80
Revision History
1
60
VDD
PTE1
2
59
VSS
PTE2
3
58
PTC3
PTE3
4
57
PTC2
5
56
PTC1
Pr
el
im
in
ar
y
PTE4
43
PTB0
VREFL
19
42
RESET_b
VSSA
20
41
PTA19
40
VREFH
PTA18
PTB1
39
44
18
VSS
17
38
VDDA
VDD
PTB2
37
45
PTA17
16
35
PGA1_DM/ADC1_DM0/ADC0_DM3
36
PTB3
PTA15
46
PTA16
PTB10
15
34
47
PGA1_DP/ADC1_DP0/ADC0_DP3
PTA14
PGA0_DM/ADC0_DM0/ADC1_DM3
33
PTB11
PTA13
48
14
32
13
PTA12
PGA0_DP/ADC0_DP0/ADC1_DP3
31
VSS
30
49
PTA5
12
PTA4
PTE19
29
VDD
PTA3
50
28
PTB16
11
PTA2
51
PTE18
27
PTE17
PTA1
PTB17
25
52
26
9
10
PTA0
PTE16
VBAT
PTB18
24
53
EXTAL32
8
23
VSS
XTAL32
PTB19
22
54
DAC0_OUT
PTC0
7
21
55
VDD
VREF_OUT
PTE5
6
Figure 24. K10 80 LQFP Pinout Diagram
9 Revision History
The following table provides a revision history for this document.
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
58
Preliminary
Freescale Semiconductor, Inc.
Revision History
Table 43. Revision History
Date
1
11/2010
Substantial Changes
Initial public revision
Pr
el
im
in
ar
y
Rev. No.
K10 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Freescale Semiconductor, Inc.
Preliminary
59
How to Reach Us:
Home Page:
www.freescale.com
Web Support:
http://www.freescale.com/support
USA/Europe or Locations Not Listed:
Freescale Semiconductor, Inc.
Technical Information Center, EL516
2100 East Elliot Road
Tempe, Arizona 85284
1-800-521-6274 or +1-480-768-2130
www.freescale.com/support
Europe, Middle East, and Africa:
Japan:
Pr
el
im
in
ar
y
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
www.freescale.com/support
Freescale Semiconductor Japan Ltd. Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064
Japan
0120 191014 or +81 3 5437 9125
[email protected]
Asia/Pacific:
Information in this document is provided solely to enable system and
software implementers to use Freescale Semiconductor products. There are
no express or implied copyright licenses granted hereunder to design or
fabricate any integrated circuits or integrated circuits based on the
information in this document.
Freescale Semiconductor China Ltd.
Exchange Building 23F
No. 118 Jianguo Road
Chaoyang District
Beijing 100022
China
+86 10 5879 8000
[email protected]
Freescale Semiconductor Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
1-800-441-2447 or +1-303-675-2140
Fax: +1-303-675-2150
[email protected]
Freescale Semiconductor reserves the right to make changes without further
notice to any products herein. Freescale Semiconductor makes no warranty,
representation or guarantee regarding the suitability of its products for any
particular purpose, nor does Freescale Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or
incidental damages. “Typical” parameters that may be provided in Freescale
Semiconductor data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer
application by customer’s technical experts. Freescale Semiconductor does
not convey any license under its patent rights nor the rights of others.
Freescale Semiconductor products are not designed, intended, or authorized
for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other
application in which the failure of the Freescale Semiconductor product could
create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended
or unauthorized application, Buyer shall indemnify and hold Freescale
Semiconductor and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized
use, even if such claim alleges that Freescale Semiconductor was negligent
regarding the design or manufacture of the part.
Freescale™ and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. ARM is the registered trademark of ARM Limited. ARM
Cortex-M4 is the trademark of ARM Limited. All other product or service
names are the property of their respective owners.
© Freescale Semiconductor, Inc. 2010. All rights reserved.
K10P81M100SF2
Rev. 1
11/2010